build/external/patches/dpdk_19.02/0001-net-ice-fixed-speed-capability-error-issue.patch

   1 From 925981b21ca765b97540d273bd0362518eb2de48 Mon Sep 17 00:00:00 2001
   2 From: Chenmin Sun <chenmin.sun@intel.com>
   3 Date: Thu, 28 Mar 2019 04:51:19 +0800
   4 Subject: [PATCH] net/ice: fixed speed capability error issue
   5
   6 Device speed capability should be specified based on different phy types
   7 instead of a fixed value, this patch fix the issue.
   8
   9 Signed-off-by: Chenmin Sun <chenmin.sun@intel.com>
  10 ---
  11  drivers/net/ice/ice_ethdev.c | 17 +++++++++++----
  12  drivers/net/ice/ice_ethdev.h | 40 ++++++++++++++++++++++++++++++++++++
  13  2 files changed, 53 insertions(+), 4 deletions(-)
  14
  15 diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
  16 index 6ab66faeb..1073eb501 100644
  17 --- a/drivers/net/ice/ice_ethdev.c
  18 +++ b/drivers/net/ice/ice_ethdev.c
  19 @@ -1819,6 +1819,8 @@ ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
  20         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
  21         struct ice_vsi *vsi = pf->main_vsi;
  22         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
  23 +       u64 phy_type_low;
  24 +       u64 phy_type_high;
  25
  26         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
  27         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
  28 @@ -1898,10 +1900,17 @@ ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
  29                                ETH_LINK_SPEED_5G |
  30                                ETH_LINK_SPEED_10G |
  31                                ETH_LINK_SPEED_20G |
  32 -                              ETH_LINK_SPEED_25G |
  33 -                              ETH_LINK_SPEED_40G |
  34 -                              ETH_LINK_SPEED_50G |
  35 -                              ETH_LINK_SPEED_100G;
  36 +                              ETH_LINK_SPEED_25G;
  37 +
  38 +       phy_type_low = hw->port_info->phy.phy_type_low;
  39 +       phy_type_high = hw->port_info->phy.phy_type_high;
  40 +
  41 +       if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
  42 +               dev_info->speed_capa |= ETH_LINK_SPEED_50G;
  43 +
  44 +       if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
  45 +                       ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
  46 +               dev_info->speed_capa |= ETH_LINK_SPEED_100G;
  47
  48         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
  49         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
  50 diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h
  51 index 3cefa5b5b..249fbef20 100644
  52 --- a/drivers/net/ice/ice_ethdev.h
  53 +++ b/drivers/net/ice/ice_ethdev.h
  54 @@ -315,4 +315,44 @@ ice_align_floor(int n)
  55                 return 0;
  56         return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
  57  }
  58 +
  59 +#define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \
  60 +       (((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \
  61 +       ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \
  62 +       ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \
  63 +       ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \
  64 +       ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \
  65 +       ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \
  66 +       ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \
  67 +       ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \
  68 +       ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \
  69 +       ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \
  70 +       ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \
  71 +       ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \
  72 +       ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \
  73 +       ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \
  74 +       ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1))
  75 +
  76 +#define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \
  77 +       (((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \
  78 +       ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \
  79 +       ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \
  80 +       ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \
  81 +       ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \
  82 +       ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \
  83 +       ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \
  84 +       ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \
  85 +       ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \
  86 +       ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \
  87 +       ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \
  88 +       ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \
  89 +       ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR))
  90 +
  91 +#define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \
  92 +       (((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \
  93 +       ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \
  94 +       ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \
  95 +       ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \
  96 +       ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2))
  97 +
  98  #endif /* _ICE_ETHDEV_H_ */
  99 --
 100 2.17.1
 101