debian/patches/dpdk-dev-ppc-enable-2-7-acl-add-AltiVec-for-ppc64.patch

   1 From: Gowrishankar Muthukrishnan <gowrishankar.m@linux.vnet.ibm.com>
   2 Date: Thu, 8 Sep 2016 22:18:04 +0530
   3 Subject: [PATCH 2/7] acl: add AltiVec for ppc64
   4
   5 This patch adds port for ACL library in ppc64le.
   6
   7 Signed-off-by: Gowrishankar Muthukrishnan <gowrishankar.m@linux.vnet.ibm.com>
   8 Acked-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
   9 Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
  10
  11 Origin: Upstream, commit:1d73135f9f1c626def280bd9c7e06a9ae157f660
  12 Author: Gowrishankar Muthukrishnan <gowrishankar.m@linux.vnet.ibm.com>
  13 Last-Update: 2016-09-21
  14 ---
  15  app/test-acl/main.c                         |   4 +
  16  config/defconfig_ppc_64-power8-linuxapp-gcc |   1 -
  17  lib/librte_acl/Makefile                     |   2 +
  18  lib/librte_acl/acl.h                        |   4 +
  19  lib/librte_acl/acl_run.h                    |   2 +
  20  lib/librte_acl/acl_run_altivec.c            |  47 ++++
  21  lib/librte_acl/acl_run_altivec.h            | 329 ++++++++++++++++++++++++++++
  22  lib/librte_acl/rte_acl.c                    |  13 ++
  23  lib/librte_acl/rte_acl.h                    |   1 +
  24  9 files changed, 402 insertions(+), 1 deletion(-)
  25  create mode 100644 lib/librte_acl/acl_run_altivec.c
  26  create mode 100644 lib/librte_acl/acl_run_altivec.h
  27
  28 --- a/app/test-acl/main.c
  29 +++ b/app/test-acl/main.c
  30 @@ -105,6 +105,10 @@
  31                 .name = "neon",
  32                 .alg = RTE_ACL_CLASSIFY_NEON,
  33         },
  34 +       {
  35 +               .name = "altivec",
  36 +               .alg = RTE_ACL_CLASSIFY_ALTIVEC,
  37 +       },
  38  };
  39
  40  static struct {
  41 --- a/config/defconfig_ppc_64-power8-linuxapp-gcc
  42 +++ b/config/defconfig_ppc_64-power8-linuxapp-gcc
  43 @@ -56,7 +56,6 @@
  44  CONFIG_RTE_LIBRTE_FM10K_PMD=n
  45
  46  # This following libraries are not available on Power. So they're turned off.
  47 -CONFIG_RTE_LIBRTE_ACL=n
  48  CONFIG_RTE_LIBRTE_SCHED=n
  49  CONFIG_RTE_LIBRTE_PORT=n
  50  CONFIG_RTE_LIBRTE_TABLE=n
  51 --- a/lib/librte_acl/Makefile
  52 +++ b/lib/librte_acl/Makefile
  53 @@ -52,6 +52,8 @@
  54  ifneq ($(filter y,$(CONFIG_RTE_ARCH_ARM) $(CONFIG_RTE_ARCH_ARM64)),)
  55  SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_neon.c
  56  CFLAGS_acl_run_neon.o += -flax-vector-conversions -Wno-maybe-uninitialized
  57 +else ifeq ($(CONFIG_RTE_ARCH_PPC_64),y)
  58 +SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_altivec.c
  59  else
  60  SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_sse.c
  61  #check if flag for SSE4.1 is already on, if not set it up manually
  62 --- a/lib/librte_acl/acl.h
  63 +++ b/lib/librte_acl/acl.h
  64 @@ -234,6 +234,10 @@
  65  rte_acl_classify_neon(const struct rte_acl_ctx *ctx, const uint8_t **data,
  66         uint32_t *results, uint32_t num, uint32_t categories);
  67
  68 +int
  69 +rte_acl_classify_altivec(const struct rte_acl_ctx *ctx, const uint8_t **data,
  70 +       uint32_t *results, uint32_t num, uint32_t categories);
  71 +
  72  #ifdef __cplusplus
  73  }
  74  #endif /* __cplusplus */
  75 --- a/lib/librte_acl/acl_run.h
  76 +++ b/lib/librte_acl/acl_run.h
  77 @@ -39,7 +39,9 @@
  78
  79  #define MAX_SEARCHES_AVX16     16
  80  #define MAX_SEARCHES_SSE8      8
  81 +#define MAX_SEARCHES_ALTIVEC8  8
  82  #define MAX_SEARCHES_SSE4      4
  83 +#define MAX_SEARCHES_ALTIVEC4  4
  84  #define MAX_SEARCHES_SCALAR    2
  85
  86  #define GET_NEXT_4BYTES(prm, idx)      \
  87 --- /dev/null
  88 +++ b/lib/librte_acl/acl_run_altivec.c
  89 @@ -0,0 +1,47 @@
  90 +/*-
  91 + *   BSD LICENSE
  92 + *
  93 + *   Copyright (C) IBM Corporation 2016.
  94 + *   All rights reserved.
  95 + *
  96 + *   Redistribution and use in source and binary forms, with or without
  97 + *   modification, are permitted provided that the following conditions
  98 + *   are met:
  99 + *
 100 + *     * Redistributions of source code must retain the above copyright
 101 + *       notice, this list of conditions and the following disclaimer.
 102 + *     * Redistributions in binary form must reproduce the above copyright
 103 + *       notice, this list of conditions and the following disclaimer in
 104 + *       the documentation and/or other materials provided with the
 105 + *       distribution.
 106 + *     * Neither the name of Intel Corporation nor the names of its
 107 + *       contributors may be used to endorse or promote products derived
 108 + *       from this software without specific prior written permission.
 109 + *
 110 + *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 111 + *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 112 + *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 113 + *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 114 + *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 115 + *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 116 + *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 117 + *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 118 + *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 119 + *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 120 + *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 121 + */
 122 +
 123 +#include "acl_run_altivec.h"
 124 +
 125 +int
 126 +rte_acl_classify_altivec(const struct rte_acl_ctx *ctx, const uint8_t **data,
 127 +       uint32_t *results, uint32_t num, uint32_t categories)
 128 +{
 129 +       if (likely(num >= MAX_SEARCHES_ALTIVEC8))
 130 +               return search_altivec_8(ctx, data, results, num, categories);
 131 +       else if (num >= MAX_SEARCHES_ALTIVEC4)
 132 +               return search_altivec_4(ctx, data, results, num, categories);
 133 +       else
 134 +               return rte_acl_classify_scalar(ctx, data, results, num,
 135 +                       categories);
 136 +}
 137 --- /dev/null
 138 +++ b/lib/librte_acl/acl_run_altivec.h
 139 @@ -0,0 +1,329 @@
 140 +/*
 141 + *   BSD LICENSE
 142 + *
 143 + *   Copyright (C) IBM Corporation 2016.
 144 + *
 145 + *   Redistribution and use in source and binary forms, with or without
 146 + *   modification, are permitted provided that the following conditions
 147 + *   are met:
 148 + *
 149 + *     * Redistributions of source code must retain the above copyright
 150 + *       notice, this list of conditions and the following disclaimer.
 151 + *     * Redistributions in binary form must reproduce the above copyright
 152 + *       notice, this list of conditions and the following disclaimer in
 153 + *       the documentation and/or other materials provided with the
 154 + *       distribution.
 155 + *     * Neither the name of IBM Corporation nor the names of its
 156 + *       contributors may be used to endorse or promote products derived
 157 + *       from this software without specific prior written permission.
 158 + *
 159 + *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 160 + *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 161 + *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 162 + *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 163 + *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 164 + *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 165 + *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 166 + *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 167 + *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 168 + *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 169 + *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 170 +*/
 171 +
 172 +#include "acl_run.h"
 173 +#include "acl_vect.h"
 174 +
 175 +struct _altivec_acl_const {
 176 +       rte_xmm_t xmm_shuffle_input;
 177 +       rte_xmm_t xmm_index_mask;
 178 +       rte_xmm_t xmm_ones_16;
 179 +       rte_xmm_t range_base;
 180 +} altivec_acl_const  __attribute__((aligned(RTE_CACHE_LINE_SIZE))) = {
 181 +       {
 182 +               .u32 = {0x00000000, 0x04040404, 0x08080808, 0x0c0c0c0c}
 183 +       },
 184 +       {
 185 +               .u32 = {RTE_ACL_NODE_INDEX, RTE_ACL_NODE_INDEX,
 186 +               RTE_ACL_NODE_INDEX, RTE_ACL_NODE_INDEX}
 187 +       },
 188 +       {
 189 +               .u16 = {1, 1, 1, 1, 1, 1, 1, 1}
 190 +       },
 191 +       {
 192 +               .u32 = {0xffffff00, 0xffffff04, 0xffffff08, 0xffffff0c}
 193 +       },
 194 +};
 195 +
 196 +/*
 197 + * Resolve priority for multiple results (altivec version).
 198 + * This consists comparing the priority of the current traversal with the
 199 + * running set of results for the packet.
 200 + * For each result, keep a running array of the result (rule number) and
 201 + * its priority for each category.
 202 + */
 203 +static inline void
 204 +resolve_priority_altivec(uint64_t transition, int n,
 205 +       const struct rte_acl_ctx *ctx, struct parms *parms,
 206 +       const struct rte_acl_match_results *p, uint32_t categories)
 207 +{
 208 +       uint32_t x;
 209 +       xmm_t results, priority, results1, priority1;
 210 +       vector bool int selector;
 211 +       xmm_t *saved_results, *saved_priority;
 212 +
 213 +       for (x = 0; x < categories; x += RTE_ACL_RESULTS_MULTIPLIER) {
 214 +
 215 +               saved_results = (xmm_t *)(&parms[n].cmplt->results[x]);
 216 +               saved_priority =
 217 +                       (xmm_t *)(&parms[n].cmplt->priority[x]);
 218 +
 219 +               /* get results and priorities for completed trie */
 220 +               results = *(const xmm_t *)&p[transition].results[x];
 221 +               priority = *(const xmm_t *)&p[transition].priority[x];
 222 +
 223 +               /* if this is not the first completed trie */
 224 +               if (parms[n].cmplt->count != ctx->num_tries) {
 225 +
 226 +                       /* get running best results and their priorities */
 227 +                       results1 = *saved_results;
 228 +                       priority1 = *saved_priority;
 229 +
 230 +                       /* select results that are highest priority */
 231 +                       selector = vec_cmpgt(priority1, priority);
 232 +                       results = vec_sel(results, results1, selector);
 233 +                       priority = vec_sel(priority, priority1,
 234 +                               selector);
 235 +               }
 236 +
 237 +               /* save running best results and their priorities */
 238 +               *saved_results = results;
 239 +               *saved_priority = priority;
 240 +       }
 241 +}
 242 +
 243 +/*
 244 + * Check for any match in 4 transitions
 245 + */
 246 +static inline __attribute__((always_inline)) uint32_t
 247 +check_any_match_x4(uint64_t val[])
 248 +{
 249 +       return (val[0] | val[1] | val[2] | val[3]) & RTE_ACL_NODE_MATCH;
 250 +}
 251 +
 252 +static inline __attribute__((always_inline)) void
 253 +acl_match_check_x4(int slot, const struct rte_acl_ctx *ctx, struct parms *parms,
 254 +       struct acl_flow_data *flows, uint64_t transitions[])
 255 +{
 256 +       while (check_any_match_x4(transitions)) {
 257 +               transitions[0] = acl_match_check(transitions[0], slot, ctx,
 258 +                       parms, flows, resolve_priority_altivec);
 259 +               transitions[1] = acl_match_check(transitions[1], slot + 1, ctx,
 260 +                       parms, flows, resolve_priority_altivec);
 261 +               transitions[2] = acl_match_check(transitions[2], slot + 2, ctx,
 262 +                       parms, flows, resolve_priority_altivec);
 263 +               transitions[3] = acl_match_check(transitions[3], slot + 3, ctx,
 264 +                       parms, flows, resolve_priority_altivec);
 265 +       }
 266 +}
 267 +
 268 +/*
 269 + * Process 4 transitions (in 2 XMM registers) in parallel
 270 + */
 271 +static inline __attribute__((optimize("O2"))) xmm_t
 272 +transition4(xmm_t next_input, const uint64_t *trans,
 273 +       xmm_t *indices1, xmm_t *indices2)
 274 +{
 275 +       xmm_t addr, tr_lo, tr_hi;
 276 +       xmm_t in, node_type, r, t;
 277 +       xmm_t dfa_ofs, quad_ofs;
 278 +       xmm_t *index_mask, *tp;
 279 +       vector bool int dfa_msk;
 280 +       vector signed char zeroes = {};
 281 +       union {
 282 +               uint64_t d64[2];
 283 +               uint32_t d32[4];
 284 +       } v;
 285 +
 286 +       /* Move low 32 into tr_lo and high 32 into tr_hi */
 287 +       tr_lo = (xmm_t){(*indices1)[0], (*indices1)[2],
 288 +                       (*indices2)[0], (*indices2)[2]};
 289 +       tr_hi = (xmm_t){(*indices1)[1], (*indices1)[3],
 290 +                       (*indices2)[1], (*indices2)[3]};
 291 +
 292 +        /* Calculate the address (array index) for all 4 transitions. */
 293 +       index_mask = (xmm_t *)&altivec_acl_const.xmm_index_mask.u32;
 294 +       t = vec_xor(*index_mask, *index_mask);
 295 +       in = vec_perm(next_input, (xmm_t){},
 296 +               *(vector unsigned char *)&altivec_acl_const.xmm_shuffle_input);
 297 +
 298 +       /* Calc node type and node addr */
 299 +       node_type = vec_and(vec_nor(*index_mask, *index_mask), tr_lo);
 300 +       addr = vec_and(tr_lo, *index_mask);
 301 +
 302 +       /* mask for DFA type(0) nodes */
 303 +       dfa_msk = vec_cmpeq(node_type, t);
 304 +
 305 +       /* DFA calculations. */
 306 +       r = vec_sr(in, (vector unsigned int){30, 30, 30, 30});
 307 +       tp = (xmm_t *)&altivec_acl_const.range_base.u32;
 308 +       r = vec_add(r, *tp);
 309 +       t = vec_sr(in, (vector unsigned int){24, 24, 24, 24});
 310 +       r = vec_perm(tr_hi, (xmm_t){(uint16_t)0 << 16},
 311 +               (vector unsigned char)r);
 312 +
 313 +       dfa_ofs = vec_sub(t, r);
 314 +
 315 +       /* QUAD/SINGLE caluclations. */
 316 +       t = (xmm_t)vec_cmpgt((vector signed char)in, (vector signed char)tr_hi);
 317 +       t = (xmm_t)vec_sel(
 318 +               vec_sel(
 319 +                       (vector signed char)vec_sub(
 320 +                               zeroes, (vector signed char)t),
 321 +                       (vector signed char)t,
 322 +                       vec_cmpgt((vector signed char)t, zeroes)),
 323 +               zeroes,
 324 +               vec_cmpeq((vector signed char)t, zeroes));
 325 +
 326 +       t = (xmm_t)vec_msum((vector signed char)t,
 327 +               (vector unsigned char)t, (xmm_t){});
 328 +       quad_ofs = (xmm_t)vec_msum((vector signed short)t,
 329 +               *(vector signed short *)&altivec_acl_const.xmm_ones_16.u16,
 330 +               (xmm_t){});
 331 +
 332 +       /* blend DFA and QUAD/SINGLE. */
 333 +       t = vec_sel(quad_ofs, dfa_ofs, dfa_msk);
 334 +
 335 +       /* calculate address for next transitions. */
 336 +       addr = vec_add(addr, t);
 337 +
 338 +       v.d64[0] = (uint64_t)trans[addr[0]];
 339 +       v.d64[1] = (uint64_t)trans[addr[1]];
 340 +       *indices1 = (xmm_t){v.d32[0], v.d32[1], v.d32[2], v.d32[3]};
 341 +       v.d64[0] = (uint64_t)trans[addr[2]];
 342 +       v.d64[1] = (uint64_t)trans[addr[3]];
 343 +       *indices2 = (xmm_t){v.d32[0], v.d32[1], v.d32[2], v.d32[3]};
 344 +
 345 +       return vec_sr(next_input,
 346 +               (vector unsigned int){CHAR_BIT, CHAR_BIT, CHAR_BIT, CHAR_BIT});
 347 +}
 348 +
 349 +/*
 350 + * Execute trie traversal with 8 traversals in parallel
 351 + */
 352 +static inline int
 353 +search_altivec_8(const struct rte_acl_ctx *ctx, const uint8_t **data,
 354 +       uint32_t *results, uint32_t total_packets, uint32_t categories)
 355 +{
 356 +       int n;
 357 +       struct acl_flow_data flows;
 358 +       uint64_t index_array[MAX_SEARCHES_ALTIVEC8];
 359 +       struct completion cmplt[MAX_SEARCHES_ALTIVEC8];
 360 +       struct parms parms[MAX_SEARCHES_ALTIVEC8];
 361 +       xmm_t input0, input1;
 362 +
 363 +       acl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results,
 364 +               total_packets, categories, ctx->trans_table);
 365 +
 366 +       for (n = 0; n < MAX_SEARCHES_ALTIVEC8; n++) {
 367 +               cmplt[n].count = 0;
 368 +               index_array[n] = acl_start_next_trie(&flows, parms, n, ctx);
 369 +       }
 370 +
 371 +        /* Check for any matches. */
 372 +       acl_match_check_x4(0, ctx, parms, &flows, (uint64_t *)&index_array[0]);
 373 +       acl_match_check_x4(4, ctx, parms, &flows, (uint64_t *)&index_array[4]);
 374 +
 375 +       while (flows.started > 0) {
 376 +
 377 +               /* Gather 4 bytes of input data for each stream. */
 378 +               input0 = (xmm_t){GET_NEXT_4BYTES(parms, 0),
 379 +                               GET_NEXT_4BYTES(parms, 1),
 380 +                               GET_NEXT_4BYTES(parms, 2),
 381 +                               GET_NEXT_4BYTES(parms, 3)};
 382 +
 383 +               input1 = (xmm_t){GET_NEXT_4BYTES(parms, 4),
 384 +                               GET_NEXT_4BYTES(parms, 5),
 385 +                               GET_NEXT_4BYTES(parms, 6),
 386 +                               GET_NEXT_4BYTES(parms, 7)};
 387 +
 388 +                /* Process the 4 bytes of input on each stream. */
 389 +
 390 +               input0 = transition4(input0, flows.trans,
 391 +                       (xmm_t *)&index_array[0], (xmm_t *)&index_array[2]);
 392 +               input1 = transition4(input1, flows.trans,
 393 +                       (xmm_t *)&index_array[4], (xmm_t *)&index_array[6]);
 394 +
 395 +               input0 = transition4(input0, flows.trans,
 396 +                       (xmm_t *)&index_array[0], (xmm_t *)&index_array[2]);
 397 +               input1 = transition4(input1, flows.trans,
 398 +                       (xmm_t *)&index_array[4], (xmm_t *)&index_array[6]);
 399 +
 400 +               input0 = transition4(input0, flows.trans,
 401 +                       (xmm_t *)&index_array[0], (xmm_t *)&index_array[2]);
 402 +               input1 = transition4(input1, flows.trans,
 403 +                       (xmm_t *)&index_array[4], (xmm_t *)&index_array[6]);
 404 +
 405 +               input0 = transition4(input0, flows.trans,
 406 +                       (xmm_t *)&index_array[0], (xmm_t *)&index_array[2]);
 407 +               input1 = transition4(input1, flows.trans,
 408 +                       (xmm_t *)&index_array[4], (xmm_t *)&index_array[6]);
 409 +
 410 +                /* Check for any matches. */
 411 +               acl_match_check_x4(0, ctx, parms, &flows,
 412 +                       (uint64_t *)&index_array[0]);
 413 +               acl_match_check_x4(4, ctx, parms, &flows,
 414 +                       (uint64_t *)&index_array[4]);
 415 +       }
 416 +
 417 +       return 0;
 418 +}
 419 +
 420 +/*
 421 + * Execute trie traversal with 4 traversals in parallel
 422 + */
 423 +static inline int
 424 +search_altivec_4(const struct rte_acl_ctx *ctx, const uint8_t **data,
 425 +        uint32_t *results, int total_packets, uint32_t categories)
 426 +{
 427 +       int n;
 428 +       struct acl_flow_data flows;
 429 +       uint64_t index_array[MAX_SEARCHES_ALTIVEC4];
 430 +       struct completion cmplt[MAX_SEARCHES_ALTIVEC4];
 431 +       struct parms parms[MAX_SEARCHES_ALTIVEC4];
 432 +       xmm_t input;
 433 +
 434 +       acl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results,
 435 +               total_packets, categories, ctx->trans_table);
 436 +
 437 +       for (n = 0; n < MAX_SEARCHES_ALTIVEC4; n++) {
 438 +               cmplt[n].count = 0;
 439 +               index_array[n] = acl_start_next_trie(&flows, parms, n, ctx);
 440 +       }
 441 +
 442 +       /* Check for any matches. */
 443 +       acl_match_check_x4(0, ctx, parms, &flows, index_array);
 444 +
 445 +       while (flows.started > 0) {
 446 +
 447 +               /* Gather 4 bytes of input data for each stream. */
 448 +               input = (xmm_t){GET_NEXT_4BYTES(parms, 0),
 449 +                               GET_NEXT_4BYTES(parms, 1),
 450 +                               GET_NEXT_4BYTES(parms, 2),
 451 +                               GET_NEXT_4BYTES(parms, 3)};
 452 +
 453 +               /* Process the 4 bytes of input on each stream. */
 454 +               input = transition4(input, flows.trans,
 455 +                       (xmm_t *)&index_array[0], (xmm_t *)&index_array[2]);
 456 +               input = transition4(input, flows.trans,
 457 +                       (xmm_t *)&index_array[0], (xmm_t *)&index_array[2]);
 458 +               input = transition4(input, flows.trans,
 459 +                       (xmm_t *)&index_array[0], (xmm_t *)&index_array[2]);
 460 +               input = transition4(input, flows.trans,
 461 +                       (xmm_t *)&index_array[0], (xmm_t *)&index_array[2]);
 462 +
 463 +               /* Check for any matches. */
 464 +               acl_match_check_x4(0, ctx, parms, &flows, index_array);
 465 +       }
 466 +
 467 +       return 0;
 468 +}
 469 --- a/lib/librte_acl/rte_acl.c
 470 +++ b/lib/librte_acl/rte_acl.c
 471 @@ -75,12 +75,23 @@
 472         return -ENOTSUP;
 473  }
 474
 475 +int __attribute__ ((weak))
 476 +rte_acl_classify_altivec(__rte_unused const struct rte_acl_ctx *ctx,
 477 +       __rte_unused const uint8_t **data,
 478 +       __rte_unused uint32_t *results,
 479 +       __rte_unused uint32_t num,
 480 +       __rte_unused uint32_t categories)
 481 +{
 482 +       return -ENOTSUP;
 483 +}
 484 +
 485  static const rte_acl_classify_t classify_fns[] = {
 486         [RTE_ACL_CLASSIFY_DEFAULT] = rte_acl_classify_scalar,
 487         [RTE_ACL_CLASSIFY_SCALAR] = rte_acl_classify_scalar,
 488         [RTE_ACL_CLASSIFY_SSE] = rte_acl_classify_sse,
 489         [RTE_ACL_CLASSIFY_AVX2] = rte_acl_classify_avx2,
 490         [RTE_ACL_CLASSIFY_NEON] = rte_acl_classify_neon,
 491 +       [RTE_ACL_CLASSIFY_ALTIVEC] = rte_acl_classify_altivec,
 492  };
 493
 494  /* by default, use always available scalar code path. */
 495 @@ -119,6 +130,8 @@
 496  #elif defined(RTE_ARCH_ARM)
 497         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON))
 498                 alg =  RTE_ACL_CLASSIFY_NEON;
 499 +#elif defined(RTE_ARCH_PPC_64)
 500 +       alg = RTE_ACL_CLASSIFY_ALTIVEC;
 501  #else
 502  #ifdef CC_AVX2_SUPPORT
 503         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
 504 --- a/lib/librte_acl/rte_acl.h
 505 +++ b/lib/librte_acl/rte_acl.h
 506 @@ -271,6 +271,7 @@
 507         RTE_ACL_CLASSIFY_SSE = 2,     /**< requires SSE4.1 support. */
 508         RTE_ACL_CLASSIFY_AVX2 = 3,    /**< requires AVX2 support. */
 509         RTE_ACL_CLASSIFY_NEON = 4,    /**< requires NEON support. */
 510 +       RTE_ACL_CLASSIFY_ALTIVEC = 5,    /**< requires ALTIVEC support. */
 511         RTE_ACL_CLASSIFY_NUM          /* should always be the last one. */
 512  };
 513