1 .. _tested_physical_topologies:
6 All :abbr:`FD.io (Fast Data Input/Ouput)` :abbr:`CSIT (Continuous System
7 Integration and Testing)` performance test results included in this
8 report are executed on the physical testbeds hosted by :abbr:`LF (Linux
9 Foundation)` FD.io project, unless otherwise noted.
11 Two physical server topology types are used:
13 - **2-Node Topology**: Consists of one server acting as a System Under
14 Test (SUT) and one server acting as a Traffic Generator (TG), with
15 both servers connected into a ring topology. Used for executing tests
16 that require frame encapsulations supported by TG.
18 - **3-Node Topology**: Consists of two servers acting as a Systems Under
19 Test (SUTs) and one server acting as a Traffic Generator (TG), with
20 all servers connected into a ring topology. Used for executing tests
21 that require frame encapsulations not supported by TG e.g. certain
22 overlay tunnel encapsulations and IPsec. Number of native Ethernet,
23 IPv4 and IPv6 encapsulation tests are also executed on these testbeds,
24 for comparison with 2-Node Topology.
26 Current FD.io production testbeds are built with SUT servers based on
27 the following processor architectures:
29 - Intel Xeon: Skylake Platinum 8180, Cascadelake 6252N, (Icelake 8358
30 installation in progress).
31 - Intel Atom: Denverton C3858.
32 - Arm: TaiShan 2280, hip07-d05.
33 - AMD EPYC: Zen2 7532.
35 CSIT-2106 report data for Intel Xeon Icelake testbeds comes from
36 testbeds in Intel labs set up per CSIT specification and running CSIT
37 code. Physical setup used is specified in 2n-icx and 3n-icx sections
38 below. For details about tested VPP and CSIT versions
39 see :ref:`vpp_performance_tests_release_notes`.
41 Server SUT performance depends on server and processor type, hence
42 results for testbeds based on different servers must be reported
43 separately, and compared if appropriate.
45 Complete technical specifications of compute servers used in CSIT
46 physical testbeds are maintained in FD.io CSIT repository:
47 https://git.fd.io/csit/tree/docs/lab/testbed_specifications.md.
49 Following is the description of existing production testbeds.
51 2-Node AMD EPYC Zen2 (2n-zn2)
52 -----------------------------
54 One 2n-zn2 testbed in in operation in FD.io labs. It is built based on
55 two SuperMicro SuperMicro AS-1114S-WTRT servers, with SUT and TG servers
56 equipped with one AMD EPYC Zen2 7532 processor each (256 MB Cache, 2.40
57 GHz, 32 cores). 2n-zn2 physical topology is shown below.
65 \graphicspath{{../_tmp/src/introduction/}}
66 \includegraphics[width=0.90\textwidth]{testbed-2n-zn2}
67 \label{fig:testbed-2n-zn2}
72 .. figure:: testbed-2n-zn2.svg
76 SUT server is populated with the following NIC models:
78 #. NIC-1: x710-DA4 4p10GE Intel.
79 #. NIC-2: xxv710-DA2 2p25GE Intel.
80 #. NIC-3: cx556a-edat ConnectX5 2p100GE Mellanox.
82 TG server runs TRex application and is populated with the following
85 #. NIC-1: x710-DA4 4p10GE Intel.
86 #. NIC-2: xxv710-DA2 2p25GE Intel.
87 #. NIC-3: cx556a-edat ConnectX5 2p100GE Mellanox.
89 All AMD EPYC Zen2 7532 servers run with AMD SMT enabled, doubling the
90 number of logical cores exposed to Linux.
92 2-Node Xeon Cascadelake (2n-clx)
93 ---------------------------------
95 Three 2n-clx testbeds are in operation in FD.io labs. Each 2n-clx testbed
96 is built with two SuperMicro SYS-7049GP-TRT servers, SUTs are equipped with two
97 Intel Xeon Gold 6252N processors (35.75 MB Cache, 2.30 GHz, 24 cores).
98 TGs are equiped with Intel Xeon Cascade Lake Platinum 8280 processors (38.5 MB
99 Cache, 2.70 GHz, 28 cores). 2n-clx physical topology is shown below.
107 \graphicspath{{../_tmp/src/introduction/}}
108 \includegraphics[width=0.90\textwidth]{testbed-2n-clx}
109 \label{fig:testbed-2n-clx}
114 .. figure:: testbed-2n-clx.svg
118 SUT servers are populated with the following NIC models:
120 #. NIC-1: x710-DA4 4p10GE Intel.
121 #. NIC-2: xxv710-DA2 2p25GE Intel.
122 #. NIC-3: cx556a-edat ConnectX5 2p100GE Mellanox.
123 #. NIC-4: empty, future expansion.
124 #. NIC-5: empty, future expansion.
125 #. NIC-6: empty, future expansion.
127 TG servers run T-Rex application and are populated with the following
130 #. NIC-1: x710-DA4 4p10GE Intel.
131 #. NIC-2: xxv710-DA2 2p25GE Intel.
132 #. NIC-3: cx556a-edat ConnectX5 2p100GE Mellanox.
133 #. NIC-4: empty, future expansion.
134 #. NIC-5: empty, future expansion.
135 #. NIC-6: x710-DA4 4p10GE Intel. (For self-tests.)
137 All Intel Xeon Cascadelake servers run with Intel Hyper-Threading enabled,
138 doubling the number of logical cores exposed to Linux.
140 2-Node Xeon Icelake (2n-icx) EXPERIMENTAL
141 -----------------------------------------
143 One 2n-icx testbed located in Intel labs was used for CSIT testing. It
144 is built with two SuperMicro SYS-740GP-TNRT servers. SUT is equipped
145 with two Intel Xeon Gold 6338N processors (48 MB Cache, 2.20 GHz, 32
146 cores). TG is equiped with two Intel Xeon Ice Lake Platinum 8360Y
147 processors (54 MB Cache, 2.40 GHz, 36 cores). 2n-icx physical topology
156 \graphicspath{{../_tmp/src/introduction/}}
157 \includegraphics[width=0.90\textwidth]{testbed-2n-icx}
158 \label{fig:testbed-2n-icx}
163 .. figure:: testbed-2n-icx.svg
167 SUT and TG servers are populated with the following NIC models:
169 #. NIC-1: E810-2CQDA2 2p100GbE Intel.
171 All Intel Xeon Icelake servers run with Intel Hyper-Threading enabled,
172 doubling the number of logical cores exposed to Linux.
174 3-Node Xeon Icelake (3n-icx) EXPERIMENTAL
175 -----------------------------------------
177 One 3n-icx testbed located in Intel labs was used for CSIT testing. It
178 is built with three SuperMicro SYS-740GP-TNRT servers. SUTs are
179 equipped each with two Intel Xeon Platinum 8360Y processors (54 MB
180 Cache, 2.40 GHz, 36 cores). TG is equiped with two Intel Xeon Ice Lake
181 Platinum 8360Y processors (54 MB Cache, 2.40 GHz, 36 cores). 3n-icx
182 physical topology is shown below.
190 \graphicspath{{../_tmp/src/introduction/}}
191 \includegraphics[width=0.90\textwidth]{testbed-3n-icx}
192 \label{fig:testbed-3n-icx}
197 .. figure:: testbed-3n-icx.svg
201 SUT and TG servers are populated with the following NIC models:
203 #. NIC-1: E810-2CQDA2 2p100GbE Intel.
205 All Intel Xeon Icelake servers run with Intel Hyper-Threading enabled,
206 doubling the number of logical cores exposed to Linux.
208 2-Node Xeon Skylake (2n-skx)
209 ----------------------------
211 Four 2n-skx testbeds are in operation in FD.io labs. Each 2n-skx testbed
212 is built with two SuperMicro SYS-7049GP-TRT servers, each in turn
213 equipped with two Intel Xeon Skylake Platinum 8180 processors (38.5 MB
214 Cache, 2.50 GHz, 28 cores). 2n-skx physical topology is shown below.
222 \graphicspath{{../_tmp/src/introduction/}}
223 \includegraphics[width=0.90\textwidth]{testbed-2n-skx}
224 \label{fig:testbed-2n-skx}
229 .. figure:: testbed-2n-skx.svg
233 SUT servers are populated with the following NIC models:
235 #. NIC-1: x710-DA4 4p10GE Intel.
236 #. NIC-2: xxv710-DA2 2p25GE Intel.
237 #. NIC-3: empty, future expansion.
238 #. NIC-4: empty, future expansion.
239 #. NIC-5: empty, future expansion.
240 #. NIC-6: empty, future expansion.
242 TG servers run T-Rex application and are populated with the following
245 #. NIC-1: x710-DA4 4p10GE Intel.
246 #. NIC-2: xxv710-DA2 2p25GE Intel.
247 #. NIC-3: empty, future expansion.
248 #. NIC-4: empty, future expansion.
249 #. NIC-5: empty, future expansion.
250 #. NIC-6: x710-DA4 4p10GE Intel. (For self-tests.)
252 All Intel Xeon Skylake servers run with Intel Hyper-Threading enabled,
253 doubling the number of logical cores exposed to Linux, with 56 logical
254 cores and 28 physical cores per processor socket.
256 3-Node Xeon Skylake (3n-skx)
257 ----------------------------
259 Two 3n-skx testbeds are in operation in FD.io labs. Each 3n-skx testbed
260 is built with three SuperMicro SYS-7049GP-TRT servers, each in turn
261 equipped with two Intel Xeon Skylake Platinum 8180 processors (38.5 MB
262 Cache, 2.50 GHz, 28 cores). 3n-skx physical topology is shown below.
270 \graphicspath{{../_tmp/src/introduction/}}
271 \includegraphics[width=0.90\textwidth]{testbed-3n-skx}
272 \label{fig:testbed-3n-skx}
277 .. figure:: testbed-3n-skx.svg
281 SUT1 and SUT2 servers are populated with the following NIC models:
283 #. NIC-1: x710-DA4 4p10GE Intel.
284 #. NIC-2: xxv710-DA2 2p25GE Intel.
285 #. NIC-3: empty, future expansion.
286 #. NIC-4: empty, future expansion.
287 #. NIC-5: empty, future expansion.
288 #. NIC-6: empty, future expansion.
290 TG servers run T-Rex application and are populated with the following
293 #. NIC-1: x710-DA4 4p10GE Intel.
294 #. NIC-2: xxv710-DA2 2p25GE Intel.
295 #. NIC-3: empty, future expansion.
296 #. NIC-4: empty, future expansion.
297 #. NIC-5: empty, future expansion.
298 #. NIC-6: x710-DA4 4p10GE Intel. (For self-tests.)
300 All Intel Xeon Skylake servers run with Intel Hyper-Threading enabled,
301 doubling the number of logical cores exposed to Linux, with 56 logical
302 cores and 28 physical cores per processor socket.
304 2-Node Atom Denverton (2n-dnv)
305 ------------------------------
307 2n-dnv testbed is built with: i) one Intel S2600WFT server acting as TG
308 and equipped with two Intel Xeon Skylake Platinum 8180 processors (38.5
309 MB Cache, 2.50 GHz, 28 cores), and ii) one SuperMicro SYS-E300-9A server
310 acting as SUT and equipped with one Intel Atom C3858 processor (12 MB
311 Cache, 2.00 GHz, 12 cores). 2n-dnv physical topology is shown below.
319 \graphicspath{{../_tmp/src/introduction/}}
320 \includegraphics[width=0.90\textwidth]{testbed-2n-dnv}
321 \label{fig:testbed-2n-dnv}
326 .. figure:: testbed-2n-dnv.svg
330 SUT server have four internal 10G NIC port:
332 #. P-1: x553 copper port.
333 #. P-2: x553 copper port.
334 #. P-3: x553 fiber port.
335 #. P-4: x553 fiber port.
337 TG server run T-Rex software traffic generator and are populated with the
338 following NIC models:
340 #. NIC-1: x550-T2 2p10GE Intel.
341 #. NIC-2: x550-T2 2p10GE Intel.
342 #. NIC-3: x520-DA2 2p10GE Intel.
343 #. NIC-4: x520-DA2 2p10GE Intel.
345 The 2n-dnv testbed is in operation in Intel SH labs.
347 3-Node Atom Denverton (3n-dnv)
348 ------------------------------
350 One 3n-dnv testbed is built with: i) one SuperMicro SYS-7049GP-TRT
351 server acting as TG and equipped with two Intel Xeon Skylake Platinum
352 8180 processors (38.5 MB Cache, 2.50 GHz, 28 cores), and ii) one
353 SuperMicro SYS-E300-9A server acting as SUT and equipped with one Intel
354 Atom C3858 processor (12 MB Cache, 2.00 GHz, 12 cores). 3n-dnv physical
355 topology is shown below.
363 \graphicspath{{../_tmp/src/introduction/}}
364 \includegraphics[width=0.90\textwidth]{testbed-3n-dnv}
365 \label{fig:testbed-3n-dnv}
370 .. figure:: testbed-3n-dnv.svg
374 SUT1 and SUT2 servers are populated with the following NIC models:
376 #. NIC-1: x553 2p10GE fiber Intel.
377 #. NIC-2: x553 2p10GE copper Intel.
379 TG servers run T-Rex application and are populated with the following
382 #. NIC-1: x710-DA4 4p10GE Intel.
384 3-Node ARM TaiShan (3n-tsh)
385 ---------------------------
387 One 3n-tsh testbed is built with: i) one SuperMicro SYS-7049GP-TRT
388 server acting as TG and equipped with two Intel Xeon Skylake Platinum
389 8180 processors (38.5 MB Cache, 2.50 GHz, 28 cores), and ii) one Huawei
390 TaiShan 2280 server acting as SUT and equipped with one hip07-d05
391 processor (64* ARM Cortex-A72). 3n-tsh physical topology is shown below.
399 \graphicspath{{../_tmp/src/introduction/}}
400 \includegraphics[width=0.90\textwidth]{testbed-3n-tsh}
401 \label{fig:testbed-3n-tsh}
406 .. figure:: testbed-3n-tsh.svg
410 SUT1 and SUT2 servers are populated with the following NIC models:
412 #. NIC-1: connectx4 2p25GE Mellanox.
413 #. NIC-2: x520 2p10GE Intel.
415 TG server runs T-Rex application and is populated with the following
418 #. NIC-1: x710-DA4 4p10GE Intel.
419 #. NIC-2: xxv710-DA2 2p25GE Intel.
420 #. NIC-3: xl710-QDA2 2p40GE Intel.
422 2-Node ARM ThunderX2 (2n-tx2)
423 ---------------------------
425 One 2n-tx2 testbed is built with: i) one SuperMicro SYS-7049GP-TRT
426 server acting as TG and equipped with two Intel Xeon Skylake Platinum
427 8180 processors (38.5 MB Cache, 2.50 GHz, 28 cores), and ii) one Marvell
428 ThnderX2 9975 (28* ThunderX2) server acting as SUT and equipped with two
429 ThunderX2 ARMv8 CN9975 processors. 2n-tx2 physical topology is shown below.
437 \graphicspath{{../_tmp/src/introduction/}}
438 \includegraphics[width=0.90\textwidth]{testbed-2n-tx2}
439 \label{fig:testbed-2n-tx2}
444 .. figure:: testbed-2n-tx2.svg
448 SUT server is populated with the following NIC models:
450 #. NIC-1: xl710-QDA2 2p40GE Intel (not connected).
451 #. NIC-2: xl710-QDA2 2p40GE Intel.
453 TG server run T-Rex application and is populated with the following
456 #. NIC-1: xl710-QDA2 2p40GE Intel.