4 This section includes summary graphs of VPP Phy-to-Phy packet latency
5 with L2 Ethernet switching measured at 50% of discovered NDR throughput
6 rate. Latency is reported for VPP running in multiple configurations of
7 VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
8 physical CPU core(s) placement.
10 VPP packet latency in 1t1c setup (1thread, 1core) is presented in the graph below.
14 <iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/64B-1t1c-l2-sel1-ndrdisc-lat50.html"></iframe>
20 \graphicspath{{../_build/_static/vpp/}}
21 \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{64B-1t1c-l2-sel1-ndrdisc-lat50}
22 \label{fig:64B-1t1c-l2-sel1-ndrdisc-lat50}
25 *Figure 1a. VPP 1thread 1core - packet latency for Phy-to-Phy L2 Ethernet
28 CSIT source code for the test cases used for above plots can be found in
29 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls1804>`_.
33 <iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/64B-1t1c-l2-sel2-ndrdisc-lat50.html"></iframe>
39 \graphicspath{{../_build/_static/vpp/}}
40 \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{64B-1t1c-l2-sel2-ndrdisc-lat50}
41 \label{fig:64B-1t1c-l2-sel2-ndrdisc-lat50.html}
44 *Figure 1b. VPP 1thread 1core - packet latency for Phy-to-Phy L2 Ethernet
47 CSIT source code for the test cases used for above plots can be found in
48 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls1804>`_.
50 VPP packet latency in 2t2c setup (2thread, 2core) is presented in the graph below.
54 <iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/64B-2t2c-l2-sel1-ndrdisc-lat50.html"></iframe>
60 \graphicspath{{../_build/_static/vpp/}}
61 \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{64B-2t2c-l2-sel1-ndrdisc-lat50}
62 \label{fig:64B-2t2c-l2-sel1-ndrdisc-lat50}
65 *Figure 2a. VPP 2threads 2cores - packet latency for Phy-to-Phy L2 Ethernet
68 CSIT source code for the test cases used for above plots can be found in
69 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls1804>`_.
73 <iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/64B-2t2c-l2-sel2-ndrdisc-lat50.html"></iframe>
79 \graphicspath{{../_build/_static/vpp/}}
80 \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{64B-2t2c-l2-sel2-ndrdisc-lat50}
81 \label{fig:64B-2t2c-l2-sel2-ndrdisc-lat50}
84 *Figure 2b. VPP 2threads 2cores - packet latency for Phy-to-Phy L2 Ethernet
87 CSIT source code for the test cases used for above plots can be found in
88 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/l2?h=rls1804>`_.