1 IPSec Crypto HW: IP4 Routed-Forwarding
2 ======================================
4 Following sections include Throughput Speedup Analysis for VPP multi-
5 core multi-thread configurations with no Hyper-Threading, specifically
6 for tested 2t2c (2threads, 2cores) and 4t4c scenarios. 1t1c throughput
7 results are used as a reference for reported speedup ratio.
8 VPP IPSec encryption is accelerated using DPDK cryptodev
9 library driving Intel Quick Assist (QAT) crypto PCIe hardware cards.
10 Performance is reported for VPP running in multiple configurations of
11 VPP worker thread(s), a.k.a. VPP data plane thread(s), and their
12 physical CPU core(s) placement.
17 VPP NDR 64B packet throughput speedup ratio is presented in the graphs
18 below for 40ge2p1xl710 network interface card.
25 <iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/40ge2p1xl710-64B-ipsechw-tsa-ndrdisc.html"></iframe>
31 \graphicspath{{../_build/_static/vpp/}}
32 \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{40ge2p1xl710-64B-ipsechw-tsa-ndrdisc}
33 \label{fig:40ge2p1xl710-64B-ipsechw-tsa-ndrdisc}
36 *Figure 1. Throughput Speedup Analysis - Multi-Core Speedup Ratio - Normalized
37 NDR Throughput for Phy-to-Phy IPSEC HW.*
39 CSIT source code for the test cases used for above plots can be found in
40 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/crypto?h=rls1804>`_.
45 VPP PDR 64B packet throughput speedup ratio is presented in the graphs
46 below for 40ge2p1xl710 network interface card.
51 VPP PDR 64B packet throughput in 1t1c setup (1thread, 1core) is presented
52 in the graph below. PDR measured for 0.5% packet loss ratio.
56 <iframe width="700" height="1000" frameborder="0" scrolling="no" src="../../_static/vpp/40ge2p1xl710-64B-ipsechw-tsa-pdrdisc.html"></iframe>
62 \graphicspath{{../_build/_static/vpp/}}
63 \includegraphics[clip, trim=0cm 8cm 5cm 0cm, width=0.70\textwidth]{40ge2p1xl710-64B-ipsechw-tsa-pdrdisc}
64 \label{fig:40ge2p1xl710-64B-ipsechw-tsa-pdrdisc}
67 *Figure 2. Throughput Speedup Analysis - Multi-Core Speedup Ratio - Normalized
68 PDR Throughput for Phy-to-Phy IPSEC HW.*
70 CSIT source code for the test cases used for above plots can be found in
71 `CSIT git repository <https://git.fd.io/csit/tree/tests/vpp/perf/crypto?h=rls1804>`_.