2 * This file is provided under a dual BSD/GPLv2 license. When using or
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7 * Copyright 2011 Freescale Semiconductor, Inc.
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56 #include <linux/types.h>
60 #include <sys/types.h>
70 #include <rte_byteorder.h>
71 #include <rte_atomic.h>
72 #include <rte_spinlock.h>
73 #include <rte_common.h>
74 #include <rte_debug.h>
76 /* The following definitions are primarily to allow the single-source driver
77 * interfaces to be included by arbitrary program code. Ie. for interfaces that
78 * are also available in kernel-space, these definitions provide compatibility
79 * with certain attributes and types used in those interfaces.
82 /* Required compiler attributes */
83 #define __maybe_unused __rte_unused
84 #define __always_unused __rte_unused
85 #define __packed __rte_packed
86 #define noinline __attribute__((noinline))
88 #define L1_CACHE_BYTES 64
89 #define ____cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES)))
90 #define __stringify_1(x) #x
91 #define __stringify(x) __stringify_1(x)
96 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
99 #define prflush(fmt, args...) \
101 printf(fmt, ##args); \
105 #define pr_crit(fmt, args...) prflush("CRIT:" fmt, ##args)
106 #define pr_err(fmt, args...) prflush("ERR:" fmt, ##args)
107 #define pr_warn(fmt, args...) prflush("WARN:" fmt, ##args)
108 #define pr_info(fmt, args...) prflush(fmt, ##args)
110 #ifdef RTE_LIBRTE_DPAA_DEBUG_BUS
114 #define pr_debug(fmt, args...) printf(fmt, ##args)
116 #define pr_debug(fmt, args...) {}
119 #define DPAA_BUG_ON(x) RTE_ASSERT(x)
123 typedef uint16_t u16;
124 typedef uint32_t u32;
125 typedef uint64_t u64;
126 typedef uint64_t dma_addr_t;
127 typedef cpu_set_t cpumask_t;
128 typedef uint32_t phandle;
129 typedef uint32_t gfp_t;
130 typedef uint32_t irqreturn_t;
132 #define IRQ_HANDLED 0
133 #define request_irq qbman_request_irq
134 #define free_irq qbman_free_irq
138 #define __raw_readb(p) (*(const volatile unsigned char *)(p))
139 #define __raw_readl(p) (*(const volatile unsigned int *)(p))
140 #define __raw_writel(v, p) {*(volatile unsigned int *)(p) = (v); }
142 /* to be used as an upper-limit only */
145 /* Waitqueue stuff */
146 typedef struct { } wait_queue_head_t;
147 #define DECLARE_WAIT_QUEUE_HEAD(x) int dummy_##x __always_unused
148 #define wake_up(x) do { } while (0)
151 static inline u32 in_be32(volatile void *__p)
153 volatile u32 *p = __p;
154 return rte_be_to_cpu_32(*p);
157 static inline void out_be32(volatile void *__p, u32 val)
159 volatile u32 *p = __p;
160 *p = rte_cpu_to_be_32(val);
163 #define dcbt_ro(p) __builtin_prefetch(p, 0)
164 #define dcbt_rw(p) __builtin_prefetch(p, 1)
166 #define dcbz(p) { asm volatile("dc zva, %0" : : "r" (p) : "memory"); }
167 #define dcbz_64(p) dcbz(p)
168 #define hwsync() rte_rmb()
169 #define lwsync() rte_wmb()
170 #define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); }
171 #define dcbf_64(p) dcbf(p)
172 #define dccivac(p) { asm volatile("dc civac, %0" : : "r"(p) : "memory"); }
174 #define dcbit_ro(p) \
177 asm volatile("prfm pldl1keep, [%0, #64]" : : "r" (p)); \
180 #define barrier() { asm volatile ("" : : : "memory"); }
181 #define cpu_relax barrier
183 static inline uint64_t mfatb(void)
185 uint64_t ret, ret_new, timeout = 200;
187 asm volatile ("mrs %0, cntvct_el0" : "=r" (ret));
188 asm volatile ("mrs %0, cntvct_el0" : "=r" (ret_new));
189 while (ret != ret_new && timeout--) {
191 asm volatile ("mrs %0, cntvct_el0" : "=r" (ret_new));
193 DPAA_BUG_ON(!timeout && (ret != ret_new));
197 /* Spin for a few cycles without bothering the bus */
198 static inline void cpu_spin(int cycles)
200 uint64_t now = mfatb();
202 while (mfatb() < (now + cycles))
206 /* Qman/Bman API inlines and macros; */
210 #define lower_32_bits(x) ((u32)(x))
215 #define upper_32_bits(x) ((u32)(((x) >> 16) >> 16))
218 * Swap bytes of a 48-bit value.
220 static inline uint64_t
221 __bswap_48(uint64_t x)
223 return ((x & 0x0000000000ffULL) << 40) |
224 ((x & 0x00000000ff00ULL) << 24) |
225 ((x & 0x000000ff0000ULL) << 8) |
226 ((x & 0x0000ff000000ULL) >> 8) |
227 ((x & 0x00ff00000000ULL) >> 24) |
228 ((x & 0xff0000000000ULL) >> 40);
232 * Swap bytes of a 40-bit value.
234 static inline uint64_t
235 __bswap_40(uint64_t x)
237 return ((x & 0x00000000ffULL) << 32) |
238 ((x & 0x000000ff00ULL) << 16) |
239 ((x & 0x0000ff0000ULL)) |
240 ((x & 0x00ff000000ULL) >> 16) |
241 ((x & 0xff00000000ULL) >> 32);
245 * Swap bytes of a 24-bit value.
247 static inline uint32_t
248 __bswap_24(uint32_t x)
250 return ((x & 0x0000ffULL) << 16) |
251 ((x & 0x00ff00ULL)) |
252 ((x & 0xff0000ULL) >> 16);
255 #define be64_to_cpu(x) rte_be_to_cpu_64(x)
256 #define be32_to_cpu(x) rte_be_to_cpu_32(x)
257 #define be16_to_cpu(x) rte_be_to_cpu_16(x)
259 #define cpu_to_be64(x) rte_cpu_to_be_64(x)
260 #define cpu_to_be32(x) rte_cpu_to_be_32(x)
261 #define cpu_to_be16(x) rte_cpu_to_be_16(x)
263 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
265 #define cpu_to_be48(x) __bswap_48(x)
266 #define be48_to_cpu(x) __bswap_48(x)
268 #define cpu_to_be40(x) __bswap_40(x)
269 #define be40_to_cpu(x) __bswap_40(x)
271 #define cpu_to_be24(x) __bswap_24(x)
272 #define be24_to_cpu(x) __bswap_24(x)
274 #else /* RTE_BIG_ENDIAN */
276 #define cpu_to_be48(x) (x)
277 #define be48_to_cpu(x) (x)
279 #define cpu_to_be40(x) (x)
280 #define be40_to_cpu(x) (x)
282 #define cpu_to_be24(x) (x)
283 #define be24_to_cpu(x) (x)
285 #endif /* RTE_BIG_ENDIAN */
287 /* When copying aligned words or shorts, try to avoid memcpy() */
288 /* memcpy() stuff - when you know alignments in advance */
289 #define CONFIG_TRY_BETTER_MEMCPY
291 #ifdef CONFIG_TRY_BETTER_MEMCPY
292 static inline void copy_words(void *dest, const void *src, size_t sz)
295 const u32 *__src = src;
296 size_t __sz = sz >> 2;
298 DPAA_BUG_ON((unsigned long)dest & 0x3);
299 DPAA_BUG_ON((unsigned long)src & 0x3);
300 DPAA_BUG_ON(sz & 0x3);
302 *(__dest++) = *(__src++);
305 static inline void copy_shorts(void *dest, const void *src, size_t sz)
308 const u16 *__src = src;
309 size_t __sz = sz >> 1;
311 DPAA_BUG_ON((unsigned long)dest & 0x1);
312 DPAA_BUG_ON((unsigned long)src & 0x1);
313 DPAA_BUG_ON(sz & 0x1);
315 *(__dest++) = *(__src++);
318 static inline void copy_bytes(void *dest, const void *src, size_t sz)
321 const u8 *__src = src;
324 *(__dest++) = *(__src++);
327 #define copy_words memcpy
328 #define copy_shorts memcpy
329 #define copy_bytes memcpy
332 /* Allocator stuff */
333 #define kmalloc(sz, t) malloc(sz)
334 #define vmalloc(sz) malloc(sz)
335 #define kfree(p) { if (p) free(p); }
336 static inline void *kzalloc(size_t sz, gfp_t __foo __rte_unused)
338 void *ptr = malloc(sz);
345 static inline unsigned long get_zeroed_page(gfp_t __foo __rte_unused)
349 if (posix_memalign(&p, 4096, 4096))
352 return (unsigned long)p;
356 #define spinlock_t rte_spinlock_t
357 #define __SPIN_LOCK_UNLOCKED(x) RTE_SPINLOCK_INITIALIZER
358 #define DEFINE_SPINLOCK(x) spinlock_t x = __SPIN_LOCK_UNLOCKED(x)
359 #define spin_lock_init(x) rte_spinlock_init(x)
360 #define spin_lock_destroy(x)
361 #define spin_lock(x) rte_spinlock_lock(x)
362 #define spin_unlock(x) rte_spinlock_unlock(x)
363 #define spin_lock_irq(x) spin_lock(x)
364 #define spin_unlock_irq(x) spin_unlock(x)
365 #define spin_lock_irqsave(x, f) spin_lock_irq(x)
366 #define spin_unlock_irqrestore(x, f) spin_unlock_irq(x)
368 #define atomic_t rte_atomic32_t
369 #define atomic_read(v) rte_atomic32_read(v)
370 #define atomic_set(v, i) rte_atomic32_set(v, i)
372 #define atomic_inc(v) rte_atomic32_add(v, 1)
373 #define atomic_dec(v) rte_atomic32_sub(v, 1)
375 #define atomic_inc_and_test(v) rte_atomic32_inc_and_test(v)
376 #define atomic_dec_and_test(v) rte_atomic32_dec_and_test(v)
378 #define atomic_inc_return(v) rte_atomic32_add_return(v, 1)
379 #define atomic_dec_return(v) rte_atomic32_sub_return(v, 1)
380 #define atomic_sub_and_test(i, v) (rte_atomic32_sub_return(v, i) == 0)
382 #include <dpaa_list.h>
383 #include <dpaa_bits.h>
385 #endif /* __COMPAT_H */