1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 /* Copyright (C) 2014-2017 aQuantia Corporation. */
4 /* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for
5 * Atlantic hardware abstraction layer.
9 #include "../atl_hw_regs.h"
11 #include "../atl_types.h"
12 #include "hw_atl_utils.h"
13 #include "hw_atl_llh.h"
15 #define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364
16 #define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360
17 #define HW_ATL_FW2X_MPI_RPC_ADDR 0x334
19 #define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368
20 #define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C
21 #define HW_ATL_FW2X_MPI_LED_ADDR 0x31c
23 #define HW_ATL_FW2X_MPI_STATE_ADDR 0x370
24 #define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374
26 #define HW_ATL_FW2X_CAP_SLEEP_PROXY BIT(CAPS_HI_SLEEP_PROXY)
27 #define HW_ATL_FW2X_CAP_WOL BIT(CAPS_HI_WOL)
29 #define HW_ATL_FW2X_CAP_EEE_1G_MASK BIT(CAPS_HI_1000BASET_FD_EEE)
30 #define HW_ATL_FW2X_CAP_EEE_2G5_MASK BIT(CAPS_HI_2P5GBASET_FD_EEE)
31 #define HW_ATL_FW2X_CAP_EEE_5G_MASK BIT(CAPS_HI_5GBASET_FD_EEE)
32 #define HW_ATL_FW2X_CAP_EEE_10G_MASK BIT(CAPS_HI_10GBASET_FD_EEE)
34 #define HAL_ATLANTIC_WOL_FILTERS_COUNT 8
35 #define HAL_ATLANTIC_UTILS_FW2X_MSG_WOL 0x0E
37 #define HW_ATL_FW_FEATURE_LED 0x03010026
39 struct fw2x_msg_wol_pattern {
42 } __attribute__((__packed__));
47 u8 magic_packet_enabled;
49 struct fw2x_msg_wol_pattern filter[HAL_ATLANTIC_WOL_FILTERS_COUNT];
54 u32 link_down_timeout;
55 } __attribute__((__packed__));
57 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed);
58 static int aq_fw2x_set_state(struct aq_hw_s *self,
59 enum hal_atl_utils_fw_state_e state);
61 static int aq_fw2x_init(struct aq_hw_s *self)
64 struct hw_aq_atl_utils_mbox mbox;
66 /* check 10 times by 1ms */
67 AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
68 aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR)),
70 AQ_HW_WAIT_FOR(0U != (self->rpc_addr =
71 aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR)),
75 hw_atl_utils_mpi_read_stats(self, &mbox);
77 self->caps_lo = mbox.info.caps_lo;
82 static int aq_fw2x_deinit(struct aq_hw_s *self)
84 int err = aq_fw2x_set_link_speed(self, 0);
87 err = aq_fw2x_set_state(self, MPI_DEINIT);
92 static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed)
94 enum hw_atl_fw2x_rate rate = 0;
96 if (speed & AQ_NIC_RATE_10G)
97 rate |= FW2X_RATE_10G;
99 if (speed & AQ_NIC_RATE_5G)
100 rate |= FW2X_RATE_5G;
102 if (speed & AQ_NIC_RATE_5G5R)
103 rate |= FW2X_RATE_5G;
105 if (speed & AQ_NIC_RATE_2G5)
106 rate |= FW2X_RATE_2G5;
108 if (speed & AQ_NIC_RATE_1G)
109 rate |= FW2X_RATE_1G;
111 if (speed & AQ_NIC_RATE_100M)
112 rate |= FW2X_RATE_100M;
117 static u32 fw2x_to_eee_mask(u32 speed)
121 if (speed & HW_ATL_FW2X_CAP_EEE_10G_MASK)
122 rate |= AQ_NIC_RATE_EEE_10G;
124 if (speed & HW_ATL_FW2X_CAP_EEE_5G_MASK)
125 rate |= AQ_NIC_RATE_EEE_5G;
127 if (speed & HW_ATL_FW2X_CAP_EEE_2G5_MASK)
128 rate |= AQ_NIC_RATE_EEE_2G5;
130 if (speed & HW_ATL_FW2X_CAP_EEE_1G_MASK)
131 rate |= AQ_NIC_RATE_EEE_1G;
136 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed)
138 u32 val = link_speed_mask_2fw2x_ratemask(speed);
140 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val);
145 static void aq_fw2x_set_mpi_flow_control(struct aq_hw_s *self, u32 *mpi_state)
147 if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_RX)
148 *mpi_state |= BIT(CAPS_HI_PAUSE);
150 *mpi_state &= ~BIT(CAPS_HI_PAUSE);
152 if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_TX)
153 *mpi_state |= BIT(CAPS_HI_ASYMMETRIC_PAUSE);
155 *mpi_state &= ~BIT(CAPS_HI_ASYMMETRIC_PAUSE);
158 static int aq_fw2x_set_state(struct aq_hw_s *self,
159 enum hal_atl_utils_fw_state_e state)
161 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
165 mpi_state &= ~BIT(CAPS_HI_LINK_DROP);
166 aq_fw2x_set_mpi_flow_control(self, &mpi_state);
169 mpi_state |= BIT(CAPS_HI_LINK_DROP);
176 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
180 static int aq_fw2x_update_link_status(struct aq_hw_s *self)
182 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
183 u32 speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G |
184 FW2X_RATE_2G5 | FW2X_RATE_5G | FW2X_RATE_10G);
185 struct aq_hw_link_status_s *link_status = &self->aq_link_status;
188 if (speed & FW2X_RATE_10G)
189 link_status->mbps = 10000;
190 else if (speed & FW2X_RATE_5G)
191 link_status->mbps = 5000;
192 else if (speed & FW2X_RATE_2G5)
193 link_status->mbps = 2500;
194 else if (speed & FW2X_RATE_1G)
195 link_status->mbps = 1000;
196 else if (speed & FW2X_RATE_100M)
197 link_status->mbps = 100;
199 link_status->mbps = 10000;
201 link_status->mbps = 0;
208 int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac)
213 u32 mac_addr[2] = { 0 };
214 u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR);
216 if (efuse_addr != 0) {
217 err = hw_atl_utils_fw_downld_dwords(self,
218 efuse_addr + (40U * 4U),
220 ARRAY_SIZE(mac_addr));
223 mac_addr[0] = rte_constant_bswap32(mac_addr[0]);
224 mac_addr[1] = rte_constant_bswap32(mac_addr[1]);
227 ether_addr_copy((struct ether_addr *)mac_addr,
228 (struct ether_addr *)mac);
230 if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) {
231 unsigned int rnd = (uint32_t)rte_rand();
233 //get_random_bytes(&rnd, sizeof(unsigned int));
240 mac[5] = (u8)(0xFFU & l);
242 mac[4] = (u8)(0xFFU & l);
244 mac[3] = (u8)(0xFFU & l);
246 mac[2] = (u8)(0xFFU & l);
247 mac[1] = (u8)(0xFFU & h);
249 mac[0] = (u8)(0xFFU & h);
254 static int aq_fw2x_update_stats(struct aq_hw_s *self)
257 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
258 u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);
260 /* Toggle statistics bit for FW to update */
261 mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);
262 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
264 /* Wait FW to report back */
265 AQ_HW_WAIT_FOR(orig_stats_val !=
266 (aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
267 BIT(CAPS_HI_STATISTICS)),
272 return hw_atl_utils_update_stats(self);
275 static int aq_fw2x_get_temp(struct aq_hw_s *self, int *temp)
278 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
279 u32 temp_val = mpi_opts & BIT(CAPS_HI_TEMPERATURE);
282 /* Toggle statistics bit for FW to 0x36C.18 (CAPS_HI_TEMPERATURE) */
283 mpi_opts = mpi_opts ^ BIT(CAPS_HI_TEMPERATURE);
284 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
286 /* Wait FW to report back */
287 AQ_HW_WAIT_FOR(temp_val !=
288 (aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
289 BIT(CAPS_HI_TEMPERATURE)), 1U, 10000U);
290 err = hw_atl_utils_fw_downld_dwords(self,
292 offsetof(struct hw_aq_atl_utils_mbox, info) +
293 offsetof(struct hw_aq_info, phy_temperature),
295 sizeof(temp_res) / sizeof(u32));
300 *temp = temp_res * 100 / 256;
304 static int aq_fw2x_get_cable_len(struct aq_hw_s *self, int *cable_len)
309 err = hw_atl_utils_fw_downld_dwords(self,
311 offsetof(struct hw_aq_atl_utils_mbox, info) +
312 offsetof(struct hw_aq_info, phy_temperature),
314 sizeof(cable_len_res) / sizeof(u32));
319 *cable_len = (cable_len_res >> 16) & 0xFF;
327 static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *self, u8 *mac)
330 struct hw_aq_atl_utils_fw_rpc *rpc = NULL;
331 struct offload_info *cfg = NULL;
332 unsigned int rpc_size = 0U;
335 rpc_size = sizeof(rpc->msg_id) + sizeof(*cfg);
337 err = hw_atl_utils_fw_rpc_wait(self, &rpc);
341 memset(rpc, 0, rpc_size);
342 cfg = (struct offload_info *)(&rpc->msg_id + 1);
344 memcpy(cfg->mac_addr, mac, ETH_ALEN);
345 cfg->len = sizeof(*cfg);
347 /* Clear bit 0x36C.23 */
348 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
349 mpi_opts &= ~HW_ATL_FW2X_CAP_SLEEP_PROXY;
351 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
353 err = hw_atl_utils_fw_rpc_call(self, rpc_size);
357 /* Set bit 0x36C.23 */
358 mpi_opts |= HW_ATL_FW2X_CAP_SLEEP_PROXY;
359 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
361 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
362 HW_ATL_FW2X_CAP_SLEEP_PROXY), 1U, 10000U);
367 static int aq_fw2x_set_wol_params(struct aq_hw_s *self, u8 *mac)
370 struct fw2x_msg_wol *msg = NULL;
373 struct hw_aq_atl_utils_fw_rpc *rpc = NULL;
375 err = hw_atl_utils_fw_rpc_wait(self, &rpc);
379 msg = (struct fw2x_msg_wol *)rpc;
381 msg->msg_id = HAL_ATLANTIC_UTILS_FW2X_MSG_WOL;
382 msg->magic_packet_enabled = true;
383 memcpy(msg->hw_addr, mac, ETH_ALEN);
385 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
386 mpi_opts &= ~(HW_ATL_FW2X_CAP_SLEEP_PROXY | HW_ATL_FW2X_CAP_WOL);
388 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
390 err = hw_atl_utils_fw_rpc_call(self, sizeof(*msg));
394 /* Set bit 0x36C.24 */
395 mpi_opts |= HW_ATL_FW2X_CAP_WOL;
396 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
398 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
399 HW_ATL_FW2X_CAP_WOL), 1U, 10000U);
404 static int aq_fw2x_set_power(struct aq_hw_s *self,
405 unsigned int power_state __rte_unused,
410 if (self->aq_nic_cfg->wol & AQ_NIC_WOL_ENABLED) {
411 err = aq_fw2x_set_sleep_proxy(self, mac);
414 err = aq_fw2x_set_wol_params(self, mac);
422 static int aq_fw2x_set_eee_rate(struct aq_hw_s *self, u32 speed)
424 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
425 mpi_opts &= ~(HW_ATL_FW2X_CAP_EEE_1G_MASK |
426 HW_ATL_FW2X_CAP_EEE_2G5_MASK | HW_ATL_FW2X_CAP_EEE_5G_MASK |
427 HW_ATL_FW2X_CAP_EEE_10G_MASK);
429 if (speed & AQ_NIC_RATE_EEE_10G)
430 mpi_opts |= HW_ATL_FW2X_CAP_EEE_10G_MASK;
432 if (speed & AQ_NIC_RATE_EEE_5G)
433 mpi_opts |= HW_ATL_FW2X_CAP_EEE_5G_MASK;
435 if (speed & AQ_NIC_RATE_EEE_2G5)
436 mpi_opts |= HW_ATL_FW2X_CAP_EEE_2G5_MASK;
438 if (speed & AQ_NIC_RATE_EEE_1G)
439 mpi_opts |= HW_ATL_FW2X_CAP_EEE_1G_MASK;
441 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
446 static int aq_fw2x_get_eee_rate(struct aq_hw_s *self, u32 *rate,
447 u32 *supported_rates)
453 err = hw_atl_utils_fw_downld_dwords(self,
455 offsetof(struct hw_aq_atl_utils_mbox, info) +
456 offsetof(struct hw_aq_info, caps_hi),
458 sizeof(caps_hi) / sizeof(u32));
463 *supported_rates = fw2x_to_eee_mask(caps_hi);
465 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR);
466 *rate = fw2x_to_eee_mask(mpi_state);
471 static int aq_fw2x_get_flow_control(struct aq_hw_s *self, u32 *fc)
473 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
475 *fc = ((mpi_state & BIT(CAPS_HI_PAUSE)) ? AQ_NIC_FC_RX : 0) |
476 ((mpi_state & BIT(CAPS_HI_ASYMMETRIC_PAUSE)) ? AQ_NIC_FC_TX : 0);
481 static int aq_fw2x_set_flow_control(struct aq_hw_s *self)
483 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
485 aq_fw2x_set_mpi_flow_control(self, &mpi_state);
487 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
492 static int aq_fw2x_led_control(struct aq_hw_s *self, u32 mode)
494 if (self->fw_ver_actual < HW_ATL_FW_FEATURE_LED)
497 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_LED_ADDR, mode);
501 static int aq_fw2x_get_eeprom(struct aq_hw_s *self, int dev_addr,
502 u32 *data, u32 len, u32 offset)
504 u32 bytes_remains = len % sizeof(u32);
505 u32 num_dwords = len / sizeof(u32);
506 struct smbus_request request;
511 if ((self->caps_lo & BIT(CAPS_LO_SMBUS_READ)) == 0)
515 request.device_id = dev_addr;
516 request.address = offset;
517 request.length = len;
519 /* Write SMBUS request to cfg memory */
520 err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr,
521 (u32 *)(void *)&request,
522 sizeof(request) / sizeof(u32));
527 /* Toggle 0x368.CAPS_LO_SMBUS_READ bit */
528 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR);
529 mpi_opts ^= BIT(CAPS_LO_SMBUS_READ);
531 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, mpi_opts);
533 /* Wait until REQUEST_BIT matched in 0x370 */
535 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR) &
536 BIT(CAPS_LO_SMBUS_READ)) == (mpi_opts & BIT(CAPS_LO_SMBUS_READ)),
542 err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr + sizeof(u32),
544 sizeof(result) / sizeof(u32));
553 err = hw_atl_utils_fw_downld_dwords(self,
554 self->rpc_addr + sizeof(u32) * 2,
565 err = hw_atl_utils_fw_downld_dwords(self,
566 self->rpc_addr + (sizeof(u32) * 2) +
567 (num_dwords * sizeof(u32)),
574 rte_memcpy((u8 *)data + len - bytes_remains,
575 &val, bytes_remains);
582 static int aq_fw2x_set_eeprom(struct aq_hw_s *self, int dev_addr,
583 u32 *data, u32 len, u32 offset)
585 struct smbus_request request;
586 u32 mpi_opts, result = 0;
589 if ((self->caps_lo & BIT(CAPS_LO_SMBUS_WRITE)) == 0)
593 request.device_id = dev_addr;
594 request.address = offset;
595 request.length = len;
597 /* Write SMBUS request to cfg memory */
598 err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr,
599 (u32 *)(void *)&request,
600 sizeof(request) / sizeof(u32));
605 /* Write SMBUS data to cfg memory */
606 u32 num_dwords = len / sizeof(u32);
607 u32 bytes_remains = len % sizeof(u32);
610 err = hw_atl_utils_fw_upload_dwords(self,
611 self->rpc_addr + sizeof(request),
622 rte_memcpy(&val, (u8 *)data + (sizeof(u32) * num_dwords),
625 err = hw_atl_utils_fw_upload_dwords(self,
626 self->rpc_addr + sizeof(request) +
627 (num_dwords * sizeof(u32)),
635 /* Toggle 0x368.CAPS_LO_SMBUS_WRITE bit */
636 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR);
637 mpi_opts ^= BIT(CAPS_LO_SMBUS_WRITE);
639 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, mpi_opts);
641 /* Wait until REQUEST_BIT matched in 0x370 */
642 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR) &
643 BIT(CAPS_LO_SMBUS_WRITE)) == (mpi_opts & BIT(CAPS_LO_SMBUS_WRITE)),
649 /* Read status of write operation */
650 err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr + sizeof(u32),
652 sizeof(result) / sizeof(u32));
663 const struct aq_fw_ops aq_fw_2x_ops = {
664 .init = aq_fw2x_init,
665 .deinit = aq_fw2x_deinit,
667 .get_mac_permanent = aq_fw2x_get_mac_permanent,
668 .set_link_speed = aq_fw2x_set_link_speed,
669 .set_state = aq_fw2x_set_state,
670 .update_link_status = aq_fw2x_update_link_status,
671 .update_stats = aq_fw2x_update_stats,
672 .set_power = aq_fw2x_set_power,
673 .get_temp = aq_fw2x_get_temp,
674 .get_cable_len = aq_fw2x_get_cable_len,
675 .set_eee_rate = aq_fw2x_set_eee_rate,
676 .get_eee_rate = aq_fw2x_get_eee_rate,
677 .get_flow_control = aq_fw2x_get_flow_control,
678 .set_flow_control = aq_fw2x_set_flow_control,
679 .led_control = aq_fw2x_led_control,
680 .get_eeprom = aq_fw2x_get_eeprom,
681 .set_eeprom = aq_fw2x_set_eeprom,