2 * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015 QLogic Corporation.
10 * All rights reserved.
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
18 #include "ecore_mfw_req.h"
19 #include "ecore_fw_defs.h"
20 #include "ecore_hsi.h"
21 #include "ecore_reg.h"
23 static elink_status_t elink_link_reset(struct elink_params *params,
24 struct elink_vars *vars,
25 uint8_t reset_ext_phy);
26 static elink_status_t elink_check_half_open_conn(struct elink_params *params,
27 struct elink_vars *vars,
29 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
30 struct elink_params *params);
32 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
33 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
34 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
35 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
36 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
38 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
39 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
40 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
41 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
42 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
43 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
44 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
45 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
46 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
47 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
48 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
49 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
50 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
51 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
52 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
53 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
54 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
56 #define MDIO_REG_BANK_RX0 0x80b0
57 #define MDIO_RX0_RX_STATUS 0x10
58 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
59 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
60 #define MDIO_RX0_RX_EQ_BOOST 0x1c
61 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
62 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
64 #define MDIO_REG_BANK_RX1 0x80c0
65 #define MDIO_RX1_RX_EQ_BOOST 0x1c
66 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
67 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
69 #define MDIO_REG_BANK_RX2 0x80d0
70 #define MDIO_RX2_RX_EQ_BOOST 0x1c
71 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
72 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
74 #define MDIO_REG_BANK_RX3 0x80e0
75 #define MDIO_RX3_RX_EQ_BOOST 0x1c
76 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
77 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
79 #define MDIO_REG_BANK_RX_ALL 0x80f0
80 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
81 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
82 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
84 #define MDIO_REG_BANK_TX0 0x8060
85 #define MDIO_TX0_TX_DRIVER 0x17
86 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
87 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
88 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
89 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
90 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
91 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
92 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
93 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
94 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
96 #define MDIO_REG_BANK_TX1 0x8070
97 #define MDIO_TX1_TX_DRIVER 0x17
98 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
99 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
100 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
101 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
102 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
103 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
104 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
105 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
106 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
108 #define MDIO_REG_BANK_TX2 0x8080
109 #define MDIO_TX2_TX_DRIVER 0x17
110 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
111 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
112 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
113 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
114 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
115 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
116 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
117 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
118 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
120 #define MDIO_REG_BANK_TX3 0x8090
121 #define MDIO_TX3_TX_DRIVER 0x17
122 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
123 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
124 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
125 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
126 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
127 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
128 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
129 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
130 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
132 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
133 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
135 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
136 #define MDIO_BLOCK1_LANE_CTRL0 0x15
137 #define MDIO_BLOCK1_LANE_CTRL1 0x16
138 #define MDIO_BLOCK1_LANE_CTRL2 0x17
139 #define MDIO_BLOCK1_LANE_PRBS 0x19
141 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
142 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
143 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
144 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
145 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
146 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
147 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
148 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
149 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
150 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
152 #define MDIO_REG_BANK_GP_STATUS 0x8120
153 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
154 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
155 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
156 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
157 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
158 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
159 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
160 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
161 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
162 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
163 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
164 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
165 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
166 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
167 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
168 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
169 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
170 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
171 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
172 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
173 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
174 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
175 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
176 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
177 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
178 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
179 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
180 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
181 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
182 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
184 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
185 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
186 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
187 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
188 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
189 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
190 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
192 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
193 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
194 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
195 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
196 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
197 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
198 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
199 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
200 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
201 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
202 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
203 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
204 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
205 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
206 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
207 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
208 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
209 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
210 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
211 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
212 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
213 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
214 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
215 #define MDIO_SERDES_DIGITAL_MISC1 0x18
216 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
217 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
218 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
219 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
220 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
221 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
222 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
223 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
224 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
225 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
226 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
227 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
228 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
229 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
230 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
231 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
232 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
233 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
235 #define MDIO_REG_BANK_OVER_1G 0x8320
236 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
237 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
238 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
239 #define MDIO_OVER_1G_UP1 0x19
240 #define MDIO_OVER_1G_UP1_2_5G 0x0001
241 #define MDIO_OVER_1G_UP1_5G 0x0002
242 #define MDIO_OVER_1G_UP1_6G 0x0004
243 #define MDIO_OVER_1G_UP1_10G 0x0010
244 #define MDIO_OVER_1G_UP1_10GH 0x0008
245 #define MDIO_OVER_1G_UP1_12G 0x0020
246 #define MDIO_OVER_1G_UP1_12_5G 0x0040
247 #define MDIO_OVER_1G_UP1_13G 0x0080
248 #define MDIO_OVER_1G_UP1_15G 0x0100
249 #define MDIO_OVER_1G_UP1_16G 0x0200
250 #define MDIO_OVER_1G_UP2 0x1A
251 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
252 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
253 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
254 #define MDIO_OVER_1G_UP3 0x1B
255 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
256 #define MDIO_OVER_1G_LP_UP1 0x1C
257 #define MDIO_OVER_1G_LP_UP2 0x1D
258 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
259 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
260 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
261 #define MDIO_OVER_1G_LP_UP3 0x1E
263 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
264 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
265 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
266 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
268 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
269 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
270 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
271 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
273 #define MDIO_REG_BANK_CL73_USERB0 0x8370
274 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
275 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
276 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
277 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
278 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
279 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
280 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
281 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
282 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
283 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
284 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
286 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
287 #define MDIO_AER_BLOCK_AER_REG 0x1E
289 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
290 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
291 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
292 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
293 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
294 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
295 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
296 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
297 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
298 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
299 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
300 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
301 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
302 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
303 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
304 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
305 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
306 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
307 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
308 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
309 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
310 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
311 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
312 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
313 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
314 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
315 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
316 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
317 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
318 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
319 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
320 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
321 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
322 Theotherbitsarereservedandshouldbezero*/
323 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
325 #define MDIO_PMA_DEVAD 0x1
327 #define MDIO_PMA_REG_CTRL 0x0
328 #define MDIO_PMA_REG_STATUS 0x1
329 #define MDIO_PMA_REG_10G_CTRL2 0x7
330 #define MDIO_PMA_REG_TX_DISABLE 0x0009
331 #define MDIO_PMA_REG_RX_SD 0xa
333 #define MDIO_PMA_REG_BNX2X_CTRL 0x0096
334 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
335 #define MDIO_PMA_LASI_RXCTRL 0x9000
336 #define MDIO_PMA_LASI_TXCTRL 0x9001
337 #define MDIO_PMA_LASI_CTRL 0x9002
338 #define MDIO_PMA_LASI_RXSTAT 0x9003
339 #define MDIO_PMA_LASI_TXSTAT 0x9004
340 #define MDIO_PMA_LASI_STAT 0x9005
341 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
342 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
343 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
344 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
345 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
346 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
347 #define MDIO_PMA_REG_GEN_CTRL 0xca10
348 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
349 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
350 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
351 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
352 #define MDIO_PMA_REG_ROM_VER1 0xca19
353 #define MDIO_PMA_REG_ROM_VER2 0xca1a
354 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
355 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
356 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
357 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
358 #define MDIO_PMA_REG_LRM_MODE 0xca3f
359 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
360 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
362 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
363 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
364 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
365 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
366 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
367 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
368 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
369 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
370 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
371 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
372 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
373 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
375 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
376 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
377 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
378 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
379 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
380 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
381 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
382 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
383 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
384 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
386 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
387 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
388 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
389 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
390 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
392 #define MDIO_PMA_REG_7101_RESET 0xc000
393 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
394 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
395 #define MDIO_PMA_REG_7101_VER1 0xc026
396 #define MDIO_PMA_REG_7101_VER2 0xc027
398 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
399 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
400 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
401 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
402 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
403 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
404 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
405 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
406 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
407 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
409 #define MDIO_WIS_DEVAD 0x2
411 #define MDIO_WIS_REG_LASI_CNTL 0x9002
412 #define MDIO_WIS_REG_LASI_STATUS 0x9005
414 #define MDIO_PCS_DEVAD 0x3
415 #define MDIO_PCS_REG_STATUS 0x0020
416 #define MDIO_PCS_REG_LASI_STATUS 0x9005
417 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
418 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
419 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
420 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
421 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
422 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
423 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
424 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
425 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
427 #define MDIO_XS_DEVAD 0x4
428 #define MDIO_XS_REG_STATUS 0x0001
429 #define MDIO_XS_PLL_SEQUENCER 0x8000
430 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
432 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
433 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
434 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
435 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
436 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
438 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
440 #define MDIO_AN_DEVAD 0x7
442 #define MDIO_AN_REG_CTRL 0x0000
443 #define MDIO_AN_REG_STATUS 0x0001
444 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
445 #define MDIO_AN_REG_ADV_PAUSE 0x0010
446 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
447 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
448 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
449 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
450 #define MDIO_AN_REG_ADV 0x0011
451 #define MDIO_AN_REG_ADV2 0x0012
452 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
453 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
454 #define MDIO_AN_REG_MASTER_STATUS 0x0021
455 #define MDIO_AN_REG_EEE_ADV 0x003c
456 #define MDIO_AN_REG_LP_EEE_ADV 0x003d
458 #define MDIO_AN_REG_LINK_STATUS 0x8304
459 #define MDIO_AN_REG_CL37_CL73 0x8370
460 #define MDIO_AN_REG_CL37_AN 0xffe0
461 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
462 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
463 #define MDIO_AN_REG_1000T_STATUS 0xffea
465 #define MDIO_AN_REG_8073_2_5G 0x8329
466 #define MDIO_AN_REG_8073_BAM 0x8350
468 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
469 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
470 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
471 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
472 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
473 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
474 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
475 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
476 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
477 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
478 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
479 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
480 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
482 /* BNX2X84823 only */
483 #define MDIO_CTL_DEVAD 0x1e
484 #define MDIO_CTL_REG_84823_MEDIA 0x401a
485 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
486 /* These pins configure the BNX2X84823 interface to MAC after reset. */
487 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
488 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
489 /* These pins configure the BNX2X84823 interface to Line after reset. */
490 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
491 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
492 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
493 /* When this pin is active high during reset, 10GBASE-T core is power
494 * down, When it is active low the 10GBASE-T is power up
496 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
497 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
498 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
499 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
500 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
501 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
502 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
503 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
504 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
505 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
506 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
507 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
509 /* BNX2X84833 only */
510 #define MDIO_84833_TOP_CFG_FW_REV 0x400f
511 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
512 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
513 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
514 #define MDIO_84833_SUPER_ISOLATE 0x8000
515 /* These are mailbox register set used by 84833. */
516 #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
517 #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
518 #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
519 #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
520 #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
521 #define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
522 #define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
523 #define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
524 #define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
525 #define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
526 #define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
527 #define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
528 #define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
529 #define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
530 #define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
531 #define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
532 #define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
533 #define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
535 /* Mailbox command set used by 84833. */
536 #define PHY84833_CMD_SET_PAIR_SWAP 0x8001
537 #define PHY84833_CMD_GET_EEE_MODE 0x8008
538 #define PHY84833_CMD_SET_EEE_MODE 0x8009
539 #define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
540 /* Mailbox status set used by 84833. */
541 #define PHY84833_STATUS_CMD_RECEIVED 0x0001
542 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
543 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
544 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
545 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
546 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
547 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
548 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
549 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
551 /* Warpcore clause 45 addressing */
552 #define MDIO_WC_DEVAD 0x3
553 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
554 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
555 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
556 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
557 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
558 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
559 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
560 #define MDIO_WC_REG_PCS_STATUS2 0x0021
561 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
562 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
563 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
564 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
565 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
566 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
567 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
568 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018
569 #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a
570 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
571 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
572 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
573 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
574 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
575 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
576 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
577 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
578 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
579 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
580 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
581 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
582 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
583 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
584 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
585 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
586 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
587 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
588 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
589 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
590 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
591 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
592 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
593 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
594 #define MDIO_WC_REG_XGXS_STATUS4 0x813c
595 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
596 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
597 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
598 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
599 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
600 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
601 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
602 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
603 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
604 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
605 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
606 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
607 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
608 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
609 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
610 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
611 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
612 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
613 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
614 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
615 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
616 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
617 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
618 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
619 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
620 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
621 #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e
622 #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7)
623 #define MDIO_WC_REG_DSC_SMC 0x8213
624 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
625 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
626 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
627 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
628 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
629 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
630 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
631 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
632 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
633 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
634 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
635 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
636 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
637 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
638 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
639 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
640 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
641 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
642 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
643 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
644 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
645 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
646 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
647 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
648 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
649 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
650 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
651 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
652 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
653 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
654 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
655 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
656 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
657 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
658 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
659 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
660 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
661 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
662 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
663 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
664 #define MDIO_WC_REG_RX66_SCW0 0x83c2
665 #define MDIO_WC_REG_RX66_SCW1 0x83c3
666 #define MDIO_WC_REG_RX66_SCW2 0x83c4
667 #define MDIO_WC_REG_RX66_SCW3 0x83c5
668 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
669 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
670 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
671 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
672 #define MDIO_WC_REG_FX100_CTRL1 0x8400
673 #define MDIO_WC_REG_FX100_CTRL3 0x8402
674 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
675 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
676 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
677 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
678 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
679 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
680 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
681 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
682 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
683 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
684 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
685 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
686 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
687 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
689 #define MDIO_WC_REG_AERBLK_AER 0xffde
690 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
691 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
693 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
694 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
695 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
697 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
699 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
702 #define MDIO_REG_GPHY_MII_STATUS 0x1
703 #define MDIO_REG_GPHY_PHYID_LSB 0x3
704 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
705 #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
706 #define MDIO_REG_GPHY_CL45_REG_READ 0xc000
707 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe
708 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
709 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
710 #define MDIO_REG_GPHY_EXP_ACCESS 0x17
711 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
712 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
713 #define MDIO_REG_GPHY_AUX_STATUS 0x19
714 #define MDIO_REG_INTR_STATUS 0x1a
715 #define MDIO_REG_INTR_MASK 0x1b
716 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
717 #define MDIO_REG_GPHY_SHADOW 0x1c
718 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
719 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
720 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
721 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
722 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
724 typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,
725 struct elink_params *
732 /********************************************************/
733 #define ELINK_ETH_HLEN 14
734 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
735 #define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8)
736 #define ELINK_ETH_MIN_PACKET_SIZE 60
737 #define ELINK_ETH_MAX_PACKET_SIZE 1500
738 #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600
739 #define ELINK_MDIO_ACCESS_TIMEOUT 1000
740 #define WC_LANE_MAX 4
741 #define I2C_SWITCH_WIDTH 2
744 #define I2C_WA_RETRY_CNT 3
745 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
746 #define MCPR_IMC_COMMAND_READ_OP 1
747 #define MCPR_IMC_COMMAND_WRITE_OP 2
749 /* LED Blink rate that will achieve ~15.9Hz */
750 #define LED_BLINK_RATE_VAL_E3 354
751 #define LED_BLINK_RATE_VAL_E1X_E2 480
752 /***********************************************************/
753 /* Shortcut definitions */
754 /***********************************************************/
756 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0
758 #define ELINK_NIG_STATUS_EMAC0_MI_INT \
759 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
760 #define ELINK_NIG_STATUS_XGXS0_LINK10G \
761 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
762 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \
763 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
764 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
765 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
766 #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \
767 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
768 #define ELINK_NIG_MASK_MI_INT \
769 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
770 #define ELINK_NIG_MASK_XGXS0_LINK10G \
771 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
772 #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \
773 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
774 #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \
775 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
777 #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \
778 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
779 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
781 #define ELINK_XGXS_RESET_BITS \
782 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
783 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
784 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
785 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
786 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
788 #define ELINK_SERDES_RESET_BITS \
789 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
790 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
791 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
792 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
794 #define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
795 #define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
796 #define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
797 #define ELINK_AUTONEG_PARALLEL \
798 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
799 #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \
800 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
801 #define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
803 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
804 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
805 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
806 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
807 #define ELINK_GP_STATUS_SPEED_MASK \
808 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
809 #define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
810 #define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
811 #define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
812 #define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
813 #define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
814 #define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
815 #define ELINK_GP_STATUS_10G_HIG \
816 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
817 #define ELINK_GP_STATUS_10G_CX4 \
818 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
819 #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
820 #define ELINK_GP_STATUS_10G_KX4 \
821 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
822 #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
823 #define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
824 #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
825 #define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
826 #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
827 #define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
828 #define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
829 #define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
830 #define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
831 #define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
832 #define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
833 #define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
834 #define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
835 #define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
836 #define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
837 #define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
838 #define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
839 #define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
840 #define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
841 #define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
843 #define ELINK_LINK_UPDATE_MASK \
844 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
845 LINK_STATUS_LINK_UP | \
846 LINK_STATUS_PHYSICAL_LINK_FLAG | \
847 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
848 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
849 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
850 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
851 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
852 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
854 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2
855 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7
856 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
857 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
859 #define ELINK_SFP_EEPROM_COMP_CODE_ADDR 0x3
860 #define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
861 #define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
862 #define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
864 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8
865 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
866 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
868 #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40
869 #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
870 #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2
872 #define ELINK_EDC_MODE_LINEAR 0x0022
873 #define ELINK_EDC_MODE_LIMITING 0x0044
874 #define ELINK_EDC_MODE_PASSIVE_DAC 0x0055
875 #define ELINK_EDC_MODE_ACTIVE_DAC 0x0066
878 #define DCBX_INVALID_COS (0xFF)
880 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
881 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
882 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
883 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
884 #define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000)
886 #define ELINK_MAX_PACKET_SIZE (9700)
887 #define MAX_KR_LINK_RETRY 4
889 /**********************************************************/
891 /**********************************************************/
893 #define CL22_WR_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
894 elink_cl45_write(_sc, _phy, \
895 (_phy)->def_md_devad, \
896 (_bank + (_addr & 0xf)), \
899 #define CL22_RD_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
900 elink_cl45_read(_sc, _phy, \
901 (_phy)->def_md_devad, \
902 (_bank + (_addr & 0xf)), \
905 static uint32_t elink_bits_en(struct bnx2x_softc *sc, uint32_t reg, uint32_t bits)
907 uint32_t val = REG_RD(sc, reg);
910 REG_WR(sc, reg, val);
914 static uint32_t elink_bits_dis(struct bnx2x_softc *sc, uint32_t reg,
917 uint32_t val = REG_RD(sc, reg);
920 REG_WR(sc, reg, val);
925 * elink_check_lfa - This function checks if link reinitialization is required,
926 * or link flap can be avoided.
928 * @params: link parameters
929 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
932 static int elink_check_lfa(struct elink_params *params)
934 uint32_t link_status, cfg_idx, lfa_mask, cfg_size;
935 uint32_t cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
936 uint32_t saved_val, req_val, eee_status;
937 struct bnx2x_softc *sc = params->sc;
940 REG_RD(sc, params->lfa_base +
941 offsetof(struct shmem_lfa, additional_config));
943 /* NOTE: must be first condition checked -
944 * to verify DCC bit is cleared in any case!
946 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
947 PMD_DRV_LOG(DEBUG, "No LFA due to DCC flap after clp exit");
948 REG_WR(sc, params->lfa_base +
949 offsetof(struct shmem_lfa, additional_config),
950 additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
951 return LFA_DCC_LFA_DISABLED;
954 /* Verify that link is up */
955 link_status = REG_RD(sc, params->shmem_base +
956 offsetof(struct shmem_region,
957 port_mb[params->port].link_status));
958 if (!(link_status & LINK_STATUS_LINK_UP))
959 return LFA_LINK_DOWN;
961 /* if loaded after BOOT from SAN, don't flap the link in any case and
962 * rely on link set by preboot driver
964 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN)
967 /* Verify that loopback mode is not set */
968 if (params->loopback_mode)
969 return LFA_LOOPBACK_ENABLED;
971 /* Verify that MFW supports LFA */
972 if (!params->lfa_base)
973 return LFA_MFW_IS_TOO_OLD;
975 if (params->num_phys == 3) {
977 lfa_mask = 0xffffffff;
984 saved_val = REG_RD(sc, params->lfa_base +
985 offsetof(struct shmem_lfa, req_duplex));
986 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
987 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
988 PMD_DRV_LOG(INFO, "Duplex mismatch %x vs. %x",
989 (saved_val & lfa_mask), (req_val & lfa_mask));
990 return LFA_DUPLEX_MISMATCH;
992 /* Compare Flow Control */
993 saved_val = REG_RD(sc, params->lfa_base +
994 offsetof(struct shmem_lfa, req_flow_ctrl));
995 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
996 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
997 PMD_DRV_LOG(DEBUG, "Flow control mismatch %x vs. %x",
998 (saved_val & lfa_mask), (req_val & lfa_mask));
999 return LFA_FLOW_CTRL_MISMATCH;
1001 /* Compare Link Speed */
1002 saved_val = REG_RD(sc, params->lfa_base +
1003 offsetof(struct shmem_lfa, req_line_speed));
1004 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
1005 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1006 PMD_DRV_LOG(DEBUG, "Link speed mismatch %x vs. %x",
1007 (saved_val & lfa_mask), (req_val & lfa_mask));
1008 return LFA_LINK_SPEED_MISMATCH;
1011 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
1012 cur_speed_cap_mask = REG_RD(sc, params->lfa_base +
1013 offsetof(struct shmem_lfa,
1014 speed_cap_mask[cfg_idx]));
1016 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
1017 PMD_DRV_LOG(DEBUG, "Speed Cap mismatch %x vs. %x",
1019 params->speed_cap_mask[cfg_idx]);
1020 return LFA_SPEED_CAP_MISMATCH;
1024 cur_req_fc_auto_adv =
1025 REG_RD(sc, params->lfa_base +
1026 offsetof(struct shmem_lfa, additional_config)) &
1027 REQ_FC_AUTO_ADV_MASK;
1029 if ((uint16_t) cur_req_fc_auto_adv != params->req_fc_auto_adv) {
1030 PMD_DRV_LOG(DEBUG, "Flow Ctrl AN mismatch %x vs. %x",
1031 cur_req_fc_auto_adv, params->req_fc_auto_adv);
1032 return LFA_FLOW_CTRL_MISMATCH;
1035 eee_status = REG_RD(sc, params->shmem2_base +
1036 offsetof(struct shmem2_region,
1037 eee_status[params->port]));
1039 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
1040 (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) ||
1041 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
1042 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) {
1043 PMD_DRV_LOG(DEBUG, "EEE mismatch %x vs. %x", params->eee_mode,
1045 return LFA_EEE_MISMATCH;
1048 /* LFA conditions are met */
1052 /******************************************************************/
1053 /* EPIO/GPIO section */
1054 /******************************************************************/
1055 static void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin,
1058 uint32_t epio_mask, gp_oenable;
1061 if (epio_pin > 31) {
1062 PMD_DRV_LOG(DEBUG, "Invalid EPIO pin %d to get", epio_pin);
1066 epio_mask = 1 << epio_pin;
1067 /* Set this EPIO to output */
1068 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1069 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
1071 *en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
1074 static void elink_set_epio(struct bnx2x_softc *sc, uint32_t epio_pin, uint32_t en)
1076 uint32_t epio_mask, gp_output, gp_oenable;
1079 if (epio_pin > 31) {
1080 PMD_DRV_LOG(DEBUG, "Invalid EPIO pin %d to set", epio_pin);
1083 PMD_DRV_LOG(DEBUG, "Setting EPIO pin %d to %d", epio_pin, en);
1084 epio_mask = 1 << epio_pin;
1085 /* Set this EPIO to output */
1086 gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);
1088 gp_output |= epio_mask;
1090 gp_output &= ~epio_mask;
1092 REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
1094 /* Set the value for this EPIO */
1095 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1096 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
1099 static void elink_set_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,
1102 if (pin_cfg == PIN_CFG_NA)
1104 if (pin_cfg >= PIN_CFG_EPIO0) {
1105 elink_set_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1107 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1108 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1109 elink_cb_gpio_write(sc, gpio_num, (uint8_t) val, gpio_port);
1113 static uint32_t elink_get_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,
1116 if (pin_cfg == PIN_CFG_NA)
1117 return ELINK_STATUS_ERROR;
1118 if (pin_cfg >= PIN_CFG_EPIO0) {
1119 elink_get_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1121 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1122 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1123 *val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
1125 return ELINK_STATUS_OK;
1129 /******************************************************************/
1131 /******************************************************************/
1132 static void elink_update_pfc_xmac(struct elink_params *params,
1133 struct elink_vars *vars)
1135 struct bnx2x_softc *sc = params->sc;
1137 uint32_t pause_val, pfc0_val, pfc1_val;
1139 /* XMAC base adrr */
1140 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1142 /* Initialize pause and pfc registers */
1143 pause_val = 0x18000;
1144 pfc0_val = 0xFFFF8000;
1147 /* No PFC support */
1148 if (!(params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
1150 /* RX flow control - Process pause frame in receive direction
1152 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
1153 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1155 /* TX flow control - Send pause packet when buffer is full */
1156 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
1157 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1158 } else { /* PFC support */
1159 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1160 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1161 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1162 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1163 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1164 /* Write pause and PFC registers */
1165 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1166 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1167 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1168 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1172 /* Write pause and PFC registers */
1173 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1174 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1175 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1177 /* Set MAC address for source TX Pause/PFC frames */
1178 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO,
1179 ((params->mac_addr[2] << 24) |
1180 (params->mac_addr[3] << 16) |
1181 (params->mac_addr[4] << 8) | (params->mac_addr[5])));
1182 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI,
1183 ((params->mac_addr[0] << 8) | (params->mac_addr[1])));
1188 /******************************************************************/
1189 /* MAC/PBF section */
1190 /******************************************************************/
1191 static void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base)
1193 uint32_t new_mode, cur_mode;
1195 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1196 * (a value of 49==0x31) and make sure that the AUTO poll is off
1198 cur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1200 if (USES_WARPCORE(sc))
1201 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1203 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1205 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1206 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1209 new_mode = cur_mode &
1210 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1211 new_mode |= clc_cnt;
1212 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1214 PMD_DRV_LOG(DEBUG, "Changing emac_mode from 0x%x to 0x%x",
1215 cur_mode, new_mode);
1216 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1220 static void elink_set_mdio_emac_per_phy(struct bnx2x_softc *sc,
1221 struct elink_params *params)
1224 /* Set mdio clock per phy */
1225 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
1227 elink_set_mdio_clk(sc, params->phy[phy_index].mdio_ctrl);
1230 static uint8_t elink_is_4_port_mode(struct bnx2x_softc *sc)
1232 uint32_t port4mode_ovwr_val;
1233 /* Check 4-port override enabled */
1234 port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
1235 if (port4mode_ovwr_val & (1 << 0)) {
1236 /* Return 4-port mode override value */
1237 return (port4mode_ovwr_val & (1 << 1)) == (1 << 1);
1239 /* Return 4-port mode from input pin */
1240 return (uint8_t) REG_RD(sc, MISC_REG_PORT4MODE_EN);
1243 static void elink_emac_init(struct elink_params *params)
1245 /* reset and unreset the emac core */
1246 struct bnx2x_softc *sc = params->sc;
1247 uint8_t port = params->port;
1248 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1252 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1253 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1255 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1256 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1258 /* init emac - use read-modify-write */
1259 /* self clear reset */
1260 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
1261 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE,
1262 (val | EMAC_MODE_RESET));
1266 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
1267 PMD_DRV_LOG(DEBUG, "EMAC reset reg is %u", val);
1269 PMD_DRV_LOG(DEBUG, "EMAC timeout!");
1273 } while (val & EMAC_MODE_RESET);
1275 elink_set_mdio_emac_per_phy(sc, params);
1276 /* Set mac address */
1277 val = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
1278 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val);
1280 val = ((params->mac_addr[2] << 24) |
1281 (params->mac_addr[3] << 16) |
1282 (params->mac_addr[4] << 8) | params->mac_addr[5]);
1283 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val);
1286 static void elink_set_xumac_nig(struct elink_params *params,
1287 uint16_t tx_pause_en, uint8_t enable)
1289 struct bnx2x_softc *sc = params->sc;
1291 REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1293 REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1295 REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1296 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1299 static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)
1301 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1303 struct bnx2x_softc *sc = params->sc;
1304 if (!(REG_RD(sc, MISC_REG_RESET_REG_2) &
1305 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1307 val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);
1309 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1310 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1312 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1313 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1314 /* Disable RX and TX */
1315 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1318 static void elink_umac_enable(struct elink_params *params,
1319 struct elink_vars *vars, uint8_t lb)
1322 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1323 struct bnx2x_softc *sc = params->sc;
1325 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1326 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1329 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1330 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1332 PMD_DRV_LOG(DEBUG, "enabling UMAC");
1334 /* This register opens the gate for the UMAC despite its name */
1335 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1);
1337 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1338 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1339 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1340 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1341 switch (vars->line_speed) {
1342 case ELINK_SPEED_10:
1345 case ELINK_SPEED_100:
1348 case ELINK_SPEED_1000:
1351 case ELINK_SPEED_2500:
1355 PMD_DRV_LOG(DEBUG, "Invalid speed for UMAC %d",
1359 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1360 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1362 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
1363 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1365 if (vars->duplex == DUPLEX_HALF)
1366 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1368 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1371 /* Configure UMAC for EEE */
1372 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1373 PMD_DRV_LOG(DEBUG, "configured UMAC for EEE");
1374 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1375 UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1376 REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1378 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1381 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1382 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0,
1383 ((params->mac_addr[2] << 24) |
1384 (params->mac_addr[3] << 16) |
1385 (params->mac_addr[4] << 8) | (params->mac_addr[5])));
1386 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1,
1387 ((params->mac_addr[0] << 8) | (params->mac_addr[1])));
1389 /* Enable RX and TX */
1390 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1391 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | UMAC_COMMAND_CONFIG_REG_RX_ENA;
1392 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1395 /* Remove SW Reset */
1396 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1398 /* Check loopback mode */
1400 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1401 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1403 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1404 * length used by the MAC receive logic to check frames.
1406 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
1407 elink_set_xumac_nig(params,
1408 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
1409 vars->mac_type = ELINK_MAC_TYPE_UMAC;
1413 /* Define the XMAC mode */
1414 static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
1416 struct bnx2x_softc *sc = params->sc;
1417 uint32_t is_port4mode = elink_is_4_port_mode(sc);
1419 /* In 4-port mode, need to set the mode only once, so if XMAC is
1420 * already out of reset, it means the mode has already been set,
1421 * and it must not* reset the XMAC again, since it controls both
1425 if (((CHIP_NUM(sc) == CHIP_NUM_57840_4_10) ||
1426 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20) ||
1427 (CHIP_NUM(sc) == CHIP_NUM_57840_OBS)) &&
1429 (REG_RD(sc, MISC_REG_RESET_REG_2) &
1430 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1431 PMD_DRV_LOG(DEBUG, "XMAC already out of reset in 4-port mode");
1436 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1437 MISC_REGISTERS_RESET_REG_2_XMAC);
1440 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1441 MISC_REGISTERS_RESET_REG_2_XMAC);
1443 PMD_DRV_LOG(DEBUG, "Init XMAC to 2 ports x 10G per path");
1445 /* Set the number of ports on the system side to up to 2 */
1446 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1448 /* Set the number of ports on the Warp Core to 10G */
1449 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1451 /* Set the number of ports on the system side to 1 */
1452 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1453 if (max_speed == ELINK_SPEED_10000) {
1455 "Init XMAC to 10G x 1 port per path");
1456 /* Set the number of ports on the Warp Core to 10G */
1457 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1460 "Init XMAC to 20G x 2 ports per path");
1461 /* Set the number of ports on the Warp Core to 20G */
1462 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1466 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1467 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1470 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1471 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1475 static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
1477 uint8_t port = params->port;
1478 struct bnx2x_softc *sc = params->sc;
1479 uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1482 if (REG_RD(sc, MISC_REG_RESET_REG_2) & MISC_REGISTERS_RESET_REG_2_XMAC) {
1483 /* Send an indication to change the state in the NIG back to XON
1484 * Clearing this bit enables the next set of this bit to get
1487 pfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI);
1488 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
1489 (pfc_ctrl & ~(1 << 1)));
1490 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
1491 (pfc_ctrl | (1 << 1)));
1492 PMD_DRV_LOG(DEBUG, "Disable XMAC on port %x", port);
1493 val = REG_RD(sc, xmac_base + XMAC_REG_CTRL);
1495 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1497 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1498 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
1502 static elink_status_t elink_xmac_enable(struct elink_params *params,
1503 struct elink_vars *vars, uint8_t lb)
1505 uint32_t val, xmac_base;
1506 struct bnx2x_softc *sc = params->sc;
1507 PMD_DRV_LOG(DEBUG, "enabling XMAC");
1509 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1511 elink_xmac_init(params, vars->line_speed);
1513 /* This register determines on which events the MAC will assert
1514 * error on the i/f to the NIG along w/ EOP.
1517 /* This register tells the NIG whether to send traffic to UMAC
1520 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 0);
1522 /* When XMAC is in XLGMII mode, disable sending idles for fault
1525 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) {
1526 REG_WR(sc, xmac_base + XMAC_REG_RX_LSS_CTRL,
1527 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1528 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1529 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1530 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1531 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1532 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1534 /* Set Max packet size */
1535 REG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1537 /* CRC append for Tx packets */
1538 REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1541 elink_update_pfc_xmac(params, vars);
1543 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1544 PMD_DRV_LOG(DEBUG, "Setting XMAC for EEE");
1545 REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1546 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1548 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1551 /* Enable TX and RX */
1552 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1554 /* Set MAC in XLGMII mode for dual-mode */
1555 if ((vars->line_speed == ELINK_SPEED_20000) &&
1556 (params->phy[ELINK_INT_PHY].supported &
1557 ELINK_SUPPORTED_20000baseKR2_Full))
1558 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1560 /* Check loopback mode */
1562 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1563 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
1564 elink_set_xumac_nig(params,
1565 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
1567 vars->mac_type = ELINK_MAC_TYPE_XMAC;
1569 return ELINK_STATUS_OK;
1572 static elink_status_t elink_emac_enable(struct elink_params *params,
1573 struct elink_vars *vars, uint8_t lb)
1575 struct bnx2x_softc *sc = params->sc;
1576 uint8_t port = params->port;
1577 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1580 PMD_DRV_LOG(DEBUG, "enabling EMAC");
1583 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1584 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1586 /* enable emac and not bmac */
1587 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 1);
1589 if (vars->phy_flags & PHY_XGXS_FLAG) {
1590 uint32_t ser_lane = ((params->lane_config &
1591 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1592 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1594 PMD_DRV_LOG(DEBUG, "XGXS");
1595 /* select the master lanes (out of 0-3) */
1596 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, ser_lane);
1598 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
1600 } else { /* SerDes */
1601 PMD_DRV_LOG(DEBUG, "SerDes");
1603 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);
1606 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
1607 EMAC_RX_MODE_RESET);
1608 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
1609 EMAC_TX_MODE_RESET);
1611 /* pause enable/disable */
1612 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
1613 EMAC_RX_MODE_FLOW_EN);
1615 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
1616 (EMAC_TX_MODE_EXT_PAUSE_EN |
1617 EMAC_TX_MODE_FLOW_EN));
1618 if (!(params->feature_config_flags &
1619 ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
1620 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
1621 elink_bits_en(sc, emac_base +
1622 EMAC_REG_EMAC_RX_MODE,
1623 EMAC_RX_MODE_FLOW_EN);
1625 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
1626 elink_bits_en(sc, emac_base +
1627 EMAC_REG_EMAC_TX_MODE,
1628 (EMAC_TX_MODE_EXT_PAUSE_EN |
1629 EMAC_TX_MODE_FLOW_EN));
1631 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
1632 EMAC_TX_MODE_FLOW_EN);
1634 /* KEEP_VLAN_TAG, promiscuous */
1635 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);
1636 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1638 /* Setting this bit causes MAC control frames (except for pause
1639 * frames) to be passed on for processing. This setting has no
1640 * affect on the operation of the pause frames. This bit effects
1641 * all packets regardless of RX Parser packet sorting logic.
1642 * Turn the PFC off to make sure we are in Xon state before
1645 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0);
1646 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
1647 PMD_DRV_LOG(DEBUG, "PFC is enabled");
1648 /* Enable PFC again */
1649 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE,
1650 EMAC_REG_RX_PFC_MODE_RX_EN |
1651 EMAC_REG_RX_PFC_MODE_TX_EN |
1652 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1654 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM,
1656 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1658 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1659 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1661 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val);
1664 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
1669 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, val);
1672 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 1);
1674 /* Enable emac for jumbo packets */
1675 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE,
1676 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1677 (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
1678 ELINK_ETH_OVREHEAD)));
1681 REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port * 4, 0x1);
1683 /* Disable the NIG in/out to the bmac */
1684 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x0);
1685 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, 0x0);
1686 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x0);
1688 /* Enable the NIG in/out to the emac */
1689 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x1);
1691 if ((params->feature_config_flags &
1692 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
1693 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1696 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, val);
1697 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x1);
1699 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x0);
1701 vars->mac_type = ELINK_MAC_TYPE_EMAC;
1702 return ELINK_STATUS_OK;
1705 static void elink_update_pfc_bmac1(struct elink_params *params,
1706 struct elink_vars *vars)
1708 uint32_t wb_data[2];
1709 struct bnx2x_softc *sc = params->sc;
1710 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1711 NIG_REG_INGRESS_BMAC0_MEM;
1713 uint32_t val = 0x14;
1714 if ((!(params->feature_config_flags &
1715 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
1716 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
1717 /* Enable BigMAC to react on received Pause packets */
1721 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1725 if (!(params->feature_config_flags &
1726 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
1727 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1731 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1734 static void elink_update_pfc_bmac2(struct elink_params *params,
1735 struct elink_vars *vars, uint8_t is_lb)
1737 /* Set rx control: Strip CRC and enable BigMAC to relay
1738 * control packets to the system as well
1740 uint32_t wb_data[2];
1741 struct bnx2x_softc *sc = params->sc;
1742 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1743 NIG_REG_INGRESS_BMAC0_MEM;
1744 uint32_t val = 0x14;
1746 if ((!(params->feature_config_flags &
1747 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
1748 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
1749 /* Enable BigMAC to react on received Pause packets */
1753 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1758 if (!(params->feature_config_flags &
1759 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
1760 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1764 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1766 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
1767 PMD_DRV_LOG(DEBUG, "PFC is enabled");
1768 /* Enable PFC RX & TX & STATS and set 8 COS */
1770 wb_data[0] |= (1 << 0); /* RX */
1771 wb_data[0] |= (1 << 1); /* TX */
1772 wb_data[0] |= (1 << 2); /* Force initial Xon */
1773 wb_data[0] |= (1 << 3); /* 8 cos */
1774 wb_data[0] |= (1 << 5); /* STATS */
1776 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1778 /* Clear the force Xon */
1779 wb_data[0] &= ~(1 << 2);
1781 PMD_DRV_LOG(DEBUG, "PFC is disabled");
1782 /* Disable PFC RX & TX & STATS and set 8 COS */
1787 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1789 /* Set Time (based unit is 512 bit time) between automatic
1790 * re-sending of PP packets amd enable automatic re-send of
1791 * Per-Priroity Packet as long as pp_gen is asserted and
1792 * pp_disable is low.
1795 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
1796 val |= (1 << 16); /* enable automatic re-send */
1800 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1804 val = 0x3; /* Enable RX and TX */
1806 val |= 0x4; /* Local loopback */
1807 PMD_DRV_LOG(DEBUG, "enable bmac loopback");
1809 /* When PFC enabled, Pass pause frames towards the NIG. */
1810 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
1811 val |= ((1 << 6) | (1 << 5));
1815 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1818 /******************************************************************************
1820 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
1821 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
1822 ******************************************************************************/
1823 static elink_status_t elink_pfc_nig_rx_priority_mask(struct bnx2x_softc *sc,
1825 uint32_t priority_mask,
1828 uint32_t nig_reg_rx_priority_mask_add = 0;
1830 switch (cos_entry) {
1832 nig_reg_rx_priority_mask_add = (port) ?
1833 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
1834 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
1837 nig_reg_rx_priority_mask_add = (port) ?
1838 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
1839 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
1842 nig_reg_rx_priority_mask_add = (port) ?
1843 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
1844 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
1848 return ELINK_STATUS_ERROR;
1849 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
1853 return ELINK_STATUS_ERROR;
1854 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
1858 return ELINK_STATUS_ERROR;
1859 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
1863 REG_WR(sc, nig_reg_rx_priority_mask_add, priority_mask);
1865 return ELINK_STATUS_OK;
1868 static void elink_update_mng(struct elink_params *params, uint32_t link_status)
1870 struct bnx2x_softc *sc = params->sc;
1872 REG_WR(sc, params->shmem_base +
1873 offsetof(struct shmem_region,
1874 port_mb[params->port].link_status), link_status);
1877 static void elink_update_link_attr(struct elink_params *params,
1880 struct bnx2x_softc *sc = params->sc;
1882 if (SHMEM2_HAS(sc, link_attr_sync))
1883 REG_WR(sc, params->shmem2_base +
1884 offsetof(struct shmem2_region,
1885 link_attr_sync[params->port]), link_attr);
1888 static void elink_update_pfc_nig(struct elink_params *params,
1889 struct elink_nig_brb_pfc_port_params
1892 uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en =
1894 uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
1895 uint32_t pkt_priority_to_cos = 0;
1896 struct bnx2x_softc *sc = params->sc;
1897 uint8_t port = params->port;
1899 int set_pfc = params->feature_config_flags &
1900 ELINK_FEATURE_CONFIG_PFC_ENABLED;
1901 PMD_DRV_LOG(DEBUG, "updating pfc nig parameters");
1903 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
1904 * MAC control frames (that are not pause packets)
1905 * will be forwarded to the XCM.
1907 xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK :
1908 NIG_REG_LLH0_XCM_MASK);
1909 /* NIG params will override non PFC params, since it's possible to
1910 * do transition from PFC to SAFC
1920 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
1921 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
1926 llfc_out_en = nig_params->llfc_out_en;
1927 llfc_enable = nig_params->llfc_enable;
1928 pause_enable = nig_params->pause_enable;
1929 } else /* Default non PFC mode - PAUSE */
1932 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
1933 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
1938 REG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN :
1939 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
1940 REG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 :
1941 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
1942 REG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 :
1943 NIG_REG_LLFC_ENABLE_0, llfc_enable);
1944 REG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 :
1945 NIG_REG_PAUSE_ENABLE_0, pause_enable);
1947 REG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 :
1948 NIG_REG_PPP_ENABLE_0, ppp_enable);
1950 REG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK :
1951 NIG_REG_LLH0_XCM_MASK, xcm_mask);
1953 REG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
1954 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
1956 /* Output enable for RX_XCM # IF */
1957 REG_WR(sc, port ? NIG_REG_XCM1_OUT_EN :
1958 NIG_REG_XCM0_OUT_EN, xcm_out_en);
1960 /* HW PFC TX enable */
1961 REG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE :
1962 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
1966 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
1968 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
1969 elink_pfc_nig_rx_priority_mask(sc, i,
1971 rx_cos_priority_mask[i],
1974 REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
1975 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
1976 nig_params->llfc_high_priority_classes);
1978 REG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
1979 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
1980 nig_params->llfc_low_priority_classes);
1982 REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
1983 NIG_REG_P0_PKT_PRIORITY_TO_COS, pkt_priority_to_cos);
1986 elink_status_t elink_update_pfc(struct elink_params *params,
1987 struct elink_vars *vars,
1988 struct elink_nig_brb_pfc_port_params
1991 /* The PFC and pause are orthogonal to one another, meaning when
1992 * PFC is enabled, the pause are disabled, and when PFC is
1993 * disabled, pause are set according to the pause result.
1996 struct bnx2x_softc *sc = params->sc;
1997 elink_status_t elink_status = ELINK_STATUS_OK;
1998 uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC);
2000 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
2001 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2003 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2005 elink_update_mng(params, vars->link_status);
2007 /* Update NIG params */
2008 elink_update_pfc_nig(params, pfc_params);
2011 return elink_status;
2013 PMD_DRV_LOG(DEBUG, "About to update PFC in BMAC");
2015 if (CHIP_IS_E3(sc)) {
2016 if (vars->mac_type == ELINK_MAC_TYPE_XMAC)
2017 elink_update_pfc_xmac(params, vars);
2019 val = REG_RD(sc, MISC_REG_RESET_REG_2);
2021 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2023 PMD_DRV_LOG(DEBUG, "About to update PFC in EMAC");
2024 elink_emac_enable(params, vars, 0);
2025 return elink_status;
2028 elink_update_pfc_bmac2(params, vars, bmac_loopback);
2030 elink_update_pfc_bmac1(params, vars);
2033 if ((params->feature_config_flags &
2034 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
2035 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2037 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port * 4, val);
2039 return elink_status;
2042 static elink_status_t elink_bmac1_enable(struct elink_params *params,
2043 struct elink_vars *vars, uint8_t is_lb)
2045 struct bnx2x_softc *sc = params->sc;
2046 uint8_t port = params->port;
2047 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2048 NIG_REG_INGRESS_BMAC0_MEM;
2049 uint32_t wb_data[2];
2052 PMD_DRV_LOG(DEBUG, "Enabling BigMAC1");
2057 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2061 wb_data[0] = ((params->mac_addr[2] << 24) |
2062 (params->mac_addr[3] << 16) |
2063 (params->mac_addr[4] << 8) | params->mac_addr[5]);
2064 wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
2065 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2071 PMD_DRV_LOG(DEBUG, "enable bmac loopback");
2075 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2078 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2080 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2082 elink_update_pfc_bmac1(params, vars);
2085 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2087 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2089 /* Set cnt max size */
2090 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2092 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2094 /* Configure SAFC */
2095 wb_data[0] = 0x1000200;
2097 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2100 return ELINK_STATUS_OK;
2103 static elink_status_t elink_bmac2_enable(struct elink_params *params,
2104 struct elink_vars *vars, uint8_t is_lb)
2106 struct bnx2x_softc *sc = params->sc;
2107 uint8_t port = params->port;
2108 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2109 NIG_REG_INGRESS_BMAC0_MEM;
2110 uint32_t wb_data[2];
2112 PMD_DRV_LOG(DEBUG, "Enabling BigMAC2");
2116 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2119 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2122 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2128 wb_data[0] = ((params->mac_addr[2] << 24) |
2129 (params->mac_addr[3] << 16) |
2130 (params->mac_addr[4] << 8) | params->mac_addr[5]);
2131 wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
2132 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2137 /* Configure SAFC */
2138 wb_data[0] = 0x1000200;
2140 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2145 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2147 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2151 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2153 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2155 /* Set cnt max size */
2156 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2;
2158 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2160 elink_update_pfc_bmac2(params, vars, is_lb);
2162 return ELINK_STATUS_OK;
2165 static elink_status_t elink_bmac_enable(struct elink_params *params,
2166 struct elink_vars *vars,
2167 uint8_t is_lb, uint8_t reset_bmac)
2169 elink_status_t rc = ELINK_STATUS_OK;
2170 uint8_t port = params->port;
2171 struct bnx2x_softc *sc = params->sc;
2173 /* Reset and unreset the BigMac */
2175 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2176 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2180 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2181 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2183 /* Enable access for bmac registers */
2184 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1);
2186 /* Enable BMAC according to BMAC type */
2188 rc = elink_bmac2_enable(params, vars, is_lb);
2190 rc = elink_bmac1_enable(params, vars, is_lb);
2191 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0x1);
2192 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 0x0);
2193 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 0x0);
2195 if ((params->feature_config_flags &
2196 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
2197 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2199 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, val);
2200 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x0);
2201 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x0);
2202 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, 0x0);
2203 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x1);
2204 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x1);
2206 vars->mac_type = ELINK_MAC_TYPE_BMAC;
2210 static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en)
2212 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2213 NIG_REG_INGRESS_BMAC0_MEM;
2214 uint32_t wb_data[2];
2215 uint32_t nig_bmac_enable =
2216 REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
2219 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2221 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2222 /* Only if the bmac is out of reset */
2223 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
2224 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && nig_bmac_enable) {
2225 /* Clear Rx Enable bit in BMAC_CONTROL register */
2226 REG_RD_DMAE(sc, bmac_addr, wb_data, 2);
2228 wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE;
2230 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
2231 REG_WR_DMAE(sc, bmac_addr, wb_data, 2);
2236 static elink_status_t elink_pbf_update(struct elink_params *params,
2237 uint32_t flow_ctrl, uint32_t line_speed)
2239 struct bnx2x_softc *sc = params->sc;
2240 uint8_t port = params->port;
2241 uint32_t init_crd, crd;
2242 uint32_t count = 1000;
2245 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x1);
2247 /* Wait for init credit */
2248 init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port * 4);
2249 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
2250 PMD_DRV_LOG(DEBUG, "init_crd 0x%x crd 0x%x", init_crd, crd);
2252 while ((init_crd != crd) && count) {
2254 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
2257 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
2258 if (init_crd != crd) {
2259 PMD_DRV_LOG(DEBUG, "BUG! init_crd 0x%x != crd 0x%x",
2261 return ELINK_STATUS_ERROR;
2264 if (flow_ctrl & ELINK_FLOW_CTRL_RX ||
2265 line_speed == ELINK_SPEED_10 ||
2266 line_speed == ELINK_SPEED_100 ||
2267 line_speed == ELINK_SPEED_1000 || line_speed == ELINK_SPEED_2500) {
2268 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 1);
2269 /* Update threshold */
2270 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, 0);
2271 /* Update init credit */
2272 init_crd = 778; /* (800-18-4) */
2275 uint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
2276 ELINK_ETH_OVREHEAD) / 16;
2277 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
2278 /* Update threshold */
2279 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, thresh);
2280 /* Update init credit */
2281 switch (line_speed) {
2282 case ELINK_SPEED_10000:
2283 init_crd = thresh + 553 - 22;
2286 PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x",
2288 return ELINK_STATUS_ERROR;
2291 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4, init_crd);
2292 PMD_DRV_LOG(DEBUG, "PBF updated to speed %d credit %d",
2293 line_speed, init_crd);
2295 /* Probe the credit changes */
2296 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x1);
2298 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x0);
2301 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x0);
2302 return ELINK_STATUS_OK;
2306 * elink_get_emac_base - retrive emac base address
2308 * @bp: driver handle
2309 * @mdc_mdio_access: access type
2312 * This function selects the MDC/MDIO access (through emac0 or
2313 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2314 * phy has a default access mode, which could also be overridden
2315 * by nvram configuration. This parameter, whether this is the
2316 * default phy configuration, or the nvram overrun
2317 * configuration, is passed here as mdc_mdio_access and selects
2318 * the emac_base for the CL45 read/writes operations
2320 static uint32_t elink_get_emac_base(struct bnx2x_softc *sc,
2321 uint32_t mdc_mdio_access, uint8_t port)
2323 uint32_t emac_base = 0;
2324 switch (mdc_mdio_access) {
2325 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2327 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2328 if (REG_RD(sc, NIG_REG_PORT_SWAP))
2329 emac_base = GRCBASE_EMAC1;
2331 emac_base = GRCBASE_EMAC0;
2333 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2334 if (REG_RD(sc, NIG_REG_PORT_SWAP))
2335 emac_base = GRCBASE_EMAC0;
2337 emac_base = GRCBASE_EMAC1;
2339 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2340 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2342 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2343 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2352 /******************************************************************/
2353 /* CL22 access functions */
2354 /******************************************************************/
2355 static elink_status_t elink_cl22_write(struct bnx2x_softc *sc,
2356 struct elink_phy *phy,
2357 uint16_t reg, uint16_t val)
2361 elink_status_t rc = ELINK_STATUS_OK;
2362 /* Switch to CL22 */
2363 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2364 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2365 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2368 tmp = ((phy->addr << 21) | (reg << 16) | val |
2369 EMAC_MDIO_COMM_COMMAND_WRITE_22 | EMAC_MDIO_COMM_START_BUSY);
2370 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2372 for (i = 0; i < 50; i++) {
2375 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2376 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2381 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2382 PMD_DRV_LOG(DEBUG, "write phy register failed");
2383 rc = ELINK_STATUS_TIMEOUT;
2385 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2389 static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,
2390 struct elink_phy *phy,
2391 uint16_t reg, uint16_t * ret_val)
2395 elink_status_t rc = ELINK_STATUS_OK;
2397 /* Switch to CL22 */
2398 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2399 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2400 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2403 val = ((phy->addr << 21) | (reg << 16) |
2404 EMAC_MDIO_COMM_COMMAND_READ_22 | EMAC_MDIO_COMM_START_BUSY);
2405 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2407 for (i = 0; i < 50; i++) {
2410 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2411 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2412 *ret_val = (uint16_t) (val & EMAC_MDIO_COMM_DATA);
2417 if (val & EMAC_MDIO_COMM_START_BUSY) {
2418 PMD_DRV_LOG(DEBUG, "read phy register failed");
2421 rc = ELINK_STATUS_TIMEOUT;
2423 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2427 /******************************************************************/
2428 /* CL45 access functions */
2429 /******************************************************************/
2430 static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
2431 struct elink_phy *phy, uint8_t devad,
2432 uint16_t reg, uint16_t * ret_val)
2436 elink_status_t rc = ELINK_STATUS_OK;
2437 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
2438 elink_set_mdio_clk(sc, phy->mdio_ctrl);
2441 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2442 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2443 EMAC_MDIO_STATUS_10MB);
2445 val = ((phy->addr << 21) | (devad << 16) | reg |
2446 EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);
2447 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2449 for (i = 0; i < 50; i++) {
2452 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2453 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2458 if (val & EMAC_MDIO_COMM_START_BUSY) {
2459 PMD_DRV_LOG(DEBUG, "read phy register failed");
2460 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
2463 rc = ELINK_STATUS_TIMEOUT;
2466 val = ((phy->addr << 21) | (devad << 16) |
2467 EMAC_MDIO_COMM_COMMAND_READ_45 |
2468 EMAC_MDIO_COMM_START_BUSY);
2469 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2471 for (i = 0; i < 50; i++) {
2474 val = REG_RD(sc, phy->mdio_ctrl +
2475 EMAC_REG_EMAC_MDIO_COMM);
2476 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2478 (uint16_t) (val & EMAC_MDIO_COMM_DATA);
2482 if (val & EMAC_MDIO_COMM_START_BUSY) {
2483 PMD_DRV_LOG(DEBUG, "read phy register failed");
2484 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
2487 rc = ELINK_STATUS_TIMEOUT;
2490 /* Work around for E3 A0 */
2491 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
2492 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
2493 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
2495 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
2499 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2500 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2501 EMAC_MDIO_STATUS_10MB);
2505 static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,
2506 struct elink_phy *phy, uint8_t devad,
2507 uint16_t reg, uint16_t val)
2511 elink_status_t rc = ELINK_STATUS_OK;
2512 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
2513 elink_set_mdio_clk(sc, phy->mdio_ctrl);
2516 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2517 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2518 EMAC_MDIO_STATUS_10MB);
2521 tmp = ((phy->addr << 21) | (devad << 16) | reg |
2522 EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);
2523 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2525 for (i = 0; i < 50; i++) {
2528 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2529 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2534 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2535 PMD_DRV_LOG(DEBUG, "write phy register failed");
2536 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
2538 rc = ELINK_STATUS_TIMEOUT;
2541 tmp = ((phy->addr << 21) | (devad << 16) | val |
2542 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2543 EMAC_MDIO_COMM_START_BUSY);
2544 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2546 for (i = 0; i < 50; i++) {
2549 tmp = REG_RD(sc, phy->mdio_ctrl +
2550 EMAC_REG_EMAC_MDIO_COMM);
2551 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2556 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2557 PMD_DRV_LOG(DEBUG, "write phy register failed");
2558 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
2560 rc = ELINK_STATUS_TIMEOUT;
2563 /* Work around for E3 A0 */
2564 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
2565 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
2566 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
2568 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
2571 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2572 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2573 EMAC_MDIO_STATUS_10MB);
2577 /******************************************************************/
2579 /******************************************************************/
2580 static uint8_t elink_eee_has_cap(struct elink_params *params)
2582 struct bnx2x_softc *sc = params->sc;
2584 if (REG_RD(sc, params->shmem2_base) <=
2585 offsetof(struct shmem2_region, eee_status[params->port]))
2591 static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode,
2592 uint32_t * idle_timer)
2594 switch (nvram_mode) {
2595 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2596 *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME;
2598 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2599 *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2601 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2602 *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME;
2609 return ELINK_STATUS_OK;
2612 static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer,
2613 uint32_t * nvram_mode)
2615 switch (idle_timer) {
2616 case ELINK_EEE_MODE_NVRAM_BALANCED_TIME:
2617 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2619 case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2620 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2622 case ELINK_EEE_MODE_NVRAM_LATENCY_TIME:
2623 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2626 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2630 return ELINK_STATUS_OK;
2633 static uint32_t elink_eee_calc_timer(struct elink_params *params)
2635 uint32_t eee_mode, eee_idle;
2636 struct bnx2x_softc *sc = params->sc;
2638 if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) {
2639 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
2640 /* time value in eee_mode --> used directly */
2641 eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK;
2643 /* hsi value in eee_mode --> time */
2644 if (elink_eee_nvram_to_time(params->eee_mode &
2645 ELINK_EEE_MODE_NVRAM_MASK,
2650 /* hsi values in nvram --> time */
2651 eee_mode = ((REG_RD(sc, params->shmem_base +
2652 offsetof(struct shmem_region,
2653 dev_info.port_feature_config
2655 port].eee_power_mode)) &
2656 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2657 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2659 if (elink_eee_nvram_to_time(eee_mode, &eee_idle))
2666 static elink_status_t elink_eee_set_timers(struct elink_params *params,
2667 struct elink_vars *vars)
2669 uint32_t eee_idle = 0, eee_mode;
2670 struct bnx2x_softc *sc = params->sc;
2672 eee_idle = elink_eee_calc_timer(params);
2675 REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2677 } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) &&
2678 (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) &&
2679 (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) {
2680 PMD_DRV_LOG(DEBUG, "Error: Tx LPI is enabled with timer 0");
2681 return ELINK_STATUS_ERROR;
2684 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2685 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
2686 /* eee_idle in 1u --> eee_status in 16u */
2688 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2689 SHMEM_EEE_TIME_OUTPUT_BIT;
2691 if (elink_eee_time_to_nvram(eee_idle, &eee_mode))
2692 return ELINK_STATUS_ERROR;
2693 vars->eee_status |= eee_mode;
2696 return ELINK_STATUS_OK;
2699 static elink_status_t elink_eee_initial_config(struct elink_params *params,
2700 struct elink_vars *vars,
2703 vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2705 /* Propogate params' bits --> vars (for migration exposure) */
2706 if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)
2707 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2709 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2711 if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI)
2712 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2714 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2716 return elink_eee_set_timers(params, vars);
2719 static elink_status_t elink_eee_disable(struct elink_phy *phy,
2720 struct elink_params *params,
2721 struct elink_vars *vars)
2723 struct bnx2x_softc *sc = params->sc;
2725 /* Make Certain LPI is disabled */
2726 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2728 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
2730 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2732 return ELINK_STATUS_OK;
2735 static elink_status_t elink_eee_advertise(struct elink_phy *phy,
2736 struct elink_params *params,
2737 struct elink_vars *vars,
2740 struct bnx2x_softc *sc = params->sc;
2743 /* Mask events preventing LPI generation */
2744 REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
2746 if (modes & SHMEM_EEE_10G_ADV) {
2747 PMD_DRV_LOG(DEBUG, "Advertise 10GBase-T EEE");
2750 if (modes & SHMEM_EEE_1G_ADV) {
2751 PMD_DRV_LOG(DEBUG, "Advertise 1GBase-T EEE");
2755 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
2757 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2758 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
2760 return ELINK_STATUS_OK;
2763 static void elink_update_mng_eee(struct elink_params *params,
2764 uint32_t eee_status)
2766 struct bnx2x_softc *sc = params->sc;
2768 if (elink_eee_has_cap(params))
2769 REG_WR(sc, params->shmem2_base +
2770 offsetof(struct shmem2_region,
2771 eee_status[params->port]), eee_status);
2774 static void elink_eee_an_resolve(struct elink_phy *phy,
2775 struct elink_params *params,
2776 struct elink_vars *vars)
2778 struct bnx2x_softc *sc = params->sc;
2779 uint16_t adv = 0, lp = 0;
2780 uint32_t lp_adv = 0;
2783 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
2784 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
2787 lp_adv |= SHMEM_EEE_100M_ADV;
2789 if (vars->line_speed == ELINK_SPEED_100)
2791 PMD_DRV_LOG(DEBUG, "EEE negotiated - 100M");
2795 lp_adv |= SHMEM_EEE_1G_ADV;
2797 if (vars->line_speed == ELINK_SPEED_1000)
2799 PMD_DRV_LOG(DEBUG, "EEE negotiated - 1G");
2803 lp_adv |= SHMEM_EEE_10G_ADV;
2805 if (vars->line_speed == ELINK_SPEED_10000)
2807 PMD_DRV_LOG(DEBUG, "EEE negotiated - 10G");
2811 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
2812 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2815 PMD_DRV_LOG(DEBUG, "EEE is active");
2816 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
2820 /******************************************************************/
2821 /* BSC access functions from E3 */
2822 /******************************************************************/
2823 static void elink_bsc_module_sel(struct elink_params *params)
2826 uint32_t board_cfg, sfp_ctrl;
2827 uint32_t i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
2828 struct bnx2x_softc *sc = params->sc;
2829 uint8_t port = params->port;
2830 /* Read I2C output PINs */
2831 board_cfg = REG_RD(sc, params->shmem_base +
2832 offsetof(struct shmem_region,
2833 dev_info.shared_hw_config.board));
2834 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
2835 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
2836 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
2838 /* Read I2C output value */
2839 sfp_ctrl = REG_RD(sc, params->shmem_base +
2840 offsetof(struct shmem_region,
2841 dev_info.port_hw_config[port].
2843 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
2844 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
2845 PMD_DRV_LOG(DEBUG, "Setting BSC switch");
2846 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
2847 elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]);
2850 static elink_status_t elink_bsc_read(struct elink_params *params,
2851 struct bnx2x_softc *sc,
2855 uint8_t xfer_cnt, uint32_t * data_array)
2858 elink_status_t rc = ELINK_STATUS_OK;
2860 if (xfer_cnt > 16) {
2861 PMD_DRV_LOG(DEBUG, "invalid xfer_cnt %d. Max is 16 bytes",
2863 return ELINK_STATUS_ERROR;
2866 elink_bsc_module_sel(params);
2868 xfer_cnt = 16 - lc_addr;
2870 /* Enable the engine */
2871 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2872 val |= MCPR_IMC_COMMAND_ENABLE;
2873 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
2875 /* Program slave device ID */
2876 val = (sl_devid << 16) | sl_addr;
2877 REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
2879 /* Start xfer with 0 byte to update the address pointer ??? */
2880 val = (MCPR_IMC_COMMAND_ENABLE) |
2881 (MCPR_IMC_COMMAND_WRITE_OP <<
2882 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
2883 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
2884 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
2886 /* Poll for completion */
2888 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2889 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
2891 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2893 PMD_DRV_LOG(DEBUG, "wr 0 byte timed out after %d try",
2895 rc = ELINK_STATUS_TIMEOUT;
2899 if (rc == ELINK_STATUS_TIMEOUT)
2902 /* Start xfer with read op */
2903 val = (MCPR_IMC_COMMAND_ENABLE) |
2904 (MCPR_IMC_COMMAND_READ_OP <<
2905 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
2906 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
2908 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
2910 /* Poll for completion */
2912 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2913 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
2915 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2917 PMD_DRV_LOG(DEBUG, "rd op timed out after %d try", i);
2918 rc = ELINK_STATUS_TIMEOUT;
2922 if (rc == ELINK_STATUS_TIMEOUT)
2925 for (i = (lc_addr >> 2); i < 4; i++) {
2926 data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i * 4));
2928 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
2929 ((data_array[i] & 0x0000ff00) << 8) |
2930 ((data_array[i] & 0x00ff0000) >> 8) |
2931 ((data_array[i] & 0xff000000) >> 24);
2937 static void elink_cl45_read_or_write(struct bnx2x_softc *sc,
2938 struct elink_phy *phy, uint8_t devad,
2939 uint16_t reg, uint16_t or_val)
2942 elink_cl45_read(sc, phy, devad, reg, &val);
2943 elink_cl45_write(sc, phy, devad, reg, val | or_val);
2946 static void elink_cl45_read_and_write(struct bnx2x_softc *sc,
2947 struct elink_phy *phy,
2948 uint8_t devad, uint16_t reg,
2952 elink_cl45_read(sc, phy, devad, reg, &val);
2953 elink_cl45_write(sc, phy, devad, reg, val & and_val);
2956 static uint8_t elink_get_warpcore_lane(struct elink_params *params)
2959 struct bnx2x_softc *sc = params->sc;
2960 uint32_t path_swap, path_swap_ovr;
2964 port = params->port;
2966 if (elink_is_4_port_mode(sc)) {
2967 uint32_t port_swap, port_swap_ovr;
2969 /* Figure out path swap value */
2970 path_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
2971 if (path_swap_ovr & 0x1)
2972 path_swap = (path_swap_ovr & 0x2);
2974 path_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP);
2979 /* Figure out port swap value */
2980 port_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
2981 if (port_swap_ovr & 0x1)
2982 port_swap = (port_swap_ovr & 0x2);
2984 port_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP);
2989 lane = (port << 1) + path;
2990 } else { /* Two port mode - no port swap */
2992 /* Figure out path swap value */
2993 path_swap_ovr = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
2994 if (path_swap_ovr & 0x1) {
2995 path_swap = (path_swap_ovr & 0x2);
2997 path_swap = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);
3007 static void elink_set_aer_mmd(struct elink_params *params,
3008 struct elink_phy *phy)
3011 uint16_t offset, aer_val;
3012 struct bnx2x_softc *sc = params->sc;
3013 ser_lane = ((params->lane_config &
3014 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3015 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3017 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3018 (phy->addr + ser_lane) : 0;
3020 if (USES_WARPCORE(sc)) {
3021 aer_val = elink_get_warpcore_lane(params);
3022 /* In Dual-lane mode, two lanes are joined together,
3023 * so in order to configure them, the AER broadcast method is
3025 * 0x200 is the broadcast address for lanes 0,1
3026 * 0x201 is the broadcast address for lanes 2,3
3028 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
3029 aer_val = (aer_val >> 1) | 0x200;
3030 } else if (CHIP_IS_E2(sc))
3031 aer_val = 0x3800 + offset - 1;
3033 aer_val = 0x3800 + offset;
3035 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3036 MDIO_AER_BLOCK_AER_REG, aer_val);
3040 /******************************************************************/
3041 /* Internal phy section */
3042 /******************************************************************/
3044 static void elink_set_serdes_access(struct bnx2x_softc *sc, uint8_t port)
3046 uint32_t emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3049 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 1);
3050 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3052 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3055 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 0);
3058 static void elink_serdes_deassert(struct bnx2x_softc *sc, uint8_t port)
3062 PMD_DRV_LOG(DEBUG, "elink_serdes_deassert");
3064 val = ELINK_SERDES_RESET_BITS << (port * 16);
3066 /* Reset and unreset the SerDes/XGXS */
3067 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3069 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3071 elink_set_serdes_access(sc, port);
3073 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port * 0x10,
3074 ELINK_DEFAULT_PHY_DEV_ADDR);
3077 static void elink_xgxs_specific_func(struct elink_phy *phy,
3078 struct elink_params *params,
3081 struct bnx2x_softc *sc = params->sc;
3083 case ELINK_PHY_INIT:
3084 /* Set correct devad */
3085 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port * 0x18, 0);
3086 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port * 0x18,
3092 static void elink_xgxs_deassert(struct elink_params *params)
3094 struct bnx2x_softc *sc = params->sc;
3097 PMD_DRV_LOG(DEBUG, "elink_xgxs_deassert");
3098 port = params->port;
3100 val = ELINK_XGXS_RESET_BITS << (port * 16);
3102 /* Reset and unreset the SerDes/XGXS */
3103 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3105 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3106 elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params,
3110 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
3111 struct elink_params *params,
3114 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3115 /* Resolve pause mode and advertisement Please refer to Table
3116 * 28B-3 of the 802.3ab-1999 spec
3119 switch (phy->req_flow_ctrl) {
3120 case ELINK_FLOW_CTRL_AUTO:
3121 switch (params->req_fc_auto_adv) {
3122 case ELINK_FLOW_CTRL_BOTH:
3123 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3125 case ELINK_FLOW_CTRL_RX:
3126 case ELINK_FLOW_CTRL_TX:
3128 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3134 case ELINK_FLOW_CTRL_TX:
3135 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3138 case ELINK_FLOW_CTRL_RX:
3139 case ELINK_FLOW_CTRL_BOTH:
3140 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3143 case ELINK_FLOW_CTRL_NONE:
3145 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3148 PMD_DRV_LOG(DEBUG, "ieee_fc = 0x%x", *ieee_fc);
3151 static void set_phy_vars(struct elink_params *params, struct elink_vars *vars)
3153 uint8_t actual_phy_idx, phy_index, link_cfg_idx;
3154 uint8_t phy_config_swapped = params->multi_phy_config &
3155 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3156 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
3158 link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index);
3159 actual_phy_idx = phy_index;
3160 if (phy_config_swapped) {
3161 if (phy_index == ELINK_EXT_PHY1)
3162 actual_phy_idx = ELINK_EXT_PHY2;
3163 else if (phy_index == ELINK_EXT_PHY2)
3164 actual_phy_idx = ELINK_EXT_PHY1;
3166 params->phy[actual_phy_idx].req_flow_ctrl =
3167 params->req_flow_ctrl[link_cfg_idx];
3169 params->phy[actual_phy_idx].req_line_speed =
3170 params->req_line_speed[link_cfg_idx];
3172 params->phy[actual_phy_idx].speed_cap_mask =
3173 params->speed_cap_mask[link_cfg_idx];
3175 params->phy[actual_phy_idx].req_duplex =
3176 params->req_duplex[link_cfg_idx];
3178 if (params->req_line_speed[link_cfg_idx] ==
3179 ELINK_SPEED_AUTO_NEG)
3180 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3182 PMD_DRV_LOG(DEBUG, "req_flow_ctrl %x, req_line_speed %x,"
3183 " speed_cap_mask %x",
3184 params->phy[actual_phy_idx].req_flow_ctrl,
3185 params->phy[actual_phy_idx].req_line_speed,
3186 params->phy[actual_phy_idx].speed_cap_mask);
3190 static void elink_ext_phy_set_pause(struct elink_params *params,
3191 struct elink_phy *phy,
3192 struct elink_vars *vars)
3195 struct bnx2x_softc *sc = params->sc;
3196 /* Read modify write pause advertizing */
3197 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3199 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3201 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3202 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3203 if ((vars->ieee_fc &
3204 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3205 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3206 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3208 if ((vars->ieee_fc &
3209 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3210 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3211 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3213 PMD_DRV_LOG(DEBUG, "Ext phy AN advertize 0x%x", val);
3214 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3217 static void elink_pause_resolve(struct elink_vars *vars, uint32_t pause_result)
3219 switch (pause_result) { /* ASYM P ASYM P */
3220 case 0xb: /* 1 0 1 1 */
3221 vars->flow_ctrl = ELINK_FLOW_CTRL_TX;
3224 case 0xe: /* 1 1 1 0 */
3225 vars->flow_ctrl = ELINK_FLOW_CTRL_RX;
3228 case 0x5: /* 0 1 0 1 */
3229 case 0x7: /* 0 1 1 1 */
3230 case 0xd: /* 1 1 0 1 */
3231 case 0xf: /* 1 1 1 1 */
3232 vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH;
3238 if (pause_result & (1 << 0))
3239 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3240 if (pause_result & (1 << 1))
3241 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3245 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
3246 struct elink_params *params,
3247 struct elink_vars *vars)
3249 uint16_t ld_pause; /* local */
3250 uint16_t lp_pause; /* link partner */
3251 uint16_t pause_result;
3252 struct bnx2x_softc *sc = params->sc;
3253 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) {
3254 elink_cl22_read(sc, phy, 0x4, &ld_pause);
3255 elink_cl22_read(sc, phy, 0x5, &lp_pause);
3256 } else if (CHIP_IS_E3(sc) && ELINK_SINGLE_MEDIA_DIRECT(params)) {
3257 uint8_t lane = elink_get_warpcore_lane(params);
3258 uint16_t gp_status, gp_mask;
3259 elink_cl45_read(sc, phy,
3260 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3262 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3263 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3265 if ((gp_status & gp_mask) == gp_mask) {
3266 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3267 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3268 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3269 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3271 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3272 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3273 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3274 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3275 ld_pause = ((ld_pause &
3276 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3278 lp_pause = ((lp_pause &
3279 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3283 elink_cl45_read(sc, phy,
3285 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3286 elink_cl45_read(sc, phy,
3288 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3290 pause_result = (ld_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3291 pause_result |= (lp_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3292 PMD_DRV_LOG(DEBUG, "Ext PHY pause result 0x%x", pause_result);
3293 elink_pause_resolve(vars, pause_result);
3297 static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
3298 struct elink_params *params,
3299 struct elink_vars *vars)
3302 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
3303 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
3304 /* Update the advertised flow-controled of LD/LP in AN */
3305 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
3306 elink_ext_phy_update_adv_fc(phy, params, vars);
3307 /* But set the flow-control result as the requested one */
3308 vars->flow_ctrl = phy->req_flow_ctrl;
3309 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
3310 vars->flow_ctrl = params->req_fc_auto_adv;
3311 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3313 elink_ext_phy_update_adv_fc(phy, params, vars);
3318 /******************************************************************/
3319 /* Warpcore section */
3320 /******************************************************************/
3321 /* The init_internal_warpcore should mirror the xgxs,
3322 * i.e. reset the lane (if needed), set aer for the
3323 * init configuration, and set/clear SGMII flag. Internal
3324 * phy init is done purely in phy_init stage.
3326 #define WC_TX_DRIVER(post2, idriver, ipre) \
3327 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3328 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3329 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3331 #define WC_TX_FIR(post, main, pre) \
3332 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3333 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3334 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3336 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
3337 struct elink_params *params,
3338 struct elink_vars *vars)
3340 struct bnx2x_softc *sc = params->sc;
3342 static struct elink_reg_set reg_set[] = {
3343 /* Step 1 - Program the TX/RX alignment markers */
3344 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3345 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3346 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3347 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3348 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3349 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3350 /* Step 2 - Configure the NP registers */
3351 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3352 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3353 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3354 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3355 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3356 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3357 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3358 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3359 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3361 PMD_DRV_LOG(DEBUG, "Enabling 20G-KR2");
3363 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3364 MDIO_WC_REG_CL49_USERB0_CTRL, (3 << 6));
3366 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3367 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3370 /* Start KR2 work-around timer which handles BNX2X8073 link-parner */
3371 vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3372 elink_update_link_attr(params, vars->link_attr_sync);
3375 static void elink_disable_kr2(struct elink_params *params,
3376 struct elink_vars *vars, struct elink_phy *phy)
3378 struct bnx2x_softc *sc = params->sc;
3380 static struct elink_reg_set reg_set[] = {
3381 /* Step 1 - Program the TX/RX alignment markers */
3382 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3383 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3384 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3385 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3386 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3387 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3388 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3389 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3390 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3391 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3392 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3393 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3394 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3395 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3396 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3398 PMD_DRV_LOG(DEBUG, "Disabling 20G-KR2");
3400 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3401 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3403 vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3404 elink_update_link_attr(params, vars->link_attr_sync);
3406 vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT;
3409 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,
3410 struct elink_params *params)
3412 struct bnx2x_softc *sc = params->sc;
3414 PMD_DRV_LOG(DEBUG, "Configure WC for LPI pass through");
3415 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3416 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3417 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3418 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3421 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,
3422 struct elink_params *params)
3424 /* Restart autoneg on the leading lane only */
3425 struct bnx2x_softc *sc = params->sc;
3426 uint16_t lane = elink_get_warpcore_lane(params);
3427 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3428 MDIO_AER_BLOCK_AER_REG, lane);
3429 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3430 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3433 elink_set_aer_mmd(params, phy);
3436 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
3437 struct elink_params *params,
3438 struct elink_vars *vars)
3440 uint16_t lane, i, cl72_ctrl, an_adv = 0;
3441 struct bnx2x_softc *sc = params->sc;
3442 static struct elink_reg_set reg_set[] = {
3443 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3444 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3445 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3446 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3447 /* Disable Autoneg: re-enable it after adv is done. */
3448 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3449 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3450 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3452 PMD_DRV_LOG(DEBUG, "Enable Auto Negotiation for KR");
3453 /* Set to default registers that may be overriden by 10G force */
3454 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3455 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3458 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3459 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3460 cl72_ctrl &= 0x08ff;
3461 cl72_ctrl |= 0x3800;
3462 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3463 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3465 /* Check adding advertisement for 1G KX */
3466 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
3467 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3468 (vars->line_speed == ELINK_SPEED_1000)) {
3469 uint16_t addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3472 /* Enable CL37 1G Parallel Detect */
3473 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);
3474 PMD_DRV_LOG(DEBUG, "Advertize 1G");
3476 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
3477 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3478 (vars->line_speed == ELINK_SPEED_10000)) {
3479 /* Check adding advertisement for 10G KR */
3481 /* Enable 10G Parallel Detect */
3482 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3483 MDIO_AER_BLOCK_AER_REG, 0);
3485 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3486 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3487 elink_set_aer_mmd(params, phy);
3488 PMD_DRV_LOG(DEBUG, "Advertize 10G");
3491 /* Set Transmit PMD settings */
3492 lane = elink_get_warpcore_lane(params);
3493 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3494 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
3495 WC_TX_DRIVER(0x02, 0x06, 0x09));
3496 /* Configure the next lane if dual mode */
3497 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
3498 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3499 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * (lane + 1),
3500 WC_TX_DRIVER(0x02, 0x06, 0x09));
3501 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3502 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 0x03f0);
3503 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3504 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 0x03f0);
3506 /* Advertised speeds */
3507 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3508 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3510 /* Advertised and set FEC (Forward Error Correction) */
3511 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3512 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3513 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3514 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3516 /* Enable CL37 BAM */
3517 if (REG_RD(sc, params->shmem_base +
3518 offsetof(struct shmem_region,
3519 dev_info.port_hw_config[params->port].
3521 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3522 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3523 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3525 PMD_DRV_LOG(DEBUG, "Enable CL37 BAM on KR");
3528 /* Advertise pause */
3529 elink_ext_phy_set_pause(params, phy, vars);
3530 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3531 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3532 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3534 /* Over 1G - AN local device user page 1 */
3535 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3536 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3538 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
3539 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3540 (phy->req_line_speed == ELINK_SPEED_20000)) {
3542 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3543 MDIO_AER_BLOCK_AER_REG, lane);
3545 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3546 MDIO_WC_REG_RX1_PCI_CTRL +
3547 (0x10 * lane), (1 << 11));
3549 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3550 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3551 elink_set_aer_mmd(params, phy);
3553 elink_warpcore_enable_AN_KR2(phy, params, vars);
3555 elink_disable_kr2(params, vars, phy);
3558 /* Enable Autoneg: only on the main lane */
3559 elink_warpcore_restart_AN_KR(phy, params);
3562 static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
3563 struct elink_params *params)
3565 struct bnx2x_softc *sc = params->sc;
3566 uint16_t val16, i, lane;
3567 static struct elink_reg_set reg_set[] = {
3568 /* Disable Autoneg */
3569 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3570 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3572 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3573 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3574 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3575 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3576 /* Leave cl72 training enable, needed for KR */
3577 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3580 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3581 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3584 lane = elink_get_warpcore_lane(params);
3585 /* Global registers */
3586 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3587 MDIO_AER_BLOCK_AER_REG, 0);
3588 /* Disable CL36 PCS Tx */
3589 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3590 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3591 val16 &= ~(0x0011 << lane);
3592 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3593 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3595 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3596 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3597 val16 |= (0x0303 << (lane << 1));
3598 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3599 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3601 elink_set_aer_mmd(params, phy);
3602 /* Set speed via PMA/PMD register */
3603 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
3604 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3606 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
3607 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3609 /* Enable encoded forced speed */
3610 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3611 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3613 /* Turn TX scramble payload only the 64/66 scrambler */
3614 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX66_CONTROL, 0x9);
3616 /* Turn RX scramble payload only the 64/66 scrambler */
3617 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3618 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3620 /* Set and clear loopback to cause a reset to 64/66 decoder */
3621 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3622 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3623 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3624 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3628 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,
3629 struct elink_params *params,
3632 struct bnx2x_softc *sc = params->sc;
3633 uint16_t misc1_val, tap_val, tx_driver_val, lane, val;
3634 uint32_t cfg_tap_val, tx_drv_brdct, tx_equal;
3636 /* Hold rxSeqStart */
3637 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3638 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3640 /* Hold tx_fifo_reset */
3641 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3642 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3644 /* Disable CL73 AN */
3645 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3647 /* Disable 100FX Enable and Auto-Detect */
3648 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3649 MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3651 /* Disable 100FX Idle detect */
3652 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3653 MDIO_WC_REG_FX100_CTRL3, 0x0080);
3655 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3656 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3657 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3659 /* Turn off auto-detect & fiber mode */
3660 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3661 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3664 /* Set filter_force_link, disable_false_link and parallel_detect */
3665 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3666 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3667 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3668 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3669 ((val | 0x0006) & 0xFFFE));
3672 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3673 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3675 misc1_val &= ~(0x1f);
3679 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
3680 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
3682 cfg_tap_val = REG_RD(sc, params->shmem_base +
3683 offsetof(struct shmem_region,
3684 dev_info.port_hw_config[params->
3685 port].sfi_tap_values));
3687 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
3689 tx_drv_brdct = (cfg_tap_val &
3690 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
3691 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
3695 /* TAP values are controlled by nvram, if value there isn't 0 */
3697 tap_val = (uint16_t) tx_equal;
3699 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
3703 WC_TX_DRIVER(0x03, (uint16_t) tx_drv_brdct, 0x06);
3705 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
3707 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3708 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3710 /* Set Transmit PMD settings */
3711 lane = elink_get_warpcore_lane(params);
3712 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3713 MDIO_WC_REG_TX_FIR_TAP,
3714 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3715 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3716 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
3719 /* Enable fiber mode, enable and invert sig_det */
3720 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3721 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
3723 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3724 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3725 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
3727 elink_warpcore_set_lpi_passthrough(phy, params);
3729 /* 10G XFI Full Duplex */
3730 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3731 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3733 /* Release tx_fifo_reset */
3734 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3735 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
3737 /* Release rxSeqStart */
3738 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3739 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
3742 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,
3743 struct elink_params *params)
3746 struct bnx2x_softc *sc = params->sc;
3747 /* Set global registers, so set AER lane to 0 */
3748 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3749 MDIO_AER_BLOCK_AER_REG, 0);
3751 /* Disable sequencer */
3752 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3753 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1 << 13));
3755 elink_set_aer_mmd(params, phy);
3757 elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,
3758 MDIO_WC_REG_PMD_KR_CONTROL, ~(1 << 1));
3759 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3761 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3762 MDIO_WC_REG_CL73_USERB0_CTRL, &val);
3765 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3766 MDIO_WC_REG_CL73_USERB0_CTRL, val);
3768 /* Set 20G KR2 force speed */
3769 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3770 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
3772 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3773 MDIO_WC_REG_DIGITAL4_MISC3, (1 << 7));
3775 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3776 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
3779 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3780 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
3781 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3782 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
3784 /* Enable sequencer (over lane 0) */
3785 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3786 MDIO_AER_BLOCK_AER_REG, 0);
3788 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3789 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1 << 13));
3791 elink_set_aer_mmd(params, phy);
3794 static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc,
3795 struct elink_phy *phy, uint16_t lane)
3797 /* Rx0 anaRxControl1G */
3798 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3799 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3801 /* Rx2 anaRxControl1G */
3802 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3803 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3805 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW0, 0xE070);
3807 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3809 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3811 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW3, 0x8090);
3813 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3814 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
3816 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3817 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
3819 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3820 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
3822 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3823 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
3825 /* Serdes Digital Misc1 */
3826 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3827 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
3829 /* Serdes Digital4 Misc3 */
3830 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3831 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
3833 /* Set Transmit PMD settings */
3834 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3835 MDIO_WC_REG_TX_FIR_TAP,
3836 (WC_TX_FIR(0x12, 0x2d, 0x00) |
3837 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3838 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3839 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
3840 WC_TX_DRIVER(0x02, 0x02, 0x02));
3843 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
3844 struct elink_params *params,
3846 uint8_t always_autoneg)
3848 struct bnx2x_softc *sc = params->sc;
3849 uint16_t val16, digctrl_kx1, digctrl_kx2;
3851 /* Clear XFI clock comp in non-10G single lane mode. */
3852 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3853 MDIO_WC_REG_RX66_CONTROL, ~(3 << 13));
3855 elink_warpcore_set_lpi_passthrough(phy, params);
3857 if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
3859 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3860 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
3862 PMD_DRV_LOG(DEBUG, "set SGMII AUTONEG");
3864 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3865 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3867 switch (phy->req_line_speed) {
3868 case ELINK_SPEED_10:
3870 case ELINK_SPEED_100:
3873 case ELINK_SPEED_1000:
3878 "Speed not supported: 0x%x",
3879 phy->req_line_speed);
3883 if (phy->req_duplex == DUPLEX_FULL)
3886 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3887 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
3889 PMD_DRV_LOG(DEBUG, "set SGMII force speed %d",
3890 phy->req_line_speed);
3891 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3892 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3893 PMD_DRV_LOG(DEBUG, " (readback) %x", val16);
3896 /* SGMII Slave mode and disable signal detect */
3897 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3898 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
3902 digctrl_kx1 &= 0xff4a;
3904 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3905 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, digctrl_kx1);
3907 /* Turn off parallel detect */
3908 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3909 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
3910 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3911 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3912 (digctrl_kx2 & ~(1 << 2)));
3914 /* Re-enable parallel detect */
3915 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3916 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3917 (digctrl_kx2 | (1 << 2)));
3919 /* Enable autodet */
3920 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3921 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3922 (digctrl_kx1 | 0x10));
3925 static void elink_warpcore_reset_lane(struct bnx2x_softc *sc,
3926 struct elink_phy *phy, uint8_t reset)
3929 /* Take lane out of reset after configuration is finished */
3930 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3931 MDIO_WC_REG_DIGITAL5_MISC6, &val);
3936 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3937 MDIO_WC_REG_DIGITAL5_MISC6, val);
3938 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3939 MDIO_WC_REG_DIGITAL5_MISC6, &val);
3942 /* Clear SFI/XFI link settings registers */
3943 static void elink_warpcore_clear_regs(struct elink_phy *phy,
3944 struct elink_params *params,
3947 struct bnx2x_softc *sc = params->sc;
3949 static struct elink_reg_set wc_regs[] = {
3950 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
3951 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
3952 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
3953 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
3954 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3956 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3958 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
3960 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
3961 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
3962 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
3963 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
3965 /* Set XFI clock comp as default. */
3966 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3967 MDIO_WC_REG_RX66_CONTROL, (3 << 13));
3969 for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
3970 elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,
3973 lane = elink_get_warpcore_lane(params);
3974 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3975 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, 0x0990);
3979 static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc,
3980 uint32_t shmem_base,
3983 uint8_t * gpio_port)
3988 if (CHIP_IS_E3(sc)) {
3989 cfg_pin = (REG_RD(sc, shmem_base +
3990 offsetof(struct shmem_region,
3991 dev_info.port_hw_config[port].
3993 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
3994 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
3996 /* Should not happen. This function called upon interrupt
3997 * triggered by GPIO ( since EPIO can only generate interrupts
3999 * So if this function was called and none of the GPIOs was set,
4000 * it means the shit hit the fan.
4002 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4003 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4005 "No cfg pin %x for module detect indication",
4007 return ELINK_STATUS_ERROR;
4010 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4011 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4013 *gpio_num = MISC_REGISTERS_GPIO_3;
4017 return ELINK_STATUS_OK;
4020 static int elink_is_sfp_module_plugged(struct elink_params *params)
4022 struct bnx2x_softc *sc = params->sc;
4023 uint8_t gpio_num, gpio_port;
4025 if (elink_get_mod_abs_int_cfg(sc,
4026 params->shmem_base, params->port,
4027 &gpio_num, &gpio_port) != ELINK_STATUS_OK)
4029 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
4031 /* Call the handling function in case module is detected */
4038 static int elink_warpcore_get_sigdet(struct elink_phy *phy,
4039 struct elink_params *params)
4041 uint16_t gp2_status_reg0, lane;
4042 struct bnx2x_softc *sc = params->sc;
4044 lane = elink_get_warpcore_lane(params);
4046 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4049 return (gp2_status_reg0 >> (8 + lane)) & 0x1;
4052 static void elink_warpcore_config_runtime(struct elink_phy *phy,
4053 struct elink_params *params,
4054 struct elink_vars *vars)
4056 struct bnx2x_softc *sc = params->sc;
4057 uint32_t serdes_net_if;
4058 uint16_t gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4060 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4062 if (!vars->turn_to_run_wc_rt)
4065 if (vars->rx_tx_asic_rst) {
4066 uint16_t lane = elink_get_warpcore_lane(params);
4067 serdes_net_if = (REG_RD(sc, params->shmem_base +
4068 offsetof(struct shmem_region,
4069 dev_info.port_hw_config
4072 PORT_HW_CFG_NET_SERDES_IF_MASK);
4074 switch (serdes_net_if) {
4075 case PORT_HW_CFG_NET_SERDES_IF_KR:
4076 /* Do we get link yet? */
4077 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,
4079 lnkup = (gp_status1 >> (8 + lane)) & 0x1; /* 1G */
4081 lnkup_kr = (gp_status1 >> (12 + lane)) & 0x1;
4083 if (lnkup_kr || lnkup) {
4084 vars->rx_tx_asic_rst = 0;
4086 /* Reset the lane to see if link comes up. */
4087 elink_warpcore_reset_lane(sc, phy, 1);
4088 elink_warpcore_reset_lane(sc, phy, 0);
4090 /* Restart Autoneg */
4091 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4092 MDIO_WC_REG_IEEE0BLK_MIICNTL,
4095 vars->rx_tx_asic_rst--;
4096 PMD_DRV_LOG(DEBUG, "0x%x retry left",
4097 vars->rx_tx_asic_rst);
4106 /*params->rx_tx_asic_rst */
4109 static void elink_warpcore_config_sfi(struct elink_phy *phy,
4110 struct elink_params *params)
4112 uint16_t lane = elink_get_warpcore_lane(params);
4114 elink_warpcore_clear_regs(phy, params, lane);
4115 if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] ==
4116 ELINK_SPEED_10000) &&
4117 (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {
4118 PMD_DRV_LOG(DEBUG, "Setting 10G SFI");
4119 elink_warpcore_set_10G_XFI(phy, params, 0);
4121 PMD_DRV_LOG(DEBUG, "Setting 1G Fiber");
4122 elink_warpcore_set_sgmii_speed(phy, params, 1, 0);
4126 static void elink_sfp_e3_set_transmitter(struct elink_params *params,
4127 struct elink_phy *phy, uint8_t tx_en)
4129 struct bnx2x_softc *sc = params->sc;
4131 uint8_t port = params->port;
4133 cfg_pin = REG_RD(sc, params->shmem_base +
4134 offsetof(struct shmem_region,
4135 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4136 PORT_HW_CFG_E3_TX_LASER_MASK;
4137 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4138 PMD_DRV_LOG(DEBUG, "Setting WC TX to %d", tx_en);
4140 /* For 20G, the expected pin to be used is 3 pins after the current */
4141 elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1);
4142 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4143 elink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1);
4146 static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
4147 struct elink_params *params,
4148 struct elink_vars *vars)
4150 struct bnx2x_softc *sc = params->sc;
4151 uint32_t serdes_net_if;
4153 uint16_t lane = elink_get_warpcore_lane(params);
4154 serdes_net_if = (REG_RD(sc, params->shmem_base +
4155 offsetof(struct shmem_region,
4156 dev_info.port_hw_config[params->port].
4158 PORT_HW_CFG_NET_SERDES_IF_MASK);
4160 "Begin Warpcore init, link_speed %d, "
4161 "serdes_net_if = 0x%x", vars->line_speed, serdes_net_if);
4162 elink_set_aer_mmd(params, phy);
4163 elink_warpcore_reset_lane(sc, phy, 1);
4164 vars->phy_flags |= PHY_XGXS_FLAG;
4165 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4166 (phy->req_line_speed &&
4167 ((phy->req_line_speed == ELINK_SPEED_100) ||
4168 (phy->req_line_speed == ELINK_SPEED_10)))) {
4169 vars->phy_flags |= PHY_SGMII_FLAG;
4170 PMD_DRV_LOG(DEBUG, "Setting SGMII mode");
4171 elink_warpcore_clear_regs(phy, params, lane);
4172 elink_warpcore_set_sgmii_speed(phy, params, 0, 1);
4174 switch (serdes_net_if) {
4175 case PORT_HW_CFG_NET_SERDES_IF_KR:
4176 /* Enable KR Auto Neg */
4177 if (params->loopback_mode != ELINK_LOOPBACK_EXT)
4178 elink_warpcore_enable_AN_KR(phy, params, vars);
4180 PMD_DRV_LOG(DEBUG, "Setting KR 10G-Force");
4181 elink_warpcore_set_10G_KR(phy, params);
4185 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4186 elink_warpcore_clear_regs(phy, params, lane);
4187 if (vars->line_speed == ELINK_SPEED_10000) {
4188 PMD_DRV_LOG(DEBUG, "Setting 10G XFI");
4189 elink_warpcore_set_10G_XFI(phy, params, 1);
4191 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
4192 PMD_DRV_LOG(DEBUG, "1G Fiber");
4195 PMD_DRV_LOG(DEBUG, "10/100/1G SGMII");
4198 elink_warpcore_set_sgmii_speed(phy,
4205 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4206 /* Issue Module detection if module is plugged, or
4207 * enabled transmitter to avoid current leakage in case
4208 * no module is connected
4210 if ((params->loopback_mode == ELINK_LOOPBACK_NONE) ||
4211 (params->loopback_mode == ELINK_LOOPBACK_EXT)) {
4212 if (elink_is_sfp_module_plugged(params))
4213 elink_sfp_module_detection(phy, params);
4215 elink_sfp_e3_set_transmitter(params,
4219 elink_warpcore_config_sfi(phy, params);
4222 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4223 if (vars->line_speed != ELINK_SPEED_20000) {
4224 PMD_DRV_LOG(DEBUG, "Speed not supported yet");
4227 PMD_DRV_LOG(DEBUG, "Setting 20G DXGXS");
4228 elink_warpcore_set_20G_DXGXS(sc, phy, lane);
4229 /* Issue Module detection */
4231 elink_sfp_module_detection(phy, params);
4233 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4234 if (!params->loopback_mode) {
4235 elink_warpcore_enable_AN_KR(phy, params, vars);
4237 PMD_DRV_LOG(DEBUG, "Setting KR 20G-Force");
4238 elink_warpcore_set_20G_force_KR2(phy, params);
4243 "Unsupported Serdes Net Interface 0x%x",
4249 /* Take lane out of reset after configuration is finished */
4250 elink_warpcore_reset_lane(sc, phy, 0);
4251 PMD_DRV_LOG(DEBUG, "Exit config init");
4256 static void elink_warpcore_link_reset(struct elink_phy *phy,
4257 struct elink_params *params)
4259 struct bnx2x_softc *sc = params->sc;
4260 uint16_t val16, lane;
4261 elink_sfp_e3_set_transmitter(params, phy, 0);
4262 elink_set_mdio_emac_per_phy(sc, params);
4263 elink_set_aer_mmd(params, phy);
4264 /* Global register */
4265 elink_warpcore_reset_lane(sc, phy, 1);
4267 /* Clear loopback settings (if any) */
4269 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4270 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4272 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4273 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4275 /* Update those 1-copy registers */
4276 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4277 MDIO_AER_BLOCK_AER_REG, 0);
4278 /* Enable 1G MDIO (1-copy) */
4279 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4280 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~0x10);
4282 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4283 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4284 lane = elink_get_warpcore_lane(params);
4285 /* Disable CL36 PCS Tx */
4286 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4287 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4288 val16 |= (0x11 << lane);
4289 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4290 val16 |= (0x22 << lane);
4291 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4292 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4294 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4295 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4296 val16 &= ~(0x0303 << (lane << 1));
4297 val16 |= (0x0101 << (lane << 1));
4298 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) {
4299 val16 &= ~(0x0c0c << (lane << 1));
4300 val16 |= (0x0404 << (lane << 1));
4303 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4304 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4306 elink_set_aer_mmd(params, phy);
4310 static void elink_set_warpcore_loopback(struct elink_phy *phy,
4311 struct elink_params *params)
4313 struct bnx2x_softc *sc = params->sc;
4316 PMD_DRV_LOG(DEBUG, "Setting Warpcore loopback type %x, speed %d",
4317 params->loopback_mode, phy->req_line_speed);
4319 if (phy->req_line_speed < ELINK_SPEED_10000 ||
4320 phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
4321 /* 10/100/1000/20G-KR2 */
4323 /* Update those 1-copy registers */
4324 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4325 MDIO_AER_BLOCK_AER_REG, 0);
4326 /* Enable 1G MDIO (1-copy) */
4327 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4328 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4330 /* Set 1G loopback based on lane (1-copy) */
4331 lane = elink_get_warpcore_lane(params);
4332 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4333 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4334 val16 |= (1 << lane);
4335 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4336 val16 |= (2 << lane);
4337 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4338 MDIO_WC_REG_XGXSBLK1_LANECTRL2, val16);
4340 /* Switch back to 4-copy registers */
4341 elink_set_aer_mmd(params, phy);
4343 /* 10G / 20G-DXGXS */
4344 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4345 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4347 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4348 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4352 static void elink_sync_link(struct elink_params *params,
4353 struct elink_vars *vars)
4355 struct bnx2x_softc *sc = params->sc;
4356 uint8_t link_10g_plus;
4357 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4358 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4359 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4360 if (vars->link_up) {
4361 PMD_DRV_LOG(DEBUG, "phy link up");
4363 vars->phy_link_up = 1;
4364 vars->duplex = DUPLEX_FULL;
4365 switch (vars->link_status & LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4366 case ELINK_LINK_10THD:
4367 vars->duplex = DUPLEX_HALF;
4369 case ELINK_LINK_10TFD:
4370 vars->line_speed = ELINK_SPEED_10;
4373 case ELINK_LINK_100TXHD:
4374 vars->duplex = DUPLEX_HALF;
4376 case ELINK_LINK_100T4:
4377 case ELINK_LINK_100TXFD:
4378 vars->line_speed = ELINK_SPEED_100;
4381 case ELINK_LINK_1000THD:
4382 vars->duplex = DUPLEX_HALF;
4384 case ELINK_LINK_1000TFD:
4385 vars->line_speed = ELINK_SPEED_1000;
4388 case ELINK_LINK_2500THD:
4389 vars->duplex = DUPLEX_HALF;
4391 case ELINK_LINK_2500TFD:
4392 vars->line_speed = ELINK_SPEED_2500;
4395 case ELINK_LINK_10GTFD:
4396 vars->line_speed = ELINK_SPEED_10000;
4398 case ELINK_LINK_20GTFD:
4399 vars->line_speed = ELINK_SPEED_20000;
4404 vars->flow_ctrl = 0;
4405 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4406 vars->flow_ctrl |= ELINK_FLOW_CTRL_TX;
4408 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4409 vars->flow_ctrl |= ELINK_FLOW_CTRL_RX;
4411 if (!vars->flow_ctrl)
4412 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4414 if (vars->line_speed &&
4415 ((vars->line_speed == ELINK_SPEED_10) ||
4416 (vars->line_speed == ELINK_SPEED_100))) {
4417 vars->phy_flags |= PHY_SGMII_FLAG;
4419 vars->phy_flags &= ~PHY_SGMII_FLAG;
4421 if (vars->line_speed &&
4422 USES_WARPCORE(sc) && (vars->line_speed == ELINK_SPEED_1000))
4423 vars->phy_flags |= PHY_SGMII_FLAG;
4424 /* Anything 10 and over uses the bmac */
4425 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
4427 if (link_10g_plus) {
4428 if (USES_WARPCORE(sc))
4429 vars->mac_type = ELINK_MAC_TYPE_XMAC;
4431 vars->mac_type = ELINK_MAC_TYPE_BMAC;
4433 if (USES_WARPCORE(sc))
4434 vars->mac_type = ELINK_MAC_TYPE_UMAC;
4436 vars->mac_type = ELINK_MAC_TYPE_EMAC;
4438 } else { /* Link down */
4439 PMD_DRV_LOG(DEBUG, "phy link down");
4441 vars->phy_link_up = 0;
4443 vars->line_speed = 0;
4444 vars->duplex = DUPLEX_FULL;
4445 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4447 /* Indicate no mac active */
4448 vars->mac_type = ELINK_MAC_TYPE_NONE;
4449 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4450 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4451 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4452 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4456 void elink_link_status_update(struct elink_params *params,
4457 struct elink_vars *vars)
4459 struct bnx2x_softc *sc = params->sc;
4460 uint8_t port = params->port;
4461 uint32_t sync_offset, media_types;
4462 /* Update PHY configuration */
4463 set_phy_vars(params, vars);
4465 vars->link_status = REG_RD(sc, params->shmem_base +
4466 offsetof(struct shmem_region,
4467 port_mb[port].link_status));
4469 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4470 if (params->loopback_mode != ELINK_LOOPBACK_NONE &&
4471 params->loopback_mode != ELINK_LOOPBACK_EXT)
4472 vars->link_status |= LINK_STATUS_LINK_UP;
4474 if (elink_eee_has_cap(params))
4475 vars->eee_status = REG_RD(sc, params->shmem2_base +
4476 offsetof(struct shmem2_region,
4477 eee_status[params->port]));
4479 vars->phy_flags = PHY_XGXS_FLAG;
4480 elink_sync_link(params, vars);
4481 /* Sync media type */
4482 sync_offset = params->shmem_base +
4483 offsetof(struct shmem_region,
4484 dev_info.port_hw_config[port].media_type);
4485 media_types = REG_RD(sc, sync_offset);
4487 params->phy[ELINK_INT_PHY].media_type =
4488 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4489 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4490 params->phy[ELINK_EXT_PHY1].media_type =
4491 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4492 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4493 params->phy[ELINK_EXT_PHY2].media_type =
4494 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4495 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4496 PMD_DRV_LOG(DEBUG, "media_types = 0x%x", media_types);
4498 /* Sync AEU offset */
4499 sync_offset = params->shmem_base +
4500 offsetof(struct shmem_region,
4501 dev_info.port_hw_config[port].aeu_int_mask);
4503 vars->aeu_int_mask = REG_RD(sc, sync_offset);
4505 /* Sync PFC status */
4506 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4507 params->feature_config_flags |=
4508 ELINK_FEATURE_CONFIG_PFC_ENABLED;
4510 params->feature_config_flags &=
4511 ~ELINK_FEATURE_CONFIG_PFC_ENABLED;
4513 if (SHMEM2_HAS(sc, link_attr_sync))
4514 vars->link_attr_sync = SHMEM2_RD(sc,
4515 link_attr_sync[params->port]);
4517 PMD_DRV_LOG(DEBUG, "link_status 0x%x phy_link_up %x int_mask 0x%x",
4518 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4519 PMD_DRV_LOG(DEBUG, "line_speed %x duplex %x flow_ctrl 0x%x",
4520 vars->line_speed, vars->duplex, vars->flow_ctrl);
4523 static void elink_set_master_ln(struct elink_params *params,
4524 struct elink_phy *phy)
4526 struct bnx2x_softc *sc = params->sc;
4527 uint16_t new_master_ln, ser_lane;
4528 ser_lane = ((params->lane_config &
4529 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4530 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4532 /* Set the master_ln for AN */
4533 CL22_RD_OVER_CL45(sc, phy,
4534 MDIO_REG_BANK_XGXS_BLOCK2,
4535 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, &new_master_ln);
4537 CL22_WR_OVER_CL45(sc, phy,
4538 MDIO_REG_BANK_XGXS_BLOCK2,
4539 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4540 (new_master_ln | ser_lane));
4543 static elink_status_t elink_reset_unicore(struct elink_params *params,
4544 struct elink_phy *phy,
4547 struct bnx2x_softc *sc = params->sc;
4548 uint16_t mii_control;
4550 CL22_RD_OVER_CL45(sc, phy,
4551 MDIO_REG_BANK_COMBO_IEEE0,
4552 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4554 /* Reset the unicore */
4555 CL22_WR_OVER_CL45(sc, phy,
4556 MDIO_REG_BANK_COMBO_IEEE0,
4557 MDIO_COMBO_IEEE0_MII_CONTROL,
4558 (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4560 elink_set_serdes_access(sc, params->port);
4562 /* Wait for the reset to self clear */
4563 for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) {
4566 /* The reset erased the previous bank value */
4567 CL22_RD_OVER_CL45(sc, phy,
4568 MDIO_REG_BANK_COMBO_IEEE0,
4569 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4571 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4573 return ELINK_STATUS_OK;
4577 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
4580 PMD_DRV_LOG(DEBUG, "BUG! XGXS is still in reset!");
4581 return ELINK_STATUS_ERROR;
4585 static void elink_set_swap_lanes(struct elink_params *params,
4586 struct elink_phy *phy)
4588 struct bnx2x_softc *sc = params->sc;
4589 /* Each two bits represents a lane number:
4590 * No swap is 0123 => 0x1b no need to enable the swap
4592 uint16_t rx_lane_swap, tx_lane_swap;
4594 rx_lane_swap = ((params->lane_config &
4595 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4596 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4597 tx_lane_swap = ((params->lane_config &
4598 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4599 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4601 if (rx_lane_swap != 0x1b) {
4602 CL22_WR_OVER_CL45(sc, phy,
4603 MDIO_REG_BANK_XGXS_BLOCK2,
4604 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4606 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4607 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4609 CL22_WR_OVER_CL45(sc, phy,
4610 MDIO_REG_BANK_XGXS_BLOCK2,
4611 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4614 if (tx_lane_swap != 0x1b) {
4615 CL22_WR_OVER_CL45(sc, phy,
4616 MDIO_REG_BANK_XGXS_BLOCK2,
4617 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4619 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4621 CL22_WR_OVER_CL45(sc, phy,
4622 MDIO_REG_BANK_XGXS_BLOCK2,
4623 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4627 static void elink_set_parallel_detection(struct elink_phy *phy,
4628 struct elink_params *params)
4630 struct bnx2x_softc *sc = params->sc;
4632 CL22_RD_OVER_CL45(sc, phy,
4633 MDIO_REG_BANK_SERDES_DIGITAL,
4634 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, &control2);
4635 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4636 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4638 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4639 PMD_DRV_LOG(DEBUG, "phy->speed_cap_mask = 0x%x, control2 = 0x%x",
4640 phy->speed_cap_mask, control2);
4641 CL22_WR_OVER_CL45(sc, phy,
4642 MDIO_REG_BANK_SERDES_DIGITAL,
4643 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, control2);
4645 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4646 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4647 PMD_DRV_LOG(DEBUG, "XGXS");
4649 CL22_WR_OVER_CL45(sc, phy,
4650 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4651 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4652 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4654 CL22_RD_OVER_CL45(sc, phy,
4655 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4656 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4660 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4662 CL22_WR_OVER_CL45(sc, phy,
4663 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4664 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4667 /* Disable parallel detection of HiG */
4668 CL22_WR_OVER_CL45(sc, phy,
4669 MDIO_REG_BANK_XGXS_BLOCK2,
4670 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4671 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4672 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4676 static void elink_set_autoneg(struct elink_phy *phy,
4677 struct elink_params *params,
4678 struct elink_vars *vars, uint8_t enable_cl73)
4680 struct bnx2x_softc *sc = params->sc;
4684 CL22_RD_OVER_CL45(sc, phy,
4685 MDIO_REG_BANK_COMBO_IEEE0,
4686 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4688 /* CL37 Autoneg Enabled */
4689 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
4690 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4691 else /* CL37 Autoneg Disabled */
4692 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4693 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4695 CL22_WR_OVER_CL45(sc, phy,
4696 MDIO_REG_BANK_COMBO_IEEE0,
4697 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4699 /* Enable/Disable Autodetection */
4701 CL22_RD_OVER_CL45(sc, phy,
4702 MDIO_REG_BANK_SERDES_DIGITAL,
4703 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
4704 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4705 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4706 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4707 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
4708 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4710 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4712 CL22_WR_OVER_CL45(sc, phy,
4713 MDIO_REG_BANK_SERDES_DIGITAL,
4714 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4716 /* Enable TetonII and BAM autoneg */
4717 CL22_RD_OVER_CL45(sc, phy,
4718 MDIO_REG_BANK_BAM_NEXT_PAGE,
4719 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, ®_val);
4720 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) {
4721 /* Enable BAM aneg Mode and TetonII aneg Mode */
4722 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4723 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4725 /* TetonII and BAM Autoneg Disabled */
4726 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4727 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4729 CL22_WR_OVER_CL45(sc, phy,
4730 MDIO_REG_BANK_BAM_NEXT_PAGE,
4731 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, reg_val);
4734 /* Enable Cl73 FSM status bits */
4735 CL22_WR_OVER_CL45(sc, phy,
4736 MDIO_REG_BANK_CL73_USERB0,
4737 MDIO_CL73_USERB0_CL73_UCTRL, 0xe);
4739 /* Enable BAM Station Manager */
4740 CL22_WR_OVER_CL45(sc, phy,
4741 MDIO_REG_BANK_CL73_USERB0,
4742 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4743 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4744 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN
4746 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4748 /* Advertise CL73 link speeds */
4749 CL22_RD_OVER_CL45(sc, phy,
4750 MDIO_REG_BANK_CL73_IEEEB1,
4751 MDIO_CL73_IEEEB1_AN_ADV2, ®_val);
4752 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4753 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4754 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4755 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4757 CL22_WR_OVER_CL45(sc, phy,
4758 MDIO_REG_BANK_CL73_IEEEB1,
4759 MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
4761 /* CL73 Autoneg Enabled */
4762 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4764 } else /* CL73 Autoneg Disabled */
4767 CL22_WR_OVER_CL45(sc, phy,
4768 MDIO_REG_BANK_CL73_IEEEB0,
4769 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4772 /* Program SerDes, forced speed */
4773 static void elink_program_serdes(struct elink_phy *phy,
4774 struct elink_params *params,
4775 struct elink_vars *vars)
4777 struct bnx2x_softc *sc = params->sc;
4780 /* Program duplex, disable autoneg and sgmii */
4781 CL22_RD_OVER_CL45(sc, phy,
4782 MDIO_REG_BANK_COMBO_IEEE0,
4783 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4784 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4785 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4786 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4787 if (phy->req_duplex == DUPLEX_FULL)
4788 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4789 CL22_WR_OVER_CL45(sc, phy,
4790 MDIO_REG_BANK_COMBO_IEEE0,
4791 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4794 * - needed only if the speed is greater than 1G (2.5G or 10G)
4796 CL22_RD_OVER_CL45(sc, phy,
4797 MDIO_REG_BANK_SERDES_DIGITAL,
4798 MDIO_SERDES_DIGITAL_MISC1, ®_val);
4799 /* Clearing the speed value before setting the right speed */
4800 PMD_DRV_LOG(DEBUG, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val);
4802 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4803 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4805 if (!((vars->line_speed == ELINK_SPEED_1000) ||
4806 (vars->line_speed == ELINK_SPEED_100) ||
4807 (vars->line_speed == ELINK_SPEED_10))) {
4809 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4810 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4811 if (vars->line_speed == ELINK_SPEED_10000)
4813 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4816 CL22_WR_OVER_CL45(sc, phy,
4817 MDIO_REG_BANK_SERDES_DIGITAL,
4818 MDIO_SERDES_DIGITAL_MISC1, reg_val);
4822 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,
4823 struct elink_params *params)
4825 struct bnx2x_softc *sc = params->sc;
4828 /* Set extended capabilities */
4829 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
4830 val |= MDIO_OVER_1G_UP1_2_5G;
4831 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4832 val |= MDIO_OVER_1G_UP1_10G;
4833 CL22_WR_OVER_CL45(sc, phy,
4834 MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP1, val);
4836 CL22_WR_OVER_CL45(sc, phy,
4837 MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP3, 0x400);
4840 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,
4841 struct elink_params *params,
4844 struct bnx2x_softc *sc = params->sc;
4846 /* For AN, we are always publishing full duplex */
4848 CL22_WR_OVER_CL45(sc, phy,
4849 MDIO_REG_BANK_COMBO_IEEE0,
4850 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
4851 CL22_RD_OVER_CL45(sc, phy,
4852 MDIO_REG_BANK_CL73_IEEEB1,
4853 MDIO_CL73_IEEEB1_AN_ADV1, &val);
4854 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
4855 val |= ((ieee_fc << 3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
4856 CL22_WR_OVER_CL45(sc, phy,
4857 MDIO_REG_BANK_CL73_IEEEB1,
4858 MDIO_CL73_IEEEB1_AN_ADV1, val);
4861 static void elink_restart_autoneg(struct elink_phy *phy,
4862 struct elink_params *params,
4863 uint8_t enable_cl73)
4865 struct bnx2x_softc *sc = params->sc;
4866 uint16_t mii_control;
4868 PMD_DRV_LOG(DEBUG, "elink_restart_autoneg");
4869 /* Enable and restart BAM/CL37 aneg */
4872 CL22_RD_OVER_CL45(sc, phy,
4873 MDIO_REG_BANK_CL73_IEEEB0,
4874 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4877 CL22_WR_OVER_CL45(sc, phy,
4878 MDIO_REG_BANK_CL73_IEEEB0,
4879 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4881 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
4882 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4885 CL22_RD_OVER_CL45(sc, phy,
4886 MDIO_REG_BANK_COMBO_IEEE0,
4887 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4889 "elink_restart_autoneg mii_control before = 0x%x",
4891 CL22_WR_OVER_CL45(sc, phy,
4892 MDIO_REG_BANK_COMBO_IEEE0,
4893 MDIO_COMBO_IEEE0_MII_CONTROL,
4895 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4896 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
4900 static void elink_initialize_sgmii_process(struct elink_phy *phy,
4901 struct elink_params *params,
4902 struct elink_vars *vars)
4904 struct bnx2x_softc *sc = params->sc;
4907 /* In SGMII mode, the unicore is always slave */
4909 CL22_RD_OVER_CL45(sc, phy,
4910 MDIO_REG_BANK_SERDES_DIGITAL,
4911 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &control1);
4912 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
4913 /* Set sgmii mode (and not fiber) */
4914 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
4915 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
4916 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
4917 CL22_WR_OVER_CL45(sc, phy,
4918 MDIO_REG_BANK_SERDES_DIGITAL,
4919 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, control1);
4921 /* If forced speed */
4922 if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) {
4923 /* Set speed, disable autoneg */
4924 uint16_t mii_control;
4926 CL22_RD_OVER_CL45(sc, phy,
4927 MDIO_REG_BANK_COMBO_IEEE0,
4928 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4929 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4930 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK |
4931 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
4933 switch (vars->line_speed) {
4934 case ELINK_SPEED_100:
4936 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
4938 case ELINK_SPEED_1000:
4940 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
4942 case ELINK_SPEED_10:
4943 /* There is nothing to set for 10M */
4946 /* Invalid speed for SGMII */
4947 PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x",
4952 /* Setting the full duplex */
4953 if (phy->req_duplex == DUPLEX_FULL)
4954 mii_control |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4955 CL22_WR_OVER_CL45(sc, phy,
4956 MDIO_REG_BANK_COMBO_IEEE0,
4957 MDIO_COMBO_IEEE0_MII_CONTROL, mii_control);
4959 } else { /* AN mode */
4960 /* Enable and restart AN */
4961 elink_restart_autoneg(phy, params, 0);
4967 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
4971 struct bnx2x_softc *sc = params->sc;
4972 uint16_t pd_10g, status2_1000x;
4973 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
4974 return ELINK_STATUS_OK;
4975 CL22_RD_OVER_CL45(sc, phy,
4976 MDIO_REG_BANK_SERDES_DIGITAL,
4977 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);
4978 CL22_RD_OVER_CL45(sc, phy,
4979 MDIO_REG_BANK_SERDES_DIGITAL,
4980 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);
4981 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
4982 PMD_DRV_LOG(DEBUG, "1G parallel detect link on port %d",
4984 return ELINK_STATUS_ERROR;
4987 CL22_RD_OVER_CL45(sc, phy,
4988 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4989 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, &pd_10g);
4991 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
4992 PMD_DRV_LOG(DEBUG, "10G parallel detect link on port %d",
4994 return ELINK_STATUS_ERROR;
4996 return ELINK_STATUS_OK;
4999 static void elink_update_adv_fc(struct elink_phy *phy,
5000 struct elink_params *params,
5001 struct elink_vars *vars, uint32_t gp_status)
5003 uint16_t ld_pause; /* local driver */
5004 uint16_t lp_pause; /* link partner */
5005 uint16_t pause_result;
5006 struct bnx2x_softc *sc = params->sc;
5008 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5009 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5010 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5011 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5013 CL22_RD_OVER_CL45(sc, phy,
5014 MDIO_REG_BANK_CL73_IEEEB1,
5015 MDIO_CL73_IEEEB1_AN_ADV1, &ld_pause);
5016 CL22_RD_OVER_CL45(sc, phy,
5017 MDIO_REG_BANK_CL73_IEEEB1,
5018 MDIO_CL73_IEEEB1_AN_LP_ADV1, &lp_pause);
5019 pause_result = (ld_pause &
5020 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5021 pause_result |= (lp_pause &
5022 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5023 PMD_DRV_LOG(DEBUG, "pause_result CL73 0x%x", pause_result);
5025 CL22_RD_OVER_CL45(sc, phy,
5026 MDIO_REG_BANK_COMBO_IEEE0,
5027 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, &ld_pause);
5028 CL22_RD_OVER_CL45(sc, phy,
5029 MDIO_REG_BANK_COMBO_IEEE0,
5030 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5032 pause_result = (ld_pause &
5033 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 5;
5034 pause_result |= (lp_pause &
5035 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 7;
5036 PMD_DRV_LOG(DEBUG, "pause_result CL37 0x%x", pause_result);
5038 elink_pause_resolve(vars, pause_result);
5042 static void elink_flow_ctrl_resolve(struct elink_phy *phy,
5043 struct elink_params *params,
5044 struct elink_vars *vars, uint32_t gp_status)
5046 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5048 /* Resolve from gp_status in case of AN complete and not sgmii */
5049 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
5050 /* Update the advertised flow-controled of LD/LP in AN */
5051 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
5052 elink_update_adv_fc(phy, params, vars, gp_status);
5053 /* But set the flow-control result as the requested one */
5054 vars->flow_ctrl = phy->req_flow_ctrl;
5055 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
5056 vars->flow_ctrl = params->req_fc_auto_adv;
5057 else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) &&
5058 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5059 if (elink_direct_parallel_detect_used(phy, params)) {
5060 vars->flow_ctrl = params->req_fc_auto_adv;
5063 elink_update_adv_fc(phy, params, vars, gp_status);
5065 PMD_DRV_LOG(DEBUG, "flow_ctrl 0x%x", vars->flow_ctrl);
5068 static void elink_check_fallback_to_cl37(struct elink_phy *phy,
5069 struct elink_params *params)
5071 struct bnx2x_softc *sc = params->sc;
5072 uint16_t rx_status, ustat_val, cl37_fsm_received;
5073 PMD_DRV_LOG(DEBUG, "elink_check_fallback_to_cl37");
5074 /* Step 1: Make sure signal is detected */
5075 CL22_RD_OVER_CL45(sc, phy,
5076 MDIO_REG_BANK_RX0, MDIO_RX0_RX_STATUS, &rx_status);
5077 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5078 (MDIO_RX0_RX_STATUS_SIGDET)) {
5079 PMD_DRV_LOG(DEBUG, "Signal is not detected. Restoring CL73."
5080 "rx_status(0x80b0) = 0x%x", rx_status);
5081 CL22_WR_OVER_CL45(sc, phy,
5082 MDIO_REG_BANK_CL73_IEEEB0,
5083 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5084 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5087 /* Step 2: Check CL73 state machine */
5088 CL22_RD_OVER_CL45(sc, phy,
5089 MDIO_REG_BANK_CL73_USERB0,
5090 MDIO_CL73_USERB0_CL73_USTAT1, &ustat_val);
5092 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5093 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5094 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5095 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5096 PMD_DRV_LOG(DEBUG, "CL73 state-machine is not stable. "
5097 "ustat_val(0x8371) = 0x%x", ustat_val);
5100 /* Step 3: Check CL37 Message Pages received to indicate LP
5101 * supports only CL37
5103 CL22_RD_OVER_CL45(sc, phy,
5104 MDIO_REG_BANK_REMOTE_PHY,
5105 MDIO_REMOTE_PHY_MISC_RX_STATUS, &cl37_fsm_received);
5106 if ((cl37_fsm_received &
5107 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5108 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5109 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5110 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5111 PMD_DRV_LOG(DEBUG, "No CL37 FSM were received. "
5112 "misc_rx_status(0x8330) = 0x%x", cl37_fsm_received);
5115 /* The combined cl37/cl73 fsm state information indicating that
5116 * we are connected to a device which does not support cl73, but
5117 * does support cl37 BAM. In this case we disable cl73 and
5118 * restart cl37 auto-neg
5122 CL22_WR_OVER_CL45(sc, phy,
5123 MDIO_REG_BANK_CL73_IEEEB0,
5124 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 0);
5125 /* Restart CL37 autoneg */
5126 elink_restart_autoneg(phy, params, 0);
5127 PMD_DRV_LOG(DEBUG, "Disabling CL73, and restarting CL37 autoneg");
5130 static void elink_xgxs_an_resolve(struct elink_phy *phy,
5131 struct elink_params *params,
5132 struct elink_vars *vars, uint32_t gp_status)
5134 if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE)
5135 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5137 if (elink_direct_parallel_detect_used(phy, params))
5138 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
5141 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
5142 struct elink_params *params __rte_unused,
5143 struct elink_vars *vars,
5144 uint16_t is_link_up,
5145 uint16_t speed_mask,
5148 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
5149 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5151 PMD_DRV_LOG(DEBUG, "phy link up");
5153 vars->phy_link_up = 1;
5154 vars->link_status |= LINK_STATUS_LINK_UP;
5156 switch (speed_mask) {
5157 case ELINK_GP_STATUS_10M:
5158 vars->line_speed = ELINK_SPEED_10;
5159 if (is_duplex == DUPLEX_FULL)
5160 vars->link_status |= ELINK_LINK_10TFD;
5162 vars->link_status |= ELINK_LINK_10THD;
5165 case ELINK_GP_STATUS_100M:
5166 vars->line_speed = ELINK_SPEED_100;
5167 if (is_duplex == DUPLEX_FULL)
5168 vars->link_status |= ELINK_LINK_100TXFD;
5170 vars->link_status |= ELINK_LINK_100TXHD;
5173 case ELINK_GP_STATUS_1G:
5174 case ELINK_GP_STATUS_1G_KX:
5175 vars->line_speed = ELINK_SPEED_1000;
5176 if (is_duplex == DUPLEX_FULL)
5177 vars->link_status |= ELINK_LINK_1000TFD;
5179 vars->link_status |= ELINK_LINK_1000THD;
5182 case ELINK_GP_STATUS_2_5G:
5183 vars->line_speed = ELINK_SPEED_2500;
5184 if (is_duplex == DUPLEX_FULL)
5185 vars->link_status |= ELINK_LINK_2500TFD;
5187 vars->link_status |= ELINK_LINK_2500THD;
5190 case ELINK_GP_STATUS_5G:
5191 case ELINK_GP_STATUS_6G:
5193 "link speed unsupported gp_status 0x%x",
5195 return ELINK_STATUS_ERROR;
5197 case ELINK_GP_STATUS_10G_KX4:
5198 case ELINK_GP_STATUS_10G_HIG:
5199 case ELINK_GP_STATUS_10G_CX4:
5200 case ELINK_GP_STATUS_10G_KR:
5201 case ELINK_GP_STATUS_10G_SFI:
5202 case ELINK_GP_STATUS_10G_XFI:
5203 vars->line_speed = ELINK_SPEED_10000;
5204 vars->link_status |= ELINK_LINK_10GTFD;
5206 case ELINK_GP_STATUS_20G_DXGXS:
5207 case ELINK_GP_STATUS_20G_KR2:
5208 vars->line_speed = ELINK_SPEED_20000;
5209 vars->link_status |= ELINK_LINK_20GTFD;
5213 "link speed unsupported gp_status 0x%x",
5215 return ELINK_STATUS_ERROR;
5217 } else { /* link_down */
5218 PMD_DRV_LOG(DEBUG, "phy link down");
5220 vars->phy_link_up = 0;
5222 vars->duplex = DUPLEX_FULL;
5223 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5224 vars->mac_type = ELINK_MAC_TYPE_NONE;
5226 PMD_DRV_LOG(DEBUG, " phy_link_up %x line_speed %d",
5227 vars->phy_link_up, vars->line_speed);
5228 return ELINK_STATUS_OK;
5231 static uint8_t elink_link_settings_status(struct elink_phy *phy,
5232 struct elink_params *params,
5233 struct elink_vars *vars)
5235 struct bnx2x_softc *sc = params->sc;
5237 uint16_t gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5238 elink_status_t rc = ELINK_STATUS_OK;
5240 /* Read gp_status */
5241 CL22_RD_OVER_CL45(sc, phy,
5242 MDIO_REG_BANK_GP_STATUS,
5243 MDIO_GP_STATUS_TOP_AN_STATUS1, &gp_status);
5244 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5245 duplex = DUPLEX_FULL;
5246 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5248 speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK;
5249 PMD_DRV_LOG(DEBUG, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x",
5250 gp_status, link_up, speed_mask);
5251 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5253 if (rc == ELINK_STATUS_ERROR)
5256 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5257 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
5258 vars->duplex = duplex;
5259 elink_flow_ctrl_resolve(phy, params, vars, gp_status);
5260 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
5261 elink_xgxs_an_resolve(phy, params, vars,
5264 } else { /* Link_down */
5265 if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
5266 ELINK_SINGLE_MEDIA_DIRECT(params)) {
5267 /* Check signal is detected */
5268 elink_check_fallback_to_cl37(phy, params);
5272 /* Read LP advertised speeds */
5273 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
5274 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5277 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1,
5278 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5280 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5281 vars->link_status |=
5282 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5283 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5284 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5285 vars->link_status |=
5286 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5288 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,
5289 MDIO_OVER_1G_LP_UP1, &val);
5291 if (val & MDIO_OVER_1G_UP1_2_5G)
5292 vars->link_status |=
5293 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5294 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5295 vars->link_status |=
5296 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5299 PMD_DRV_LOG(DEBUG, "duplex %x flow_ctrl 0x%x link_status 0x%x",
5300 vars->duplex, vars->flow_ctrl, vars->link_status);
5304 static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
5305 struct elink_params *params,
5306 struct elink_vars *vars)
5308 struct bnx2x_softc *sc = params->sc;
5310 uint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5311 elink_status_t rc = ELINK_STATUS_OK;
5312 lane = elink_get_warpcore_lane(params);
5313 /* Read gp_status */
5314 if ((params->loopback_mode) && (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {
5315 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5316 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5317 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5318 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5320 } else if ((phy->req_line_speed > ELINK_SPEED_10000) &&
5321 (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {
5322 uint16_t temp_link_up;
5323 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &temp_link_up);
5324 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &link_up);
5325 PMD_DRV_LOG(DEBUG, "PCS RX link status = 0x%x-->0x%x",
5326 temp_link_up, link_up);
5327 link_up &= (1 << 2);
5329 elink_ext_phy_resolve_fc(phy, params, vars);
5331 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5332 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5333 PMD_DRV_LOG(DEBUG, "0x81d1 = 0x%x", gp_status1);
5334 /* Check for either KR, 1G, or AN up. */
5335 link_up = ((gp_status1 >> 8) |
5336 (gp_status1 >> 12) | (gp_status1)) & (1 << lane);
5337 if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
5339 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
5340 MDIO_AN_REG_STATUS, &an_link);
5341 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
5342 MDIO_AN_REG_STATUS, &an_link);
5343 link_up |= (an_link & (1 << 2));
5345 if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) {
5346 uint16_t pd, gp_status4;
5347 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
5348 /* Check Autoneg complete */
5349 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5350 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5352 if (gp_status4 & ((1 << 12) << lane))
5353 vars->link_status |=
5354 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5356 /* Check parallel detect used */
5357 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5358 MDIO_WC_REG_PAR_DET_10G_STATUS,
5361 vars->link_status |=
5362 LINK_STATUS_PARALLEL_DETECTION_USED;
5364 elink_ext_phy_resolve_fc(phy, params, vars);
5365 vars->duplex = duplex;
5369 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5370 ELINK_SINGLE_MEDIA_DIRECT(params)) {
5373 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
5374 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5376 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5377 vars->link_status |=
5378 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5379 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5380 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5381 vars->link_status |=
5382 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5384 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5385 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5387 if (val & MDIO_OVER_1G_UP1_2_5G)
5388 vars->link_status |=
5389 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5390 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5391 vars->link_status |=
5392 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5397 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5398 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5400 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5401 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5403 PMD_DRV_LOG(DEBUG, "lane %d gp_speed 0x%x", lane, gp_speed);
5405 if ((lane & 1) == 0)
5408 link_up = ! !link_up;
5410 /* Reset the TX FIFO to fix SGMII issue */
5411 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5414 /* In case of KR link down, start up the recovering procedure */
5415 if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) &&
5416 (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))
5417 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5419 PMD_DRV_LOG(DEBUG, "duplex %x flow_ctrl 0x%x link_status 0x%x",
5420 vars->duplex, vars->flow_ctrl, vars->link_status);
5424 static void elink_set_gmii_tx_driver(struct elink_params *params)
5426 struct bnx2x_softc *sc = params->sc;
5427 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
5433 CL22_RD_OVER_CL45(sc, phy,
5434 MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_LP_UP2, &lp_up2);
5436 /* Bits [10:7] at lp_up2, positioned at [15:12] */
5437 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5438 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5439 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5444 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5445 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5446 CL22_RD_OVER_CL45(sc, phy,
5447 bank, MDIO_TX0_TX_DRIVER, &tx_driver);
5449 /* Replace tx_driver bits [15:12] */
5450 if (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5451 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5452 tx_driver |= lp_up2;
5453 CL22_WR_OVER_CL45(sc, phy,
5454 bank, MDIO_TX0_TX_DRIVER, tx_driver);
5459 static elink_status_t elink_emac_program(struct elink_params *params,
5460 struct elink_vars *vars)
5462 struct bnx2x_softc *sc = params->sc;
5463 uint8_t port = params->port;
5466 PMD_DRV_LOG(DEBUG, "setting link speed & duplex");
5467 elink_bits_dis(sc, GRCBASE_EMAC0 + port * 0x400 +
5469 (EMAC_MODE_25G_MODE |
5470 EMAC_MODE_PORT_MII_10M | EMAC_MODE_HALF_DUPLEX));
5471 switch (vars->line_speed) {
5472 case ELINK_SPEED_10:
5473 mode |= EMAC_MODE_PORT_MII_10M;
5476 case ELINK_SPEED_100:
5477 mode |= EMAC_MODE_PORT_MII;
5480 case ELINK_SPEED_1000:
5481 mode |= EMAC_MODE_PORT_GMII;
5484 case ELINK_SPEED_2500:
5485 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5489 /* 10G not valid for EMAC */
5490 PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x", vars->line_speed);
5491 return ELINK_STATUS_ERROR;
5494 if (vars->duplex == DUPLEX_HALF)
5495 mode |= EMAC_MODE_HALF_DUPLEX;
5497 GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE, mode);
5499 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
5500 return ELINK_STATUS_OK;
5503 static void elink_set_preemphasis(struct elink_phy *phy,
5504 struct elink_params *params)
5507 uint16_t bank, i = 0;
5508 struct bnx2x_softc *sc = params->sc;
5510 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5511 bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0), i++) {
5512 CL22_WR_OVER_CL45(sc, phy,
5514 MDIO_RX0_RX_EQ_BOOST, phy->rx_preemphasis[i]);
5517 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5518 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5519 CL22_WR_OVER_CL45(sc, phy,
5521 MDIO_TX0_TX_DRIVER, phy->tx_preemphasis[i]);
5525 static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
5526 struct elink_params *params,
5527 struct elink_vars *vars)
5529 uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
5530 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
5532 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5533 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
5534 (params->feature_config_flags &
5535 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5536 elink_set_preemphasis(phy, params);
5538 /* Forced speed requested? */
5539 if (vars->line_speed != ELINK_SPEED_AUTO_NEG ||
5540 (ELINK_SINGLE_MEDIA_DIRECT(params) &&
5541 params->loopback_mode == ELINK_LOOPBACK_EXT)) {
5542 PMD_DRV_LOG(DEBUG, "not SGMII, no AN");
5544 /* Disable autoneg */
5545 elink_set_autoneg(phy, params, vars, 0);
5547 /* Program speed and duplex */
5548 elink_program_serdes(phy, params, vars);
5550 } else { /* AN_mode */
5551 PMD_DRV_LOG(DEBUG, "not SGMII, AN");
5554 elink_set_brcm_cl37_advertisement(phy, params);
5556 /* Program duplex & pause advertisement (for aneg) */
5557 elink_set_ieee_aneg_advertisement(phy, params,
5560 /* Enable autoneg */
5561 elink_set_autoneg(phy, params, vars, enable_cl73);
5563 /* Enable and restart AN */
5564 elink_restart_autoneg(phy, params, enable_cl73);
5567 } else { /* SGMII mode */
5568 PMD_DRV_LOG(DEBUG, "SGMII");
5570 elink_initialize_sgmii_process(phy, params, vars);
5576 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
5577 struct elink_params *params,
5578 struct elink_vars *vars)
5581 vars->phy_flags |= PHY_XGXS_FLAG;
5582 if ((phy->req_line_speed &&
5583 ((phy->req_line_speed == ELINK_SPEED_100) ||
5584 (phy->req_line_speed == ELINK_SPEED_10))) ||
5585 (!phy->req_line_speed &&
5586 (phy->speed_cap_mask >=
5587 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5588 (phy->speed_cap_mask <
5589 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5590 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5591 vars->phy_flags |= PHY_SGMII_FLAG;
5593 vars->phy_flags &= ~PHY_SGMII_FLAG;
5595 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5596 elink_set_aer_mmd(params, phy);
5597 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5598 elink_set_master_ln(params, phy);
5600 rc = elink_reset_unicore(params, phy, 0);
5601 /* Reset the SerDes and wait for reset bit return low */
5602 if (rc != ELINK_STATUS_OK)
5605 elink_set_aer_mmd(params, phy);
5606 /* Setting the masterLn_def again after the reset */
5607 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5608 elink_set_master_ln(params, phy);
5609 elink_set_swap_lanes(params, phy);
5615 static uint16_t elink_wait_reset_complete(struct bnx2x_softc *sc,
5616 struct elink_phy *phy,
5617 struct elink_params *params)
5620 /* Wait for soft reset to get cleared up to 1 sec */
5621 for (cnt = 0; cnt < 1000; cnt++) {
5622 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
5623 elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &ctrl);
5625 elink_cl45_read(sc, phy,
5627 MDIO_PMA_REG_CTRL, &ctrl);
5628 if (!(ctrl & (1 << 15)))
5634 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
5637 PMD_DRV_LOG(DEBUG, "control reg 0x%x (after %d ms)", ctrl, cnt);
5641 static void elink_link_int_enable(struct elink_params *params)
5643 uint8_t port = params->port;
5645 struct bnx2x_softc *sc = params->sc;
5647 /* Setting the status to report on link up for either XGXS or SerDes */
5648 if (CHIP_IS_E3(sc)) {
5649 mask = ELINK_NIG_MASK_XGXS0_LINK_STATUS;
5650 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)))
5651 mask |= ELINK_NIG_MASK_MI_INT;
5652 } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
5653 mask = (ELINK_NIG_MASK_XGXS0_LINK10G |
5654 ELINK_NIG_MASK_XGXS0_LINK_STATUS);
5655 PMD_DRV_LOG(DEBUG, "enabled XGXS interrupt");
5656 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
5657 params->phy[ELINK_INT_PHY].type !=
5658 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5659 mask |= ELINK_NIG_MASK_MI_INT;
5660 PMD_DRV_LOG(DEBUG, "enabled external phy int");
5663 } else { /* SerDes */
5664 mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS;
5665 PMD_DRV_LOG(DEBUG, "enabled SerDes interrupt");
5666 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
5667 params->phy[ELINK_INT_PHY].type !=
5668 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5669 mask |= ELINK_NIG_MASK_MI_INT;
5670 PMD_DRV_LOG(DEBUG, "enabled external phy int");
5673 elink_bits_en(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, mask);
5675 PMD_DRV_LOG(DEBUG, "port %x, is_xgxs %x, int_status 0x%x", port,
5676 (params->switch_cfg == ELINK_SWITCH_CFG_10G),
5677 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
5678 PMD_DRV_LOG(DEBUG, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x",
5679 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
5680 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18),
5682 NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
5683 PMD_DRV_LOG(DEBUG, " 10G %x, XGXS_LINK %x",
5684 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
5685 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
5688 static void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port,
5691 uint32_t latch_status = 0;
5693 /* Disable the MI INT ( external phy int ) by writing 1 to the
5694 * status register. Link down indication is high-active-signal,
5695 * so in this case we need to write the status to clear the XOR
5697 /* Read Latched signals */
5698 latch_status = REG_RD(sc, NIG_REG_LATCH_STATUS_0 + port * 8);
5699 PMD_DRV_LOG(DEBUG, "latch_status = 0x%x", latch_status);
5700 /* Handle only those with latched-signal=up. */
5703 NIG_REG_STATUS_INTERRUPT_PORT0
5704 + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);
5707 NIG_REG_STATUS_INTERRUPT_PORT0
5708 + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);
5710 if (latch_status & 1) {
5712 /* For all latched-signal=up : Re-Arm Latch signals */
5713 REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port * 8,
5714 (latch_status & 0xfffe) | (latch_status & 1));
5716 /* For all latched-signal=up,Write original_signal to status */
5719 static void elink_link_int_ack(struct elink_params *params,
5720 struct elink_vars *vars, uint8_t is_10g_plus)
5722 struct bnx2x_softc *sc = params->sc;
5723 uint8_t port = params->port;
5725 /* First reset all status we assume only one line will be
5728 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4,
5729 (ELINK_NIG_STATUS_XGXS0_LINK10G |
5730 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
5731 ELINK_NIG_STATUS_SERDES0_LINK_STATUS));
5732 if (vars->phy_link_up) {
5733 if (USES_WARPCORE(sc))
5734 mask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS;
5737 mask = ELINK_NIG_STATUS_XGXS0_LINK10G;
5738 else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
5739 /* Disable the link interrupt by writing 1 to
5740 * the relevant lane in the status register
5743 ((params->lane_config &
5744 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5745 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5746 mask = ((1 << ser_lane) <<
5747 ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5749 mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS;
5751 PMD_DRV_LOG(DEBUG, "Ack link up interrupt with mask 0x%x",
5754 NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4, mask);
5758 static uint8_t elink_format_ver(uint32_t num, uint8_t * str,
5761 uint8_t *str_ptr = str;
5762 uint32_t mask = 0xf0000000;
5763 uint8_t shift = 8 * 4;
5765 uint8_t remove_leading_zeros = 1;
5767 /* Need more than 10chars for this format */
5770 return ELINK_STATUS_ERROR;
5775 digit = ((num & mask) >> shift);
5776 if (digit == 0 && remove_leading_zeros) {
5779 } else if (digit < 0xa)
5780 *str_ptr = digit + '0';
5782 *str_ptr = digit - 0xa + 'a';
5783 remove_leading_zeros = 0;
5787 if (shift == 4 * 4) {
5791 remove_leading_zeros = 1;
5794 return ELINK_STATUS_OK;
5797 static uint8_t elink_null_format_ver(__rte_unused uint32_t spirom_ver,
5798 uint8_t * str, uint16_t * len)
5802 return ELINK_STATUS_OK;
5805 static void elink_set_xgxs_loopback(struct elink_phy *phy,
5806 struct elink_params *params)
5808 uint8_t port = params->port;
5809 struct bnx2x_softc *sc = params->sc;
5811 if (phy->req_line_speed != ELINK_SPEED_1000) {
5812 uint32_t md_devad = 0;
5814 PMD_DRV_LOG(DEBUG, "XGXS 10G loopback enable");
5816 if (!CHIP_IS_E3(sc)) {
5817 /* Change the uni_phy_addr in the nig */
5818 md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5821 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18,
5825 elink_cl45_write(sc, phy,
5827 (MDIO_REG_BANK_AER_BLOCK +
5828 (MDIO_AER_BLOCK_AER_REG & 0xf)), 0x2800);
5830 elink_cl45_write(sc, phy,
5832 (MDIO_REG_BANK_CL73_IEEEB0 +
5833 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5836 /* Set aer mmd back */
5837 elink_set_aer_mmd(params, phy);
5839 if (!CHIP_IS_E3(sc)) {
5841 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18,
5846 PMD_DRV_LOG(DEBUG, "XGXS 1G loopback enable");
5847 elink_cl45_read(sc, phy, 5,
5848 (MDIO_REG_BANK_COMBO_IEEE0 +
5849 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5851 elink_cl45_write(sc, phy, 5,
5852 (MDIO_REG_BANK_COMBO_IEEE0 +
5853 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5855 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5859 elink_status_t elink_set_led(struct elink_params *params,
5860 struct elink_vars *vars, uint8_t mode,
5863 uint8_t port = params->port;
5864 uint16_t hw_led_mode = params->hw_led_mode;
5865 elink_status_t rc = ELINK_STATUS_OK;
5868 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5869 struct bnx2x_softc *sc = params->sc;
5870 PMD_DRV_LOG(DEBUG, "elink_set_led: port %x, mode %d", port, mode);
5871 PMD_DRV_LOG(DEBUG, "speed 0x%x, hw_led_mode 0x%x", speed, hw_led_mode);
5873 for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
5874 if (params->phy[phy_idx].set_link_led) {
5875 params->phy[phy_idx].set_link_led(¶ms->phy[phy_idx],
5881 case ELINK_LED_MODE_FRONT_PANEL_OFF:
5882 case ELINK_LED_MODE_OFF:
5883 REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 0);
5884 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
5885 SHARED_HW_CFG_LED_MAC1);
5887 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
5888 if (params->phy[ELINK_EXT_PHY1].type ==
5889 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
5890 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
5891 EMAC_LED_100MB_OVERRIDE |
5892 EMAC_LED_10MB_OVERRIDE);
5894 tmp |= EMAC_LED_OVERRIDE;
5896 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp);
5899 case ELINK_LED_MODE_OPER:
5900 /* For all other phys, OPER mode is same as ON, so in case
5901 * link is down, do nothing
5905 case ELINK_LED_MODE_ON:
5906 if (((params->phy[ELINK_EXT_PHY1].type ==
5907 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727) ||
5908 (params->phy[ELINK_EXT_PHY1].type ==
5909 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722)) &&
5910 CHIP_IS_E2(sc) && params->num_phys == 2) {
5911 /* This is a work-around for E2+8727 Configurations */
5912 if (mode == ELINK_LED_MODE_ON ||
5913 speed == ELINK_SPEED_10000) {
5914 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
5915 REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);
5918 elink_cb_reg_read(sc,
5921 elink_cb_reg_write(sc,
5924 (tmp | EMAC_LED_OVERRIDE));
5925 /* Return here without enabling traffic
5926 * LED blink and setting rate in ON mode.
5927 * In oper mode, enabling LED blink
5928 * and setting rate is needed.
5930 if (mode == ELINK_LED_MODE_ON)
5933 } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
5934 /* This is a work-around for HW issue found when link
5937 if ((!CHIP_IS_E3(sc)) ||
5938 (CHIP_IS_E3(sc) && mode == ELINK_LED_MODE_ON))
5939 REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);
5941 if (CHIP_IS_E1x(sc) ||
5942 CHIP_IS_E2(sc) || (mode == ELINK_LED_MODE_ON))
5943 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
5945 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
5947 } else if ((params->phy[ELINK_EXT_PHY1].type ==
5948 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) &&
5949 (mode == ELINK_LED_MODE_ON)) {
5950 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
5952 elink_cb_reg_read(sc,
5953 emac_base + EMAC_REG_EMAC_LED);
5954 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
5955 tmp | EMAC_LED_OVERRIDE |
5956 EMAC_LED_1000MB_OVERRIDE);
5957 /* Break here; otherwise, it'll disable the
5958 * intended override.
5962 uint32_t nig_led_mode = ((params->hw_led_mode <<
5963 SHARED_HW_CFG_LED_MODE_SHIFT)
5965 SHARED_HW_CFG_LED_EXTPHY2)
5966 ? (SHARED_HW_CFG_LED_PHY1 >>
5967 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
5968 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
5972 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port * 4,
5974 /* Set blinking rate to ~15.9Hz */
5976 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4,
5977 LED_BLINK_RATE_VAL_E3);
5979 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4,
5980 LED_BLINK_RATE_VAL_E1X_E2);
5981 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port * 4, 1);
5982 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
5983 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
5984 (tmp & (~EMAC_LED_OVERRIDE)));
5989 rc = ELINK_STATUS_ERROR;
5990 PMD_DRV_LOG(DEBUG, "elink_set_led: Invalid led mode %d", mode);
5997 static elink_status_t elink_link_initialize(struct elink_params *params,
5998 struct elink_vars *vars)
6000 elink_status_t rc = ELINK_STATUS_OK;
6001 uint8_t phy_index, non_ext_phy;
6002 struct bnx2x_softc *sc = params->sc;
6003 /* In case of external phy existence, the line speed would be the
6004 * line speed linked up by the external phy. In case it is direct
6005 * only, then the line_speed during initialization will be
6006 * equal to the req_line_speed
6008 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
6010 /* Initialize the internal phy in case this is a direct board
6011 * (no external phys), or this board has external phy which requires
6014 if (!USES_WARPCORE(sc))
6015 elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars);
6016 /* init ext phy and enable link state int */
6017 non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
6018 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
6021 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||
6022 (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {
6023 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
6024 if (vars->line_speed == ELINK_SPEED_AUTO_NEG &&
6025 (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc)))
6026 elink_set_parallel_detection(phy, params);
6027 if (params->phy[ELINK_INT_PHY].config_init)
6028 params->phy[ELINK_INT_PHY].config_init(phy,
6032 /* Re-read this value in case it was changed inside config_init due to
6033 * limitations of optic module
6035 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
6037 /* Init external phy */
6039 if (params->phy[ELINK_INT_PHY].supported &
6040 ELINK_SUPPORTED_FIBRE)
6041 vars->link_status |= LINK_STATUS_SERDES_LINK;
6043 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
6045 /* No need to initialize second phy in case of first
6046 * phy only selection. In case of second phy, we do
6047 * need to initialize the first phy, since they are
6050 if (params->phy[phy_index].supported &
6051 ELINK_SUPPORTED_FIBRE)
6052 vars->link_status |= LINK_STATUS_SERDES_LINK;
6054 if (phy_index == ELINK_EXT_PHY2 &&
6055 (elink_phy_selection(params) ==
6056 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6058 "Not initializing second phy");
6061 params->phy[phy_index].config_init(¶ms->
6066 /* Reset the interrupt indication after phy was initialized */
6067 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +
6069 (ELINK_NIG_STATUS_XGXS0_LINK10G |
6070 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
6071 ELINK_NIG_STATUS_SERDES0_LINK_STATUS |
6072 ELINK_NIG_MASK_MI_INT));
6076 static void elink_int_link_reset(__rte_unused struct elink_phy *phy,
6077 struct elink_params *params)
6079 /* Reset the SerDes/XGXS */
6080 REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6081 (0x1ff << (params->port * 16)));
6084 static void elink_common_ext_link_reset(__rte_unused struct elink_phy *phy,
6085 struct elink_params *params)
6087 struct bnx2x_softc *sc = params->sc;
6091 gpio_port = SC_PATH(sc);
6093 gpio_port = params->port;
6094 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6095 MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
6096 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
6097 MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
6098 PMD_DRV_LOG(DEBUG, "reset external PHY");
6101 static elink_status_t elink_update_link_down(struct elink_params *params,
6102 struct elink_vars *vars)
6104 struct bnx2x_softc *sc = params->sc;
6105 uint8_t port = params->port;
6107 PMD_DRV_LOG(DEBUG, "Port %x: Link is down", port);
6108 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
6109 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6110 /* Indicate no mac active */
6111 vars->mac_type = ELINK_MAC_TYPE_NONE;
6113 /* Update shared memory */
6114 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
6115 vars->line_speed = 0;
6116 elink_update_mng(params, vars->link_status);
6118 /* Activate nig drain */
6119 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1);
6122 if (!CHIP_IS_E3(sc))
6123 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
6126 /* Reset BigMac/Xmac */
6127 if (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))
6128 elink_set_bmac_rx(sc, params->port, 0);
6130 if (CHIP_IS_E3(sc)) {
6131 /* Prevent LPI Generation by chip */
6132 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6134 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6136 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6137 SHMEM_EEE_ACTIVE_BIT);
6139 elink_update_mng_eee(params, vars->eee_status);
6140 elink_set_xmac_rxtx(params, 0);
6141 elink_set_umac_rxtx(params, 0);
6144 return ELINK_STATUS_OK;
6147 static elink_status_t elink_update_link_up(struct elink_params *params,
6148 struct elink_vars *vars,
6151 struct bnx2x_softc *sc = params->sc;
6152 uint8_t phy_idx, port = params->port;
6153 elink_status_t rc = ELINK_STATUS_OK;
6155 vars->link_status |= (LINK_STATUS_LINK_UP |
6156 LINK_STATUS_PHYSICAL_LINK_FLAG);
6157 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6159 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
6160 vars->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6162 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
6163 vars->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6164 if (USES_WARPCORE(sc)) {
6166 if (elink_xmac_enable(params, vars, 0) ==
6167 ELINK_STATUS_NO_LINK) {
6168 PMD_DRV_LOG(DEBUG, "Found errors on XMAC");
6170 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6171 vars->link_status &= ~LINK_STATUS_LINK_UP;
6174 elink_umac_enable(params, vars, 0);
6175 elink_set_led(params, vars,
6176 ELINK_LED_MODE_OPER, vars->line_speed);
6178 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6179 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6180 PMD_DRV_LOG(DEBUG, "Enabling LPI assertion");
6181 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6182 (params->port << 2), 1);
6183 REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6184 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6185 (params->port << 2), 0xfc20);
6188 if ((CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))) {
6190 if (elink_bmac_enable(params, vars, 0, 1) ==
6191 ELINK_STATUS_NO_LINK) {
6192 PMD_DRV_LOG(DEBUG, "Found errors on BMAC");
6194 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6195 vars->link_status &= ~LINK_STATUS_LINK_UP;
6198 elink_set_led(params, vars,
6199 ELINK_LED_MODE_OPER, ELINK_SPEED_10000);
6201 rc = elink_emac_program(params, vars);
6202 elink_emac_enable(params, vars, 0);
6205 if ((vars->link_status &
6206 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6207 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6208 ELINK_SINGLE_MEDIA_DIRECT(params))
6209 elink_set_gmii_tx_driver(params);
6214 if (CHIP_IS_E1x(sc))
6215 rc |= elink_pbf_update(params, vars->flow_ctrl,
6219 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 0);
6221 /* Update shared memory */
6222 elink_update_mng(params, vars->link_status);
6223 elink_update_mng_eee(params, vars->eee_status);
6224 /* Check remote fault */
6225 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
6226 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
6227 elink_check_half_open_conn(params, vars, 0);
6235 /* The elink_link_update function should be called upon link
6237 * Link is considered up as follows:
6238 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6240 * - SINGLE_MEDIA - The link between the 577xx and the external
6241 * phy (XGXS) need to up as well as the external link of the
6243 * - DUAL_MEDIA - The link between the 577xx and the first
6244 * external phy needs to be up, and at least one of the 2
6245 * external phy link must be up.
6247 elink_status_t elink_link_update(struct elink_params * params,
6248 struct elink_vars * vars)
6250 struct bnx2x_softc *sc = params->sc;
6251 struct elink_vars phy_vars[ELINK_MAX_PHYS];
6252 uint8_t port = params->port;
6253 uint8_t link_10g_plus, phy_index;
6254 uint8_t ext_phy_link_up = 0, cur_link_up;
6255 elink_status_t rc = ELINK_STATUS_OK;
6256 __rte_unused uint8_t is_mi_int = 0;
6257 uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6258 uint8_t active_external_phy = ELINK_INT_PHY;
6259 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6260 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
6261 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
6263 phy_vars[phy_index].flow_ctrl = 0;
6264 phy_vars[phy_index].link_status = ETH_LINK_DOWN;
6265 phy_vars[phy_index].line_speed = 0;
6266 phy_vars[phy_index].duplex = DUPLEX_FULL;
6267 phy_vars[phy_index].phy_link_up = 0;
6268 phy_vars[phy_index].link_up = 0;
6269 phy_vars[phy_index].fault_detected = 0;
6270 /* different consideration, since vars holds inner state */
6271 phy_vars[phy_index].eee_status = vars->eee_status;
6274 if (USES_WARPCORE(sc))
6275 elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]);
6277 PMD_DRV_LOG(DEBUG, "port %x, XGXS?%x, int_status 0x%x",
6278 port, (vars->phy_flags & PHY_XGXS_FLAG),
6279 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
6281 is_mi_int = (uint8_t) (REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6283 PMD_DRV_LOG(DEBUG, "int_mask 0x%x MI_INT %x, SERDES_LINK %x",
6284 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
6287 NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
6289 PMD_DRV_LOG(DEBUG, " 10G %x, XGXS_LINK %x",
6290 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
6291 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
6294 if (!CHIP_IS_E3(sc))
6295 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
6298 * Check external link change only for external phys, and apply
6299 * priority selection between them in case the link on both phys
6300 * is up. Note that instead of the common vars, a temporary
6301 * vars argument is used since each phy may have different link/
6302 * speed/duplex result
6304 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
6306 struct elink_phy *phy = ¶ms->phy[phy_index];
6307 if (!phy->read_status)
6309 /* Read link status and params of this ext phy */
6310 cur_link_up = phy->read_status(phy, params,
6311 &phy_vars[phy_index]);
6313 PMD_DRV_LOG(DEBUG, "phy in index %d link is up",
6316 PMD_DRV_LOG(DEBUG, "phy in index %d link is down",
6321 if (!ext_phy_link_up) {
6322 ext_phy_link_up = 1;
6323 active_external_phy = phy_index;
6325 switch (elink_phy_selection(params)) {
6326 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6327 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6328 /* In this option, the first PHY makes sure to pass the
6329 * traffic through itself only.
6330 * Its not clear how to reset the link on the second phy
6332 active_external_phy = ELINK_EXT_PHY1;
6334 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6335 /* In this option, the first PHY makes sure to pass the
6336 * traffic through the second PHY.
6338 active_external_phy = ELINK_EXT_PHY2;
6341 /* Link indication on both PHYs with the following cases
6343 * - FIRST_PHY means that second phy wasn't initialized,
6344 * hence its link is expected to be down
6345 * - SECOND_PHY means that first phy should not be able
6346 * to link up by itself (using configuration)
6347 * - DEFAULT should be overriden during initialiazation
6349 PMD_DRV_LOG(DEBUG, "Invalid link indication"
6350 "mpc=0x%x. DISABLING LINK !!!",
6351 params->multi_phy_config);
6352 ext_phy_link_up = 0;
6357 prev_line_speed = vars->line_speed;
6359 * Read the status of the internal phy. In case of
6360 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6361 * otherwise this is the link between the 577xx and the first
6364 if (params->phy[ELINK_INT_PHY].read_status)
6365 params->phy[ELINK_INT_PHY].read_status(¶ms->
6368 /* The INT_PHY flow control reside in the vars. This include the
6369 * case where the speed or flow control are not set to AUTO.
6370 * Otherwise, the active external phy flow control result is set
6371 * to the vars. The ext_phy_line_speed is needed to check if the
6372 * speed is different between the internal phy and external phy.
6373 * This case may be result of intermediate link speed change.
6375 if (active_external_phy > ELINK_INT_PHY) {
6376 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6377 /* Link speed is taken from the XGXS. AN and FC result from
6380 vars->link_status |= phy_vars[active_external_phy].link_status;
6382 /* if active_external_phy is first PHY and link is up - disable
6383 * disable TX on second external PHY
6385 if (active_external_phy == ELINK_EXT_PHY1) {
6386 if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {
6387 PMD_DRV_LOG(DEBUG, "Disabling TX on EXT_PHY2");
6388 params->phy[ELINK_EXT_PHY2].
6389 phy_specific_func(¶ms->
6390 phy[ELINK_EXT_PHY2],
6391 params, ELINK_DISABLE_TX);
6395 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6396 vars->duplex = phy_vars[active_external_phy].duplex;
6397 if (params->phy[active_external_phy].supported &
6398 ELINK_SUPPORTED_FIBRE)
6399 vars->link_status |= LINK_STATUS_SERDES_LINK;
6401 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6403 vars->eee_status = phy_vars[active_external_phy].eee_status;
6405 PMD_DRV_LOG(DEBUG, "Active external phy selected: %x",
6406 active_external_phy);
6409 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
6411 if (params->phy[phy_index].flags &
6412 ELINK_FLAGS_REARM_LATCH_SIGNAL) {
6413 elink_rearm_latch_signal(sc, port,
6415 active_external_phy);
6419 PMD_DRV_LOG(DEBUG, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6420 " ext_phy_line_speed = %d", vars->flow_ctrl,
6421 vars->link_status, ext_phy_line_speed);
6422 /* Upon link speed change set the NIG into drain mode. Comes to
6423 * deals with possible FIFO glitch due to clk change when speed
6424 * is decreased without link down indicator
6427 if (vars->phy_link_up) {
6428 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6429 (ext_phy_line_speed != vars->line_speed)) {
6430 PMD_DRV_LOG(DEBUG, "Internal link speed %d is"
6431 " different than the external"
6432 " link speed %d", vars->line_speed,
6433 ext_phy_line_speed);
6434 vars->phy_link_up = 0;
6435 } else if (prev_line_speed != vars->line_speed) {
6437 NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4,
6443 /* Anything 10 and over uses the bmac */
6444 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
6446 elink_link_int_ack(params, vars, link_10g_plus);
6448 /* In case external phy link is up, and internal link is down
6449 * (not initialized yet probably after link initialization, it
6450 * needs to be initialized.
6451 * Note that after link down-up as result of cable plug, the xgxs
6452 * link would probably become up again without the need
6455 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) {
6456 PMD_DRV_LOG(DEBUG, "ext_phy_link_up = %d, int_link_up = %d,"
6457 " init_preceding = %d", ext_phy_link_up,
6459 params->phy[ELINK_EXT_PHY1].flags &
6460 ELINK_FLAGS_INIT_XGXS_FIRST);
6461 if (!(params->phy[ELINK_EXT_PHY1].flags &
6462 ELINK_FLAGS_INIT_XGXS_FIRST)
6463 && ext_phy_link_up && !vars->phy_link_up) {
6464 vars->line_speed = ext_phy_line_speed;
6465 if (vars->line_speed < ELINK_SPEED_1000)
6466 vars->phy_flags |= PHY_SGMII_FLAG;
6468 vars->phy_flags &= ~PHY_SGMII_FLAG;
6470 if (params->phy[ELINK_INT_PHY].config_init)
6471 params->phy[ELINK_INT_PHY].config_init(¶ms->
6478 /* Link is up only if both local phy and external phy (in case of
6479 * non-direct board) are up and no fault detected on active PHY.
6481 vars->link_up = (vars->phy_link_up &&
6483 ELINK_SINGLE_MEDIA_DIRECT(params)) &&
6484 (phy_vars[active_external_phy].fault_detected == 0));
6486 /* Update the PFC configuration in case it was changed */
6487 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
6488 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6490 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6493 rc = elink_update_link_up(params, vars, link_10g_plus);
6495 rc = elink_update_link_down(params, vars);
6497 /* Update MCP link status was changed */
6499 feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)
6500 elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
6505 /*****************************************************************************/
6506 /* External Phy section */
6507 /*****************************************************************************/
6508 static void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port)
6510 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6511 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6513 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6514 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6517 static void elink_save_spirom_version(struct bnx2x_softc *sc,
6518 __rte_unused uint8_t port,
6519 uint32_t spirom_ver, uint32_t ver_addr)
6521 PMD_DRV_LOG(DEBUG, "FW version 0x%x:0x%x for port %d",
6522 (uint16_t) (spirom_ver >> 16), (uint16_t) spirom_ver, port);
6525 REG_WR(sc, ver_addr, spirom_ver);
6528 static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc *sc,
6529 struct elink_phy *phy, uint8_t port)
6531 uint16_t fw_ver1, fw_ver2;
6533 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
6534 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6535 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
6536 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6537 elink_save_spirom_version(sc, port,
6538 (uint32_t) (fw_ver1 << 16 | fw_ver2),
6542 static void elink_ext_phy_10G_an_resolve(struct bnx2x_softc *sc,
6543 struct elink_phy *phy,
6544 struct elink_vars *vars)
6547 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);
6548 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);
6550 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6551 if ((val & (1 << 0)) == 0)
6552 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6555 /******************************************************************/
6556 /* common BNX2X8073/BNX2X8727 PHY SECTION */
6557 /******************************************************************/
6558 static void elink_8073_resolve_fc(struct elink_phy *phy,
6559 struct elink_params *params,
6560 struct elink_vars *vars)
6562 struct bnx2x_softc *sc = params->sc;
6563 if (phy->req_line_speed == ELINK_SPEED_10 ||
6564 phy->req_line_speed == ELINK_SPEED_100) {
6565 vars->flow_ctrl = phy->req_flow_ctrl;
6569 if (elink_ext_phy_resolve_fc(phy, params, vars) &&
6570 (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) {
6571 uint16_t pause_result;
6572 uint16_t ld_pause; /* local */
6573 uint16_t lp_pause; /* link partner */
6574 elink_cl45_read(sc, phy,
6576 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6578 elink_cl45_read(sc, phy,
6580 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6581 pause_result = (ld_pause &
6582 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6583 pause_result |= (lp_pause &
6584 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6586 elink_pause_resolve(vars, pause_result);
6587 PMD_DRV_LOG(DEBUG, "Ext PHY CL37 pause result 0x%x",
6592 static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,
6593 struct elink_phy *phy,
6597 uint16_t fw_ver1 = 0, fw_msgout;
6598 elink_status_t rc = ELINK_STATUS_OK;
6600 /* Boot port from external ROM */
6602 elink_cl45_write(sc, phy,
6603 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
6605 /* Ucode reboot and rst */
6606 elink_cl45_write(sc, phy,
6607 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x008c);
6609 elink_cl45_write(sc, phy,
6610 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6612 /* Reset internal microprocessor */
6613 elink_cl45_write(sc, phy,
6615 MDIO_PMA_REG_GEN_CTRL,
6616 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6618 /* Release srst bit */
6619 elink_cl45_write(sc, phy,
6621 MDIO_PMA_REG_GEN_CTRL,
6622 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6624 /* Delay 100ms per the PHY specifications */
6627 /* 8073 sometimes taking longer to download */
6632 "elink_8073_8727_external_rom_boot port %x:"
6633 "Download failed. fw version = 0x%x",
6635 rc = ELINK_STATUS_ERROR;
6639 elink_cl45_read(sc, phy,
6641 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6642 elink_cl45_read(sc, phy,
6644 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6647 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6648 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6649 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073)));
6651 /* Clear ser_boot_ctl bit */
6652 elink_cl45_write(sc, phy,
6653 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6654 elink_save_bnx2x_spirom_ver(sc, phy, port);
6657 "elink_8073_8727_external_rom_boot port %x:"
6658 "Download complete. fw version = 0x%x", port, fw_ver1);
6663 /******************************************************************/
6664 /* BNX2X8073 PHY SECTION */
6665 /******************************************************************/
6666 static elink_status_t elink_8073_is_snr_needed(struct bnx2x_softc *sc,
6667 struct elink_phy *phy)
6669 /* This is only required for 8073A1, version 102 only */
6672 /* Read 8073 HW revision */
6673 elink_cl45_read(sc, phy,
6674 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
6677 /* No need to workaround in 8073 A1 */
6678 return ELINK_STATUS_OK;
6681 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &val);
6683 /* SNR should be applied only for version 0x102 */
6685 return ELINK_STATUS_OK;
6687 return ELINK_STATUS_ERROR;
6690 static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
6691 struct elink_phy *phy)
6693 uint16_t val, cnt, cnt1;
6695 elink_cl45_read(sc, phy,
6696 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
6699 /* No need to workaround in 8073 A1 */
6700 return ELINK_STATUS_OK;
6702 /* XAUI workaround in 8073 A0: */
6704 /* After loading the boot ROM and restarting Autoneg, poll
6708 for (cnt = 0; cnt < 1000; cnt++) {
6709 elink_cl45_read(sc, phy,
6711 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &val);
6712 /* If bit [14] = 0 or bit [13] = 0, continue on with
6713 * system initialization (XAUI work-around not required, as
6714 * these bits indicate 2.5G or 1G link up).
6716 if (!(val & (1 << 14)) || !(val & (1 << 13))) {
6717 PMD_DRV_LOG(DEBUG, "XAUI work-around not required");
6718 return ELINK_STATUS_OK;
6719 } else if (!(val & (1 << 15))) {
6720 PMD_DRV_LOG(DEBUG, "bit 15 went off");
6721 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6722 * MSB (bit15) goes to 1 (indicating that the XAUI
6723 * workaround has completed), then continue on with
6724 * system initialization.
6726 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
6727 elink_cl45_read(sc, phy,
6729 MDIO_PMA_REG_8073_XAUI_WA,
6731 if (val & (1 << 15)) {
6733 "XAUI workaround has completed");
6734 return ELINK_STATUS_OK;
6742 PMD_DRV_LOG(DEBUG, "Warning: XAUI work-around timeout !!!");
6743 return ELINK_STATUS_ERROR;
6746 static void elink_807x_force_10G(struct bnx2x_softc *sc, struct elink_phy *phy)
6748 /* Force KR or KX */
6749 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6750 elink_cl45_write(sc, phy,
6751 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
6752 elink_cl45_write(sc, phy,
6753 MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0000);
6754 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6757 static void elink_8073_set_pause_cl37(struct elink_params *params,
6758 struct elink_phy *phy,
6759 struct elink_vars *vars)
6762 struct bnx2x_softc *sc = params->sc;
6763 elink_cl45_read(sc, phy,
6764 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6766 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6767 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6768 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6769 if ((vars->ieee_fc &
6770 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
6771 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
6772 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
6774 if ((vars->ieee_fc &
6775 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
6776 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
6777 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
6779 if ((vars->ieee_fc &
6780 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
6781 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
6782 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6784 PMD_DRV_LOG(DEBUG, "Ext phy AN advertize cl37 0x%x", cl37_val);
6786 elink_cl45_write(sc, phy,
6787 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6791 static void elink_8073_specific_func(struct elink_phy *phy,
6792 struct elink_params *params,
6795 struct bnx2x_softc *sc = params->sc;
6797 case ELINK_PHY_INIT:
6799 elink_cl45_write(sc, phy,
6800 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
6802 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
6808 static uint8_t elink_8073_config_init(struct elink_phy *phy,
6809 struct elink_params *params,
6810 struct elink_vars *vars)
6812 struct bnx2x_softc *sc = params->sc;
6813 uint16_t val = 0, tmp1;
6815 PMD_DRV_LOG(DEBUG, "Init 8073");
6818 gpio_port = SC_PATH(sc);
6820 gpio_port = params->port;
6821 /* Restore normal power mode */
6822 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
6823 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6825 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6826 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6828 elink_8073_specific_func(phy, params, ELINK_PHY_INIT);
6829 elink_8073_set_pause_cl37(params, phy, vars);
6831 elink_cl45_read(sc, phy,
6832 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6834 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
6836 PMD_DRV_LOG(DEBUG, "Before rom RX_ALARM(port1): 0x%x", tmp1);
6838 /* Swap polarity if required - Must be done only in non-1G mode */
6839 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
6840 /* Configure the 8073 to swap _P and _N of the KR lines */
6841 PMD_DRV_LOG(DEBUG, "Swapping polarity for the 8073");
6842 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6843 elink_cl45_read(sc, phy,
6845 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
6846 elink_cl45_write(sc, phy,
6848 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
6852 /* Enable CL37 BAM */
6853 if (REG_RD(sc, params->shmem_base +
6854 offsetof(struct shmem_region,
6855 dev_info.port_hw_config[params->port].
6857 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
6859 elink_cl45_read(sc, phy,
6860 MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, &val);
6861 elink_cl45_write(sc, phy,
6862 MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, val | 1);
6863 PMD_DRV_LOG(DEBUG, "Enable CL37 BAM on KR");
6865 if (params->loopback_mode == ELINK_LOOPBACK_EXT) {
6866 elink_807x_force_10G(sc, phy);
6867 PMD_DRV_LOG(DEBUG, "Forced speed 10G on 807X");
6868 return ELINK_STATUS_OK;
6870 elink_cl45_write(sc, phy,
6871 MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0002);
6873 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {
6874 if (phy->req_line_speed == ELINK_SPEED_10000) {
6876 } else if (phy->req_line_speed == ELINK_SPEED_2500) {
6878 /* Note that 2.5G works only when used with 1G
6885 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6888 /* Note that 2.5G works only when used with 1G advertisement */
6889 if (phy->speed_cap_mask &
6890 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
6891 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6893 PMD_DRV_LOG(DEBUG, "807x autoneg val = 0x%x", val);
6896 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
6897 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6899 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
6900 (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) ||
6901 (phy->req_line_speed == ELINK_SPEED_2500)) {
6903 /* Allow 2.5G for A1 and above */
6904 elink_cl45_read(sc, phy,
6905 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
6907 PMD_DRV_LOG(DEBUG, "Add 2.5G");
6913 PMD_DRV_LOG(DEBUG, "Disable 2.5G");
6917 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
6918 /* Add support for CL37 (passive mode) II */
6920 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
6921 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
6922 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
6925 /* Add support for CL37 (passive mode) III */
6926 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6928 /* The SNR will improve about 2db by changing BW and FEE main
6929 * tap. Rest commands are executed after link is up
6930 * Change FFE main cursor to 5 in EDC register
6932 if (elink_8073_is_snr_needed(sc, phy))
6933 elink_cl45_write(sc, phy,
6934 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
6937 /* Enable FEC (Forware Error Correction) Request in the AN */
6938 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
6940 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
6942 elink_ext_phy_set_pause(params, phy, vars);
6944 /* Restart autoneg */
6946 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
6947 PMD_DRV_LOG(DEBUG, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x",
6948 ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0));
6949 return ELINK_STATUS_OK;
6952 static uint8_t elink_8073_read_status(struct elink_phy *phy,
6953 struct elink_params *params,
6954 struct elink_vars *vars)
6956 struct bnx2x_softc *sc = params->sc;
6957 uint8_t link_up = 0;
6958 uint16_t val1, val2;
6959 uint16_t link_status = 0;
6960 uint16_t an1000_status = 0;
6962 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
6964 PMD_DRV_LOG(DEBUG, "8703 LASI status 0x%x", val1);
6966 /* Clear the interrupt LASI status register */
6967 elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
6968 elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
6969 PMD_DRV_LOG(DEBUG, "807x PCS status 0x%x->0x%x", val2, val1);
6971 elink_cl45_read(sc, phy,
6972 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
6974 /* Check the LASI */
6975 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
6977 PMD_DRV_LOG(DEBUG, "KR 0x9003 0x%x", val2);
6979 /* Check the link status */
6980 elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
6981 PMD_DRV_LOG(DEBUG, "KR PCS status 0x%x", val2);
6983 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6984 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
6985 link_up = ((val1 & 4) == 4);
6986 PMD_DRV_LOG(DEBUG, "PMA_REG_STATUS=0x%x", val1);
6988 if (link_up && ((phy->req_line_speed != ELINK_SPEED_10000))) {
6989 if (elink_8073_xaui_wa(sc, phy) != 0)
6992 elink_cl45_read(sc, phy,
6993 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
6994 elink_cl45_read(sc, phy,
6995 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
6997 /* Check the link status on 1.1.2 */
6998 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6999 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7000 PMD_DRV_LOG(DEBUG, "KR PMA status 0x%x->0x%x,"
7001 "an_link_status=0x%x", val2, val1, an1000_status);
7003 link_up = (((val1 & 4) == 4) || (an1000_status & (1 << 1)));
7004 if (link_up && elink_8073_is_snr_needed(sc, phy)) {
7005 /* The SNR will improve about 2dbby changing the BW and FEE main
7006 * tap. The 1st write to change FFE main tap is set before
7007 * restart AN. Change PLL Bandwidth in EDC register
7009 elink_cl45_write(sc, phy,
7010 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7013 /* Change CDR Bandwidth in EDC register */
7014 elink_cl45_write(sc, phy,
7015 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7018 elink_cl45_read(sc, phy,
7019 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7022 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7023 if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {
7025 vars->line_speed = ELINK_SPEED_10000;
7026 PMD_DRV_LOG(DEBUG, "port %x: External link up in 10G",
7028 } else if ((link_status & (1 << 1)) && (!(link_status & (1 << 14)))) {
7030 vars->line_speed = ELINK_SPEED_2500;
7031 PMD_DRV_LOG(DEBUG, "port %x: External link up in 2.5G",
7033 } else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {
7035 vars->line_speed = ELINK_SPEED_1000;
7036 PMD_DRV_LOG(DEBUG, "port %x: External link up in 1G",
7040 PMD_DRV_LOG(DEBUG, "port %x: External link is down",
7045 /* Swap polarity if required */
7046 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7047 /* Configure the 8073 to swap P and N of the KR lines */
7048 elink_cl45_read(sc, phy,
7050 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7051 /* Set bit 3 to invert Rx in 1G mode and clear this bit
7052 * when it`s in 10G mode.
7054 if (vars->line_speed == ELINK_SPEED_1000) {
7055 PMD_DRV_LOG(DEBUG, "Swapping 1G polarity for"
7061 elink_cl45_write(sc, phy,
7063 MDIO_XS_REG_8073_RX_CTRL_PCIE, val1);
7065 elink_ext_phy_10G_an_resolve(sc, phy, vars);
7066 elink_8073_resolve_fc(phy, params, vars);
7067 vars->duplex = DUPLEX_FULL;
7070 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7071 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
7072 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7074 if (val1 & (1 << 5))
7075 vars->link_status |=
7076 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7077 if (val1 & (1 << 7))
7078 vars->link_status |=
7079 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7085 static void elink_8073_link_reset(__rte_unused struct elink_phy *phy,
7086 struct elink_params *params)
7088 struct bnx2x_softc *sc = params->sc;
7091 gpio_port = SC_PATH(sc);
7093 gpio_port = params->port;
7094 PMD_DRV_LOG(DEBUG, "Setting 8073 port %d into low power mode",
7096 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
7097 MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
7100 /******************************************************************/
7101 /* BNX2X8705 PHY SECTION */
7102 /******************************************************************/
7103 static uint8_t elink_8705_config_init(struct elink_phy *phy,
7104 struct elink_params *params,
7105 __rte_unused struct elink_vars
7108 struct bnx2x_softc *sc = params->sc;
7109 PMD_DRV_LOG(DEBUG, "init 8705");
7110 /* Restore normal power mode */
7111 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
7112 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7114 elink_ext_phy_hw_reset(sc, params->port);
7115 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7116 elink_wait_reset_complete(sc, phy, params);
7118 elink_cl45_write(sc, phy,
7119 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7120 elink_cl45_write(sc, phy,
7121 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7122 elink_cl45_write(sc, phy,
7123 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7124 elink_cl45_write(sc, phy, MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7125 /* BNX2X8705 doesn't have microcode, hence the 0 */
7126 elink_save_spirom_version(sc, params->port, params->shmem_base, 0);
7127 return ELINK_STATUS_OK;
7130 static uint8_t elink_8705_read_status(struct elink_phy *phy,
7131 struct elink_params *params,
7132 struct elink_vars *vars)
7134 uint8_t link_up = 0;
7135 uint16_t val1, rx_sd;
7136 struct bnx2x_softc *sc = params->sc;
7137 PMD_DRV_LOG(DEBUG, "read status 8705");
7138 elink_cl45_read(sc, phy,
7139 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7140 PMD_DRV_LOG(DEBUG, "8705 LASI status 0x%x", val1);
7142 elink_cl45_read(sc, phy,
7143 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7144 PMD_DRV_LOG(DEBUG, "8705 LASI status 0x%x", val1);
7146 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7148 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);
7149 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);
7151 PMD_DRV_LOG(DEBUG, "8705 1.c809 val=0x%x", val1);
7152 link_up = ((rx_sd & 0x1) && (val1 & (1 << 9))
7153 && ((val1 & (1 << 8)) == 0));
7155 vars->line_speed = ELINK_SPEED_10000;
7156 elink_ext_phy_resolve_fc(phy, params, vars);
7161 /******************************************************************/
7162 /* SFP+ module Section */
7163 /******************************************************************/
7164 static void elink_set_disable_pmd_transmit(struct elink_params *params,
7165 struct elink_phy *phy,
7168 struct bnx2x_softc *sc = params->sc;
7169 /* Disable transmitter only for bootcodes which can enable it afterwards
7173 if (params->feature_config_flags &
7174 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {
7175 PMD_DRV_LOG(DEBUG, "Disabling PMD transmitter");
7177 PMD_DRV_LOG(DEBUG, "NOT disabling PMD transmitter");
7181 PMD_DRV_LOG(DEBUG, "Enabling PMD transmitter");
7183 elink_cl45_write(sc, phy,
7184 MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7187 static uint8_t elink_get_gpio_port(struct elink_params *params)
7190 uint32_t swap_val, swap_override;
7191 struct bnx2x_softc *sc = params->sc;
7192 if (CHIP_IS_E2(sc)) {
7193 gpio_port = SC_PATH(sc);
7195 gpio_port = params->port;
7197 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
7198 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
7199 return gpio_port ^ (swap_val && swap_override);
7202 static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
7203 struct elink_phy *phy, uint8_t tx_en)
7206 uint8_t port = params->port;
7207 struct bnx2x_softc *sc = params->sc;
7208 uint32_t tx_en_mode;
7210 /* Disable/Enable transmitter ( TX laser of the SFP+ module.) */
7211 tx_en_mode = REG_RD(sc, params->shmem_base +
7212 offsetof(struct shmem_region,
7213 dev_info.port_hw_config[port].sfp_ctrl)) &
7214 PORT_HW_CFG_TX_LASER_MASK;
7215 PMD_DRV_LOG(DEBUG, "Setting transmitter tx_en=%x for port %x "
7216 "mode = %x", tx_en, port, tx_en_mode);
7217 switch (tx_en_mode) {
7218 case PORT_HW_CFG_TX_LASER_MDIO:
7220 elink_cl45_read(sc, phy,
7222 MDIO_PMA_REG_PHY_IDENTIFIER, &val);
7229 elink_cl45_write(sc, phy,
7231 MDIO_PMA_REG_PHY_IDENTIFIER, val);
7233 case PORT_HW_CFG_TX_LASER_GPIO0:
7234 case PORT_HW_CFG_TX_LASER_GPIO1:
7235 case PORT_HW_CFG_TX_LASER_GPIO2:
7236 case PORT_HW_CFG_TX_LASER_GPIO3:
7239 uint8_t gpio_port, gpio_mode;
7241 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7243 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7245 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7246 gpio_port = elink_get_gpio_port(params);
7247 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
7251 PMD_DRV_LOG(DEBUG, "Invalid TX_LASER_MDIO 0x%x", tx_en_mode);
7256 static void elink_sfp_set_transmitter(struct elink_params *params,
7257 struct elink_phy *phy, uint8_t tx_en)
7259 struct bnx2x_softc *sc = params->sc;
7260 PMD_DRV_LOG(DEBUG, "Setting SFP+ transmitter to %d", tx_en);
7262 elink_sfp_e3_set_transmitter(params, phy, tx_en);
7264 elink_sfp_e1e2_set_transmitter(params, phy, tx_en);
7267 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
7274 __rte_unused uint8_t
7277 struct bnx2x_softc *sc = params->sc;
7280 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
7281 PMD_DRV_LOG(DEBUG, "Reading from eeprom is limited to 0xf");
7282 return ELINK_STATUS_ERROR;
7284 /* Set the read command byte count */
7285 elink_cl45_write(sc, phy,
7286 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7287 (byte_cnt | (dev_addr << 8)));
7289 /* Set the read command address */
7290 elink_cl45_write(sc, phy,
7291 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7294 /* Activate read command */
7295 elink_cl45_write(sc, phy,
7296 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7299 /* Wait up to 500us for command complete status */
7300 for (i = 0; i < 100; i++) {
7301 elink_cl45_read(sc, phy,
7303 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7304 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7305 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7310 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7311 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7313 "Got bad status 0x%x when reading from SFP+ EEPROM",
7314 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7315 return ELINK_STATUS_ERROR;
7318 /* Read the buffer */
7319 for (i = 0; i < byte_cnt; i++) {
7320 elink_cl45_read(sc, phy,
7322 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7324 (uint8_t) (val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7327 for (i = 0; i < 100; i++) {
7328 elink_cl45_read(sc, phy,
7330 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7331 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7332 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7333 return ELINK_STATUS_OK;
7336 return ELINK_STATUS_ERROR;
7339 static void elink_warpcore_power_module(struct elink_params *params,
7343 struct bnx2x_softc *sc = params->sc;
7345 pin_cfg = (REG_RD(sc, params->shmem_base +
7346 offsetof(struct shmem_region,
7347 dev_info.port_hw_config[params->port].
7348 e3_sfp_ctrl)) & PORT_HW_CFG_E3_PWR_DIS_MASK)
7349 >> PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7351 if (pin_cfg == PIN_CFG_NA)
7353 PMD_DRV_LOG(DEBUG, "Setting SFP+ module power to %d using pin cfg %d",
7355 /* Low ==> corresponding SFP+ module is powered
7356 * high ==> the SFP+ module is powered down
7358 elink_set_cfg_pin(sc, pin_cfg, power ^ 1);
7361 static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct
7371 elink_status_t rc = ELINK_STATUS_OK;
7372 uint8_t i, j = 0, cnt = 0;
7373 uint32_t data_array[4];
7375 struct bnx2x_softc *sc = params->sc;
7377 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
7379 "Reading from eeprom is limited to 16 bytes");
7380 return ELINK_STATUS_ERROR;
7383 /* 4 byte aligned address */
7384 addr32 = addr & (~0x3);
7386 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7387 elink_warpcore_power_module(params, 0);
7388 /* Note that 100us are not enough here */
7390 elink_warpcore_power_module(params, 1);
7392 rc = elink_bsc_read(params, sc, dev_addr, addr32, 0, byte_cnt,
7394 } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT));
7396 if (rc == ELINK_STATUS_OK) {
7397 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7398 o_buf[j] = *((uint8_t *) data_array + i);
7406 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
7413 __rte_unused uint8_t
7416 struct bnx2x_softc *sc = params->sc;
7419 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
7420 PMD_DRV_LOG(DEBUG, "Reading from eeprom is limited to 0xf");
7421 return ELINK_STATUS_ERROR;
7424 /* Set 2-wire transfer rate of SFP+ module EEPROM
7425 * to 100Khz since some DACs(direct attached cables) do
7426 * not work at 400Khz.
7428 elink_cl45_write(sc, phy,
7430 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7431 ((dev_addr << 8) | 1));
7433 /* Need to read from 1.8000 to clear it */
7434 elink_cl45_read(sc, phy,
7435 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7437 /* Set the read command byte count */
7438 elink_cl45_write(sc, phy,
7440 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7441 ((byte_cnt < 2) ? 2 : byte_cnt));
7443 /* Set the read command address */
7444 elink_cl45_write(sc, phy,
7446 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, addr);
7447 /* Set the destination address */
7448 elink_cl45_write(sc, phy,
7450 0x8004, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7452 /* Activate read command */
7453 elink_cl45_write(sc, phy,
7455 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 0x8002);
7456 /* Wait appropriate time for two-wire command to finish before
7457 * polling the status register
7461 /* Wait up to 500us for command complete status */
7462 for (i = 0; i < 100; i++) {
7463 elink_cl45_read(sc, phy,
7465 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7466 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7467 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7472 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7473 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7475 "Got bad status 0x%x when reading from SFP+ EEPROM",
7476 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7477 return ELINK_STATUS_TIMEOUT;
7480 /* Read the buffer */
7481 for (i = 0; i < byte_cnt; i++) {
7482 elink_cl45_read(sc, phy,
7484 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7486 (uint8_t) (val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7489 for (i = 0; i < 100; i++) {
7490 elink_cl45_read(sc, phy,
7492 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7493 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7494 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7495 return ELINK_STATUS_OK;
7499 return ELINK_STATUS_ERROR;
7502 static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
7503 struct elink_params *params,
7509 elink_status_t rc = ELINK_STATUS_OK;
7511 uint8_t *user_data = o_buf;
7512 read_sfp_module_eeprom_func_p read_func;
7514 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
7515 PMD_DRV_LOG(DEBUG, "invalid dev_addr 0x%x", dev_addr);
7516 return ELINK_STATUS_ERROR;
7519 switch (phy->type) {
7520 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
7521 read_func = elink_8726_read_sfp_module_eeprom;
7523 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
7524 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
7525 read_func = elink_8727_read_sfp_module_eeprom;
7527 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7528 read_func = elink_warpcore_read_sfp_module_eeprom;
7531 return ELINK_OP_NOT_SUPPORTED;
7534 while (!rc && (byte_cnt > 0)) {
7535 xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ?
7536 ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;
7537 rc = read_func(phy, params, dev_addr, addr, xfer_size,
7539 byte_cnt -= xfer_size;
7540 user_data += xfer_size;
7546 static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
7547 struct elink_params *params,
7548 uint16_t * edc_mode)
7550 struct bnx2x_softc *sc = params->sc;
7551 uint32_t sync_offset = 0, phy_idx, media_types;
7552 uint8_t gport, val[2], check_limiting_mode = 0;
7553 *edc_mode = ELINK_EDC_MODE_LIMITING;
7554 phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;
7555 /* First check for copper cable */
7556 if (elink_read_sfp_module_eeprom(phy,
7558 ELINK_I2C_DEV_ADDR_A0,
7559 ELINK_SFP_EEPROM_CON_TYPE_ADDR,
7560 2, (uint8_t *) val) != 0) {
7561 PMD_DRV_LOG(DEBUG, "Failed to read from SFP+ module EEPROM");
7562 return ELINK_STATUS_ERROR;
7566 case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER:
7568 uint8_t copper_module_type;
7569 phy->media_type = ELINK_ETH_PHY_DA_TWINAX;
7570 /* Check if its active cable (includes SFP+ module)
7573 if (elink_read_sfp_module_eeprom(phy,
7575 ELINK_I2C_DEV_ADDR_A0,
7576 ELINK_SFP_EEPROM_FC_TX_TECH_ADDR,
7578 &copper_module_type) !=
7581 "Failed to read copper-cable-type"
7582 " from SFP+ EEPROM");
7583 return ELINK_STATUS_ERROR;
7586 if (copper_module_type &
7587 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7589 "Active Copper cable detected");
7591 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
7592 *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;
7594 check_limiting_mode = 1;
7595 } else if (copper_module_type &
7596 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE)
7599 "Passive Copper cable detected");
7600 *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;
7603 "Unknown copper-cable-type 0x%x !!!",
7604 copper_module_type);
7605 return ELINK_STATUS_ERROR;
7609 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:
7610 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:
7611 check_limiting_mode = 1;
7612 if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK |
7613 ELINK_SFP_EEPROM_COMP_CODE_LR_MASK |
7614 ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
7615 PMD_DRV_LOG(DEBUG, "1G SFP module detected");
7616 gport = params->port;
7617 phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;
7618 if (phy->req_line_speed != ELINK_SPEED_1000) {
7619 phy->req_line_speed = ELINK_SPEED_1000;
7620 if (!CHIP_IS_E1x(sc)) {
7621 gport = SC_PATH(sc) +
7622 (params->port << 1);
7624 elink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps."
7625 // " Current SFP module in port %d is not"
7626 // " compliant with 10G Ethernet",
7630 int idx, cfg_idx = 0;
7631 PMD_DRV_LOG(DEBUG, "10G Optic module detected");
7632 for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) {
7633 if (params->phy[idx].type == phy->type) {
7634 cfg_idx = ELINK_LINK_CONFIG_IDX(idx);
7638 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
7639 phy->req_line_speed = params->req_line_speed[cfg_idx];
7643 PMD_DRV_LOG(DEBUG, "Unable to determine module type 0x%x !!!",
7645 return ELINK_STATUS_ERROR;
7647 sync_offset = params->shmem_base +
7648 offsetof(struct shmem_region,
7649 dev_info.port_hw_config[params->port].media_type);
7650 media_types = REG_RD(sc, sync_offset);
7651 /* Update media type for non-PMF sync */
7652 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
7653 if (&(params->phy[phy_idx]) == phy) {
7654 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7655 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
7659 media_type & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7660 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7664 REG_WR(sc, sync_offset, media_types);
7665 if (check_limiting_mode) {
7666 uint8_t options[ELINK_SFP_EEPROM_OPTIONS_SIZE];
7667 if (elink_read_sfp_module_eeprom(phy,
7669 ELINK_I2C_DEV_ADDR_A0,
7670 ELINK_SFP_EEPROM_OPTIONS_ADDR,
7671 ELINK_SFP_EEPROM_OPTIONS_SIZE,
7674 "Failed to read Option field from module EEPROM");
7675 return ELINK_STATUS_ERROR;
7677 if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7678 *edc_mode = ELINK_EDC_MODE_LINEAR;
7680 *edc_mode = ELINK_EDC_MODE_LIMITING;
7682 PMD_DRV_LOG(DEBUG, "EDC mode is set to 0x%x", *edc_mode);
7683 return ELINK_STATUS_OK;
7686 /* This function read the relevant field from the module (SFP+), and verify it
7687 * is compliant with this board
7689 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
7690 struct elink_params *params)
7692 struct bnx2x_softc *sc = params->sc;
7694 uint32_t fw_resp, fw_cmd_param;
7695 char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE + 1];
7696 char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE + 1];
7697 phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;
7698 val = REG_RD(sc, params->shmem_base +
7699 offsetof(struct shmem_region,
7700 dev_info.port_feature_config[params->port].
7702 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7703 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7704 PMD_DRV_LOG(DEBUG, "NOT enforcing module verification");
7705 return ELINK_STATUS_OK;
7708 if (params->feature_config_flags &
7709 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7710 /* Use specific phy request */
7711 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7712 } else if (params->feature_config_flags &
7713 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7714 /* Use first phy request only in case of non-dual media */
7715 if (ELINK_DUAL_MEDIA(params)) {
7717 "FW does not support OPT MDL verification");
7718 return ELINK_STATUS_ERROR;
7720 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7722 /* No support in OPT MDL detection */
7723 PMD_DRV_LOG(DEBUG, "FW does not support OPT MDL verification");
7724 return ELINK_STATUS_ERROR;
7727 fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7728 fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param);
7729 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7730 PMD_DRV_LOG(DEBUG, "Approved module");
7731 return ELINK_STATUS_OK;
7734 /* Format the warning message */
7735 if (elink_read_sfp_module_eeprom(phy,
7737 ELINK_I2C_DEV_ADDR_A0,
7738 ELINK_SFP_EEPROM_VENDOR_NAME_ADDR,
7739 ELINK_SFP_EEPROM_VENDOR_NAME_SIZE,
7740 (uint8_t *) vendor_name))
7741 vendor_name[0] = '\0';
7743 vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7744 if (elink_read_sfp_module_eeprom(phy,
7746 ELINK_I2C_DEV_ADDR_A0,
7747 ELINK_SFP_EEPROM_PART_NO_ADDR,
7748 ELINK_SFP_EEPROM_PART_NO_SIZE,
7749 (uint8_t *) vendor_pn))
7750 vendor_pn[0] = '\0';
7752 vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0';
7754 elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected,"
7755 // " Port %d from %s part number %s",
7757 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
7758 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
7759 phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED;
7760 return ELINK_STATUS_ERROR;
7763 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy
7771 /* Initialization time after hot-plug may take up to 300ms for
7772 * some phys type ( e.g. JDSU )
7775 for (timeout = 0; timeout < 60; timeout++) {
7776 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
7777 rc = elink_warpcore_read_sfp_module_eeprom(phy, params,
7778 ELINK_I2C_DEV_ADDR_A0,
7782 rc = elink_read_sfp_module_eeprom(phy, params,
7783 ELINK_I2C_DEV_ADDR_A0,
7787 "SFP+ module initialization took %d ms",
7789 return ELINK_STATUS_OK;
7793 rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0,
7798 static void elink_8727_power_module(struct bnx2x_softc *sc,
7799 struct elink_phy *phy, uint8_t is_power_up)
7801 /* Make sure GPIOs are not using for LED mode */
7803 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
7804 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7806 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7807 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7808 * where the 1st bit is the over-current(only input), and 2nd bit is
7809 * for power( only output )
7811 * In case of NOC feature is disabled and power is up, set GPIO control
7812 * as input to enable listening of over-current indication
7814 if (phy->flags & ELINK_FLAGS_NOC)
7819 /* Set GPIO control to OUTPUT, and set the power bit
7820 * to according to the is_power_up
7824 elink_cl45_write(sc, phy,
7825 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);
7828 static elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc,
7829 struct elink_phy *phy,
7832 uint16_t cur_limiting_mode;
7834 elink_cl45_read(sc, phy,
7836 MDIO_PMA_REG_ROM_VER2, &cur_limiting_mode);
7837 PMD_DRV_LOG(DEBUG, "Current Limiting mode is 0x%x", cur_limiting_mode);
7839 if (edc_mode == ELINK_EDC_MODE_LIMITING) {
7840 PMD_DRV_LOG(DEBUG, "Setting LIMITING MODE");
7841 elink_cl45_write(sc, phy,
7843 MDIO_PMA_REG_ROM_VER2,
7844 ELINK_EDC_MODE_LIMITING);
7845 } else { /* LRM mode ( default ) */
7847 PMD_DRV_LOG(DEBUG, "Setting LRM MODE");
7849 /* Changing to LRM mode takes quite few seconds. So do it only
7850 * if current mode is limiting (default is LRM)
7852 if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING)
7853 return ELINK_STATUS_OK;
7855 elink_cl45_write(sc, phy,
7856 MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0);
7857 elink_cl45_write(sc, phy,
7858 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, 0x128);
7859 elink_cl45_write(sc, phy,
7861 MDIO_PMA_REG_MISC_CTRL0, 0x4008);
7862 elink_cl45_write(sc, phy,
7863 MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0xaaaa);
7865 return ELINK_STATUS_OK;
7868 static elink_status_t elink_8727_set_limiting_mode(struct bnx2x_softc *sc,
7869 struct elink_phy *phy,
7872 uint16_t phy_identifier;
7873 uint16_t rom_ver2_val;
7874 elink_cl45_read(sc, phy,
7876 MDIO_PMA_REG_PHY_IDENTIFIER, &phy_identifier);
7878 elink_cl45_write(sc, phy,
7880 MDIO_PMA_REG_PHY_IDENTIFIER,
7881 (phy_identifier & ~(1 << 9)));
7883 elink_cl45_read(sc, phy,
7884 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &rom_ver2_val);
7885 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7886 elink_cl45_write(sc, phy,
7888 MDIO_PMA_REG_ROM_VER2,
7889 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
7891 elink_cl45_write(sc, phy,
7893 MDIO_PMA_REG_PHY_IDENTIFIER,
7894 (phy_identifier | (1 << 9)));
7896 return ELINK_STATUS_OK;
7899 static void elink_8727_specific_func(struct elink_phy *phy,
7900 struct elink_params *params,
7903 struct bnx2x_softc *sc = params->sc;
7906 case ELINK_DISABLE_TX:
7907 elink_sfp_set_transmitter(params, phy, 0);
7909 case ELINK_ENABLE_TX:
7910 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED))
7911 elink_sfp_set_transmitter(params, phy, 1);
7913 case ELINK_PHY_INIT:
7914 elink_cl45_write(sc, phy,
7915 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
7916 (1 << 2) | (1 << 5));
7917 elink_cl45_write(sc, phy,
7918 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);
7919 elink_cl45_write(sc, phy,
7920 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
7921 /* Make MOD_ABS give interrupt on change */
7922 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7923 MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);
7925 if (phy->flags & ELINK_FLAGS_NOC)
7927 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
7928 * status which reflect SFP+ module over-current
7930 if (!(phy->flags & ELINK_FLAGS_NOC))
7931 val &= 0xff8f; /* Reset bits 4-6 */
7932 elink_cl45_write(sc, phy,
7933 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
7937 PMD_DRV_LOG(DEBUG, "Function 0x%x not supported by 8727",
7943 static void elink_set_e1e2_module_fault_led(struct elink_params *params,
7946 struct bnx2x_softc *sc = params->sc;
7948 uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +
7949 offsetof(struct shmem_region,
7951 port_hw_config[params->port].
7953 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
7954 switch (fault_led_gpio) {
7955 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
7957 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
7958 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
7959 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
7960 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
7962 uint8_t gpio_port = elink_get_gpio_port(params);
7963 uint16_t gpio_pin = fault_led_gpio -
7964 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
7965 PMD_DRV_LOG(DEBUG, "Set fault module-detected led "
7966 "pin %x port %x mode %x",
7967 gpio_pin, gpio_port, gpio_mode);
7968 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
7972 PMD_DRV_LOG(DEBUG, "Error: Invalid fault led mode 0x%x",
7977 static void elink_set_e3_module_fault_led(struct elink_params *params,
7981 uint8_t port = params->port;
7982 struct bnx2x_softc *sc = params->sc;
7983 pin_cfg = (REG_RD(sc, params->shmem_base +
7984 offsetof(struct shmem_region,
7985 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
7986 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
7987 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
7988 PMD_DRV_LOG(DEBUG, "Setting Fault LED to %d using pin cfg %d",
7989 gpio_mode, pin_cfg);
7990 elink_set_cfg_pin(sc, pin_cfg, gpio_mode);
7993 static void elink_set_sfp_module_fault_led(struct elink_params *params,
7996 struct bnx2x_softc *sc = params->sc;
7997 PMD_DRV_LOG(DEBUG, "Setting SFP+ module fault LED to %d", gpio_mode);
7998 if (CHIP_IS_E3(sc)) {
7999 /* Low ==> if SFP+ module is supported otherwise
8000 * High ==> if SFP+ module is not on the approved vendor list
8002 elink_set_e3_module_fault_led(params, gpio_mode);
8004 elink_set_e1e2_module_fault_led(params, gpio_mode);
8007 static void elink_warpcore_hw_reset(__rte_unused struct elink_phy *phy,
8008 struct elink_params *params)
8010 struct bnx2x_softc *sc = params->sc;
8011 elink_warpcore_power_module(params, 0);
8012 /* Put Warpcore in low power mode */
8013 REG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e);
8015 /* Put LCPLL in low power mode */
8016 REG_WR(sc, MISC_REG_LCPLL_E40_PWRDWN, 1);
8017 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8018 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8021 static void elink_power_sfp_module(struct elink_params *params,
8022 struct elink_phy *phy, uint8_t power)
8024 PMD_DRV_LOG(DEBUG, "Setting SFP+ power to %x", power);
8026 switch (phy->type) {
8027 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
8028 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
8029 elink_8727_power_module(params->sc, phy, power);
8031 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8032 elink_warpcore_power_module(params, power);
8039 static void elink_warpcore_set_limiting_mode(struct elink_params *params,
8040 struct elink_phy *phy,
8044 uint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8045 struct bnx2x_softc *sc = params->sc;
8047 uint8_t lane = elink_get_warpcore_lane(params);
8048 /* This is a global register which controls all lanes */
8049 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
8050 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8051 val &= ~(0xf << (lane << 2));
8054 case ELINK_EDC_MODE_LINEAR:
8055 case ELINK_EDC_MODE_LIMITING:
8056 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8058 case ELINK_EDC_MODE_PASSIVE_DAC:
8059 case ELINK_EDC_MODE_ACTIVE_DAC:
8060 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8066 val |= (mode << (lane << 2));
8067 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
8068 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8070 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
8071 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8073 /* Restart microcode to re-read the new mode */
8074 elink_warpcore_reset_lane(sc, phy, 1);
8075 elink_warpcore_reset_lane(sc, phy, 0);
8079 static void elink_set_limiting_mode(struct elink_params *params,
8080 struct elink_phy *phy, uint16_t edc_mode)
8082 switch (phy->type) {
8083 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
8084 elink_8726_set_limiting_mode(params->sc, phy, edc_mode);
8086 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
8087 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
8088 elink_8727_set_limiting_mode(params->sc, phy, edc_mode);
8090 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8091 elink_warpcore_set_limiting_mode(params, phy, edc_mode);
8096 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
8097 struct elink_params *params)
8099 struct bnx2x_softc *sc = params->sc;
8101 elink_status_t rc = ELINK_STATUS_OK;
8103 uint32_t val = REG_RD(sc, params->shmem_base +
8104 offsetof(struct shmem_region,
8105 dev_info.port_feature_config[params->
8108 /* Enabled transmitter by default */
8109 elink_sfp_set_transmitter(params, phy, 1);
8110 PMD_DRV_LOG(DEBUG, "SFP+ module plugged in/out detected on port %d",
8112 /* Power up module */
8113 elink_power_sfp_module(params, phy, 1);
8114 if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {
8115 PMD_DRV_LOG(DEBUG, "Failed to get valid module type");
8116 return ELINK_STATUS_ERROR;
8117 } else if (elink_verify_sfp_module(phy, params) != 0) {
8118 /* Check SFP+ module compatibility */
8119 PMD_DRV_LOG(DEBUG, "Module verification failed!!");
8120 rc = ELINK_STATUS_ERROR;
8121 /* Turn on fault module-detected led */
8122 elink_set_sfp_module_fault_led(params,
8123 MISC_REGISTERS_GPIO_HIGH);
8125 /* Check if need to power down the SFP+ module */
8126 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8127 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8128 PMD_DRV_LOG(DEBUG, "Shutdown SFP+ module!!");
8129 elink_power_sfp_module(params, phy, 0);
8133 /* Turn off fault module-detected led */
8134 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8137 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8138 * is done automatically
8140 elink_set_limiting_mode(params, phy, edc_mode);
8142 /* Disable transmit for this module if the module is not approved, and
8143 * laser needs to be disabled.
8146 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8147 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8148 elink_sfp_set_transmitter(params, phy, 0);
8153 void elink_handle_module_detect_int(struct elink_params *params)
8155 struct bnx2x_softc *sc = params->sc;
8156 struct elink_phy *phy;
8158 uint8_t gpio_num, gpio_port;
8159 if (CHIP_IS_E3(sc)) {
8160 phy = ¶ms->phy[ELINK_INT_PHY];
8161 /* Always enable TX laser,will be disabled in case of fault */
8162 elink_sfp_set_transmitter(params, phy, 1);
8164 phy = ¶ms->phy[ELINK_EXT_PHY1];
8166 if (elink_get_mod_abs_int_cfg(sc, params->shmem_base,
8167 params->port, &gpio_num, &gpio_port) ==
8168 ELINK_STATUS_ERROR) {
8169 PMD_DRV_LOG(DEBUG, "Failed to get MOD_ABS interrupt config");
8173 /* Set valid module led off */
8174 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8176 /* Get current gpio val reflecting module plugged in / out */
8177 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
8179 /* Call the handling function in case module is detected */
8180 if (gpio_val == 0) {
8181 elink_set_mdio_emac_per_phy(sc, params);
8182 elink_set_aer_mmd(params, phy);
8184 elink_power_sfp_module(params, phy, 1);
8185 elink_cb_gpio_int_write(sc, gpio_num,
8186 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8188 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
8189 elink_sfp_module_detection(phy, params);
8190 if (CHIP_IS_E3(sc)) {
8191 uint16_t rx_tx_in_reset;
8192 /* In case WC is out of reset, reconfigure the
8193 * link speed while taking into account 1G
8194 * module limitation.
8196 elink_cl45_read(sc, phy,
8198 MDIO_WC_REG_DIGITAL5_MISC6,
8200 if ((!rx_tx_in_reset) &&
8201 (params->link_flags &
8202 ELINK_PHY_INITIALIZED)) {
8203 elink_warpcore_reset_lane(sc, phy, 1);
8204 elink_warpcore_config_sfi(phy, params);
8205 elink_warpcore_reset_lane(sc, phy, 0);
8209 PMD_DRV_LOG(DEBUG, "SFP+ module is not initialized");
8212 elink_cb_gpio_int_write(sc, gpio_num,
8213 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8215 /* Module was plugged out.
8216 * Disable transmit for this module
8218 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
8222 /******************************************************************/
8223 /* Used by 8706 and 8727 */
8224 /******************************************************************/
8225 static void elink_sfp_mask_fault(struct bnx2x_softc *sc,
8226 struct elink_phy *phy,
8227 uint16_t alarm_status_offset,
8228 uint16_t alarm_ctrl_offset)
8230 uint16_t alarm_status, val;
8231 elink_cl45_read(sc, phy,
8232 MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);
8233 elink_cl45_read(sc, phy,
8234 MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);
8235 /* Mask or enable the fault event. */
8236 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8237 if (alarm_status & (1 << 0))
8241 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8244 /******************************************************************/
8245 /* common BNX2X8706/BNX2X8726 PHY SECTION */
8246 /******************************************************************/
8247 static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
8248 struct elink_params *params,
8249 struct elink_vars *vars)
8251 uint8_t link_up = 0;
8252 uint16_t val1, val2, rx_sd, pcs_status;
8253 struct bnx2x_softc *sc = params->sc;
8254 PMD_DRV_LOG(DEBUG, "XGXS 8706/8726");
8255 /* Clear RX Alarm */
8256 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8258 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
8259 MDIO_PMA_LASI_TXCTRL);
8261 /* Clear LASI indication */
8262 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8263 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8264 PMD_DRV_LOG(DEBUG, "8706/8726 LASI status 0x%x--> 0x%x", val1, val2);
8266 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8267 elink_cl45_read(sc, phy,
8268 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8269 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8270 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8272 PMD_DRV_LOG(DEBUG, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8273 " link_status 0x%x", rx_sd, pcs_status, val2);
8274 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8275 * are set, or if the autoneg bit 1 is set
8277 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1 << 1)));
8279 if (val2 & (1 << 1))
8280 vars->line_speed = ELINK_SPEED_1000;
8282 vars->line_speed = ELINK_SPEED_10000;
8283 elink_ext_phy_resolve_fc(phy, params, vars);
8284 vars->duplex = DUPLEX_FULL;
8287 /* Capture 10G link fault. Read twice to clear stale value. */
8288 if (vars->line_speed == ELINK_SPEED_10000) {
8289 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8290 MDIO_PMA_LASI_TXSTAT, &val1);
8291 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8292 MDIO_PMA_LASI_TXSTAT, &val1);
8293 if (val1 & (1 << 0))
8294 vars->fault_detected = 1;
8300 /******************************************************************/
8301 /* BNX2X8706 PHY SECTION */
8302 /******************************************************************/
8303 static uint8_t elink_8706_config_init(struct elink_phy *phy,
8304 struct elink_params *params,
8305 __rte_unused struct elink_vars *vars)
8307 uint32_t tx_en_mode;
8308 uint16_t cnt, val, tmp1;
8309 struct bnx2x_softc *sc = params->sc;
8311 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8312 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8314 elink_ext_phy_hw_reset(sc, params->port);
8315 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8316 elink_wait_reset_complete(sc, phy, params);
8318 /* Wait until fw is loaded */
8319 for (cnt = 0; cnt < 100; cnt++) {
8320 elink_cl45_read(sc, phy,
8321 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8326 PMD_DRV_LOG(DEBUG, "XGXS 8706 is initialized after %d ms", cnt);
8327 if ((params->feature_config_flags &
8328 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8331 for (i = 0; i < 4; i++) {
8332 reg = MDIO_XS_8706_REG_BANK_RX0 +
8333 i * (MDIO_XS_8706_REG_BANK_RX1 -
8334 MDIO_XS_8706_REG_BANK_RX0);
8335 elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);
8336 /* Clear first 3 bits of the control */
8338 /* Set control bits according to configuration */
8339 val |= (phy->rx_preemphasis[i] & 0x7);
8340 PMD_DRV_LOG(DEBUG, "Setting RX Equalizer to BNX2X8706"
8341 " reg 0x%x <-- val 0x%x", reg, val);
8342 elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);
8346 if (phy->req_line_speed == ELINK_SPEED_10000) {
8347 PMD_DRV_LOG(DEBUG, "XGXS 8706 force 10Gbps");
8349 elink_cl45_write(sc, phy,
8351 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8352 elink_cl45_write(sc, phy,
8353 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);
8354 /* Arm LASI for link and Tx fault. */
8355 elink_cl45_write(sc, phy,
8356 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8358 /* Force 1Gbps using autoneg with 1G advertisement */
8360 /* Allow CL37 through CL73 */
8361 PMD_DRV_LOG(DEBUG, "XGXS 8706 AutoNeg");
8362 elink_cl45_write(sc, phy,
8363 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8365 /* Enable Full-Duplex advertisement on CL37 */
8366 elink_cl45_write(sc, phy,
8367 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8368 /* Enable CL37 AN */
8369 elink_cl45_write(sc, phy,
8370 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8372 elink_cl45_write(sc, phy,
8373 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1 << 5));
8375 /* Enable clause 73 AN */
8376 elink_cl45_write(sc, phy,
8377 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8378 elink_cl45_write(sc, phy,
8379 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x0400);
8380 elink_cl45_write(sc, phy,
8381 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
8383 elink_save_bnx2x_spirom_ver(sc, phy, params->port);
8385 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8386 * power mode, if TX Laser is disabled
8389 tx_en_mode = REG_RD(sc, params->shmem_base +
8390 offsetof(struct shmem_region,
8391 dev_info.port_hw_config[params->port].
8393 & PORT_HW_CFG_TX_LASER_MASK;
8395 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8396 PMD_DRV_LOG(DEBUG, "Enabling TXONOFF_PWRDN_DIS");
8397 elink_cl45_read(sc, phy,
8398 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,
8401 elink_cl45_write(sc, phy,
8402 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,
8406 return ELINK_STATUS_OK;
8409 static uint8_t elink_8706_read_status(struct elink_phy *phy,
8410 struct elink_params *params,
8411 struct elink_vars *vars)
8413 return elink_8706_8726_read_status(phy, params, vars);
8416 /******************************************************************/
8417 /* BNX2X8726 PHY SECTION */
8418 /******************************************************************/
8419 static void elink_8726_config_loopback(struct elink_phy *phy,
8420 struct elink_params *params)
8422 struct bnx2x_softc *sc = params->sc;
8423 PMD_DRV_LOG(DEBUG, "PMA/PMD ext_phy_loopback: 8726");
8424 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8427 static void elink_8726_external_rom_boot(struct elink_phy *phy,
8428 struct elink_params *params)
8430 struct bnx2x_softc *sc = params->sc;
8431 /* Need to wait 100ms after reset */
8434 /* Micro controller re-boot */
8435 elink_cl45_write(sc, phy,
8436 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8438 /* Set soft reset */
8439 elink_cl45_write(sc, phy,
8441 MDIO_PMA_REG_GEN_CTRL,
8442 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8444 elink_cl45_write(sc, phy,
8445 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8447 elink_cl45_write(sc, phy,
8449 MDIO_PMA_REG_GEN_CTRL,
8450 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8452 /* Wait for 150ms for microcode load */
8455 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8456 elink_cl45_write(sc, phy,
8457 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8460 elink_save_bnx2x_spirom_ver(sc, phy, params->port);
8463 static uint8_t elink_8726_read_status(struct elink_phy *phy,
8464 struct elink_params *params,
8465 struct elink_vars *vars)
8467 struct bnx2x_softc *sc = params->sc;
8469 uint8_t link_up = elink_8706_8726_read_status(phy, params, vars);
8471 elink_cl45_read(sc, phy,
8472 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8474 if (val1 & (1 << 15)) {
8475 PMD_DRV_LOG(DEBUG, "Tx is disabled");
8477 vars->line_speed = 0;
8483 static uint8_t elink_8726_config_init(struct elink_phy *phy,
8484 struct elink_params *params,
8485 struct elink_vars *vars)
8487 struct bnx2x_softc *sc = params->sc;
8488 PMD_DRV_LOG(DEBUG, "Initializing BNX2X8726");
8490 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
8491 elink_wait_reset_complete(sc, phy, params);
8493 elink_8726_external_rom_boot(phy, params);
8495 /* Need to call module detected on initialization since the module
8496 * detection triggered by actual module insertion might occur before
8497 * driver is loaded, and when driver is loaded, it reset all
8498 * registers, including the transmitter
8500 elink_sfp_module_detection(phy, params);
8502 if (phy->req_line_speed == ELINK_SPEED_1000) {
8503 PMD_DRV_LOG(DEBUG, "Setting 1G force");
8504 elink_cl45_write(sc, phy,
8505 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8506 elink_cl45_write(sc, phy,
8507 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8508 elink_cl45_write(sc, phy,
8509 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8510 elink_cl45_write(sc, phy,
8511 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);
8512 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
8513 (phy->speed_cap_mask &
8514 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8515 ((phy->speed_cap_mask &
8516 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8517 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8518 PMD_DRV_LOG(DEBUG, "Setting 1G clause37");
8519 /* Set Flow control */
8520 elink_ext_phy_set_pause(params, phy, vars);
8521 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8522 elink_cl45_write(sc, phy,
8523 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8524 elink_cl45_write(sc, phy,
8525 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8526 elink_cl45_write(sc, phy,
8527 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8528 elink_cl45_write(sc, phy,
8529 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8530 /* Enable RX-ALARM control to receive interrupt for 1G speed
8533 elink_cl45_write(sc, phy,
8534 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8535 elink_cl45_write(sc, phy,
8536 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);
8538 } else { /* Default 10G. Set only LASI control */
8539 elink_cl45_write(sc, phy,
8540 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8543 /* Set TX PreEmphasis if needed */
8544 if ((params->feature_config_flags &
8545 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8547 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
8548 phy->tx_preemphasis[0], phy->tx_preemphasis[1]);
8549 elink_cl45_write(sc, phy,
8551 MDIO_PMA_REG_8726_TX_CTRL1,
8552 phy->tx_preemphasis[0]);
8554 elink_cl45_write(sc, phy,
8556 MDIO_PMA_REG_8726_TX_CTRL2,
8557 phy->tx_preemphasis[1]);
8560 return ELINK_STATUS_OK;
8564 static void elink_8726_link_reset(struct elink_phy *phy,
8565 struct elink_params *params)
8567 struct bnx2x_softc *sc = params->sc;
8568 PMD_DRV_LOG(DEBUG, "elink_8726_link_reset port %d", params->port);
8569 /* Set serial boot control for external load */
8570 elink_cl45_write(sc, phy,
8571 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
8574 /******************************************************************/
8575 /* BNX2X8727 PHY SECTION */
8576 /******************************************************************/
8578 static void elink_8727_set_link_led(struct elink_phy *phy,
8579 struct elink_params *params, uint8_t mode)
8581 struct bnx2x_softc *sc = params->sc;
8582 uint16_t led_mode_bitmask = 0;
8583 uint16_t gpio_pins_bitmask = 0;
8585 /* Only NOC flavor requires to set the LED specifically */
8586 if (!(phy->flags & ELINK_FLAGS_NOC))
8589 case ELINK_LED_MODE_FRONT_PANEL_OFF:
8590 case ELINK_LED_MODE_OFF:
8591 led_mode_bitmask = 0;
8592 gpio_pins_bitmask = 0x03;
8594 case ELINK_LED_MODE_ON:
8595 led_mode_bitmask = 0;
8596 gpio_pins_bitmask = 0x02;
8598 case ELINK_LED_MODE_OPER:
8599 led_mode_bitmask = 0x60;
8600 gpio_pins_bitmask = 0x11;
8603 elink_cl45_read(sc, phy,
8604 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);
8606 val |= led_mode_bitmask;
8607 elink_cl45_write(sc, phy,
8608 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8609 elink_cl45_read(sc, phy,
8610 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, &val);
8612 val |= gpio_pins_bitmask;
8613 elink_cl45_write(sc, phy,
8614 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);
8617 static void elink_8727_hw_reset(__rte_unused struct elink_phy *phy,
8618 struct elink_params *params)
8620 uint32_t swap_val, swap_override;
8622 /* The PHY reset is controlled by GPIO 1. Fake the port number
8623 * to cancel the swap done in set_gpio()
8625 struct bnx2x_softc *sc = params->sc;
8626 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
8627 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
8628 port = (swap_val && swap_override) ^ 1;
8629 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
8630 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8633 static void elink_8727_config_speed(struct elink_phy *phy,
8634 struct elink_params *params)
8636 struct bnx2x_softc *sc = params->sc;
8638 /* Set option 1G speed */
8639 if ((phy->req_line_speed == ELINK_SPEED_1000) ||
8640 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
8641 PMD_DRV_LOG(DEBUG, "Setting 1G force");
8642 elink_cl45_write(sc, phy,
8643 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8644 elink_cl45_write(sc, phy,
8645 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8646 elink_cl45_read(sc, phy,
8647 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8648 PMD_DRV_LOG(DEBUG, "1.7 = 0x%x", tmp1);
8649 /* Power down the XAUI until link is up in case of dual-media
8652 if (ELINK_DUAL_MEDIA(params)) {
8653 elink_cl45_read(sc, phy,
8655 MDIO_PMA_REG_8727_PCS_GP, &val);
8657 elink_cl45_write(sc, phy,
8659 MDIO_PMA_REG_8727_PCS_GP, val);
8661 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
8662 ((phy->speed_cap_mask &
8663 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8664 ((phy->speed_cap_mask &
8665 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8666 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8668 PMD_DRV_LOG(DEBUG, "Setting 1G clause37");
8669 elink_cl45_write(sc, phy,
8670 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8671 elink_cl45_write(sc, phy,
8672 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8674 /* Since the 8727 has only single reset pin, need to set the 10G
8675 * registers although it is default
8677 elink_cl45_write(sc, phy,
8678 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8680 elink_cl45_write(sc, phy,
8681 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8682 elink_cl45_write(sc, phy,
8683 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8684 elink_cl45_write(sc, phy,
8685 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8690 static uint8_t elink_8727_config_init(struct elink_phy *phy,
8691 struct elink_params *params,
8692 __rte_unused struct elink_vars
8695 uint32_t tx_en_mode;
8696 uint16_t tmp1, mod_abs, tmp2;
8697 struct bnx2x_softc *sc = params->sc;
8698 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8700 elink_wait_reset_complete(sc, phy, params);
8702 PMD_DRV_LOG(DEBUG, "Initializing BNX2X8727");
8704 elink_8727_specific_func(phy, params, ELINK_PHY_INIT);
8705 /* Initially configure MOD_ABS to interrupt when module is
8708 elink_cl45_read(sc, phy,
8709 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8710 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
8711 * When the EDC is off it locks onto a reference clock and avoids
8714 mod_abs &= ~(1 << 8);
8715 if (!(phy->flags & ELINK_FLAGS_NOC))
8716 mod_abs &= ~(1 << 9);
8717 elink_cl45_write(sc, phy,
8718 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8720 /* Enable/Disable PHY transmitter output */
8721 elink_set_disable_pmd_transmit(params, phy, 0);
8723 elink_8727_power_module(sc, phy, 1);
8725 elink_cl45_read(sc, phy,
8726 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8728 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8730 elink_8727_config_speed(phy, params);
8732 /* Set TX PreEmphasis if needed */
8733 if ((params->feature_config_flags &
8734 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8735 PMD_DRV_LOG(DEBUG, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
8736 phy->tx_preemphasis[0], phy->tx_preemphasis[1]);
8737 elink_cl45_write(sc, phy,
8738 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8739 phy->tx_preemphasis[0]);
8741 elink_cl45_write(sc, phy,
8742 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8743 phy->tx_preemphasis[1]);
8746 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8747 * power mode, if TX Laser is disabled
8749 tx_en_mode = REG_RD(sc, params->shmem_base +
8750 offsetof(struct shmem_region,
8751 dev_info.port_hw_config[params->port].
8753 & PORT_HW_CFG_TX_LASER_MASK;
8755 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8757 PMD_DRV_LOG(DEBUG, "Enabling TXONOFF_PWRDN_DIS");
8758 elink_cl45_read(sc, phy,
8759 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,
8763 elink_cl45_write(sc, phy,
8764 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,
8766 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8767 MDIO_PMA_REG_PHY_IDENTIFIER, &tmp2);
8768 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
8769 MDIO_PMA_REG_PHY_IDENTIFIER, (tmp2 & 0x7fff));
8772 return ELINK_STATUS_OK;
8775 static void elink_8727_handle_mod_abs(struct elink_phy *phy,
8776 struct elink_params *params)
8778 struct bnx2x_softc *sc = params->sc;
8779 uint16_t mod_abs, rx_alarm_status;
8780 uint32_t val = REG_RD(sc, params->shmem_base +
8781 offsetof(struct shmem_region,
8782 dev_info.port_feature_config[params->
8784 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8786 if (mod_abs & (1 << 8)) {
8788 /* Module is absent */
8789 PMD_DRV_LOG(DEBUG, "MOD_ABS indication show module is absent");
8790 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
8791 /* 1. Set mod_abs to detect next module
8793 * 2. Set EDC off by setting OPTXLOS signal input to low
8795 * When the EDC is off it locks onto a reference clock and
8796 * avoids becoming 'lost'.
8798 mod_abs &= ~(1 << 8);
8799 if (!(phy->flags & ELINK_FLAGS_NOC))
8800 mod_abs &= ~(1 << 9);
8801 elink_cl45_write(sc, phy,
8803 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8805 /* Clear RX alarm since it stays up as long as
8806 * the mod_abs wasn't changed
8808 elink_cl45_read(sc, phy,
8810 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8813 /* Module is present */
8814 PMD_DRV_LOG(DEBUG, "MOD_ABS indication show module is present");
8815 /* First disable transmitter, and if the module is ok, the
8816 * module_detection will enable it
8817 * 1. Set mod_abs to detect next module absent event ( bit 8)
8818 * 2. Restore the default polarity of the OPRXLOS signal and
8819 * this signal will then correctly indicate the presence or
8820 * absence of the Rx signal. (bit 9)
8822 mod_abs |= (1 << 8);
8823 if (!(phy->flags & ELINK_FLAGS_NOC))
8824 mod_abs |= (1 << 9);
8825 elink_cl45_write(sc, phy,
8827 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8829 /* Clear RX alarm since it stays up as long as the mod_abs
8830 * wasn't changed. This is need to be done before calling the
8831 * module detection, otherwise it will clear* the link update
8834 elink_cl45_read(sc, phy,
8836 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8838 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8839 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8840 elink_sfp_set_transmitter(params, phy, 0);
8842 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
8843 elink_sfp_module_detection(phy, params);
8845 PMD_DRV_LOG(DEBUG, "SFP+ module is not initialized");
8848 /* Reconfigure link speed based on module type limitations */
8849 elink_8727_config_speed(phy, params);
8852 PMD_DRV_LOG(DEBUG, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
8853 /* No need to check link status in case of module plugged in/out */
8856 static uint8_t elink_8727_read_status(struct elink_phy *phy,
8857 struct elink_params *params,
8858 struct elink_vars *vars)
8860 struct bnx2x_softc *sc = params->sc;
8861 uint8_t link_up = 0, oc_port = params->port;
8862 uint16_t link_status = 0;
8863 uint16_t rx_alarm_status, lasi_ctrl, val1;
8865 /* If PHY is not initialized, do not check link status */
8866 elink_cl45_read(sc, phy,
8867 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, &lasi_ctrl);
8871 /* Check the LASI on Rx */
8872 elink_cl45_read(sc, phy,
8873 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8874 vars->line_speed = 0;
8875 PMD_DRV_LOG(DEBUG, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
8877 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
8878 MDIO_PMA_LASI_TXCTRL);
8880 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8882 PMD_DRV_LOG(DEBUG, "8727 LASI status 0x%x", val1);
8885 elink_cl45_read(sc, phy,
8886 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8888 /* If a module is present and there is need to check
8891 if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1 << 5))) {
8892 /* Check over-current using 8727 GPIO0 input */
8893 elink_cl45_read(sc, phy,
8894 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
8897 if ((val1 & (1 << 8)) == 0) {
8898 if (!CHIP_IS_E1x(sc))
8899 oc_port = SC_PATH(sc) + (params->port << 1);
8901 "8727 Power fault has been detected on port %d",
8903 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has "
8904 // "been detected and the power to "
8905 // "that SFP+ module has been removed "
8906 // "to prevent failure of the card. "
8907 // "Please remove the SFP+ module and "
8908 // "restart the system to clear this "
8910 /* Disable all RX_ALARMs except for mod_abs */
8911 elink_cl45_write(sc, phy,
8913 MDIO_PMA_LASI_RXCTRL, (1 << 5));
8915 elink_cl45_read(sc, phy,
8917 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8918 /* Wait for module_absent_event */
8920 elink_cl45_write(sc, phy,
8922 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
8923 /* Clear RX alarm */
8924 elink_cl45_read(sc, phy,
8926 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8927 elink_8727_power_module(params->sc, phy, 0);
8932 /* Over current check */
8933 /* When module absent bit is set, check module */
8934 if (rx_alarm_status & (1 << 5)) {
8935 elink_8727_handle_mod_abs(phy, params);
8936 /* Enable all mod_abs and link detection bits */
8937 elink_cl45_write(sc, phy,
8938 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8939 ((1 << 5) | (1 << 2)));
8942 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
8943 PMD_DRV_LOG(DEBUG, "Enabling 8727 TX laser");
8944 elink_sfp_set_transmitter(params, phy, 1);
8946 PMD_DRV_LOG(DEBUG, "Tx is disabled");
8950 elink_cl45_read(sc, phy,
8952 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
8954 /* Bits 0..2 --> speed detected,
8955 * Bits 13..15--> link is down
8957 if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {
8959 vars->line_speed = ELINK_SPEED_10000;
8960 PMD_DRV_LOG(DEBUG, "port %x: External link up in 10G",
8962 } else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {
8964 vars->line_speed = ELINK_SPEED_1000;
8965 PMD_DRV_LOG(DEBUG, "port %x: External link up in 1G",
8969 PMD_DRV_LOG(DEBUG, "port %x: External link is down",
8973 /* Capture 10G link fault. */
8974 if (vars->line_speed == ELINK_SPEED_10000) {
8975 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8976 MDIO_PMA_LASI_TXSTAT, &val1);
8978 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8979 MDIO_PMA_LASI_TXSTAT, &val1);
8981 if (val1 & (1 << 0)) {
8982 vars->fault_detected = 1;
8987 elink_ext_phy_resolve_fc(phy, params, vars);
8988 vars->duplex = DUPLEX_FULL;
8989 PMD_DRV_LOG(DEBUG, "duplex = 0x%x", vars->duplex);
8992 if ((ELINK_DUAL_MEDIA(params)) &&
8993 (phy->req_line_speed == ELINK_SPEED_1000)) {
8994 elink_cl45_read(sc, phy,
8996 MDIO_PMA_REG_8727_PCS_GP, &val1);
8997 /* In case of dual-media board and 1G, power up the XAUI side,
8998 * otherwise power it down. For 10G it is done automatically
9004 elink_cl45_write(sc, phy,
9006 MDIO_PMA_REG_8727_PCS_GP, val1);
9011 static void elink_8727_link_reset(struct elink_phy *phy,
9012 struct elink_params *params)
9014 struct bnx2x_softc *sc = params->sc;
9016 /* Enable/Disable PHY transmitter output */
9017 elink_set_disable_pmd_transmit(params, phy, 1);
9019 /* Disable Transmitter */
9020 elink_sfp_set_transmitter(params, phy, 0);
9022 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9026 /******************************************************************/
9027 /* BNX2X8481/BNX2X84823/BNX2X84833 PHY SECTION */
9028 /******************************************************************/
9029 static void elink_save_848xx_spirom_version(struct elink_phy *phy,
9030 struct bnx2x_softc *sc, uint8_t port)
9032 uint16_t val, fw_ver2, cnt, i;
9033 static struct elink_reg_set reg_set[] = {
9034 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9035 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9036 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9037 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9038 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9042 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9043 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9044 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9045 elink_save_spirom_version(sc, port, fw_ver1 & 0xfff,
9048 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9049 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9050 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9051 elink_cl45_write(sc, phy, reg_set[i].devad,
9052 reg_set[i].reg, reg_set[i].val);
9054 for (cnt = 0; cnt < 100; cnt++) {
9055 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9061 PMD_DRV_LOG(DEBUG, "Unable to read 848xx "
9062 "phy fw version(1)");
9063 elink_save_spirom_version(sc, port, 0, phy->ver_addr);
9067 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9068 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9069 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9070 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9071 for (cnt = 0; cnt < 100; cnt++) {
9072 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9078 PMD_DRV_LOG(DEBUG, "Unable to read 848xx phy fw "
9080 elink_save_spirom_version(sc, port, 0, phy->ver_addr);
9084 /* lower 16 bits of the register SPI_FW_STATUS */
9085 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9086 /* upper 16 bits of register SPI_FW_STATUS */
9087 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9089 elink_save_spirom_version(sc, port, (fw_ver2 << 16) | fw_ver1,
9095 static void elink_848xx_set_led(struct bnx2x_softc *sc, struct elink_phy *phy)
9097 uint16_t val, offset, i;
9098 static struct elink_reg_set reg_set[] = {
9099 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9100 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9101 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9102 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9103 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9104 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9105 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9107 /* PHYC_CTL_LED_CTL */
9108 elink_cl45_read(sc, phy,
9109 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9113 elink_cl45_write(sc, phy,
9114 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9116 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9117 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
9120 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9121 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))
9122 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9124 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9126 /* stretch_en for LED3 */
9127 elink_cl45_read_or_write(sc, phy,
9128 MDIO_PMA_DEVAD, offset,
9129 MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9132 static void elink_848xx_specific_func(struct elink_phy *phy,
9133 struct elink_params *params,
9136 struct bnx2x_softc *sc = params->sc;
9138 case ELINK_PHY_INIT:
9139 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
9140 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9141 /* Save spirom version */
9142 elink_save_848xx_spirom_version(phy, sc, params->port);
9144 /* This phy uses the NIG latch mechanism since link indication
9145 * arrives through its LED4 and not via its LASI signal, so we
9146 * get steady signal instead of clear on read
9148 elink_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port * 4,
9149 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
9151 elink_848xx_set_led(sc, phy);
9156 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
9157 struct elink_params *params,
9158 struct elink_vars *vars)
9160 struct bnx2x_softc *sc = params->sc;
9161 uint16_t autoneg_val, an_1000_val, an_10_100_val;
9163 elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);
9164 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9166 /* set 1000 speed advertisement */
9167 elink_cl45_read(sc, phy,
9168 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9171 elink_ext_phy_set_pause(params, phy, vars);
9172 elink_cl45_read(sc, phy,
9174 MDIO_AN_REG_8481_LEGACY_AN_ADV, &an_10_100_val);
9175 elink_cl45_read(sc, phy,
9176 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9178 /* Disable forced speed */
9180 ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
9181 an_10_100_val &= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8));
9183 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
9184 (phy->speed_cap_mask &
9185 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9186 (phy->req_line_speed == ELINK_SPEED_1000)) {
9187 an_1000_val |= (1 << 8);
9188 autoneg_val |= (1 << 9 | 1 << 12);
9189 if (phy->req_duplex == DUPLEX_FULL)
9190 an_1000_val |= (1 << 9);
9191 PMD_DRV_LOG(DEBUG, "Advertising 1G");
9193 an_1000_val &= ~((1 << 8) | (1 << 9));
9195 elink_cl45_write(sc, phy,
9196 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9199 /* Set 10/100 speed advertisement */
9200 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
9201 if (phy->speed_cap_mask &
9202 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9203 /* Enable autoneg and restart autoneg for legacy speeds
9205 autoneg_val |= (1 << 9 | 1 << 12);
9206 an_10_100_val |= (1 << 8);
9207 PMD_DRV_LOG(DEBUG, "Advertising 100M-FD");
9210 if (phy->speed_cap_mask &
9211 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9212 /* Enable autoneg and restart autoneg for legacy speeds
9214 autoneg_val |= (1 << 9 | 1 << 12);
9215 an_10_100_val |= (1 << 7);
9216 PMD_DRV_LOG(DEBUG, "Advertising 100M-HD");
9219 if ((phy->speed_cap_mask &
9220 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
9221 (phy->supported & ELINK_SUPPORTED_10baseT_Full)) {
9222 an_10_100_val |= (1 << 6);
9223 autoneg_val |= (1 << 9 | 1 << 12);
9224 PMD_DRV_LOG(DEBUG, "Advertising 10M-FD");
9227 if ((phy->speed_cap_mask &
9228 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
9229 (phy->supported & ELINK_SUPPORTED_10baseT_Half)) {
9230 an_10_100_val |= (1 << 5);
9231 autoneg_val |= (1 << 9 | 1 << 12);
9232 PMD_DRV_LOG(DEBUG, "Advertising 10M-HD");
9236 /* Only 10/100 are allowed to work in FORCE mode */
9237 if ((phy->req_line_speed == ELINK_SPEED_100) &&
9239 (ELINK_SUPPORTED_100baseT_Half | ELINK_SUPPORTED_100baseT_Full))) {
9240 autoneg_val |= (1 << 13);
9241 /* Enabled AUTO-MDIX when autoneg is disabled */
9242 elink_cl45_write(sc, phy,
9243 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9244 (1 << 15 | 1 << 9 | 7 << 0));
9245 /* The PHY needs this set even for forced link. */
9246 an_10_100_val |= (1 << 8) | (1 << 7);
9247 PMD_DRV_LOG(DEBUG, "Setting 100M force");
9249 if ((phy->req_line_speed == ELINK_SPEED_10) &&
9251 (ELINK_SUPPORTED_10baseT_Half | ELINK_SUPPORTED_10baseT_Full))) {
9252 /* Enabled AUTO-MDIX when autoneg is disabled */
9253 elink_cl45_write(sc, phy,
9254 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9255 (1 << 15 | 1 << 9 | 7 << 0));
9256 PMD_DRV_LOG(DEBUG, "Setting 10M force");
9259 elink_cl45_write(sc, phy,
9260 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9263 if (phy->req_duplex == DUPLEX_FULL)
9264 autoneg_val |= (1 << 8);
9266 /* Always write this if this is not 84833/4.
9267 * For 84833/4, write it only when it's a forced speed.
9269 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
9270 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) ||
9271 ((autoneg_val & (1 << 12)) == 0))
9272 elink_cl45_write(sc, phy,
9274 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9276 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
9277 (phy->speed_cap_mask &
9278 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9279 (phy->req_line_speed == ELINK_SPEED_10000)) {
9280 PMD_DRV_LOG(DEBUG, "Advertising 10G");
9281 /* Restart autoneg for 10G */
9283 elink_cl45_read_or_write(sc, phy,
9285 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9287 elink_cl45_write(sc, phy,
9288 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x3200);
9290 elink_cl45_write(sc, phy,
9292 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 1);
9294 return ELINK_STATUS_OK;
9297 static uint8_t elink_8481_config_init(struct elink_phy *phy,
9298 struct elink_params *params,
9299 struct elink_vars *vars)
9301 struct bnx2x_softc *sc = params->sc;
9302 /* Restore normal power mode */
9303 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
9304 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9307 elink_ext_phy_hw_reset(sc, params->port);
9308 elink_wait_reset_complete(sc, phy, params);
9310 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
9311 return elink_848xx_cmn_config_init(phy, params, vars);
9314 #define PHY84833_CMDHDLR_WAIT 300
9315 #define PHY84833_CMDHDLR_MAX_ARGS 5
9316 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
9317 struct elink_params *params,
9318 uint16_t fw_cmd, uint16_t cmd_args[],
9323 struct bnx2x_softc *sc = params->sc;
9324 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9325 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9326 MDIO_84833_CMD_HDLR_STATUS,
9327 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9328 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9329 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9330 MDIO_84833_CMD_HDLR_STATUS, &val);
9331 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9335 if (idx >= PHY84833_CMDHDLR_WAIT) {
9336 PMD_DRV_LOG(DEBUG, "FW cmd: FW not ready.");
9337 return ELINK_STATUS_ERROR;
9340 /* Prepare argument(s) and issue command */
9341 for (idx = 0; idx < argc; idx++) {
9342 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9343 MDIO_84833_CMD_HDLR_DATA1 + idx,
9346 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9347 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9348 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9349 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9350 MDIO_84833_CMD_HDLR_STATUS, &val);
9351 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9352 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9356 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9357 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9358 PMD_DRV_LOG(DEBUG, "FW cmd failed.");
9359 return ELINK_STATUS_ERROR;
9361 /* Gather returning data */
9362 for (idx = 0; idx < argc; idx++) {
9363 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9364 MDIO_84833_CMD_HDLR_DATA1 + idx,
9367 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9368 MDIO_84833_CMD_HDLR_STATUS,
9369 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9370 return ELINK_STATUS_OK;
9373 static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy,
9374 struct elink_params *params,
9375 __rte_unused struct elink_vars
9379 uint16_t data[PHY84833_CMDHDLR_MAX_ARGS];
9380 elink_status_t status;
9381 struct bnx2x_softc *sc = params->sc;
9383 /* Check for configuration. */
9384 pair_swap = REG_RD(sc, params->shmem_base +
9385 offsetof(struct shmem_region,
9386 dev_info.port_hw_config[params->port].
9388 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9391 return ELINK_STATUS_OK;
9393 /* Only the second argument is used for this command */
9394 data[1] = (uint16_t) pair_swap;
9396 status = elink_84833_cmd_hdlr(phy, params,
9397 PHY84833_CMD_SET_PAIR_SWAP, data,
9398 PHY84833_CMDHDLR_MAX_ARGS);
9399 if (status == ELINK_STATUS_OK) {
9400 PMD_DRV_LOG(DEBUG, "Pairswap OK, val=0x%x", data[1]);
9406 static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc *sc,
9407 uint32_t shmem_base_path[],
9408 __rte_unused uint32_t chip_id)
9410 uint32_t reset_pin[2];
9412 uint8_t reset_gpios;
9413 if (CHIP_IS_E3(sc)) {
9414 /* Assume that these will be GPIOs, not EPIOs. */
9415 for (idx = 0; idx < 2; idx++) {
9416 /* Map config param to register bit. */
9417 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
9418 offsetof(struct shmem_region,
9423 (reset_pin[idx] & PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9424 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9425 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9426 reset_pin[idx] = (1 << reset_pin[idx]);
9428 reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);
9430 /* E2, look from diff place of shmem. */
9431 for (idx = 0; idx < 2; idx++) {
9432 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
9433 offsetof(struct shmem_region,
9437 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9438 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9439 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9440 reset_pin[idx] = (1 << reset_pin[idx]);
9442 reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);
9448 static void elink_84833_hw_reset_phy(struct elink_phy *phy,
9449 struct elink_params *params)
9451 struct bnx2x_softc *sc = params->sc;
9452 uint8_t reset_gpios;
9453 uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +
9454 offsetof(struct shmem2_region,
9455 other_shmem_base_addr));
9457 uint32_t shmem_base_path[2];
9459 /* Work around for 84833 LED failure inside RESET status */
9460 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
9461 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9462 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9463 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
9464 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9465 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9467 shmem_base_path[0] = params->shmem_base;
9468 shmem_base_path[1] = other_shmem_base_addr;
9470 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path,
9473 elink_cb_gpio_mult_write(sc, reset_gpios,
9474 MISC_REGISTERS_GPIO_OUTPUT_LOW);
9476 PMD_DRV_LOG(DEBUG, "84833 hw reset on pin values 0x%x", reset_gpios);
9479 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
9480 struct elink_params *params,
9481 struct elink_vars *vars)
9484 uint16_t cmd_args = 0;
9486 PMD_DRV_LOG(DEBUG, "Don't Advertise 10GBase-T EEE");
9488 /* Prevent Phy from working in EEE and advertising it */
9489 rc = elink_84833_cmd_hdlr(phy, params,
9490 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9491 if (rc != ELINK_STATUS_OK) {
9492 PMD_DRV_LOG(DEBUG, "EEE disable failed.");
9496 return elink_eee_disable(phy, params, vars);
9499 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
9500 struct elink_params *params,
9501 struct elink_vars *vars)
9504 uint16_t cmd_args = 1;
9506 rc = elink_84833_cmd_hdlr(phy, params,
9507 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9508 if (rc != ELINK_STATUS_OK) {
9509 PMD_DRV_LOG(DEBUG, "EEE enable failed.");
9513 return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
9516 #define PHY84833_CONSTANT_LATENCY 1193
9517 static uint8_t elink_848x3_config_init(struct elink_phy *phy,
9518 struct elink_params *params,
9519 struct elink_vars *vars)
9521 struct bnx2x_softc *sc = params->sc;
9522 uint8_t port, initialize = 1;
9524 uint32_t actual_phy_selection;
9525 uint16_t cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
9526 elink_status_t rc = ELINK_STATUS_OK;
9530 if (!(CHIP_IS_E1x(sc)))
9533 port = params->port;
9535 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
9536 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
9537 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
9540 elink_cl45_write(sc, phy,
9541 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x8000);
9544 elink_wait_reset_complete(sc, phy, params);
9546 /* Wait for GPHY to come out of reset */
9548 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
9549 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9550 /* BNX2X84823 requires that XGXS links up first @ 10G for normal
9554 temp = vars->line_speed;
9555 vars->line_speed = ELINK_SPEED_10000;
9556 elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0);
9557 elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars);
9558 vars->line_speed = temp;
9561 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9562 MDIO_CTL_REG_84823_MEDIA, &val);
9563 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9564 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9565 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9566 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9567 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9569 if (CHIP_IS_E3(sc)) {
9570 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9571 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9573 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9574 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9577 actual_phy_selection = elink_phy_selection(params);
9579 switch (actual_phy_selection) {
9580 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9581 /* Do nothing. Essentially this is like the priority copper */
9583 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9584 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9586 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9587 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9589 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9590 /* Do nothing here. The first PHY won't be initialized at all */
9592 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9593 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9597 if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000)
9598 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9600 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9601 MDIO_CTL_REG_84823_MEDIA, val);
9602 PMD_DRV_LOG(DEBUG, "Multi_phy config = 0x%x, Media control = 0x%x",
9603 params->multi_phy_config, val);
9605 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9606 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9607 elink_84833_pair_swap_cfg(phy, params, vars);
9609 /* Keep AutogrEEEn disabled. */
9612 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
9613 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
9614 rc = elink_84833_cmd_hdlr(phy, params,
9615 PHY84833_CMD_SET_EEE_MODE, cmd_args,
9616 PHY84833_CMDHDLR_MAX_ARGS);
9617 if (rc != ELINK_STATUS_OK) {
9618 PMD_DRV_LOG(DEBUG, "Cfg AutogrEEEn failed.");
9622 rc = elink_848xx_cmn_config_init(phy, params, vars);
9624 elink_save_848xx_spirom_version(phy, sc, params->port);
9626 /* 84833 PHY has a better feature and doesn't need to support this. */
9627 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
9628 uint32_t cms_enable = REG_RD(sc, params->shmem_base +
9629 offsetof(struct shmem_region,
9631 port_hw_config[params->
9634 PORT_HW_CFG_ENABLE_CMS_MASK;
9636 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9637 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9639 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9641 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9642 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9643 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9646 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9647 MDIO_84833_TOP_CFG_FW_REV, &val);
9649 /* Configure EEE support */
9650 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
9651 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
9652 elink_eee_has_cap(params)) {
9653 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
9654 if (rc != ELINK_STATUS_OK) {
9655 PMD_DRV_LOG(DEBUG, "Failed to configure EEE timers");
9656 elink_8483x_disable_eee(phy, params, vars);
9660 if ((phy->req_duplex == DUPLEX_FULL) &&
9661 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
9662 (elink_eee_calc_timer(params) ||
9663 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)))
9664 rc = elink_8483x_enable_eee(phy, params, vars);
9666 rc = elink_8483x_disable_eee(phy, params, vars);
9667 if (rc != ELINK_STATUS_OK) {
9668 PMD_DRV_LOG(DEBUG, "Failed to set EEE advertisement");
9672 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
9675 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9676 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9677 /* Bring PHY out of super isolate mode as the final step. */
9678 elink_cl45_read_and_write(sc, phy,
9680 MDIO_84833_TOP_CFG_XGPHY_STRAP1,
9682 MDIO_84833_SUPER_ISOLATE);
9687 static uint8_t elink_848xx_read_status(struct elink_phy *phy,
9688 struct elink_params *params,
9689 struct elink_vars *vars)
9691 struct bnx2x_softc *sc = params->sc;
9692 uint16_t val, val1, val2;
9693 uint8_t link_up = 0;
9695 /* Check 10G-BaseT link status */
9696 /* Check PMD signal ok */
9697 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 0xFFFA, &val1);
9698 elink_cl45_read(sc, phy,
9699 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, &val2);
9700 PMD_DRV_LOG(DEBUG, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2);
9702 /* Check link 10G */
9703 if (val2 & (1 << 11)) {
9704 vars->line_speed = ELINK_SPEED_10000;
9705 vars->duplex = DUPLEX_FULL;
9707 elink_ext_phy_10G_an_resolve(sc, phy, vars);
9708 } else { /* Check Legacy speed link */
9709 uint16_t legacy_status, legacy_speed, mii_ctrl;
9711 /* Enable expansion register 0x42 (Operation mode status) */
9712 elink_cl45_write(sc, phy,
9714 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9716 /* Get legacy speed operation status */
9717 elink_cl45_read(sc, phy,
9719 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9722 PMD_DRV_LOG(DEBUG, "Legacy speed status = 0x%x", legacy_status);
9723 link_up = ((legacy_status & (1 << 11)) == (1 << 11));
9724 legacy_speed = (legacy_status & (3 << 9));
9725 if (legacy_speed == (0 << 9))
9726 vars->line_speed = ELINK_SPEED_10;
9727 else if (legacy_speed == (1 << 9))
9728 vars->line_speed = ELINK_SPEED_100;
9729 else if (legacy_speed == (2 << 9))
9730 vars->line_speed = ELINK_SPEED_1000;
9731 else { /* Should not happen: Treat as link down */
9732 vars->line_speed = 0;
9736 if (params->feature_config_flags &
9737 ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {
9738 elink_cl45_read(sc, phy,
9740 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9742 /* For IEEE testing, check for a fake link. */
9743 link_up |= ((mii_ctrl & 0x3040) == 0x40);
9747 if (legacy_status & (1 << 8))
9748 vars->duplex = DUPLEX_FULL;
9750 vars->duplex = DUPLEX_HALF;
9753 "Link is up in %dMbps, is_duplex_full= %d",
9755 (vars->duplex == DUPLEX_FULL));
9756 /* Check legacy speed AN resolution */
9757 elink_cl45_read(sc, phy,
9759 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9762 vars->link_status |=
9763 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9764 elink_cl45_read(sc, phy,
9766 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9768 if ((val & (1 << 0)) == 0)
9769 vars->link_status |=
9770 LINK_STATUS_PARALLEL_DETECTION_USED;
9774 PMD_DRV_LOG(DEBUG, "BNX2X848x3: link speed is %d",
9776 elink_ext_phy_resolve_fc(phy, params, vars);
9778 /* Read LP advertised speeds */
9779 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
9780 MDIO_AN_REG_CL37_FC_LP, &val);
9782 vars->link_status |=
9783 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
9785 vars->link_status |=
9786 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
9788 vars->link_status |=
9789 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
9791 vars->link_status |=
9792 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
9794 vars->link_status |=
9795 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
9797 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
9798 MDIO_AN_REG_1000T_STATUS, &val);
9800 if (val & (1 << 10))
9801 vars->link_status |=
9802 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
9803 if (val & (1 << 11))
9804 vars->link_status |=
9805 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
9807 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
9808 MDIO_AN_REG_MASTER_STATUS, &val);
9810 if (val & (1 << 11))
9811 vars->link_status |=
9812 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
9814 /* Determine if EEE was negotiated */
9815 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9816 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))
9817 elink_eee_an_resolve(phy, params, vars);
9823 static uint8_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t * str,
9826 elink_status_t status = ELINK_STATUS_OK;
9827 uint32_t spirom_ver;
9828 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9829 status = elink_format_ver(spirom_ver, str, len);
9833 static void elink_8481_hw_reset(__rte_unused struct elink_phy *phy,
9834 struct elink_params *params)
9836 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
9837 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9838 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
9839 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9842 static void elink_8481_link_reset(struct elink_phy *phy,
9843 struct elink_params *params)
9845 elink_cl45_write(params->sc, phy,
9846 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9847 elink_cl45_write(params->sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9850 static void elink_848x3_link_reset(struct elink_phy *phy,
9851 struct elink_params *params)
9853 struct bnx2x_softc *sc = params->sc;
9857 if (!(CHIP_IS_E1x(sc)))
9860 port = params->port;
9862 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
9863 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
9864 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9866 elink_cl45_read(sc, phy,
9868 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
9869 val16 |= MDIO_84833_SUPER_ISOLATE;
9870 elink_cl45_write(sc, phy,
9872 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
9876 static void elink_848xx_set_link_led(struct elink_phy *phy,
9877 struct elink_params *params, uint8_t mode)
9879 struct bnx2x_softc *sc = params->sc;
9881 __rte_unused uint8_t port;
9883 if (!(CHIP_IS_E1x(sc)))
9886 port = params->port;
9889 case ELINK_LED_MODE_OFF:
9891 PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE OFF", port);
9893 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9894 SHARED_HW_CFG_LED_EXTPHY1) {
9897 elink_cl45_write(sc, phy,
9899 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9901 elink_cl45_write(sc, phy,
9903 MDIO_PMA_REG_8481_LED2_MASK, 0x0);
9905 elink_cl45_write(sc, phy,
9907 MDIO_PMA_REG_8481_LED3_MASK, 0x0);
9909 elink_cl45_write(sc, phy,
9911 MDIO_PMA_REG_8481_LED5_MASK, 0x0);
9914 elink_cl45_write(sc, phy,
9916 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9919 case ELINK_LED_MODE_FRONT_PANEL_OFF:
9921 PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE FRONT PANEL OFF", port);
9923 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9924 SHARED_HW_CFG_LED_EXTPHY1) {
9927 elink_cl45_write(sc, phy,
9929 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9931 elink_cl45_write(sc, phy,
9933 MDIO_PMA_REG_8481_LED2_MASK, 0x0);
9935 elink_cl45_write(sc, phy,
9937 MDIO_PMA_REG_8481_LED3_MASK, 0x0);
9939 elink_cl45_write(sc, phy,
9941 MDIO_PMA_REG_8481_LED5_MASK, 0x20);
9944 elink_cl45_write(sc, phy,
9946 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9947 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
9948 /* Disable MI_INT interrupt before setting LED4
9949 * source to constant off.
9951 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
9953 ELINK_NIG_MASK_MI_INT) {
9954 params->link_flags |=
9955 ELINK_LINK_FLAGS_INT_DISABLED;
9958 NIG_REG_MASK_INTERRUPT_PORT0
9960 ELINK_NIG_MASK_MI_INT);
9962 elink_cl45_write(sc, phy,
9964 MDIO_PMA_REG_8481_SIGNAL_MASK,
9969 case ELINK_LED_MODE_ON:
9971 PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE ON", port);
9973 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9974 SHARED_HW_CFG_LED_EXTPHY1) {
9975 /* Set control reg */
9976 elink_cl45_read(sc, phy,
9978 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9982 elink_cl45_write(sc, phy,
9984 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9987 elink_cl45_write(sc, phy,
9989 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9991 elink_cl45_write(sc, phy,
9993 MDIO_PMA_REG_8481_LED2_MASK, 0x20);
9995 elink_cl45_write(sc, phy,
9997 MDIO_PMA_REG_8481_LED3_MASK, 0x20);
9999 elink_cl45_write(sc, phy,
10001 MDIO_PMA_REG_8481_LED5_MASK, 0x0);
10003 elink_cl45_write(sc, phy,
10005 MDIO_PMA_REG_8481_LED1_MASK, 0x20);
10006 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
10007 /* Disable MI_INT interrupt before setting LED4
10008 * source to constant on.
10010 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
10011 params->port * 4) &
10012 ELINK_NIG_MASK_MI_INT) {
10013 params->link_flags |=
10014 ELINK_LINK_FLAGS_INT_DISABLED;
10017 NIG_REG_MASK_INTERRUPT_PORT0
10018 + params->port * 4,
10019 ELINK_NIG_MASK_MI_INT);
10021 elink_cl45_write(sc, phy,
10023 MDIO_PMA_REG_8481_SIGNAL_MASK,
10029 case ELINK_LED_MODE_OPER:
10031 PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE OPER", port);
10033 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10034 SHARED_HW_CFG_LED_EXTPHY1) {
10036 /* Set control reg */
10037 elink_cl45_read(sc, phy,
10039 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
10042 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10044 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT))
10046 PMD_DRV_LOG(DEBUG, "Setting LINK_SIGNAL");
10047 elink_cl45_write(sc, phy,
10049 MDIO_PMA_REG_8481_LINK_SIGNAL,
10053 /* Set LED masks */
10054 elink_cl45_write(sc, phy,
10056 MDIO_PMA_REG_8481_LED1_MASK, 0x10);
10058 elink_cl45_write(sc, phy,
10060 MDIO_PMA_REG_8481_LED2_MASK, 0x80);
10062 elink_cl45_write(sc, phy,
10064 MDIO_PMA_REG_8481_LED3_MASK, 0x98);
10066 elink_cl45_write(sc, phy,
10068 MDIO_PMA_REG_8481_LED5_MASK, 0x40);
10071 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
10072 * sources are all wired through LED1, rather than only
10073 * 10G in other modes.
10075 val = ((params->hw_led_mode <<
10076 SHARED_HW_CFG_LED_MODE_SHIFT) ==
10077 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
10079 elink_cl45_write(sc, phy,
10081 MDIO_PMA_REG_8481_LED1_MASK, val);
10083 /* Tell LED3 to blink on source */
10084 elink_cl45_read(sc, phy,
10086 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
10088 val |= (1 << 6); /* A83B[8:6]= 1 */
10089 elink_cl45_write(sc, phy,
10091 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
10092 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
10093 /* Restore LED4 source to external link,
10094 * and re-enable interrupts.
10096 elink_cl45_write(sc, phy,
10098 MDIO_PMA_REG_8481_SIGNAL_MASK,
10100 if (params->link_flags &
10101 ELINK_LINK_FLAGS_INT_DISABLED) {
10102 elink_link_int_enable(params);
10103 params->link_flags &=
10104 ~ELINK_LINK_FLAGS_INT_DISABLED;
10111 /* This is a workaround for E3+84833 until autoneg
10112 * restart is fixed in f/w
10114 if (CHIP_IS_E3(sc)) {
10115 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
10116 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10120 /******************************************************************/
10121 /* 54618SE PHY SECTION */
10122 /******************************************************************/
10123 static void elink_54618se_specific_func(struct elink_phy *phy,
10124 struct elink_params *params,
10127 struct bnx2x_softc *sc = params->sc;
10130 case ELINK_PHY_INIT:
10131 /* Configure LED4: set to INTR (0x6). */
10132 /* Accessing shadow register 0xe. */
10133 elink_cl22_write(sc, phy,
10134 MDIO_REG_GPHY_SHADOW,
10135 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10136 elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
10137 temp &= ~(0xf << 4);
10138 temp |= (0x6 << 4);
10139 elink_cl22_write(sc, phy,
10140 MDIO_REG_GPHY_SHADOW,
10141 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10142 /* Configure INTR based on link status change. */
10143 elink_cl22_write(sc, phy,
10144 MDIO_REG_INTR_MASK,
10145 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10150 static uint8_t elink_54618se_config_init(struct elink_phy *phy,
10151 struct elink_params *params,
10152 struct elink_vars *vars)
10154 struct bnx2x_softc *sc = params->sc;
10156 uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10159 PMD_DRV_LOG(DEBUG, "54618SE cfg init");
10162 /* This works with E3 only, no need to check the chip
10163 * before determining the port.
10165 port = params->port;
10167 cfg_pin = (REG_RD(sc, params->shmem_base +
10168 offsetof(struct shmem_region,
10169 dev_info.port_hw_config[port].
10171 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10172 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10174 /* Drive pin high to bring the GPHY out of reset. */
10175 elink_set_cfg_pin(sc, cfg_pin, 1);
10177 /* wait for GPHY to reset */
10181 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x8000);
10182 elink_wait_reset_complete(sc, phy, params);
10184 /* Wait for GPHY to reset */
10187 elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);
10188 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10189 elink_cl22_write(sc, phy,
10190 MDIO_REG_GPHY_SHADOW,
10191 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10192 elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
10193 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10194 elink_cl22_write(sc, phy,
10195 MDIO_REG_GPHY_SHADOW,
10196 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10199 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10200 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10202 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10203 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10204 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10206 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10207 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10208 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10210 /* Read all advertisement */
10211 elink_cl22_read(sc, phy, 0x09, &an_1000_val);
10213 elink_cl22_read(sc, phy, 0x04, &an_10_100_val);
10215 elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &autoneg_val);
10217 /* Disable forced speed */
10219 ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
10221 ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 10) |
10224 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10225 (phy->speed_cap_mask &
10226 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10227 (phy->req_line_speed == ELINK_SPEED_1000)) {
10228 an_1000_val |= (1 << 8);
10229 autoneg_val |= (1 << 9 | 1 << 12);
10230 if (phy->req_duplex == DUPLEX_FULL)
10231 an_1000_val |= (1 << 9);
10232 PMD_DRV_LOG(DEBUG, "Advertising 1G");
10234 an_1000_val &= ~((1 << 8) | (1 << 9));
10236 elink_cl22_write(sc, phy, 0x09, an_1000_val);
10237 elink_cl22_read(sc, phy, 0x09, &an_1000_val);
10239 /* Advertise 10/100 link speed */
10240 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
10241 if (phy->speed_cap_mask &
10242 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
10243 an_10_100_val |= (1 << 5);
10244 autoneg_val |= (1 << 9 | 1 << 12);
10245 PMD_DRV_LOG(DEBUG, "Advertising 10M-HD");
10247 if (phy->speed_cap_mask &
10248 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
10249 an_10_100_val |= (1 << 6);
10250 autoneg_val |= (1 << 9 | 1 << 12);
10251 PMD_DRV_LOG(DEBUG, "Advertising 10M-FD");
10253 if (phy->speed_cap_mask &
10254 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
10255 an_10_100_val |= (1 << 7);
10256 autoneg_val |= (1 << 9 | 1 << 12);
10257 PMD_DRV_LOG(DEBUG, "Advertising 100M-HD");
10259 if (phy->speed_cap_mask &
10260 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
10261 an_10_100_val |= (1 << 8);
10262 autoneg_val |= (1 << 9 | 1 << 12);
10263 PMD_DRV_LOG(DEBUG, "Advertising 100M-FD");
10267 /* Only 10/100 are allowed to work in FORCE mode */
10268 if (phy->req_line_speed == ELINK_SPEED_100) {
10269 autoneg_val |= (1 << 13);
10270 /* Enabled AUTO-MDIX when autoneg is disabled */
10271 elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
10272 PMD_DRV_LOG(DEBUG, "Setting 100M force");
10274 if (phy->req_line_speed == ELINK_SPEED_10) {
10275 /* Enabled AUTO-MDIX when autoneg is disabled */
10276 elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
10277 PMD_DRV_LOG(DEBUG, "Setting 10M force");
10280 if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {
10283 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS,
10284 MDIO_REG_GPHY_EXP_ACCESS_TOP |
10285 MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10286 elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10288 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10290 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10291 if (rc != ELINK_STATUS_OK) {
10292 PMD_DRV_LOG(DEBUG, "Failed to configure EEE timers");
10293 elink_eee_disable(phy, params, vars);
10294 } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
10295 (phy->req_duplex == DUPLEX_FULL) &&
10296 (elink_eee_calc_timer(params) ||
10297 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) {
10298 /* Need to advertise EEE only when requested,
10299 * and either no LPI assertion was requested,
10300 * or it was requested and a valid timer was set.
10301 * Also notice full duplex is required for EEE.
10303 elink_eee_advertise(phy, params, vars,
10306 PMD_DRV_LOG(DEBUG, "Don't Advertise 1GBase-T EEE");
10307 elink_eee_disable(phy, params, vars);
10310 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10311 SHMEM_EEE_SUPPORTED_SHIFT;
10313 if (phy->flags & ELINK_FLAGS_EEE) {
10314 /* Handle legacy auto-grEEEn */
10315 if (params->feature_config_flags &
10316 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10318 PMD_DRV_LOG(DEBUG, "Enabling Auto-GrEEEn");
10321 PMD_DRV_LOG(DEBUG, "Don't Adv. EEE");
10323 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
10324 MDIO_AN_REG_EEE_ADV, temp);
10328 elink_cl22_write(sc, phy, 0x04, an_10_100_val | fc_val);
10330 if (phy->req_duplex == DUPLEX_FULL)
10331 autoneg_val |= (1 << 8);
10333 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, autoneg_val);
10335 return ELINK_STATUS_OK;
10338 static void elink_5461x_set_link_led(struct elink_phy *phy,
10339 struct elink_params *params, uint8_t mode)
10341 struct bnx2x_softc *sc = params->sc;
10344 elink_cl22_write(sc, phy,
10345 MDIO_REG_GPHY_SHADOW, MDIO_REG_GPHY_SHADOW_LED_SEL1);
10346 elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
10349 PMD_DRV_LOG(DEBUG, "54618x set link led (mode=%x)", mode);
10351 case ELINK_LED_MODE_FRONT_PANEL_OFF:
10352 case ELINK_LED_MODE_OFF:
10355 case ELINK_LED_MODE_OPER:
10358 case ELINK_LED_MODE_ON:
10364 elink_cl22_write(sc, phy,
10365 MDIO_REG_GPHY_SHADOW,
10366 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10370 static void elink_54618se_link_reset(struct elink_phy *phy,
10371 struct elink_params *params)
10373 struct bnx2x_softc *sc = params->sc;
10377 /* In case of no EPIO routed to reset the GPHY, put it
10378 * in low power mode.
10380 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);
10381 /* This works with E3 only, no need to check the chip
10382 * before determining the port.
10384 port = params->port;
10385 cfg_pin = (REG_RD(sc, params->shmem_base +
10386 offsetof(struct shmem_region,
10387 dev_info.port_hw_config[port].
10389 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10390 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10392 /* Drive pin low to put GPHY in reset. */
10393 elink_set_cfg_pin(sc, cfg_pin, 0);
10396 static uint8_t elink_54618se_read_status(struct elink_phy *phy,
10397 struct elink_params *params,
10398 struct elink_vars *vars)
10400 struct bnx2x_softc *sc = params->sc;
10402 uint8_t link_up = 0;
10403 uint16_t legacy_status, legacy_speed;
10405 /* Get speed operation status */
10406 elink_cl22_read(sc, phy, MDIO_REG_GPHY_AUX_STATUS, &legacy_status);
10407 PMD_DRV_LOG(DEBUG, "54618SE read_status: 0x%x", legacy_status);
10409 /* Read status to clear the PHY interrupt. */
10410 elink_cl22_read(sc, phy, MDIO_REG_INTR_STATUS, &val);
10412 link_up = ((legacy_status & (1 << 2)) == (1 << 2));
10415 legacy_speed = (legacy_status & (7 << 8));
10416 if (legacy_speed == (7 << 8)) {
10417 vars->line_speed = ELINK_SPEED_1000;
10418 vars->duplex = DUPLEX_FULL;
10419 } else if (legacy_speed == (6 << 8)) {
10420 vars->line_speed = ELINK_SPEED_1000;
10421 vars->duplex = DUPLEX_HALF;
10422 } else if (legacy_speed == (5 << 8)) {
10423 vars->line_speed = ELINK_SPEED_100;
10424 vars->duplex = DUPLEX_FULL;
10426 /* Omitting 100Base-T4 for now */
10427 else if (legacy_speed == (3 << 8)) {
10428 vars->line_speed = ELINK_SPEED_100;
10429 vars->duplex = DUPLEX_HALF;
10430 } else if (legacy_speed == (2 << 8)) {
10431 vars->line_speed = ELINK_SPEED_10;
10432 vars->duplex = DUPLEX_FULL;
10433 } else if (legacy_speed == (1 << 8)) {
10434 vars->line_speed = ELINK_SPEED_10;
10435 vars->duplex = DUPLEX_HALF;
10436 } else /* Should not happen */
10437 vars->line_speed = 0;
10440 "Link is up in %dMbps, is_duplex_full= %d",
10441 vars->line_speed, (vars->duplex == DUPLEX_FULL));
10443 /* Check legacy speed AN resolution */
10444 elink_cl22_read(sc, phy, 0x01, &val);
10445 if (val & (1 << 5))
10446 vars->link_status |=
10447 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10448 elink_cl22_read(sc, phy, 0x06, &val);
10449 if ((val & (1 << 0)) == 0)
10450 vars->link_status |=
10451 LINK_STATUS_PARALLEL_DETECTION_USED;
10453 PMD_DRV_LOG(DEBUG, "BNX2X54618SE: link speed is %d",
10456 elink_ext_phy_resolve_fc(phy, params, vars);
10458 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
10459 /* Report LP advertised speeds */
10460 elink_cl22_read(sc, phy, 0x5, &val);
10462 if (val & (1 << 5))
10463 vars->link_status |=
10464 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10465 if (val & (1 << 6))
10466 vars->link_status |=
10467 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10468 if (val & (1 << 7))
10469 vars->link_status |=
10470 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10471 if (val & (1 << 8))
10472 vars->link_status |=
10473 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10474 if (val & (1 << 9))
10475 vars->link_status |=
10476 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10478 elink_cl22_read(sc, phy, 0xa, &val);
10479 if (val & (1 << 10))
10480 vars->link_status |=
10481 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10482 if (val & (1 << 11))
10483 vars->link_status |=
10484 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10486 if ((phy->flags & ELINK_FLAGS_EEE) &&
10487 elink_eee_has_cap(params))
10488 elink_eee_an_resolve(phy, params, vars);
10494 static void elink_54618se_config_loopback(struct elink_phy *phy,
10495 struct elink_params *params)
10497 struct bnx2x_softc *sc = params->sc;
10499 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10501 PMD_DRV_LOG(DEBUG, "2PMA/PMD ext_phy_loopback: 54618se");
10503 /* Enable master/slave manual mmode and set to master */
10504 /* mii write 9 [bits set 11 12] */
10505 elink_cl22_write(sc, phy, 0x09, 3 << 11);
10507 /* forced 1G and disable autoneg */
10508 /* set val [mii read 0] */
10509 /* set val [expr $val & [bits clear 6 12 13]] */
10510 /* set val [expr $val | [bits set 6 8]] */
10511 /* mii write 0 $val */
10512 elink_cl22_read(sc, phy, 0x00, &val);
10513 val &= ~((1 << 6) | (1 << 12) | (1 << 13));
10514 val |= (1 << 6) | (1 << 8);
10515 elink_cl22_write(sc, phy, 0x00, val);
10517 /* Set external loopback and Tx using 6dB coding */
10518 /* mii write 0x18 7 */
10519 /* set val [mii read 0x18] */
10520 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10521 elink_cl22_write(sc, phy, 0x18, 7);
10522 elink_cl22_read(sc, phy, 0x18, &val);
10523 elink_cl22_write(sc, phy, 0x18, val | (1 << 10) | (1 << 15));
10525 /* This register opens the gate for the UMAC despite its name */
10526 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1);
10528 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10529 * length used by the MAC receive logic to check frames.
10531 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
10534 /******************************************************************/
10535 /* SFX7101 PHY SECTION */
10536 /******************************************************************/
10537 static void elink_7101_config_loopback(struct elink_phy *phy,
10538 struct elink_params *params)
10540 struct bnx2x_softc *sc = params->sc;
10541 /* SFX7101_XGXS_TEST1 */
10542 elink_cl45_write(sc, phy,
10543 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10546 static uint8_t elink_7101_config_init(struct elink_phy *phy,
10547 struct elink_params *params,
10548 struct elink_vars *vars)
10550 uint16_t fw_ver1, fw_ver2, val;
10551 struct bnx2x_softc *sc = params->sc;
10552 PMD_DRV_LOG(DEBUG, "Setting the SFX7101 LASI indication");
10554 /* Restore normal power mode */
10555 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
10556 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10558 elink_ext_phy_hw_reset(sc, params->port);
10559 elink_wait_reset_complete(sc, phy, params);
10561 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10562 PMD_DRV_LOG(DEBUG, "Setting the SFX7101 LED to blink on traffic");
10563 elink_cl45_write(sc, phy,
10564 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1 << 3));
10566 elink_ext_phy_set_pause(params, phy, vars);
10567 /* Restart autoneg */
10568 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10570 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10572 /* Save spirom version */
10573 elink_cl45_read(sc, phy,
10574 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10576 elink_cl45_read(sc, phy,
10577 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10578 elink_save_spirom_version(sc, params->port,
10579 (uint32_t) (fw_ver1 << 16 | fw_ver2),
10581 return ELINK_STATUS_OK;
10584 static uint8_t elink_7101_read_status(struct elink_phy *phy,
10585 struct elink_params *params,
10586 struct elink_vars *vars)
10588 struct bnx2x_softc *sc = params->sc;
10590 uint16_t val1, val2;
10591 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10592 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10593 PMD_DRV_LOG(DEBUG, "10G-base-T LASI status 0x%x->0x%x", val2, val1);
10594 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10595 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10596 PMD_DRV_LOG(DEBUG, "10G-base-T PMA status 0x%x->0x%x", val2, val1);
10597 link_up = ((val1 & 4) == 4);
10598 /* If link is up print the AN outcome of the SFX7101 PHY */
10600 elink_cl45_read(sc, phy,
10601 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10603 vars->line_speed = ELINK_SPEED_10000;
10604 vars->duplex = DUPLEX_FULL;
10605 PMD_DRV_LOG(DEBUG, "SFX7101 AN status 0x%x->Master=%x",
10606 val2, (val2 & (1 << 14)));
10607 elink_ext_phy_10G_an_resolve(sc, phy, vars);
10608 elink_ext_phy_resolve_fc(phy, params, vars);
10610 /* Read LP advertised speeds */
10611 if (val2 & (1 << 11))
10612 vars->link_status |=
10613 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10618 static uint8_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str,
10622 return ELINK_STATUS_ERROR;
10623 str[0] = (spirom_ver & 0xFF);
10624 str[1] = (spirom_ver & 0xFF00) >> 8;
10625 str[2] = (spirom_ver & 0xFF0000) >> 16;
10626 str[3] = (spirom_ver & 0xFF000000) >> 24;
10629 return ELINK_STATUS_OK;
10632 static void elink_7101_hw_reset(__rte_unused struct elink_phy *phy,
10633 struct elink_params *params)
10635 /* Low power mode is controlled by GPIO 2 */
10636 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2,
10637 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10638 /* The PHY reset is controlled by GPIO 1 */
10639 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
10640 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10643 static void elink_7101_set_link_led(struct elink_phy *phy,
10644 struct elink_params *params, uint8_t mode)
10647 struct bnx2x_softc *sc = params->sc;
10649 case ELINK_LED_MODE_FRONT_PANEL_OFF:
10650 case ELINK_LED_MODE_OFF:
10653 case ELINK_LED_MODE_ON:
10656 case ELINK_LED_MODE_OPER:
10660 elink_cl45_write(sc, phy,
10661 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LINK_LED_CNTL, val);
10664 /******************************************************************/
10665 /* STATIC PHY DECLARATION */
10666 /******************************************************************/
10668 static const struct elink_phy phy_null = {
10669 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10672 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
10673 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10674 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10677 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
10679 .req_flow_ctrl = 0,
10680 .req_line_speed = 0,
10681 .speed_cap_mask = 0,
10684 .config_init = NULL,
10685 .read_status = NULL,
10686 .link_reset = NULL,
10687 .config_loopback = NULL,
10688 .format_fw_ver = NULL,
10690 .set_link_led = NULL,
10691 .phy_specific_func = NULL
10694 static const struct elink_phy phy_serdes = {
10695 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10699 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10700 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10702 .supported = (ELINK_SUPPORTED_10baseT_Half |
10703 ELINK_SUPPORTED_10baseT_Full |
10704 ELINK_SUPPORTED_100baseT_Half |
10705 ELINK_SUPPORTED_100baseT_Full |
10706 ELINK_SUPPORTED_1000baseT_Full |
10707 ELINK_SUPPORTED_2500baseX_Full |
10708 ELINK_SUPPORTED_TP |
10709 ELINK_SUPPORTED_Autoneg |
10710 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10711 .media_type = ELINK_ETH_PHY_BASE_T,
10713 .req_flow_ctrl = 0,
10714 .req_line_speed = 0,
10715 .speed_cap_mask = 0,
10718 .config_init = elink_xgxs_config_init,
10719 .read_status = elink_link_settings_status,
10720 .link_reset = elink_int_link_reset,
10721 .config_loopback = NULL,
10722 .format_fw_ver = NULL,
10724 .set_link_led = NULL,
10725 .phy_specific_func = NULL
10728 static const struct elink_phy phy_xgxs = {
10729 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10733 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10734 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10736 .supported = (ELINK_SUPPORTED_10baseT_Half |
10737 ELINK_SUPPORTED_10baseT_Full |
10738 ELINK_SUPPORTED_100baseT_Half |
10739 ELINK_SUPPORTED_100baseT_Full |
10740 ELINK_SUPPORTED_1000baseT_Full |
10741 ELINK_SUPPORTED_2500baseX_Full |
10742 ELINK_SUPPORTED_10000baseT_Full |
10743 ELINK_SUPPORTED_FIBRE |
10744 ELINK_SUPPORTED_Autoneg |
10745 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10746 .media_type = ELINK_ETH_PHY_CX4,
10748 .req_flow_ctrl = 0,
10749 .req_line_speed = 0,
10750 .speed_cap_mask = 0,
10753 .config_init = elink_xgxs_config_init,
10754 .read_status = elink_link_settings_status,
10755 .link_reset = elink_int_link_reset,
10756 .config_loopback = elink_set_xgxs_loopback,
10757 .format_fw_ver = NULL,
10759 .set_link_led = NULL,
10760 .phy_specific_func = elink_xgxs_specific_func
10763 static const struct elink_phy phy_warpcore = {
10764 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10767 .flags = ELINK_FLAGS_TX_ERROR_CHECK,
10768 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10769 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10771 .supported = (ELINK_SUPPORTED_10baseT_Half |
10772 ELINK_SUPPORTED_10baseT_Full |
10773 ELINK_SUPPORTED_100baseT_Half |
10774 ELINK_SUPPORTED_100baseT_Full |
10775 ELINK_SUPPORTED_1000baseT_Full |
10776 ELINK_SUPPORTED_10000baseT_Full |
10777 ELINK_SUPPORTED_20000baseKR2_Full |
10778 ELINK_SUPPORTED_20000baseMLD2_Full |
10779 ELINK_SUPPORTED_FIBRE |
10780 ELINK_SUPPORTED_Autoneg |
10781 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10782 .media_type = ELINK_ETH_PHY_UNSPECIFIED,
10784 .req_flow_ctrl = 0,
10785 .req_line_speed = 0,
10786 .speed_cap_mask = 0,
10787 /* req_duplex = */ 0,
10789 .config_init = elink_warpcore_config_init,
10790 .read_status = elink_warpcore_read_status,
10791 .link_reset = elink_warpcore_link_reset,
10792 .config_loopback = elink_set_warpcore_loopback,
10793 .format_fw_ver = NULL,
10794 .hw_reset = elink_warpcore_hw_reset,
10795 .set_link_led = NULL,
10796 .phy_specific_func = NULL
10799 static const struct elink_phy phy_7101 = {
10800 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10803 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ,
10804 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10805 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10807 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10808 ELINK_SUPPORTED_TP |
10809 ELINK_SUPPORTED_Autoneg |
10810 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10811 .media_type = ELINK_ETH_PHY_BASE_T,
10813 .req_flow_ctrl = 0,
10814 .req_line_speed = 0,
10815 .speed_cap_mask = 0,
10818 .config_init = elink_7101_config_init,
10819 .read_status = elink_7101_read_status,
10820 .link_reset = elink_common_ext_link_reset,
10821 .config_loopback = elink_7101_config_loopback,
10822 .format_fw_ver = elink_7101_format_ver,
10823 .hw_reset = elink_7101_hw_reset,
10824 .set_link_led = elink_7101_set_link_led,
10825 .phy_specific_func = NULL
10828 static const struct elink_phy phy_8073 = {
10829 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073,
10833 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10834 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10836 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10837 ELINK_SUPPORTED_2500baseX_Full |
10838 ELINK_SUPPORTED_1000baseT_Full |
10839 ELINK_SUPPORTED_FIBRE |
10840 ELINK_SUPPORTED_Autoneg |
10841 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10842 .media_type = ELINK_ETH_PHY_KR,
10844 .req_flow_ctrl = 0,
10845 .req_line_speed = 0,
10846 .speed_cap_mask = 0,
10849 .config_init = elink_8073_config_init,
10850 .read_status = elink_8073_read_status,
10851 .link_reset = elink_8073_link_reset,
10852 .config_loopback = NULL,
10853 .format_fw_ver = elink_format_ver,
10855 .set_link_led = NULL,
10856 .phy_specific_func = elink_8073_specific_func
10859 static const struct elink_phy phy_8705 = {
10860 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705,
10863 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
10864 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10865 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10867 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10868 ELINK_SUPPORTED_FIBRE |
10869 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10870 .media_type = ELINK_ETH_PHY_XFP_FIBER,
10872 .req_flow_ctrl = 0,
10873 .req_line_speed = 0,
10874 .speed_cap_mask = 0,
10877 .config_init = elink_8705_config_init,
10878 .read_status = elink_8705_read_status,
10879 .link_reset = elink_common_ext_link_reset,
10880 .config_loopback = NULL,
10881 .format_fw_ver = elink_null_format_ver,
10883 .set_link_led = NULL,
10884 .phy_specific_func = NULL
10887 static const struct elink_phy phy_8706 = {
10888 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706,
10891 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
10892 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10893 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10895 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10896 ELINK_SUPPORTED_1000baseT_Full |
10897 ELINK_SUPPORTED_FIBRE |
10898 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10899 .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER,
10901 .req_flow_ctrl = 0,
10902 .req_line_speed = 0,
10903 .speed_cap_mask = 0,
10906 .config_init = elink_8706_config_init,
10907 .read_status = elink_8706_read_status,
10908 .link_reset = elink_common_ext_link_reset,
10909 .config_loopback = NULL,
10910 .format_fw_ver = elink_format_ver,
10912 .set_link_led = NULL,
10913 .phy_specific_func = NULL
10916 static const struct elink_phy phy_8726 = {
10917 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726,
10920 .flags = (ELINK_FLAGS_INIT_XGXS_FIRST | ELINK_FLAGS_TX_ERROR_CHECK),
10921 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10922 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10924 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10925 ELINK_SUPPORTED_1000baseT_Full |
10926 ELINK_SUPPORTED_Autoneg |
10927 ELINK_SUPPORTED_FIBRE |
10928 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10929 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
10931 .req_flow_ctrl = 0,
10932 .req_line_speed = 0,
10933 .speed_cap_mask = 0,
10936 .config_init = elink_8726_config_init,
10937 .read_status = elink_8726_read_status,
10938 .link_reset = elink_8726_link_reset,
10939 .config_loopback = elink_8726_config_loopback,
10940 .format_fw_ver = elink_format_ver,
10942 .set_link_led = NULL,
10943 .phy_specific_func = NULL
10946 static const struct elink_phy phy_8727 = {
10947 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727,
10950 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | ELINK_FLAGS_TX_ERROR_CHECK),
10951 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10952 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10954 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10955 ELINK_SUPPORTED_1000baseT_Full |
10956 ELINK_SUPPORTED_FIBRE |
10957 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10958 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
10960 .req_flow_ctrl = 0,
10961 .req_line_speed = 0,
10962 .speed_cap_mask = 0,
10965 .config_init = elink_8727_config_init,
10966 .read_status = elink_8727_read_status,
10967 .link_reset = elink_8727_link_reset,
10968 .config_loopback = NULL,
10969 .format_fw_ver = elink_format_ver,
10970 .hw_reset = elink_8727_hw_reset,
10971 .set_link_led = elink_8727_set_link_led,
10972 .phy_specific_func = elink_8727_specific_func
10975 static const struct elink_phy phy_8481 = {
10976 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481,
10979 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
10980 ELINK_FLAGS_REARM_LATCH_SIGNAL,
10981 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10982 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10984 .supported = (ELINK_SUPPORTED_10baseT_Half |
10985 ELINK_SUPPORTED_10baseT_Full |
10986 ELINK_SUPPORTED_100baseT_Half |
10987 ELINK_SUPPORTED_100baseT_Full |
10988 ELINK_SUPPORTED_1000baseT_Full |
10989 ELINK_SUPPORTED_10000baseT_Full |
10990 ELINK_SUPPORTED_TP |
10991 ELINK_SUPPORTED_Autoneg |
10992 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10993 .media_type = ELINK_ETH_PHY_BASE_T,
10995 .req_flow_ctrl = 0,
10996 .req_line_speed = 0,
10997 .speed_cap_mask = 0,
11000 .config_init = elink_8481_config_init,
11001 .read_status = elink_848xx_read_status,
11002 .link_reset = elink_8481_link_reset,
11003 .config_loopback = NULL,
11004 .format_fw_ver = elink_848xx_format_ver,
11005 .hw_reset = elink_8481_hw_reset,
11006 .set_link_led = elink_848xx_set_link_led,
11007 .phy_specific_func = NULL
11010 static const struct elink_phy phy_84823 = {
11011 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823,
11014 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
11015 ELINK_FLAGS_REARM_LATCH_SIGNAL | ELINK_FLAGS_TX_ERROR_CHECK),
11016 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11017 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11019 .supported = (ELINK_SUPPORTED_10baseT_Half |
11020 ELINK_SUPPORTED_10baseT_Full |
11021 ELINK_SUPPORTED_100baseT_Half |
11022 ELINK_SUPPORTED_100baseT_Full |
11023 ELINK_SUPPORTED_1000baseT_Full |
11024 ELINK_SUPPORTED_10000baseT_Full |
11025 ELINK_SUPPORTED_TP |
11026 ELINK_SUPPORTED_Autoneg |
11027 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11028 .media_type = ELINK_ETH_PHY_BASE_T,
11030 .req_flow_ctrl = 0,
11031 .req_line_speed = 0,
11032 .speed_cap_mask = 0,
11035 .config_init = elink_848x3_config_init,
11036 .read_status = elink_848xx_read_status,
11037 .link_reset = elink_848x3_link_reset,
11038 .config_loopback = NULL,
11039 .format_fw_ver = elink_848xx_format_ver,
11041 .set_link_led = elink_848xx_set_link_led,
11042 .phy_specific_func = elink_848xx_specific_func
11045 static const struct elink_phy phy_84833 = {
11046 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833,
11049 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
11050 ELINK_FLAGS_REARM_LATCH_SIGNAL |
11051 ELINK_FLAGS_TX_ERROR_CHECK | ELINK_FLAGS_TEMPERATURE),
11052 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11053 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11055 .supported = (ELINK_SUPPORTED_100baseT_Half |
11056 ELINK_SUPPORTED_100baseT_Full |
11057 ELINK_SUPPORTED_1000baseT_Full |
11058 ELINK_SUPPORTED_10000baseT_Full |
11059 ELINK_SUPPORTED_TP |
11060 ELINK_SUPPORTED_Autoneg |
11061 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11062 .media_type = ELINK_ETH_PHY_BASE_T,
11064 .req_flow_ctrl = 0,
11065 .req_line_speed = 0,
11066 .speed_cap_mask = 0,
11069 .config_init = elink_848x3_config_init,
11070 .read_status = elink_848xx_read_status,
11071 .link_reset = elink_848x3_link_reset,
11072 .config_loopback = NULL,
11073 .format_fw_ver = elink_848xx_format_ver,
11074 .hw_reset = elink_84833_hw_reset_phy,
11075 .set_link_led = elink_848xx_set_link_led,
11076 .phy_specific_func = elink_848xx_specific_func
11079 static const struct elink_phy phy_84834 = {
11080 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834,
11083 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
11084 ELINK_FLAGS_REARM_LATCH_SIGNAL,
11085 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11086 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11088 .supported = (ELINK_SUPPORTED_100baseT_Half |
11089 ELINK_SUPPORTED_100baseT_Full |
11090 ELINK_SUPPORTED_1000baseT_Full |
11091 ELINK_SUPPORTED_10000baseT_Full |
11092 ELINK_SUPPORTED_TP |
11093 ELINK_SUPPORTED_Autoneg |
11094 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11095 .media_type = ELINK_ETH_PHY_BASE_T,
11097 .req_flow_ctrl = 0,
11098 .req_line_speed = 0,
11099 .speed_cap_mask = 0,
11102 .config_init = elink_848x3_config_init,
11103 .read_status = elink_848xx_read_status,
11104 .link_reset = elink_848x3_link_reset,
11105 .config_loopback = NULL,
11106 .format_fw_ver = elink_848xx_format_ver,
11107 .hw_reset = elink_84833_hw_reset_phy,
11108 .set_link_led = elink_848xx_set_link_led,
11109 .phy_specific_func = elink_848xx_specific_func
11112 static const struct elink_phy phy_54618se = {
11113 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE,
11116 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
11117 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11118 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11120 .supported = (ELINK_SUPPORTED_10baseT_Half |
11121 ELINK_SUPPORTED_10baseT_Full |
11122 ELINK_SUPPORTED_100baseT_Half |
11123 ELINK_SUPPORTED_100baseT_Full |
11124 ELINK_SUPPORTED_1000baseT_Full |
11125 ELINK_SUPPORTED_TP |
11126 ELINK_SUPPORTED_Autoneg |
11127 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11128 .media_type = ELINK_ETH_PHY_BASE_T,
11130 .req_flow_ctrl = 0,
11131 .req_line_speed = 0,
11132 .speed_cap_mask = 0,
11133 /* req_duplex = */ 0,
11135 .config_init = elink_54618se_config_init,
11136 .read_status = elink_54618se_read_status,
11137 .link_reset = elink_54618se_link_reset,
11138 .config_loopback = elink_54618se_config_loopback,
11139 .format_fw_ver = NULL,
11141 .set_link_led = elink_5461x_set_link_led,
11142 .phy_specific_func = elink_54618se_specific_func
11145 /*****************************************************************/
11147 /* Populate the phy according. Main function: elink_populate_phy */
11149 /*****************************************************************/
11151 static void elink_populate_preemphasis(struct bnx2x_softc *sc,
11152 uint32_t shmem_base,
11153 struct elink_phy *phy, uint8_t port,
11156 /* Get the 4 lanes xgxs config rx and tx */
11157 uint32_t rx = 0, tx = 0, i;
11158 for (i = 0; i < 2; i++) {
11159 /* INT_PHY and ELINK_EXT_PHY1 share the same value location in
11160 * the shmem. When num_phys is greater than 1, than this value
11161 * applies only to ELINK_EXT_PHY1
11163 if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) {
11164 rx = REG_RD(sc, shmem_base +
11165 offsetof(struct shmem_region,
11166 dev_info.port_hw_config[port].
11167 xgxs_config_rx[i << 1]));
11169 tx = REG_RD(sc, shmem_base +
11170 offsetof(struct shmem_region,
11171 dev_info.port_hw_config[port].
11172 xgxs_config_tx[i << 1]));
11174 rx = REG_RD(sc, shmem_base +
11175 offsetof(struct shmem_region,
11176 dev_info.port_hw_config[port].
11177 xgxs_config2_rx[i << 1]));
11179 tx = REG_RD(sc, shmem_base +
11180 offsetof(struct shmem_region,
11181 dev_info.port_hw_config[port].
11182 xgxs_config2_rx[i << 1]));
11185 phy->rx_preemphasis[i << 1] = ((rx >> 16) & 0xffff);
11186 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11188 phy->tx_preemphasis[i << 1] = ((tx >> 16) & 0xffff);
11189 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11193 static uint32_t elink_get_ext_phy_config(struct bnx2x_softc *sc,
11194 uint32_t shmem_base, uint8_t phy_index,
11197 uint32_t ext_phy_config = 0;
11198 switch (phy_index) {
11199 case ELINK_EXT_PHY1:
11200 ext_phy_config = REG_RD(sc, shmem_base +
11201 offsetof(struct shmem_region,
11202 dev_info.port_hw_config[port].
11203 external_phy_config));
11205 case ELINK_EXT_PHY2:
11206 ext_phy_config = REG_RD(sc, shmem_base +
11207 offsetof(struct shmem_region,
11208 dev_info.port_hw_config[port].
11209 external_phy_config2));
11212 PMD_DRV_LOG(DEBUG, "Invalid phy_index %d", phy_index);
11213 return ELINK_STATUS_ERROR;
11216 return ext_phy_config;
11219 static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
11220 uint32_t shmem_base, uint8_t port,
11221 struct elink_phy *phy)
11224 __rte_unused uint32_t chip_id;
11225 uint32_t switch_cfg = (REG_RD(sc, shmem_base +
11226 offsetof(struct shmem_region,
11228 port_feature_config[port].
11230 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11232 (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
11233 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
11235 PMD_DRV_LOG(DEBUG, ":chip_id = 0x%x", chip_id);
11236 if (USES_WARPCORE(sc)) {
11237 uint32_t serdes_net_if;
11238 phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
11239 *phy = phy_warpcore;
11240 if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11241 phy->flags |= ELINK_FLAGS_4_PORT_MODE;
11243 phy->flags &= ~ELINK_FLAGS_4_PORT_MODE;
11244 /* Check Dual mode */
11245 serdes_net_if = (REG_RD(sc, shmem_base +
11246 offsetof(struct shmem_region,
11247 dev_info.port_hw_config[port].
11249 PORT_HW_CFG_NET_SERDES_IF_MASK);
11250 /* Set the appropriate supported and flags indications per
11251 * interface type of the chip
11253 switch (serdes_net_if) {
11254 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11255 phy->supported &= (ELINK_SUPPORTED_10baseT_Half |
11256 ELINK_SUPPORTED_10baseT_Full |
11257 ELINK_SUPPORTED_100baseT_Half |
11258 ELINK_SUPPORTED_100baseT_Full |
11259 ELINK_SUPPORTED_1000baseT_Full |
11260 ELINK_SUPPORTED_FIBRE |
11261 ELINK_SUPPORTED_Autoneg |
11262 ELINK_SUPPORTED_Pause |
11263 ELINK_SUPPORTED_Asym_Pause);
11264 phy->media_type = ELINK_ETH_PHY_BASE_T;
11266 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11267 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
11268 ELINK_SUPPORTED_10000baseT_Full |
11269 ELINK_SUPPORTED_FIBRE |
11270 ELINK_SUPPORTED_Pause |
11271 ELINK_SUPPORTED_Asym_Pause);
11272 phy->media_type = ELINK_ETH_PHY_XFP_FIBER;
11274 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11275 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
11276 ELINK_SUPPORTED_10000baseT_Full |
11277 ELINK_SUPPORTED_FIBRE |
11278 ELINK_SUPPORTED_Pause |
11279 ELINK_SUPPORTED_Asym_Pause);
11280 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
11282 case PORT_HW_CFG_NET_SERDES_IF_KR:
11283 phy->media_type = ELINK_ETH_PHY_KR;
11284 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
11285 ELINK_SUPPORTED_10000baseT_Full |
11286 ELINK_SUPPORTED_FIBRE |
11287 ELINK_SUPPORTED_Autoneg |
11288 ELINK_SUPPORTED_Pause |
11289 ELINK_SUPPORTED_Asym_Pause);
11291 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11292 phy->media_type = ELINK_ETH_PHY_KR;
11293 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
11294 phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full |
11295 ELINK_SUPPORTED_FIBRE |
11296 ELINK_SUPPORTED_Pause |
11297 ELINK_SUPPORTED_Asym_Pause);
11299 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11300 phy->media_type = ELINK_ETH_PHY_KR;
11301 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
11302 phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |
11303 ELINK_SUPPORTED_10000baseT_Full |
11304 ELINK_SUPPORTED_1000baseT_Full |
11305 ELINK_SUPPORTED_Autoneg |
11306 ELINK_SUPPORTED_FIBRE |
11307 ELINK_SUPPORTED_Pause |
11308 ELINK_SUPPORTED_Asym_Pause);
11309 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
11312 PMD_DRV_LOG(DEBUG, "Unknown WC interface type 0x%x",
11317 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11318 * was not set as expected. For B0, ECO will be enabled so there
11319 * won't be an issue there
11321 if (CHIP_REV(sc) == CHIP_REV_Ax)
11322 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA;
11324 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;
11326 switch (switch_cfg) {
11327 case ELINK_SWITCH_CFG_1G:
11328 phy_addr = REG_RD(sc,
11329 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11333 case ELINK_SWITCH_CFG_10G:
11334 phy_addr = REG_RD(sc,
11335 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11340 PMD_DRV_LOG(DEBUG, "Invalid switch_cfg");
11341 return ELINK_STATUS_ERROR;
11344 phy->addr = (uint8_t) phy_addr;
11345 phy->mdio_ctrl = elink_get_emac_base(sc,
11346 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11348 if (CHIP_IS_E2(sc))
11349 phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;
11351 phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;
11353 PMD_DRV_LOG(DEBUG, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x",
11354 port, phy->addr, phy->mdio_ctrl);
11356 elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);
11357 return ELINK_STATUS_OK;
11360 static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,
11362 uint32_t shmem_base,
11363 uint32_t shmem2_base,
11365 struct elink_phy *phy)
11367 uint32_t ext_phy_config, phy_type, config2;
11368 uint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11369 ext_phy_config = elink_get_ext_phy_config(sc, shmem_base,
11371 phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
11372 /* Select the phy type */
11373 switch (phy_type) {
11374 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073:
11375 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11378 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705:
11381 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706:
11384 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
11385 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11388 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC:
11389 /* BNX2X8727_NOC => BNX2X8727 no over current */
11390 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11392 phy->flags |= ELINK_FLAGS_NOC;
11394 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
11395 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
11396 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11399 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481:
11402 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823:
11405 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833:
11408 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:
11411 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616:
11412 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE:
11413 *phy = phy_54618se;
11414 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
11415 phy->flags |= ELINK_FLAGS_EEE;
11417 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11420 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11422 return ELINK_STATUS_ERROR;
11425 /* In case external PHY wasn't found */
11426 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
11427 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11428 return ELINK_STATUS_ERROR;
11429 return ELINK_STATUS_OK;
11432 phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);
11433 elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index);
11435 /* The shmem address of the phy version is located on different
11436 * structures. In case this structure is too old, do not set
11439 config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,
11440 dev_info.shared_hw_config.
11442 if (phy_index == ELINK_EXT_PHY1) {
11443 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11445 ext_phy_fw_version);
11447 /* Check specific mdc mdio settings */
11448 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11449 mdc_mdio_access = config2 &
11450 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11452 uint32_t size = REG_RD(sc, shmem2_base);
11454 if (size > offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11455 phy->ver_addr = shmem2_base +
11456 offsetof(struct shmem2_region,
11457 ext_phy_fw_version2[port]);
11459 /* Check specific mdc mdio settings */
11460 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11461 mdc_mdio_access = (config2 &
11462 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11463 >> (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11464 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11466 phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);
11468 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
11469 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) &&
11471 /* Remove 100Mb link supported for BNX2X84833/4 when phy fw
11472 * version lower than or equal to 1.39
11474 uint32_t raw_ver = REG_RD(sc, phy->ver_addr);
11475 if (((raw_ver & 0x7F) <= 39) && (((raw_ver & 0xF80) >> 7) <= 1))
11476 phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |
11477 ELINK_SUPPORTED_100baseT_Full);
11480 PMD_DRV_LOG(DEBUG, "phy_type 0x%x port %d found in index %d",
11481 phy_type, port, phy_index);
11482 PMD_DRV_LOG(DEBUG, " addr=0x%x, mdio_ctl=0x%x",
11483 phy->addr, phy->mdio_ctrl);
11484 return ELINK_STATUS_OK;
11487 static elink_status_t elink_populate_phy(struct bnx2x_softc *sc,
11488 uint8_t phy_index, uint32_t shmem_base,
11489 uint32_t shmem2_base, uint8_t port,
11490 struct elink_phy *phy)
11492 elink_status_t status = ELINK_STATUS_OK;
11493 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11494 if (phy_index == ELINK_INT_PHY)
11495 return elink_populate_int_phy(sc, shmem_base, port, phy);
11496 status = elink_populate_ext_phy(sc, phy_index, shmem_base, shmem2_base,
11501 static void elink_phy_def_cfg(struct elink_params *params,
11502 struct elink_phy *phy, uint8_t phy_index)
11504 struct bnx2x_softc *sc = params->sc;
11505 uint32_t link_config;
11506 /* Populate the default phy configuration for MF mode */
11507 if (phy_index == ELINK_EXT_PHY2) {
11508 link_config = REG_RD(sc, params->shmem_base +
11509 offsetof(struct shmem_region,
11510 dev_info.port_feature_config
11511 [params->port].link_config2));
11512 phy->speed_cap_mask =
11514 params->shmem_base + offsetof(struct shmem_region,
11515 dev_info.port_hw_config
11517 speed_capability_mask2));
11519 link_config = REG_RD(sc, params->shmem_base +
11520 offsetof(struct shmem_region,
11521 dev_info.port_feature_config
11522 [params->port].link_config));
11523 phy->speed_cap_mask =
11525 params->shmem_base + offsetof(struct shmem_region,
11526 dev_info.port_hw_config
11528 speed_capability_mask));
11532 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x",
11533 phy_index, link_config, phy->speed_cap_mask);
11535 phy->req_duplex = DUPLEX_FULL;
11536 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11537 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11538 phy->req_duplex = DUPLEX_HALF;
11539 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11540 phy->req_line_speed = ELINK_SPEED_10;
11542 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11543 phy->req_duplex = DUPLEX_HALF;
11544 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11545 phy->req_line_speed = ELINK_SPEED_100;
11547 case PORT_FEATURE_LINK_SPEED_1G:
11548 phy->req_line_speed = ELINK_SPEED_1000;
11550 case PORT_FEATURE_LINK_SPEED_2_5G:
11551 phy->req_line_speed = ELINK_SPEED_2500;
11553 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11554 phy->req_line_speed = ELINK_SPEED_10000;
11557 phy->req_line_speed = ELINK_SPEED_AUTO_NEG;
11561 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
11562 case PORT_FEATURE_FLOW_CONTROL_AUTO:
11563 phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;
11565 case PORT_FEATURE_FLOW_CONTROL_TX:
11566 phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX;
11568 case PORT_FEATURE_FLOW_CONTROL_RX:
11569 phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX;
11571 case PORT_FEATURE_FLOW_CONTROL_BOTH:
11572 phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH;
11575 phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;
11580 uint32_t elink_phy_selection(struct elink_params *params)
11582 uint32_t phy_config_swapped, prio_cfg;
11583 uint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11585 phy_config_swapped = params->multi_phy_config &
11586 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11588 prio_cfg = params->multi_phy_config & PORT_HW_CFG_PHY_SELECTION_MASK;
11590 if (phy_config_swapped) {
11591 switch (prio_cfg) {
11592 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11594 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11596 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11598 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11600 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11601 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11603 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11604 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11608 return_cfg = prio_cfg;
11613 elink_status_t elink_phy_probe(struct elink_params * params)
11615 uint8_t phy_index, actual_phy_idx;
11616 uint32_t phy_config_swapped, sync_offset, media_types;
11617 struct bnx2x_softc *sc = params->sc;
11618 struct elink_phy *phy;
11619 params->num_phys = 0;
11620 PMD_DRV_LOG(DEBUG, "Begin phy probe");
11622 phy_config_swapped = params->multi_phy_config &
11623 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11625 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {
11626 actual_phy_idx = phy_index;
11627 if (phy_config_swapped) {
11628 if (phy_index == ELINK_EXT_PHY1)
11629 actual_phy_idx = ELINK_EXT_PHY2;
11630 else if (phy_index == ELINK_EXT_PHY2)
11631 actual_phy_idx = ELINK_EXT_PHY1;
11633 PMD_DRV_LOG(DEBUG, "phy_config_swapped %x, phy_index %x,"
11634 " actual_phy_idx %x", phy_config_swapped,
11635 phy_index, actual_phy_idx);
11636 phy = ¶ms->phy[actual_phy_idx];
11637 if (elink_populate_phy(sc, phy_index, params->shmem_base,
11638 params->shmem2_base, params->port,
11639 phy) != ELINK_STATUS_OK) {
11640 params->num_phys = 0;
11641 PMD_DRV_LOG(DEBUG, "phy probe failed in phy index %d",
11643 for (phy_index = ELINK_INT_PHY;
11644 phy_index < ELINK_MAX_PHYS; phy_index++)
11646 return ELINK_STATUS_ERROR;
11648 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11651 if (params->feature_config_flags &
11652 ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
11653 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
11655 if (!(params->feature_config_flags &
11656 ELINK_FEATURE_CONFIG_MT_SUPPORT))
11657 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;
11659 sync_offset = params->shmem_base +
11660 offsetof(struct shmem_region,
11661 dev_info.port_hw_config[params->port].media_type);
11662 media_types = REG_RD(sc, sync_offset);
11664 /* Update media type for non-PMF sync only for the first time
11665 * In case the media type changes afterwards, it will be updated
11666 * using the update_status function
11668 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11669 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11670 actual_phy_idx))) == 0) {
11671 media_types |= ((phy->media_type &
11672 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11673 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11676 REG_WR(sc, sync_offset, media_types);
11678 elink_phy_def_cfg(params, phy, phy_index);
11679 params->num_phys++;
11682 PMD_DRV_LOG(DEBUG, "End phy probe. #phys found %x", params->num_phys);
11683 return ELINK_STATUS_OK;
11686 static void elink_init_bmac_loopback(struct elink_params *params,
11687 struct elink_vars *vars)
11689 struct bnx2x_softc *sc = params->sc;
11691 vars->line_speed = ELINK_SPEED_10000;
11692 vars->duplex = DUPLEX_FULL;
11693 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11694 vars->mac_type = ELINK_MAC_TYPE_BMAC;
11696 vars->phy_flags = PHY_XGXS_FLAG;
11698 elink_xgxs_deassert(params);
11700 /* Set bmac loopback */
11701 elink_bmac_enable(params, vars, 1, 1);
11703 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11706 static void elink_init_emac_loopback(struct elink_params *params,
11707 struct elink_vars *vars)
11709 struct bnx2x_softc *sc = params->sc;
11711 vars->line_speed = ELINK_SPEED_1000;
11712 vars->duplex = DUPLEX_FULL;
11713 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11714 vars->mac_type = ELINK_MAC_TYPE_EMAC;
11716 vars->phy_flags = PHY_XGXS_FLAG;
11718 elink_xgxs_deassert(params);
11719 /* Set bmac loopback */
11720 elink_emac_enable(params, vars, 1);
11721 elink_emac_program(params, vars);
11722 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11725 static void elink_init_xmac_loopback(struct elink_params *params,
11726 struct elink_vars *vars)
11728 struct bnx2x_softc *sc = params->sc;
11730 if (!params->req_line_speed[0])
11731 vars->line_speed = ELINK_SPEED_10000;
11733 vars->line_speed = params->req_line_speed[0];
11734 vars->duplex = DUPLEX_FULL;
11735 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11736 vars->mac_type = ELINK_MAC_TYPE_XMAC;
11737 vars->phy_flags = PHY_XGXS_FLAG;
11738 /* Set WC to loopback mode since link is required to provide clock
11739 * to the XMAC in 20G mode
11741 elink_set_aer_mmd(params, ¶ms->phy[0]);
11742 elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0);
11743 params->phy[ELINK_INT_PHY].config_loopback(¶ms->phy[ELINK_INT_PHY],
11746 elink_xmac_enable(params, vars, 1);
11747 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11750 static void elink_init_umac_loopback(struct elink_params *params,
11751 struct elink_vars *vars)
11753 struct bnx2x_softc *sc = params->sc;
11755 vars->line_speed = ELINK_SPEED_1000;
11756 vars->duplex = DUPLEX_FULL;
11757 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11758 vars->mac_type = ELINK_MAC_TYPE_UMAC;
11759 vars->phy_flags = PHY_XGXS_FLAG;
11760 elink_umac_enable(params, vars, 1);
11762 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11765 static void elink_init_xgxs_loopback(struct elink_params *params,
11766 struct elink_vars *vars)
11768 struct bnx2x_softc *sc = params->sc;
11769 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
11771 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11772 vars->duplex = DUPLEX_FULL;
11773 if (params->req_line_speed[0] == ELINK_SPEED_1000)
11774 vars->line_speed = ELINK_SPEED_1000;
11775 else if ((params->req_line_speed[0] == ELINK_SPEED_20000) ||
11776 (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE))
11777 vars->line_speed = ELINK_SPEED_20000;
11779 vars->line_speed = ELINK_SPEED_10000;
11781 if (!USES_WARPCORE(sc))
11782 elink_xgxs_deassert(params);
11783 elink_link_initialize(params, vars);
11785 if (params->req_line_speed[0] == ELINK_SPEED_1000) {
11786 if (USES_WARPCORE(sc))
11787 elink_umac_enable(params, vars, 0);
11789 elink_emac_program(params, vars);
11790 elink_emac_enable(params, vars, 0);
11793 if (USES_WARPCORE(sc))
11794 elink_xmac_enable(params, vars, 0);
11796 elink_bmac_enable(params, vars, 0, 1);
11799 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) {
11800 /* Set 10G XGXS loopback */
11801 int_phy->config_loopback(int_phy, params);
11803 /* Set external phy loopback */
11805 for (phy_index = ELINK_EXT_PHY1;
11806 phy_index < params->num_phys; phy_index++)
11807 if (params->phy[phy_index].config_loopback)
11808 params->phy[phy_index].config_loopback(¶ms->
11813 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11815 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
11818 void elink_set_rx_filter(struct elink_params *params, uint8_t en)
11820 struct bnx2x_softc *sc = params->sc;
11821 uint8_t val = en * 0x1F;
11823 /* Open / close the gate between the NIG and the BRB */
11824 if (!CHIP_IS_E1x(sc))
11826 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port * 4, val);
11828 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port * 4, en * 0x3);
11830 REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11831 NIG_REG_LLH0_BRB1_NOT_MCP), en);
11834 static elink_status_t elink_avoid_link_flap(struct elink_params *params,
11835 struct elink_vars *vars)
11838 uint32_t dont_clear_stat, lfa_sts;
11839 struct bnx2x_softc *sc = params->sc;
11841 /* Sync the link parameters */
11842 elink_link_status_update(params, vars);
11845 * The module verification was already done by previous link owner,
11846 * so this call is meant only to get warning message
11849 for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) {
11850 struct elink_phy *phy = ¶ms->phy[phy_idx];
11851 if (phy->phy_specific_func) {
11852 PMD_DRV_LOG(DEBUG, "Calling PHY specific func");
11853 phy->phy_specific_func(phy, params, ELINK_PHY_INIT);
11855 if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||
11856 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) ||
11857 (phy->media_type == ELINK_ETH_PHY_DA_TWINAX))
11858 elink_verify_sfp_module(phy, params);
11860 lfa_sts = REG_RD(sc, params->lfa_base +
11861 offsetof(struct shmem_lfa, lfa_sts));
11863 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
11865 /* Re-enable the NIG/MAC */
11866 if (CHIP_IS_E3(sc)) {
11867 if (!dont_clear_stat) {
11868 REG_WR(sc, GRCBASE_MISC +
11869 MISC_REGISTERS_RESET_REG_2_CLEAR,
11870 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
11872 REG_WR(sc, GRCBASE_MISC +
11873 MISC_REGISTERS_RESET_REG_2_SET,
11874 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
11877 if (vars->line_speed < ELINK_SPEED_10000)
11878 elink_umac_enable(params, vars, 0);
11880 elink_xmac_enable(params, vars, 0);
11882 if (vars->line_speed < ELINK_SPEED_10000)
11883 elink_emac_enable(params, vars, 0);
11885 elink_bmac_enable(params, vars, 0, !dont_clear_stat);
11888 /* Increment LFA count */
11889 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
11890 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
11891 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
11892 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
11893 /* Clear link flap reason */
11894 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
11896 REG_WR(sc, params->lfa_base +
11897 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
11899 /* Disable NIG DRAIN */
11900 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11902 /* Enable interrupts */
11903 elink_link_int_enable(params);
11904 return ELINK_STATUS_OK;
11907 static void elink_cannot_avoid_link_flap(struct elink_params *params,
11908 struct elink_vars *vars,
11911 uint32_t lfa_sts, cfg_idx, tmp_val;
11912 struct bnx2x_softc *sc = params->sc;
11914 elink_link_reset(params, vars, 1);
11916 if (!params->lfa_base)
11918 /* Store the new link parameters */
11919 REG_WR(sc, params->lfa_base +
11920 offsetof(struct shmem_lfa, req_duplex),
11921 params->req_duplex[0] | (params->req_duplex[1] << 16));
11923 REG_WR(sc, params->lfa_base +
11924 offsetof(struct shmem_lfa, req_flow_ctrl),
11925 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
11927 REG_WR(sc, params->lfa_base +
11928 offsetof(struct shmem_lfa, req_line_speed),
11929 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
11931 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
11932 REG_WR(sc, params->lfa_base +
11933 offsetof(struct shmem_lfa,
11934 speed_cap_mask[cfg_idx]),
11935 params->speed_cap_mask[cfg_idx]);
11938 tmp_val = REG_RD(sc, params->lfa_base +
11939 offsetof(struct shmem_lfa, additional_config));
11940 tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
11941 tmp_val |= params->req_fc_auto_adv;
11943 REG_WR(sc, params->lfa_base +
11944 offsetof(struct shmem_lfa, additional_config), tmp_val);
11946 lfa_sts = REG_RD(sc, params->lfa_base +
11947 offsetof(struct shmem_lfa, lfa_sts));
11949 /* Clear the "Don't Clear Statistics" bit, and set reason */
11950 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
11952 /* Set link flap reason */
11953 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
11954 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
11955 LFA_LINK_FLAP_REASON_OFFSET);
11957 /* Increment link flap counter */
11958 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
11959 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
11960 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
11961 << LINK_FLAP_COUNT_OFFSET));
11962 REG_WR(sc, params->lfa_base +
11963 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
11964 /* Proceed with regular link initialization */
11967 elink_status_t elink_phy_init(struct elink_params *params,
11968 struct elink_vars *vars)
11971 struct bnx2x_softc *sc = params->sc;
11972 PMD_DRV_LOG(DEBUG, "Phy Initialization started");
11973 PMD_DRV_LOG(DEBUG, "(1) req_speed %d, req_flowctrl %d",
11974 params->req_line_speed[0], params->req_flow_ctrl[0]);
11975 PMD_DRV_LOG(DEBUG, "(2) req_speed %d, req_flowctrl %d",
11976 params->req_line_speed[1], params->req_flow_ctrl[1]);
11977 PMD_DRV_LOG(DEBUG, "req_adv_flow_ctrl 0x%x", params->req_fc_auto_adv);
11978 vars->link_status = 0;
11979 vars->phy_link_up = 0;
11981 vars->line_speed = 0;
11982 vars->duplex = DUPLEX_FULL;
11983 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11984 vars->mac_type = ELINK_MAC_TYPE_NONE;
11985 vars->phy_flags = 0;
11986 vars->check_kr2_recovery_cnt = 0;
11987 params->link_flags = ELINK_PHY_INITIALIZED;
11988 /* Driver opens NIG-BRB filters */
11989 elink_set_rx_filter(params, 1);
11990 /* Check if link flap can be avoided */
11991 lfa_status = elink_check_lfa(params);
11993 if (lfa_status == 0) {
11994 PMD_DRV_LOG(DEBUG, "Link Flap Avoidance in progress");
11995 return elink_avoid_link_flap(params, vars);
11998 PMD_DRV_LOG(DEBUG, "Cannot avoid link flap lfa_sta=0x%x", lfa_status);
11999 elink_cannot_avoid_link_flap(params, vars, lfa_status);
12001 /* Disable attentions */
12002 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4,
12003 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12004 ELINK_NIG_MASK_XGXS0_LINK10G |
12005 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12006 ELINK_NIG_MASK_MI_INT));
12008 elink_emac_init(params);
12010 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
12011 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12013 if ((params->num_phys == 0) && !CHIP_REV_IS_SLOW(sc)) {
12014 PMD_DRV_LOG(DEBUG, "No phy found for initialization !!");
12015 return ELINK_STATUS_ERROR;
12017 set_phy_vars(params, vars);
12019 PMD_DRV_LOG(DEBUG, "Num of phys on board: %d", params->num_phys);
12021 switch (params->loopback_mode) {
12022 case ELINK_LOOPBACK_BMAC:
12023 elink_init_bmac_loopback(params, vars);
12025 case ELINK_LOOPBACK_EMAC:
12026 elink_init_emac_loopback(params, vars);
12028 case ELINK_LOOPBACK_XMAC:
12029 elink_init_xmac_loopback(params, vars);
12031 case ELINK_LOOPBACK_UMAC:
12032 elink_init_umac_loopback(params, vars);
12034 case ELINK_LOOPBACK_XGXS:
12035 case ELINK_LOOPBACK_EXT_PHY:
12036 elink_init_xgxs_loopback(params, vars);
12039 if (!CHIP_IS_E3(sc)) {
12040 if (params->switch_cfg == ELINK_SWITCH_CFG_10G)
12041 elink_xgxs_deassert(params);
12043 elink_serdes_deassert(sc, params->port);
12045 elink_link_initialize(params, vars);
12047 elink_link_int_enable(params);
12050 elink_update_mng(params, vars->link_status);
12052 elink_update_mng_eee(params, vars->eee_status);
12053 return ELINK_STATUS_OK;
12056 static elink_status_t elink_link_reset(struct elink_params *params,
12057 struct elink_vars *vars,
12058 uint8_t reset_ext_phy)
12060 struct bnx2x_softc *sc = params->sc;
12061 uint8_t phy_index, port = params->port, clear_latch_ind = 0;
12062 PMD_DRV_LOG(DEBUG, "Resetting the link of port %d", port);
12063 /* Disable attentions */
12064 vars->link_status = 0;
12065 elink_update_mng(params, vars->link_status);
12066 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12067 SHMEM_EEE_ACTIVE_BIT);
12068 elink_update_mng_eee(params, vars->eee_status);
12069 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4,
12070 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12071 ELINK_NIG_MASK_XGXS0_LINK10G |
12072 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12073 ELINK_NIG_MASK_MI_INT));
12075 /* Activate nig drain */
12076 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1);
12078 /* Disable nig egress interface */
12079 if (!CHIP_IS_E3(sc)) {
12080 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0);
12081 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0);
12083 if (!CHIP_IS_E3(sc))
12084 elink_set_bmac_rx(sc, port, 0);
12085 if (CHIP_IS_E3(sc) && !CHIP_REV_IS_FPGA(sc)) {
12086 elink_set_xmac_rxtx(params, 0);
12087 elink_set_umac_rxtx(params, 0);
12090 if (!CHIP_IS_E3(sc))
12091 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
12094 /* The PHY reset is controlled by GPIO 1
12095 * Hold it as vars low
12097 /* Clear link led */
12098 elink_set_mdio_emac_per_phy(sc, params);
12099 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
12101 if (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) {
12102 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
12104 if (params->phy[phy_index].link_reset) {
12105 elink_set_aer_mmd(params,
12106 ¶ms->phy[phy_index]);
12107 params->phy[phy_index].link_reset(¶ms->
12112 if (params->phy[phy_index].flags &
12113 ELINK_FLAGS_REARM_LATCH_SIGNAL)
12114 clear_latch_ind = 1;
12118 if (clear_latch_ind) {
12119 /* Clear latching indication */
12120 elink_rearm_latch_signal(sc, port, 0);
12121 elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port * 4,
12122 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
12124 if (params->phy[ELINK_INT_PHY].link_reset)
12125 params->phy[ELINK_INT_PHY].link_reset(¶ms->
12130 /* Disable nig ingress interface */
12131 if (!CHIP_IS_E3(sc)) {
12133 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12134 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12135 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0);
12136 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0);
12138 uint32_t xmac_base =
12139 (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12140 elink_set_xumac_nig(params, 0, 0);
12141 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
12142 MISC_REGISTERS_RESET_REG_2_XMAC)
12143 REG_WR(sc, xmac_base + XMAC_REG_CTRL,
12144 XMAC_CTRL_REG_SOFT_RESET);
12147 vars->phy_flags = 0;
12148 return ELINK_STATUS_OK;
12151 elink_status_t elink_lfa_reset(struct elink_params * params,
12152 struct elink_vars * vars)
12154 struct bnx2x_softc *sc = params->sc;
12156 vars->phy_flags = 0;
12157 params->link_flags &= ~ELINK_PHY_INITIALIZED;
12158 if (!params->lfa_base)
12159 return elink_link_reset(params, vars, 1);
12161 * Activate NIG drain so that during this time the device won't send
12162 * anything while it is unable to response.
12164 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 1);
12167 * Close gracefully the gate from BMAC to NIG such that no half packets
12170 if (!CHIP_IS_E3(sc))
12171 elink_set_bmac_rx(sc, params->port, 0);
12173 if (CHIP_IS_E3(sc)) {
12174 elink_set_xmac_rxtx(params, 0);
12175 elink_set_umac_rxtx(params, 0);
12177 /* Wait 10ms for the pipe to clean up */
12180 /* Clean the NIG-BRB using the network filters in a way that will
12181 * not cut a packet in the middle.
12183 elink_set_rx_filter(params, 0);
12186 * Re-open the gate between the BMAC and the NIG, after verifying the
12187 * gate to the BRB is closed, otherwise packets may arrive to the
12188 * firmware before driver had initialized it. The target is to achieve
12189 * minimum management protocol down time.
12191 if (!CHIP_IS_E3(sc))
12192 elink_set_bmac_rx(sc, params->port, 1);
12194 if (CHIP_IS_E3(sc)) {
12195 elink_set_xmac_rxtx(params, 1);
12196 elink_set_umac_rxtx(params, 1);
12198 /* Disable NIG drain */
12199 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12200 return ELINK_STATUS_OK;
12203 /****************************************************************************/
12204 /* Common function */
12205 /****************************************************************************/
12206 static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
12207 uint32_t shmem_base_path[],
12208 uint32_t shmem2_base_path[],
12210 __rte_unused uint32_t chip_id)
12212 struct elink_phy phy[PORT_MAX];
12213 struct elink_phy *phy_blk[PORT_MAX];
12216 int8_t port_of_path = 0;
12217 uint32_t swap_val, swap_override;
12218 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
12219 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
12220 port ^= (swap_val && swap_override);
12221 elink_ext_phy_hw_reset(sc, port);
12222 /* PART1 - Reset both phys */
12223 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12224 uint32_t shmem_base, shmem2_base;
12225 /* In E2, same phy is using for port0 of the two paths */
12226 if (CHIP_IS_E1x(sc)) {
12227 shmem_base = shmem_base_path[0];
12228 shmem2_base = shmem2_base_path[0];
12229 port_of_path = port;
12231 shmem_base = shmem_base_path[port];
12232 shmem2_base = shmem2_base_path[port];
12236 /* Extract the ext phy address for the port */
12237 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12238 port_of_path, &phy[port]) !=
12240 PMD_DRV_LOG(DEBUG, "populate_phy failed");
12241 return ELINK_STATUS_ERROR;
12243 /* Disable attentions */
12244 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
12246 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12247 ELINK_NIG_MASK_XGXS0_LINK10G |
12248 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12249 ELINK_NIG_MASK_MI_INT));
12251 /* Need to take the phy out of low power mode in order
12252 * to write to access its registers
12254 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
12255 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
12257 /* Reset the phy */
12258 elink_cl45_write(sc, &phy[port],
12259 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
12262 /* Add delay of 150ms after reset */
12265 if (phy[PORT_0].addr & 0x1) {
12266 phy_blk[PORT_0] = &(phy[PORT_1]);
12267 phy_blk[PORT_1] = &(phy[PORT_0]);
12269 phy_blk[PORT_0] = &(phy[PORT_0]);
12270 phy_blk[PORT_1] = &(phy[PORT_1]);
12273 /* PART2 - Download firmware to both phys */
12274 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12275 if (CHIP_IS_E1x(sc))
12276 port_of_path = port;
12280 PMD_DRV_LOG(DEBUG, "Loading spirom for phy address 0x%x",
12281 phy_blk[port]->addr);
12282 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
12284 return ELINK_STATUS_ERROR;
12286 /* Only set bit 10 = 1 (Tx power down) */
12287 elink_cl45_read(sc, phy_blk[port],
12289 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12291 /* Phase1 of TX_POWER_DOWN reset */
12292 elink_cl45_write(sc, phy_blk[port],
12294 MDIO_PMA_REG_TX_POWER_DOWN, (val | 1 << 10));
12297 /* Toggle Transmitter: Power down and then up with 600ms delay
12302 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12303 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12304 /* Phase2 of POWER_DOWN_RESET */
12305 /* Release bit 10 (Release Tx power down) */
12306 elink_cl45_read(sc, phy_blk[port],
12308 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12310 elink_cl45_write(sc, phy_blk[port],
12312 MDIO_PMA_REG_TX_POWER_DOWN,
12313 (val & (~(1 << 10))));
12316 /* Read modify write the SPI-ROM version select register */
12317 elink_cl45_read(sc, phy_blk[port],
12319 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12320 elink_cl45_write(sc, phy_blk[port],
12322 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1 << 12)));
12324 /* set GPIO2 back to LOW */
12325 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
12326 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12328 return ELINK_STATUS_OK;
12331 static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc,
12332 uint32_t shmem_base_path[],
12333 uint32_t shmem2_base_path[],
12335 __rte_unused uint32_t chip_id)
12339 struct elink_phy phy;
12340 /* Use port1 because of the static port-swap */
12341 /* Enable the module detection interrupt */
12342 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
12343 val |= ((1 << MISC_REGISTERS_GPIO_3) |
12345 (MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12346 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);
12348 elink_ext_phy_hw_reset(sc, 0);
12350 for (port = 0; port < PORT_MAX; port++) {
12351 uint32_t shmem_base, shmem2_base;
12353 /* In E2, same phy is using for port0 of the two paths */
12354 if (CHIP_IS_E1x(sc)) {
12355 shmem_base = shmem_base_path[0];
12356 shmem2_base = shmem2_base_path[0];
12358 shmem_base = shmem_base_path[port];
12359 shmem2_base = shmem2_base_path[port];
12361 /* Extract the ext phy address for the port */
12362 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12363 port, &phy) != ELINK_STATUS_OK) {
12364 PMD_DRV_LOG(DEBUG, "populate phy failed");
12365 return ELINK_STATUS_ERROR;
12369 elink_cl45_write(sc, &phy,
12370 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12372 /* Set fault module detected LED on */
12373 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0,
12374 MISC_REGISTERS_GPIO_HIGH, port);
12377 return ELINK_STATUS_OK;
12380 static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc *sc,
12381 uint32_t shmem_base, uint8_t * io_gpio,
12385 uint32_t phy_gpio_reset = REG_RD(sc, shmem_base +
12386 offsetof(struct shmem_region,
12388 port_hw_config[PORT_0].
12390 switch (phy_gpio_reset) {
12391 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12395 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12399 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12403 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12407 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12411 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12415 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12419 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12424 /* Don't override the io_gpio and io_port */
12429 static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
12430 uint32_t shmem_base_path[],
12431 uint32_t shmem2_base_path[],
12433 __rte_unused uint32_t chip_id)
12435 int8_t port, reset_gpio;
12436 uint32_t swap_val, swap_override;
12437 struct elink_phy phy[PORT_MAX];
12438 struct elink_phy *phy_blk[PORT_MAX];
12439 int8_t port_of_path;
12440 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
12441 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
12443 reset_gpio = MISC_REGISTERS_GPIO_1;
12446 /* Retrieve the reset gpio/port which control the reset.
12447 * Default is GPIO1, PORT1
12449 elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0],
12450 (uint8_t *) & reset_gpio,
12451 (uint8_t *) & port);
12453 /* Calculate the port based on port swap */
12454 port ^= (swap_val && swap_override);
12456 /* Initiate PHY reset */
12457 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12460 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12465 /* PART1 - Reset both phys */
12466 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12467 uint32_t shmem_base, shmem2_base;
12469 /* In E2, same phy is using for port0 of the two paths */
12470 if (CHIP_IS_E1x(sc)) {
12471 shmem_base = shmem_base_path[0];
12472 shmem2_base = shmem2_base_path[0];
12473 port_of_path = port;
12475 shmem_base = shmem_base_path[port];
12476 shmem2_base = shmem2_base_path[port];
12480 /* Extract the ext phy address for the port */
12481 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12482 port_of_path, &phy[port]) !=
12484 PMD_DRV_LOG(DEBUG, "populate phy failed");
12485 return ELINK_STATUS_ERROR;
12487 /* disable attentions */
12488 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
12490 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12491 ELINK_NIG_MASK_XGXS0_LINK10G |
12492 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12493 ELINK_NIG_MASK_MI_INT));
12495 /* Reset the phy */
12496 elink_cl45_write(sc, &phy[port],
12497 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
12500 /* Add delay of 150ms after reset */
12502 if (phy[PORT_0].addr & 0x1) {
12503 phy_blk[PORT_0] = &(phy[PORT_1]);
12504 phy_blk[PORT_1] = &(phy[PORT_0]);
12506 phy_blk[PORT_0] = &(phy[PORT_0]);
12507 phy_blk[PORT_1] = &(phy[PORT_1]);
12509 /* PART2 - Download firmware to both phys */
12510 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12511 if (CHIP_IS_E1x(sc))
12512 port_of_path = port;
12515 PMD_DRV_LOG(DEBUG, "Loading spirom for phy address 0x%x",
12516 phy_blk[port]->addr);
12517 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
12519 return ELINK_STATUS_ERROR;
12520 /* Disable PHY transmitter output */
12521 elink_cl45_write(sc, phy_blk[port],
12522 MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, 1);
12525 return ELINK_STATUS_OK;
12528 static elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc,
12529 uint32_t shmem_base_path[],
12530 __rte_unused uint32_t
12531 shmem2_base_path[],
12532 __rte_unused uint8_t
12533 phy_index, uint32_t chip_id)
12535 uint8_t reset_gpios;
12536 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id);
12537 elink_cb_gpio_mult_write(sc, reset_gpios,
12538 MISC_REGISTERS_GPIO_OUTPUT_LOW);
12540 elink_cb_gpio_mult_write(sc, reset_gpios,
12541 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
12542 PMD_DRV_LOG(DEBUG, "84833 reset pulse on pin values 0x%x", reset_gpios);
12543 return ELINK_STATUS_OK;
12546 static elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc,
12547 uint32_t shmem_base_path[],
12548 uint32_t shmem2_base_path[],
12550 uint32_t ext_phy_type,
12553 elink_status_t rc = ELINK_STATUS_OK;
12555 switch (ext_phy_type) {
12556 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073:
12557 rc = elink_8073_common_init_phy(sc, shmem_base_path,
12559 phy_index, chip_id);
12561 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
12562 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
12563 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC:
12564 rc = elink_8727_common_init_phy(sc, shmem_base_path,
12566 phy_index, chip_id);
12569 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
12570 /* GPIO1 affects both ports, so there's need to pull
12571 * it for single port alone
12573 rc = elink_8726_common_init_phy(sc, shmem_base_path,
12575 phy_index, chip_id);
12577 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833:
12578 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:
12579 /* GPIO3's are linked, and so both need to be toggled
12580 * to obtain required 2us pulse.
12582 rc = elink_84833_common_init_phy(sc, shmem_base_path,
12584 phy_index, chip_id);
12586 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12587 rc = ELINK_STATUS_ERROR;
12591 "ext_phy 0x%x common init not required",
12596 if (rc != ELINK_STATUS_OK)
12597 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized,"
12603 elink_status_t elink_common_init_phy(struct bnx2x_softc * sc,
12604 uint32_t shmem_base_path[],
12605 uint32_t shmem2_base_path[],
12607 __rte_unused uint8_t one_port_enabled)
12609 elink_status_t rc = ELINK_STATUS_OK;
12610 uint32_t phy_ver, val;
12611 uint8_t phy_index = 0;
12612 uint32_t ext_phy_type, ext_phy_config;
12614 elink_set_mdio_clk(sc, GRCBASE_EMAC0);
12615 elink_set_mdio_clk(sc, GRCBASE_EMAC1);
12616 PMD_DRV_LOG(DEBUG, "Begin common phy init");
12617 if (CHIP_IS_E3(sc)) {
12619 val = REG_RD(sc, MISC_REG_GEN_PURP_HWG);
12620 REG_WR(sc, MISC_REG_GEN_PURP_HWG, val | 1);
12622 /* Check if common init was already done */
12623 phy_ver = REG_RD(sc, shmem_base_path[0] +
12624 offsetof(struct shmem_region,
12625 port_mb[PORT_0].ext_phy_fw_version));
12627 PMD_DRV_LOG(DEBUG, "Not doing common init; phy ver is 0x%x",
12629 return ELINK_STATUS_OK;
12632 /* Read the ext_phy_type for arbitrary port(0) */
12633 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
12635 ext_phy_config = elink_get_ext_phy_config(sc,
12636 shmem_base_path[0],
12638 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
12639 rc |= elink_ext_phy_common_init(sc, shmem_base_path,
12641 phy_index, ext_phy_type,
12647 static void elink_check_over_curr(struct elink_params *params,
12648 struct elink_vars *vars)
12650 struct bnx2x_softc *sc = params->sc;
12652 uint8_t port = params->port;
12655 cfg_pin = (REG_RD(sc, params->shmem_base +
12656 offsetof(struct shmem_region,
12657 dev_info.port_hw_config[port].
12658 e3_cmn_pin_cfg1)) &
12659 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12660 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12662 /* Ignore check if no external input PIN available */
12663 if (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK)
12667 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12668 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has"
12669 // " been detected and the power to "
12670 // "that SFP+ module has been removed"
12671 // " to prevent failure of the card."
12672 // " Please remove the SFP+ module and"
12673 // " restart the system to clear this"
12675 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12676 elink_warpcore_power_module(params, 0);
12679 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12682 /* Returns 0 if no change occured since last check; 1 otherwise. */
12683 static uint8_t elink_analyze_link_error(struct elink_params *params,
12684 struct elink_vars *vars,
12685 uint32_t status, uint32_t phy_flag,
12686 uint32_t link_flag, uint8_t notify)
12688 struct bnx2x_softc *sc = params->sc;
12689 /* Compare new value with previous value */
12691 uint32_t old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
12693 if ((status ^ old_status) == 0)
12696 /* If values differ */
12697 switch (phy_flag) {
12698 case PHY_HALF_OPEN_CONN_FLAG:
12699 PMD_DRV_LOG(DEBUG, "Analyze Remote Fault");
12701 case PHY_SFP_TX_FAULT_FLAG:
12702 PMD_DRV_LOG(DEBUG, "Analyze TX Fault");
12705 PMD_DRV_LOG(DEBUG, "Analyze UNKNOWN");
12707 PMD_DRV_LOG(DEBUG, "Link changed:[%x %x]->%x", vars->link_up,
12708 old_status, status);
12710 /* a. Update shmem->link_status accordingly
12711 * b. Update elink_vars->link_up
12714 vars->link_status &= ~LINK_STATUS_LINK_UP;
12715 vars->link_status |= link_flag;
12717 vars->phy_flags |= phy_flag;
12719 /* activate nig drain */
12720 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 1);
12721 /* Set LED mode to off since the PHY doesn't know about these
12724 led_mode = ELINK_LED_MODE_OFF;
12726 vars->link_status |= LINK_STATUS_LINK_UP;
12727 vars->link_status &= ~link_flag;
12729 vars->phy_flags &= ~phy_flag;
12730 led_mode = ELINK_LED_MODE_OPER;
12732 /* Clear nig drain */
12733 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12735 elink_sync_link(params, vars);
12736 /* Update the LED according to the link state */
12737 elink_set_led(params, vars, led_mode, ELINK_SPEED_10000);
12739 /* Update link status in the shared memory */
12740 elink_update_mng(params, vars->link_status);
12742 /* C. Trigger General Attention */
12743 vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT;
12745 elink_cb_notify_link_changed(sc);
12750 /******************************************************************************
12752 * This function checks for half opened connection change indication.
12753 * When such change occurs, it calls the elink_analyze_link_error
12754 * to check if Remote Fault is set or cleared. Reception of remote fault
12755 * status message in the MAC indicates that the peer's MAC has detected
12756 * a fault, for example, due to break in the TX side of fiber.
12758 ******************************************************************************/
12759 static elink_status_t elink_check_half_open_conn(struct elink_params *params,
12760 struct elink_vars *vars,
12763 struct bnx2x_softc *sc = params->sc;
12764 uint32_t lss_status = 0;
12766 /* In case link status is physically up @ 10G do */
12767 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
12768 (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4)))
12769 return ELINK_STATUS_OK;
12771 if (CHIP_IS_E3(sc) &&
12772 (REG_RD(sc, MISC_REG_RESET_REG_2) &
12773 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
12774 /* Check E3 XMAC */
12775 /* Note that link speed cannot be queried here, since it may be
12776 * zero while link is down. In case UMAC is active, LSS will
12777 * simply not be set
12779 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12781 /* Clear stick bits (Requires rising edge) */
12782 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
12783 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
12784 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
12785 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
12786 if (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS))
12789 elink_analyze_link_error(params, vars, lss_status,
12790 PHY_HALF_OPEN_CONN_FLAG,
12791 LINK_STATUS_NONE, notify);
12792 } else if (REG_RD(sc, MISC_REG_RESET_REG_2) &
12793 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
12794 /* Check E1X / E2 BMAC */
12795 uint32_t lss_status_reg;
12796 uint32_t wb_data[2];
12797 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12798 NIG_REG_INGRESS_BMAC0_MEM;
12799 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
12800 if (CHIP_IS_E2(sc))
12801 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12803 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12805 REG_RD_DMAE(sc, mac_base + lss_status_reg, wb_data, 2);
12806 lss_status = (wb_data[0] > 0);
12808 elink_analyze_link_error(params, vars, lss_status,
12809 PHY_HALF_OPEN_CONN_FLAG,
12810 LINK_STATUS_NONE, notify);
12812 return ELINK_STATUS_OK;
12815 static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
12816 struct elink_params *params,
12817 struct elink_vars *vars)
12819 struct bnx2x_softc *sc = params->sc;
12820 uint32_t cfg_pin, value = 0;
12821 uint8_t led_change, port = params->port;
12823 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
12824 cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
12829 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
12830 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
12832 if (elink_get_cfg_pin(sc, cfg_pin, &value)) {
12833 PMD_DRV_LOG(DEBUG, "Failed to read pin 0x%02x", cfg_pin);
12837 led_change = elink_analyze_link_error(params, vars, value,
12838 PHY_SFP_TX_FAULT_FLAG,
12839 LINK_STATUS_SFP_TX_FAULT, 1);
12842 /* Change TX_Fault led, set link status for further syncs */
12845 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
12846 led_mode = MISC_REGISTERS_GPIO_HIGH;
12847 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
12849 led_mode = MISC_REGISTERS_GPIO_LOW;
12850 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
12853 /* If module is unapproved, led should be on regardless */
12854 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
12855 PMD_DRV_LOG(DEBUG, "Change TX_Fault LED: ->%x",
12857 elink_set_e3_module_fault_led(params, led_mode);
12862 static void elink_kr2_recovery(struct elink_params *params,
12863 struct elink_vars *vars, struct elink_phy *phy)
12865 PMD_DRV_LOG(DEBUG, "KR2 recovery");
12867 elink_warpcore_enable_AN_KR2(phy, params, vars);
12868 elink_warpcore_restart_AN_KR(phy, params);
12871 static void elink_check_kr2_wa(struct elink_params *params,
12872 struct elink_vars *vars, struct elink_phy *phy)
12874 struct bnx2x_softc *sc = params->sc;
12875 uint16_t base_page, next_page, not_kr2_device, lane;
12878 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
12879 * Since some switches tend to reinit the AN process and clear the
12880 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
12881 * and recovered many times
12883 if (vars->check_kr2_recovery_cnt > 0) {
12884 vars->check_kr2_recovery_cnt--;
12888 sigdet = elink_warpcore_get_sigdet(phy, params);
12890 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
12891 elink_kr2_recovery(params, vars, phy);
12892 PMD_DRV_LOG(DEBUG, "No sigdet");
12897 lane = elink_get_warpcore_lane(params);
12898 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
12899 MDIO_AER_BLOCK_AER_REG, lane);
12900 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
12901 MDIO_AN_REG_LP_AUTO_NEG, &base_page);
12902 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
12903 MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
12904 elink_set_aer_mmd(params, phy);
12906 /* CL73 has not begun yet */
12907 if (base_page == 0) {
12908 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
12909 elink_kr2_recovery(params, vars, phy);
12910 PMD_DRV_LOG(DEBUG, "No BP");
12915 /* In case NP bit is not set in the BasePage, or it is set,
12916 * but only KX is advertised, declare this link partner as non-KR2
12919 not_kr2_device = (((base_page & 0x8000) == 0) ||
12920 (((base_page & 0x8000) &&
12921 ((next_page & 0xe0) == 0x20))));
12923 /* In case KR2 is already disabled, check if we need to re-enable it */
12924 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
12925 if (!not_kr2_device) {
12926 PMD_DRV_LOG(DEBUG, "BP=0x%x, NP=0x%x", base_page,
12928 elink_kr2_recovery(params, vars, phy);
12932 /* KR2 is enabled, but not KR2 device */
12933 if (not_kr2_device) {
12934 /* Disable KR2 on both lanes */
12935 PMD_DRV_LOG(DEBUG, "BP=0x%x, NP=0x%x", base_page, next_page);
12936 elink_disable_kr2(params, vars, phy);
12937 /* Restart AN on leading lane */
12938 elink_warpcore_restart_AN_KR(phy, params);
12943 void elink_period_func(struct elink_params *params, struct elink_vars *vars)
12946 struct bnx2x_softc *sc = params->sc;
12947 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
12948 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
12949 elink_set_aer_mmd(params, ¶ms->phy[phy_idx]);
12950 if (elink_check_half_open_conn(params, vars, 1) !=
12952 PMD_DRV_LOG(DEBUG, "Fault detection failed");
12958 if (CHIP_IS_E3(sc)) {
12959 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
12960 elink_set_aer_mmd(params, phy);
12961 if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) &&
12962 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
12963 elink_check_kr2_wa(params, vars, phy);
12964 elink_check_over_curr(params, vars);
12965 if (vars->rx_tx_asic_rst)
12966 elink_warpcore_config_runtime(phy, params, vars);
12968 if ((REG_RD(sc, params->shmem_base +
12969 offsetof(struct shmem_region,
12970 dev_info.port_hw_config[params->port].
12972 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
12973 PORT_HW_CFG_NET_SERDES_IF_SFI) {
12974 if (elink_is_sfp_module_plugged(params)) {
12975 elink_sfp_tx_fault_detection(phy, params, vars);
12976 } else if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) {
12977 /* Clean trail, interrupt corrects the leds */
12978 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
12979 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
12980 /* Update link status in the shared memory */
12981 elink_update_mng(params, vars->link_status);
12987 uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc,
12988 uint32_t shmem_base,
12989 uint32_t shmem2_base, uint8_t port)
12991 uint8_t phy_index, fan_failure_det_req = 0;
12992 struct elink_phy phy;
12993 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
12995 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12997 != ELINK_STATUS_OK) {
12998 PMD_DRV_LOG(DEBUG, "populate phy failed");
13001 fan_failure_det_req |= (phy.flags &
13002 ELINK_FLAGS_FAN_FAILURE_DET_REQ);
13004 return fan_failure_det_req;
13007 void elink_hw_reset_phy(struct elink_params *params)
13010 struct bnx2x_softc *sc = params->sc;
13011 elink_update_mng(params, 0);
13012 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4,
13013 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
13014 ELINK_NIG_MASK_XGXS0_LINK10G |
13015 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
13016 ELINK_NIG_MASK_MI_INT));
13018 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {
13019 if (params->phy[phy_index].hw_reset) {
13020 params->phy[phy_index].hw_reset(¶ms->phy[phy_index],
13022 params->phy[phy_index] = phy_null;
13027 void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
13028 __rte_unused uint32_t chip_id, uint32_t shmem_base,
13029 uint32_t shmem2_base, uint8_t port)
13031 uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index;
13033 uint32_t offset, aeu_mask, swap_val, swap_override, sync_offset;
13034 if (CHIP_IS_E3(sc)) {
13035 if (elink_get_mod_abs_int_cfg(sc,
13039 &gpio_port) != ELINK_STATUS_OK)
13042 struct elink_phy phy;
13043 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
13045 if (elink_populate_phy(sc, phy_index, shmem_base,
13046 shmem2_base, port, &phy)
13047 != ELINK_STATUS_OK) {
13048 PMD_DRV_LOG(DEBUG, "populate phy failed");
13051 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726) {
13052 gpio_num = MISC_REGISTERS_GPIO_3;
13059 if (gpio_num == 0xff)
13062 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13063 elink_cb_gpio_write(sc, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z,
13066 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
13067 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
13068 gpio_port ^= (swap_val && swap_override);
13070 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13071 (gpio_num + (gpio_port << 2));
13073 sync_offset = shmem_base +
13074 offsetof(struct shmem_region,
13075 dev_info.port_hw_config[port].aeu_int_mask);
13076 REG_WR(sc, sync_offset, vars->aeu_int_mask);
13078 PMD_DRV_LOG(DEBUG, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x",
13079 gpio_num, gpio_port, vars->aeu_int_mask);
13082 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13084 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13086 /* Open appropriate AEU for interrupts */
13087 aeu_mask = REG_RD(sc, offset);
13088 aeu_mask |= vars->aeu_int_mask;
13089 REG_WR(sc, offset, aeu_mask);
13091 /* Enable the GPIO to trigger interrupt */
13092 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
13093 val |= 1 << (gpio_num + (gpio_port << 2));
13094 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);