4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_ethdev.h>
39 #include <rte_malloc.h>
40 #include <rte_cycles.h>
44 #include "bnxt_filter.h"
45 #include "bnxt_hwrm.h"
47 #include "bnxt_ring.h"
50 #include "bnxt_stats.h"
53 #include "bnxt_vnic.h"
54 #include "hsi_struct_def_dpdk.h"
56 #define DRV_MODULE_NAME "bnxt"
57 static const char bnxt_version[] =
58 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
60 #define PCI_VENDOR_ID_BROADCOM 0x14E4
62 #define BROADCOM_DEV_ID_57301 0x16c8
63 #define BROADCOM_DEV_ID_57302 0x16c9
64 #define BROADCOM_DEV_ID_57304_PF 0x16ca
65 #define BROADCOM_DEV_ID_57304_VF 0x16cb
66 #define BROADCOM_DEV_ID_57417_MF 0x16cc
67 #define BROADCOM_DEV_ID_NS2 0x16cd
68 #define BROADCOM_DEV_ID_57311 0x16ce
69 #define BROADCOM_DEV_ID_57312 0x16cf
70 #define BROADCOM_DEV_ID_57402 0x16d0
71 #define BROADCOM_DEV_ID_57404 0x16d1
72 #define BROADCOM_DEV_ID_57406_PF 0x16d2
73 #define BROADCOM_DEV_ID_57406_VF 0x16d3
74 #define BROADCOM_DEV_ID_57402_MF 0x16d4
75 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
76 #define BROADCOM_DEV_ID_57412 0x16d6
77 #define BROADCOM_DEV_ID_57414 0x16d7
78 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
79 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
80 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
81 #define BROADCOM_DEV_ID_57412_MF 0x16de
82 #define BROADCOM_DEV_ID_57314 0x16df
83 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
84 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
85 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
86 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
87 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
88 #define BROADCOM_DEV_ID_57404_MF 0x16e7
89 #define BROADCOM_DEV_ID_57406_MF 0x16e8
90 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
91 #define BROADCOM_DEV_ID_57407_MF 0x16ea
92 #define BROADCOM_DEV_ID_57414_MF 0x16ec
93 #define BROADCOM_DEV_ID_57416_MF 0x16ee
95 static struct rte_pci_id bnxt_pci_id_map[] = {
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
128 { .vendor_id = 0, /* sentinel */ },
131 #define BNXT_ETH_RSS_SUPPORT ( \
133 ETH_RSS_NONFRAG_IPV4_TCP | \
134 ETH_RSS_NONFRAG_IPV4_UDP | \
136 ETH_RSS_NONFRAG_IPV6_TCP | \
137 ETH_RSS_NONFRAG_IPV6_UDP)
139 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
141 /***********************/
144 * High level utility functions
147 static void bnxt_free_mem(struct bnxt *bp)
149 bnxt_free_filter_mem(bp);
150 bnxt_free_vnic_attributes(bp);
151 bnxt_free_vnic_mem(bp);
154 bnxt_free_tx_rings(bp);
155 bnxt_free_rx_rings(bp);
156 bnxt_free_def_cp_ring(bp);
159 static int bnxt_alloc_mem(struct bnxt *bp)
163 /* Default completion ring */
164 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
168 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
169 bp->def_cp_ring, "def_cp");
173 rc = bnxt_alloc_vnic_mem(bp);
177 rc = bnxt_alloc_vnic_attributes(bp);
181 rc = bnxt_alloc_filter_mem(bp);
192 static int bnxt_init_chip(struct bnxt *bp)
194 unsigned int i, rss_idx, fw_idx;
195 struct rte_eth_link new;
198 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
200 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
204 rc = bnxt_alloc_hwrm_rings(bp);
206 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
210 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
212 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
216 rc = bnxt_mq_rx_configure(bp);
218 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
222 /* VNIC configuration */
223 for (i = 0; i < bp->nr_vnics; i++) {
224 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
226 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
228 RTE_LOG(ERR, PMD, "HWRM vnic alloc failure rc: %x\n",
233 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
236 "HWRM vnic ctx alloc failure rc: %x\n", rc);
240 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
242 RTE_LOG(ERR, PMD, "HWRM vnic cfg failure rc: %x\n", rc);
246 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
248 RTE_LOG(ERR, PMD, "HWRM vnic filter failure rc: %x\n",
252 if (vnic->rss_table && vnic->hash_type) {
254 * Fill the RSS hash & redirection table with
255 * ring group ids for all VNICs
257 for (rss_idx = 0, fw_idx = 0;
258 rss_idx < HW_HASH_INDEX_SIZE;
259 rss_idx++, fw_idx++) {
260 if (vnic->fw_grp_ids[fw_idx] ==
263 vnic->rss_table[rss_idx] =
264 vnic->fw_grp_ids[fw_idx];
266 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
269 "HWRM vnic set RSS failure rc: %x\n",
275 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]);
278 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
282 rc = bnxt_get_hwrm_link_config(bp, &new);
284 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
288 if (!bp->link_info.link_up) {
289 rc = bnxt_set_hwrm_link_config(bp, true);
292 "HWRM link config failure rc: %x\n", rc);
296 bnxt_print_link_info(bp->eth_dev);
301 bnxt_free_all_hwrm_resources(bp);
306 static int bnxt_shutdown_nic(struct bnxt *bp)
308 bnxt_free_all_hwrm_resources(bp);
309 bnxt_free_all_filters(bp);
310 bnxt_free_all_vnics(bp);
314 static int bnxt_init_nic(struct bnxt *bp)
318 rc = bnxt_init_ring_grps(bp);
322 bnxt_init_filters(bp);
324 rc = bnxt_init_chip(bp);
332 * Device configuration and status function
335 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
336 struct rte_eth_dev_info *dev_info)
338 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
339 uint16_t max_vnics, i, j, vpool, vrxq;
342 dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
343 dev_info->max_hash_mac_addrs = 0;
345 /* PF/VF specifics */
347 dev_info->max_rx_queues = bp->pf.max_rx_rings;
348 dev_info->max_tx_queues = bp->pf.max_tx_rings;
349 dev_info->max_vfs = bp->pf.active_vfs;
350 dev_info->reta_size = bp->pf.max_rsscos_ctx;
351 max_vnics = bp->pf.max_vnics;
353 dev_info->max_rx_queues = bp->vf.max_rx_rings;
354 dev_info->max_tx_queues = bp->vf.max_tx_rings;
355 dev_info->reta_size = bp->vf.max_rsscos_ctx;
356 max_vnics = bp->vf.max_vnics;
359 /* Fast path specifics */
360 dev_info->min_rx_bufsize = 1;
361 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
363 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
364 DEV_RX_OFFLOAD_IPV4_CKSUM |
365 DEV_RX_OFFLOAD_UDP_CKSUM |
366 DEV_RX_OFFLOAD_TCP_CKSUM |
367 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
368 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
369 DEV_TX_OFFLOAD_IPV4_CKSUM |
370 DEV_TX_OFFLOAD_TCP_CKSUM |
371 DEV_TX_OFFLOAD_UDP_CKSUM |
372 DEV_TX_OFFLOAD_TCP_TSO;
375 dev_info->default_rxconf = (struct rte_eth_rxconf) {
381 .rx_free_thresh = 32,
385 dev_info->default_txconf = (struct rte_eth_txconf) {
391 .tx_free_thresh = 32,
393 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
394 ETH_TXQ_FLAGS_NOOFFLOADS,
396 eth_dev->data->dev_conf.intr_conf.lsc = 1;
401 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
402 * need further investigation.
406 vpool = 64; /* ETH_64_POOLS */
407 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
408 for (i = 0; i < 4; vpool >>= 1, i++) {
409 if (max_vnics > vpool) {
410 for (j = 0; j < 5; vrxq >>= 1, j++) {
411 if (dev_info->max_rx_queues > vrxq) {
417 /* Not enough resources to support VMDq */
421 /* Not enough resources to support VMDq */
425 dev_info->max_vmdq_pools = vpool;
426 dev_info->vmdq_queue_num = vrxq;
428 dev_info->vmdq_pool_base = 0;
429 dev_info->vmdq_queue_base = 0;
432 /* Configure the device based on the configuration provided */
433 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
435 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
437 bp->rx_queues = (void *)eth_dev->data->rx_queues;
438 bp->tx_queues = (void *)eth_dev->data->tx_queues;
440 /* Inherit new configurations */
441 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
442 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
443 bp->rx_cp_nr_rings = bp->rx_nr_rings;
444 bp->tx_cp_nr_rings = bp->tx_nr_rings;
446 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
448 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
449 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
453 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
455 struct rte_eth_link *link = ð_dev->data->dev_link;
457 if (link->link_status)
458 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
459 (uint8_t)(eth_dev->data->port_id),
460 (uint32_t)link->link_speed,
461 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
462 ("full-duplex") : ("half-duplex\n"));
464 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
465 (uint8_t)(eth_dev->data->port_id));
468 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
470 bnxt_print_link_info(eth_dev);
474 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
476 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
480 rc = bnxt_hwrm_func_reset(bp);
482 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
487 rc = bnxt_setup_int(bp);
491 rc = bnxt_alloc_mem(bp);
495 rc = bnxt_request_int(bp);
499 rc = bnxt_init_nic(bp);
505 bnxt_link_update_op(eth_dev, 1);
509 bnxt_shutdown_nic(bp);
510 bnxt_disable_int(bp);
512 bnxt_free_tx_mbufs(bp);
513 bnxt_free_rx_mbufs(bp);
518 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
520 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
523 if (!bp->link_info.link_up)
524 rc = bnxt_set_hwrm_link_config(bp, true);
526 eth_dev->data->dev_link.link_status = 1;
528 bnxt_print_link_info(eth_dev);
532 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
534 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
536 eth_dev->data->dev_link.link_status = 0;
537 bnxt_set_hwrm_link_config(bp, false);
538 bp->link_info.link_up = 0;
543 /* Unload the driver, release resources */
544 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
546 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
548 if (bp->eth_dev->data->dev_started) {
549 /* TBD: STOP HW queues DMA */
550 eth_dev->data->dev_link.link_status = 0;
552 bnxt_set_hwrm_link_config(bp, false);
553 bnxt_disable_int(bp);
555 bnxt_shutdown_nic(bp);
559 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
561 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
563 if (bp->dev_stopped == 0)
564 bnxt_dev_stop_op(eth_dev);
566 bnxt_free_tx_mbufs(bp);
567 bnxt_free_rx_mbufs(bp);
569 if (eth_dev->data->mac_addrs != NULL) {
570 rte_free(eth_dev->data->mac_addrs);
571 eth_dev->data->mac_addrs = NULL;
573 if (bp->grp_info != NULL) {
574 rte_free(bp->grp_info);
579 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
582 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
583 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
584 struct bnxt_vnic_info *vnic;
585 struct bnxt_filter_info *filter, *temp_filter;
586 uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
590 * Loop through all VNICs from the specified filter flow pools to
591 * remove the corresponding MAC addr filter
593 for (i = 0; i < pool; i++) {
594 if (!(pool_mask & (1ULL << i)))
597 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
598 filter = STAILQ_FIRST(&vnic->filter);
600 temp_filter = STAILQ_NEXT(filter, next);
601 if (filter->mac_index == index) {
602 STAILQ_REMOVE(&vnic->filter, filter,
603 bnxt_filter_info, next);
604 bnxt_hwrm_clear_filter(bp, filter);
605 filter->mac_index = INVALID_MAC_INDEX;
606 memset(&filter->l2_addr, 0,
609 &bp->free_filter_list,
612 filter = temp_filter;
618 static void bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
619 struct ether_addr *mac_addr,
620 uint32_t index, uint32_t pool)
622 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
623 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
624 struct bnxt_filter_info *filter;
627 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
632 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
635 /* Attach requested MAC address to the new l2_filter */
636 STAILQ_FOREACH(filter, &vnic->filter, next) {
637 if (filter->mac_index == index) {
639 "MAC addr already existed for pool %d\n", pool);
643 filter = bnxt_alloc_filter(bp);
645 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
648 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
649 filter->mac_index = index;
650 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
651 bnxt_hwrm_set_filter(bp, vnic, filter);
654 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
657 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
658 struct rte_eth_link new;
659 unsigned int cnt = BNXT_LINK_WAIT_CNT;
661 memset(&new, 0, sizeof(new));
663 /* Retrieve link info from hardware */
664 rc = bnxt_get_hwrm_link_config(bp, &new);
666 new.link_speed = ETH_LINK_SPEED_100M;
667 new.link_duplex = ETH_LINK_FULL_DUPLEX;
669 "Failed to retrieve link rc = 0x%x!", rc);
672 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
674 if (!wait_to_complete)
676 } while (!new.link_status && cnt--);
679 /* Timed out or success */
680 if (new.link_status != eth_dev->data->dev_link.link_status ||
681 new.link_speed != eth_dev->data->dev_link.link_speed) {
682 memcpy(ð_dev->data->dev_link, &new,
683 sizeof(struct rte_eth_link));
684 bnxt_print_link_info(eth_dev);
690 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
692 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
693 struct bnxt_vnic_info *vnic;
695 if (bp->vnic_info == NULL)
698 vnic = &bp->vnic_info[0];
700 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
701 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
704 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
706 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
707 struct bnxt_vnic_info *vnic;
709 if (bp->vnic_info == NULL)
712 vnic = &bp->vnic_info[0];
714 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
715 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
718 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
720 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
721 struct bnxt_vnic_info *vnic;
723 if (bp->vnic_info == NULL)
726 vnic = &bp->vnic_info[0];
728 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
729 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
732 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
734 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
735 struct bnxt_vnic_info *vnic;
737 if (bp->vnic_info == NULL)
740 vnic = &bp->vnic_info[0];
742 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
743 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
746 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
747 struct rte_eth_rss_reta_entry64 *reta_conf,
750 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
751 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
752 struct bnxt_vnic_info *vnic;
755 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
758 if (reta_size != HW_HASH_INDEX_SIZE) {
759 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
760 "(%d) must equal the size supported by the hardware "
761 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
764 /* Update the RSS VNIC(s) */
765 for (i = 0; i < MAX_FF_POOLS; i++) {
766 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
767 memcpy(vnic->rss_table, reta_conf, reta_size);
769 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
775 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
776 struct rte_eth_rss_reta_entry64 *reta_conf,
779 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
780 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
782 /* Retrieve from the default VNIC */
785 if (!vnic->rss_table)
788 if (reta_size != HW_HASH_INDEX_SIZE) {
789 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
790 "(%d) must equal the size supported by the hardware "
791 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
794 /* EW - need to revisit here copying from u64 to u16 */
795 memcpy(reta_conf, vnic->rss_table, reta_size);
797 if (rte_intr_allow_others(ð_dev->pci_dev->intr_handle)) {
798 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
799 bnxt_dev_lsc_intr_setup(eth_dev);
805 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
806 struct rte_eth_rss_conf *rss_conf)
808 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
809 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
810 struct bnxt_vnic_info *vnic;
811 uint16_t hash_type = 0;
815 * If RSS enablement were different than dev_configure,
816 * then return -EINVAL
818 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
819 if (!rss_conf->rss_hf)
822 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
825 if (rss_conf->rss_hf & ETH_RSS_IPV4)
826 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
827 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
828 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
829 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
830 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
831 if (rss_conf->rss_hf & ETH_RSS_IPV6)
832 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
833 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
834 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
835 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
836 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
838 /* Update the RSS VNIC(s) */
839 for (i = 0; i < MAX_FF_POOLS; i++) {
840 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
841 vnic->hash_type = hash_type;
844 * Use the supplied key if the key length is
845 * acceptable and the rss_key is not NULL
847 if (rss_conf->rss_key &&
848 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
849 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
850 rss_conf->rss_key_len);
852 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
858 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
859 struct rte_eth_rss_conf *rss_conf)
861 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
862 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
866 /* RSS configuration is the same for all VNICs */
867 if (vnic && vnic->rss_hash_key) {
868 if (rss_conf->rss_key) {
869 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
870 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
871 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
874 hash_types = vnic->hash_type;
875 rss_conf->rss_hf = 0;
876 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
877 rss_conf->rss_hf |= ETH_RSS_IPV4;
878 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
880 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
881 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
883 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
885 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
886 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
888 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
890 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
891 rss_conf->rss_hf |= ETH_RSS_IPV6;
892 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
894 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
895 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
897 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
899 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
900 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
902 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
906 "Unknwon RSS config from firmware (%08x), RSS disabled",
911 rss_conf->rss_hf = 0;
916 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
917 struct rte_eth_fc_conf *fc_conf __rte_unused)
919 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
920 struct rte_eth_link link_info;
923 rc = bnxt_get_hwrm_link_config(bp, &link_info);
927 memset(fc_conf, 0, sizeof(*fc_conf));
928 if (bp->link_info.auto_pause)
929 fc_conf->autoneg = 1;
930 switch (bp->link_info.pause) {
932 fc_conf->mode = RTE_FC_NONE;
934 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
935 fc_conf->mode = RTE_FC_TX_PAUSE;
937 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
938 fc_conf->mode = RTE_FC_RX_PAUSE;
940 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
941 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
942 fc_conf->mode = RTE_FC_FULL;
948 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
949 struct rte_eth_fc_conf *fc_conf)
951 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
953 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
954 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
958 switch (fc_conf->mode) {
960 bp->link_info.auto_pause = 0;
961 bp->link_info.force_pause = 0;
963 case RTE_FC_RX_PAUSE:
964 if (fc_conf->autoneg) {
965 bp->link_info.auto_pause =
966 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
967 bp->link_info.force_pause = 0;
969 bp->link_info.auto_pause = 0;
970 bp->link_info.force_pause =
971 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
974 case RTE_FC_TX_PAUSE:
975 if (fc_conf->autoneg) {
976 bp->link_info.auto_pause =
977 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
978 bp->link_info.force_pause = 0;
980 bp->link_info.auto_pause = 0;
981 bp->link_info.force_pause =
982 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
986 if (fc_conf->autoneg) {
987 bp->link_info.auto_pause =
988 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
989 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
990 bp->link_info.force_pause = 0;
992 bp->link_info.auto_pause = 0;
993 bp->link_info.force_pause =
994 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
995 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
999 return bnxt_set_hwrm_link_config(bp, true);
1006 static struct eth_dev_ops bnxt_dev_ops = {
1007 .dev_infos_get = bnxt_dev_info_get_op,
1008 .dev_close = bnxt_dev_close_op,
1009 .dev_configure = bnxt_dev_configure_op,
1010 .dev_start = bnxt_dev_start_op,
1011 .dev_stop = bnxt_dev_stop_op,
1012 .dev_set_link_up = bnxt_dev_set_link_up_op,
1013 .dev_set_link_down = bnxt_dev_set_link_down_op,
1014 .stats_get = bnxt_stats_get_op,
1015 .stats_reset = bnxt_stats_reset_op,
1016 .rx_queue_setup = bnxt_rx_queue_setup_op,
1017 .rx_queue_release = bnxt_rx_queue_release_op,
1018 .tx_queue_setup = bnxt_tx_queue_setup_op,
1019 .tx_queue_release = bnxt_tx_queue_release_op,
1020 .reta_update = bnxt_reta_update_op,
1021 .reta_query = bnxt_reta_query_op,
1022 .rss_hash_update = bnxt_rss_hash_update_op,
1023 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
1024 .link_update = bnxt_link_update_op,
1025 .promiscuous_enable = bnxt_promiscuous_enable_op,
1026 .promiscuous_disable = bnxt_promiscuous_disable_op,
1027 .allmulticast_enable = bnxt_allmulticast_enable_op,
1028 .allmulticast_disable = bnxt_allmulticast_disable_op,
1029 .mac_addr_add = bnxt_mac_addr_add_op,
1030 .mac_addr_remove = bnxt_mac_addr_remove_op,
1031 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
1032 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
1035 static bool bnxt_vf_pciid(uint16_t id)
1037 if (id == BROADCOM_DEV_ID_57304_VF ||
1038 id == BROADCOM_DEV_ID_57406_VF ||
1039 id == BROADCOM_DEV_ID_5731X_VF ||
1040 id == BROADCOM_DEV_ID_5741X_VF)
1045 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
1048 struct bnxt *bp = eth_dev->data->dev_private;
1050 /* enable device (incl. PCI PM wakeup), and bus-mastering */
1051 if (!eth_dev->pci_dev->mem_resource[0].addr) {
1053 "Cannot find PCI device base address, aborting\n");
1055 goto init_err_disable;
1058 bp->eth_dev = eth_dev;
1059 bp->pdev = eth_dev->pci_dev;
1061 bp->bar0 = (void *)eth_dev->pci_dev->mem_resource[0].addr;
1063 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
1065 goto init_err_release;
1079 bnxt_dev_init(struct rte_eth_dev *eth_dev)
1081 static int version_printed;
1085 if (version_printed++ == 0)
1086 RTE_LOG(INFO, PMD, "%s", bnxt_version);
1088 rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
1089 bp = eth_dev->data->dev_private;
1091 if (bnxt_vf_pciid(eth_dev->pci_dev->id.device_id))
1092 bp->flags |= BNXT_FLAG_VF;
1094 rc = bnxt_init_board(eth_dev);
1097 "Board initialization failed rc: %x\n", rc);
1100 eth_dev->dev_ops = &bnxt_dev_ops;
1101 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
1102 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
1104 rc = bnxt_alloc_hwrm_resources(bp);
1107 "hwrm resource allocation failure rc: %x\n", rc);
1110 rc = bnxt_hwrm_ver_get(bp);
1113 bnxt_hwrm_queue_qportcfg(bp);
1115 bnxt_hwrm_func_qcfg(bp);
1117 /* Get the MAX capabilities for this function */
1118 rc = bnxt_hwrm_func_qcaps(bp);
1120 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
1123 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
1124 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
1125 if (eth_dev->data->mac_addrs == NULL) {
1127 "Failed to alloc %u bytes needed to store MAC addr tbl",
1128 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
1132 /* Copy the permanent MAC from the qcap response address now. */
1134 memcpy(bp->mac_addr, bp->pf.mac_addr, sizeof(bp->mac_addr));
1136 memcpy(bp->mac_addr, bp->vf.mac_addr, sizeof(bp->mac_addr));
1137 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1138 bp->grp_info = rte_zmalloc("bnxt_grp_info",
1139 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
1140 if (!bp->grp_info) {
1142 "Failed to alloc %zu bytes needed to store group info table\n",
1143 sizeof(*bp->grp_info) * bp->max_ring_grps);
1148 rc = bnxt_hwrm_func_driver_register(bp, 0,
1152 "Failed to register driver");
1158 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
1159 eth_dev->pci_dev->mem_resource[0].phys_addr,
1160 eth_dev->pci_dev->mem_resource[0].addr);
1162 bp->dev_stopped = 0;
1167 eth_dev->driver->eth_dev_uninit(eth_dev);
1173 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
1174 struct bnxt *bp = eth_dev->data->dev_private;
1177 if (eth_dev->data->mac_addrs != NULL) {
1178 rte_free(eth_dev->data->mac_addrs);
1179 eth_dev->data->mac_addrs = NULL;
1181 if (bp->grp_info != NULL) {
1182 rte_free(bp->grp_info);
1183 bp->grp_info = NULL;
1185 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
1186 bnxt_free_hwrm_resources(bp);
1187 if (bp->dev_stopped == 0)
1188 bnxt_dev_close_op(eth_dev);
1189 eth_dev->dev_ops = NULL;
1190 eth_dev->rx_pkt_burst = NULL;
1191 eth_dev->tx_pkt_burst = NULL;
1196 static struct eth_driver bnxt_rte_pmd = {
1198 .id_table = bnxt_pci_id_map,
1199 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
1200 RTE_PCI_DRV_DETACHABLE | RTE_PCI_DRV_INTR_LSC,
1201 .probe = rte_eth_dev_pci_probe,
1202 .remove = rte_eth_dev_pci_remove
1204 .eth_dev_init = bnxt_dev_init,
1205 .eth_dev_uninit = bnxt_dev_uninit,
1206 .dev_private_size = sizeof(struct bnxt),
1209 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd.pci_drv);
1210 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);