4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <rte_byteorder.h>
37 #include <rte_common.h>
38 #include <rte_cycles.h>
39 #include <rte_malloc.h>
40 #include <rte_memzone.h>
41 #include <rte_version.h>
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
49 #include "bnxt_ring.h"
52 #include "bnxt_vnic.h"
53 #include "hsi_struct_def_dpdk.h"
57 #define HWRM_CMD_TIMEOUT 10000
59 struct bnxt_plcmodes_cfg {
61 uint16_t jumbo_thresh;
63 uint16_t hds_threshold;
66 static int page_getenum(size_t size)
82 RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
83 return sizeof(void *) * 8 - 1;
86 static int page_roundup(size_t size)
88 return 1 << page_getenum(size);
92 * HWRM Functions (sent to HWRM)
93 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
94 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
95 * command was failed by the ChiMP.
98 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
102 struct input *req = msg;
103 struct output *resp = bp->hwrm_cmd_resp_addr;
104 uint32_t *data = msg;
107 uint16_t max_req_len = bp->max_req_len;
108 struct hwrm_short_input short_input = { 0 };
110 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
111 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
113 memset(short_cmd_req, 0, bp->max_req_len);
114 memcpy(short_cmd_req, req, msg_len);
116 short_input.req_type = rte_cpu_to_le_16(req->req_type);
117 short_input.signature = rte_cpu_to_le_16(
118 HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
119 short_input.size = rte_cpu_to_le_16(msg_len);
120 short_input.req_addr =
121 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
123 data = (uint32_t *)&short_input;
124 msg_len = sizeof(short_input);
126 /* Sync memory write before updating doorbell */
129 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
132 /* Write request msg to hwrm channel */
133 for (i = 0; i < msg_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + i;
135 rte_write32(*data, bar);
139 /* Zero the rest of the request space */
140 for (; i < max_req_len; i += 4) {
141 bar = (uint8_t *)bp->bar0 + i;
145 /* Ring channel doorbell */
146 bar = (uint8_t *)bp->bar0 + 0x100;
149 /* Poll for the valid bit */
150 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
151 /* Sanity check on the resp->resp_len */
153 if (resp->resp_len && resp->resp_len <=
155 /* Last byte of resp contains the valid key */
156 valid = (uint8_t *)resp + resp->resp_len - 1;
157 if (*valid == HWRM_RESP_VALID_KEY)
163 if (i >= HWRM_CMD_TIMEOUT) {
164 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
175 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
176 * spinlock, and does initial processing.
178 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
179 * releases the spinlock only if it returns. If the regular int return codes
180 * are not used by the function, HWRM_CHECK_RESULT() should not be used
181 * directly, rather it should be copied and modified to suit the function.
183 * HWRM_UNLOCK() must be called after all response processing is completed.
185 #define HWRM_PREP(req, type) do { \
186 rte_spinlock_lock(&bp->hwrm_lock); \
187 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
188 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
189 req.cmpl_ring = rte_cpu_to_le_16(-1); \
190 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
191 req.target_id = rte_cpu_to_le_16(0xffff); \
192 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
195 #define HWRM_CHECK_RESULT() do {\
197 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
199 rte_spinlock_unlock(&bp->hwrm_lock); \
200 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 if (resp->resp_len >= 16) { \
209 struct hwrm_err_output *tmp_hwrm_err_op = \
212 "%s error %d:%d:%08x:%04x\n", \
214 rc, tmp_hwrm_err_op->cmd_err, \
216 tmp_hwrm_err_op->opaque_0), \
218 tmp_hwrm_err_op->opaque_1)); \
222 "%s error %d\n", __func__, rc); \
224 rte_spinlock_unlock(&bp->hwrm_lock); \
225 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
233 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
235 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
238 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
239 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
241 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
242 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
253 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
254 struct bnxt_vnic_info *vnic,
256 struct bnxt_vlan_table_entry *vlan_table)
259 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
260 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
263 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
266 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
267 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
269 /* FIXME add multicast flag, when multicast adding options is supported
272 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
273 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
274 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
275 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
276 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
277 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
278 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
279 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
280 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
281 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
282 if (vnic->mc_addr_cnt) {
283 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
284 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
285 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
288 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
289 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
290 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
291 rte_mem_virt2iova(vlan_table));
292 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
294 req.mask = rte_cpu_to_le_32(mask);
296 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
304 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
306 struct bnxt_vlan_antispoof_table_entry *vlan_table)
309 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
310 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
311 bp->hwrm_cmd_resp_addr;
314 * Older HWRM versions did not support this command, and the set_rx_mask
315 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
316 * removed from set_rx_mask call, and this command was added.
318 * This command is also present from 1.7.8.11 and higher,
321 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
322 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
323 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
328 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
329 req.fid = rte_cpu_to_le_16(fid);
331 req.vlan_tag_mask_tbl_addr =
332 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
333 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
335 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
343 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
344 struct bnxt_filter_info *filter)
347 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
348 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
350 if (filter->fw_l2_filter_id == UINT64_MAX)
353 HWRM_PREP(req, CFA_L2_FILTER_FREE);
355 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
362 filter->fw_l2_filter_id = -1;
367 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
369 struct bnxt_filter_info *filter)
372 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
374 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
375 const struct rte_eth_vmdq_rx_conf *conf =
376 &dev_conf->rx_adv_conf.vmdq_rx_conf;
377 uint32_t enables = 0;
378 uint16_t j = dst_id - 1;
380 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
381 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
382 conf->pool_map[j].pools & (1UL << j)) {
384 "Add vlan %u to vmdq pool %u\n",
385 conf->pool_map[j].vlan_id, j);
387 filter->l2_ivlan = conf->pool_map[j].vlan_id;
389 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
390 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
393 if (filter->fw_l2_filter_id != UINT64_MAX)
394 bnxt_hwrm_clear_l2_filter(bp, filter);
396 HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
398 req.flags = rte_cpu_to_le_32(filter->flags);
400 rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
402 enables = filter->enables |
403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
404 req.dst_id = rte_cpu_to_le_16(dst_id);
407 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
408 memcpy(req.l2_addr, filter->l2_addr,
411 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
412 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
415 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
416 req.l2_ovlan = filter->l2_ovlan;
418 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
419 req.l2_ivlan = filter->l2_ivlan;
421 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
422 req.l2_ovlan_mask = filter->l2_ovlan_mask;
424 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
425 req.l2_ivlan_mask = filter->l2_ivlan_mask;
426 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
427 req.src_id = rte_cpu_to_le_32(filter->src_id);
428 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
429 req.src_type = filter->src_type;
431 req.enables = rte_cpu_to_le_32(enables);
433 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
437 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
443 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
446 struct hwrm_func_qcaps_input req = {.req_type = 0 };
447 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
448 uint16_t new_max_vfs;
451 HWRM_PREP(req, FUNC_QCAPS);
453 req.fid = rte_cpu_to_le_16(0xffff);
455 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
459 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
461 bp->pf.port_id = resp->port_id;
462 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
463 new_max_vfs = bp->pdev->max_vfs;
464 if (new_max_vfs != bp->pf.max_vfs) {
466 rte_free(bp->pf.vf_info);
467 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
468 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
469 bp->pf.max_vfs = new_max_vfs;
470 for (i = 0; i < new_max_vfs; i++) {
471 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
472 bp->pf.vf_info[i].vlan_table =
473 rte_zmalloc("VF VLAN table",
476 if (bp->pf.vf_info[i].vlan_table == NULL)
478 "Fail to alloc VLAN table for VF %d\n",
482 bp->pf.vf_info[i].vlan_table);
483 bp->pf.vf_info[i].vlan_as_table =
484 rte_zmalloc("VF VLAN AS table",
487 if (bp->pf.vf_info[i].vlan_as_table == NULL)
489 "Alloc VLAN AS table for VF %d fail\n",
493 bp->pf.vf_info[i].vlan_as_table);
494 STAILQ_INIT(&bp->pf.vf_info[i].filter);
499 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
500 memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
501 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
502 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
503 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
504 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
505 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
506 /* TODO: For now, do not support VMDq/RFS on VFs. */
511 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
515 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
517 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
523 int bnxt_hwrm_func_reset(struct bnxt *bp)
526 struct hwrm_func_reset_input req = {.req_type = 0 };
527 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
529 HWRM_PREP(req, FUNC_RESET);
531 req.enables = rte_cpu_to_le_32(0);
533 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
541 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
544 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
545 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
547 if (bp->flags & BNXT_FLAG_REGISTERED)
550 HWRM_PREP(req, FUNC_DRV_RGTR);
551 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
552 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
553 req.ver_maj = RTE_VER_YEAR;
554 req.ver_min = RTE_VER_MONTH;
555 req.ver_upd = RTE_VER_MINOR;
558 req.enables |= rte_cpu_to_le_32(
559 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
560 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
561 RTE_MIN(sizeof(req.vf_req_fwd),
562 sizeof(bp->pf.vf_req_fwd)));
565 req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1); /* TODO: Use MACRO */
566 //memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
568 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
573 bp->flags |= BNXT_FLAG_REGISTERED;
578 int bnxt_hwrm_ver_get(struct bnxt *bp)
581 struct hwrm_ver_get_input req = {.req_type = 0 };
582 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
585 uint16_t max_resp_len;
586 char type[RTE_MEMZONE_NAMESIZE];
587 uint32_t dev_caps_cfg;
589 bp->max_req_len = HWRM_MAX_REQ_LEN;
590 HWRM_PREP(req, VER_GET);
592 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
593 req.hwrm_intf_min = HWRM_VERSION_MINOR;
594 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
596 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
600 RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
601 resp->hwrm_intf_maj, resp->hwrm_intf_min,
603 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
604 bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
605 (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
606 RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
607 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
609 my_version = HWRM_VERSION_MAJOR << 16;
610 my_version |= HWRM_VERSION_MINOR << 8;
611 my_version |= HWRM_VERSION_UPDATE;
613 fw_version = resp->hwrm_intf_maj << 16;
614 fw_version |= resp->hwrm_intf_min << 8;
615 fw_version |= resp->hwrm_intf_upd;
617 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
618 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
623 if (my_version != fw_version) {
624 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
625 if (my_version < fw_version) {
627 "Firmware API version is newer than driver.\n");
629 "The driver may be missing features.\n");
632 "Firmware API version is older than driver.\n");
634 "Not all driver features may be functional.\n");
638 if (bp->max_req_len > resp->max_req_win_len) {
639 RTE_LOG(ERR, PMD, "Unsupported request length\n");
642 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
643 max_resp_len = resp->max_resp_len;
644 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
646 if (bp->max_resp_len != max_resp_len) {
647 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
648 bp->pdev->addr.domain, bp->pdev->addr.bus,
649 bp->pdev->addr.devid, bp->pdev->addr.function);
651 rte_free(bp->hwrm_cmd_resp_addr);
653 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
654 if (bp->hwrm_cmd_resp_addr == NULL) {
658 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
659 bp->hwrm_cmd_resp_dma_addr =
660 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
661 if (bp->hwrm_cmd_resp_dma_addr == 0) {
663 "Unable to map response buffer to physical memory.\n");
667 bp->max_resp_len = max_resp_len;
671 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
673 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
674 RTE_LOG(DEBUG, PMD, "Short command supported\n");
676 rte_free(bp->hwrm_short_cmd_req_addr);
678 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
680 if (bp->hwrm_short_cmd_req_addr == NULL) {
684 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
685 bp->hwrm_short_cmd_req_dma_addr =
686 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
687 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
688 rte_free(bp->hwrm_short_cmd_req_addr);
690 "Unable to map buffer to physical memory.\n");
695 bp->flags |= BNXT_FLAG_SHORT_CMD;
703 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
706 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
707 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
709 if (!(bp->flags & BNXT_FLAG_REGISTERED))
712 HWRM_PREP(req, FUNC_DRV_UNRGTR);
715 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
720 bp->flags &= ~BNXT_FLAG_REGISTERED;
725 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
728 struct hwrm_port_phy_cfg_input req = {0};
729 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
730 uint32_t enables = 0;
732 HWRM_PREP(req, PORT_PHY_CFG);
735 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
736 if (bp->link_info.auto_mode && conf->link_speed) {
737 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
738 RTE_LOG(DEBUG, PMD, "Disabling AutoNeg\n");
741 req.flags = rte_cpu_to_le_32(conf->phy_flags);
742 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
743 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
745 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
746 * any auto mode, even "none".
748 if (!conf->link_speed) {
749 /* No speeds specified. Enable AutoNeg - all speeds */
751 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
753 /* AutoNeg - Advertise speeds specified. */
754 if (conf->auto_link_speed_mask &&
755 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
757 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
758 req.auto_link_speed_mask =
759 conf->auto_link_speed_mask;
761 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
764 req.auto_duplex = conf->duplex;
765 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
766 req.auto_pause = conf->auto_pause;
767 req.force_pause = conf->force_pause;
768 /* Set force_pause if there is no auto or if there is a force */
769 if (req.auto_pause && !req.force_pause)
770 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
772 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
774 req.enables = rte_cpu_to_le_32(enables);
777 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
778 RTE_LOG(INFO, PMD, "Force Link Down\n");
781 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
789 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
790 struct bnxt_link_info *link_info)
793 struct hwrm_port_phy_qcfg_input req = {0};
794 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
796 HWRM_PREP(req, PORT_PHY_QCFG);
798 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
802 link_info->phy_link_status = resp->link;
804 (link_info->phy_link_status ==
805 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
806 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
807 link_info->duplex = resp->duplex_cfg;
808 link_info->pause = resp->pause;
809 link_info->auto_pause = resp->auto_pause;
810 link_info->force_pause = resp->force_pause;
811 link_info->auto_mode = resp->auto_mode;
812 link_info->phy_type = resp->phy_type;
813 link_info->media_type = resp->media_type;
815 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
816 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
817 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
818 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
819 link_info->phy_ver[0] = resp->phy_maj;
820 link_info->phy_ver[1] = resp->phy_min;
821 link_info->phy_ver[2] = resp->phy_bld;
825 RTE_LOG(DEBUG, PMD, "Link Speed %d\n", link_info->link_speed);
826 RTE_LOG(DEBUG, PMD, "Auto Mode %d\n", link_info->auto_mode);
827 RTE_LOG(DEBUG, PMD, "Support Speeds %x\n", link_info->support_speeds);
828 RTE_LOG(DEBUG, PMD, "Auto Link Speed %x\n", link_info->auto_link_speed);
829 RTE_LOG(DEBUG, PMD, "Auto Link Speed Mask %x\n",
830 link_info->auto_link_speed_mask);
831 RTE_LOG(DEBUG, PMD, "Forced Link Speed %x\n",
832 link_info->force_link_speed);
837 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
840 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
841 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
843 HWRM_PREP(req, QUEUE_QPORTCFG);
845 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
849 #define GET_QUEUE_INFO(x) \
850 bp->cos_queue[x].id = resp->queue_id##x; \
851 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
867 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
868 struct bnxt_ring *ring,
869 uint32_t ring_type, uint32_t map_index,
870 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
873 uint32_t enables = 0;
874 struct hwrm_ring_alloc_input req = {.req_type = 0 };
875 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
877 HWRM_PREP(req, RING_ALLOC);
879 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
880 req.fbo = rte_cpu_to_le_32(0);
881 /* Association of ring index with doorbell index */
882 req.logical_id = rte_cpu_to_le_16(map_index);
883 req.length = rte_cpu_to_le_32(ring->ring_size);
886 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
887 req.queue_id = bp->cos_queue[0].id;
889 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
890 req.ring_type = ring_type;
891 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
892 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
893 if (stats_ctx_id != INVALID_STATS_CTX_ID)
895 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
897 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
898 req.ring_type = ring_type;
900 * TODO: Some HWRM versions crash with
901 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
903 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
906 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
911 req.enables = rte_cpu_to_le_32(enables);
913 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
915 if (rc || resp->error_code) {
916 if (rc == 0 && resp->error_code)
917 rc = rte_le_to_cpu_16(resp->error_code);
919 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
921 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
924 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
926 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
929 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
931 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
935 RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
941 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
946 int bnxt_hwrm_ring_free(struct bnxt *bp,
947 struct bnxt_ring *ring, uint32_t ring_type)
950 struct hwrm_ring_free_input req = {.req_type = 0 };
951 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
953 HWRM_PREP(req, RING_FREE);
955 req.ring_type = ring_type;
956 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
958 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
960 if (rc || resp->error_code) {
961 if (rc == 0 && resp->error_code)
962 rc = rte_le_to_cpu_16(resp->error_code);
966 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
967 RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
970 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
971 RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
974 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
975 RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
979 RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
987 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
990 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
991 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
993 HWRM_PREP(req, RING_GRP_ALLOC);
995 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
996 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
997 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
998 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1000 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1002 HWRM_CHECK_RESULT();
1004 bp->grp_info[idx].fw_grp_id =
1005 rte_le_to_cpu_16(resp->ring_group_id);
1012 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1015 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1016 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1018 HWRM_PREP(req, RING_GRP_FREE);
1020 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1022 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1024 HWRM_CHECK_RESULT();
1027 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1031 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1034 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1035 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1037 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1040 HWRM_PREP(req, STAT_CTX_CLR_STATS);
1042 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1044 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1046 HWRM_CHECK_RESULT();
1052 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1053 unsigned int idx __rte_unused)
1056 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1057 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1059 HWRM_PREP(req, STAT_CTX_ALLOC);
1061 req.update_period_ms = rte_cpu_to_le_32(0);
1063 req.stats_dma_addr =
1064 rte_cpu_to_le_64(cpr->hw_stats_map);
1066 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1068 HWRM_CHECK_RESULT();
1070 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1077 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1078 unsigned int idx __rte_unused)
1081 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1082 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1084 HWRM_PREP(req, STAT_CTX_FREE);
1086 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1088 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1090 HWRM_CHECK_RESULT();
1096 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1099 struct hwrm_vnic_alloc_input req = { 0 };
1100 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1102 /* map ring groups to this vnic */
1103 RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
1104 vnic->start_grp_id, vnic->end_grp_id);
1105 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1106 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1108 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1109 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1110 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1111 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1112 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1113 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1114 HWRM_PREP(req, VNIC_ALLOC);
1116 if (vnic->func_default)
1118 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1119 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1121 HWRM_CHECK_RESULT();
1123 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1125 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1129 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1130 struct bnxt_vnic_info *vnic,
1131 struct bnxt_plcmodes_cfg *pmode)
1134 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1135 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1137 HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1139 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1141 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1143 HWRM_CHECK_RESULT();
1145 pmode->flags = rte_le_to_cpu_32(resp->flags);
1146 /* dflt_vnic bit doesn't exist in the _cfg command */
1147 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1148 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1149 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1150 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1157 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1158 struct bnxt_vnic_info *vnic,
1159 struct bnxt_plcmodes_cfg *pmode)
1162 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1163 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1165 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1167 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1168 req.flags = rte_cpu_to_le_32(pmode->flags);
1169 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1170 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1171 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1172 req.enables = rte_cpu_to_le_32(
1173 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1174 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1175 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1178 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1180 HWRM_CHECK_RESULT();
1186 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1189 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1190 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1191 uint32_t ctx_enable_flag = 0;
1192 struct bnxt_plcmodes_cfg pmodes;
1194 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1195 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1199 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1203 HWRM_PREP(req, VNIC_CFG);
1205 /* Only RSS support for now TBD: COS & LB */
1207 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1208 if (vnic->lb_rule != 0xffff)
1209 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1210 if (vnic->cos_rule != 0xffff)
1211 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1212 if (vnic->rss_rule != 0xffff) {
1213 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1214 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1216 req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1217 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1218 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1219 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1220 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1221 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1222 req.mru = rte_cpu_to_le_16(vnic->mru);
1223 if (vnic->func_default)
1225 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1226 if (vnic->vlan_strip)
1228 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1231 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1232 if (vnic->roce_dual)
1233 req.flags |= rte_cpu_to_le_32(
1234 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1235 if (vnic->roce_only)
1236 req.flags |= rte_cpu_to_le_32(
1237 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1238 if (vnic->rss_dflt_cr)
1239 req.flags |= rte_cpu_to_le_32(
1240 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1242 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1244 HWRM_CHECK_RESULT();
1247 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1252 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1256 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1257 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1259 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1260 RTE_LOG(DEBUG, PMD, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1263 HWRM_PREP(req, VNIC_QCFG);
1266 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1267 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1268 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1270 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1272 HWRM_CHECK_RESULT();
1274 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1275 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1276 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1277 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1278 vnic->mru = rte_le_to_cpu_16(resp->mru);
1279 vnic->func_default = rte_le_to_cpu_32(
1280 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1281 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1282 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1283 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1284 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1285 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1286 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1287 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1288 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1289 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1290 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1297 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1300 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1301 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1302 bp->hwrm_cmd_resp_addr;
1304 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1306 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1308 HWRM_CHECK_RESULT();
1310 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1312 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1317 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1320 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1321 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1322 bp->hwrm_cmd_resp_addr;
1324 if (vnic->rss_rule == 0xffff) {
1325 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1328 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1330 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1332 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1334 HWRM_CHECK_RESULT();
1337 vnic->rss_rule = INVALID_HW_RING_ID;
1342 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1345 struct hwrm_vnic_free_input req = {.req_type = 0 };
1346 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1348 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1349 RTE_LOG(DEBUG, PMD, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1353 HWRM_PREP(req, VNIC_FREE);
1355 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1359 HWRM_CHECK_RESULT();
1362 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1366 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1367 struct bnxt_vnic_info *vnic)
1370 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1371 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1373 HWRM_PREP(req, VNIC_RSS_CFG);
1375 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1377 req.ring_grp_tbl_addr =
1378 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1379 req.hash_key_tbl_addr =
1380 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1381 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1383 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1385 HWRM_CHECK_RESULT();
1391 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1392 struct bnxt_vnic_info *vnic)
1395 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1396 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1399 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1400 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1404 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1406 req.flags = rte_cpu_to_le_32(
1407 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1409 req.enables = rte_cpu_to_le_32(
1410 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1412 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1413 size -= RTE_PKTMBUF_HEADROOM;
1415 req.jumbo_thresh = rte_cpu_to_le_16(size);
1416 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1418 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1420 HWRM_CHECK_RESULT();
1426 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1427 struct bnxt_vnic_info *vnic, bool enable)
1430 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1431 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1433 HWRM_PREP(req, VNIC_TPA_CFG);
1436 req.enables = rte_cpu_to_le_32(
1437 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1438 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1439 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1440 req.flags = rte_cpu_to_le_32(
1441 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1442 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1443 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1444 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1445 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1446 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1447 req.max_agg_segs = rte_cpu_to_le_16(5);
1449 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1450 req.min_agg_len = rte_cpu_to_le_32(512);
1452 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1454 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1456 HWRM_CHECK_RESULT();
1462 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1464 struct hwrm_func_cfg_input req = {0};
1465 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1468 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1469 req.enables = rte_cpu_to_le_32(
1470 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1471 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1472 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1474 HWRM_PREP(req, FUNC_CFG);
1476 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1477 HWRM_CHECK_RESULT();
1480 bp->pf.vf_info[vf].random_mac = false;
1485 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1489 struct hwrm_func_qstats_input req = {.req_type = 0};
1490 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1492 HWRM_PREP(req, FUNC_QSTATS);
1494 req.fid = rte_cpu_to_le_16(fid);
1496 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1498 HWRM_CHECK_RESULT();
1501 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1508 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1509 struct rte_eth_stats *stats)
1512 struct hwrm_func_qstats_input req = {.req_type = 0};
1513 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1515 HWRM_PREP(req, FUNC_QSTATS);
1517 req.fid = rte_cpu_to_le_16(fid);
1519 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1521 HWRM_CHECK_RESULT();
1523 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1524 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1525 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1526 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1527 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1528 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1530 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1531 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1532 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1533 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1534 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1535 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1537 stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1538 stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1540 stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1547 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1550 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1551 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1553 HWRM_PREP(req, FUNC_CLR_STATS);
1555 req.fid = rte_cpu_to_le_16(fid);
1557 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1559 HWRM_CHECK_RESULT();
1566 * HWRM utility functions
1569 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1574 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1575 struct bnxt_tx_queue *txq;
1576 struct bnxt_rx_queue *rxq;
1577 struct bnxt_cp_ring_info *cpr;
1579 if (i >= bp->rx_cp_nr_rings) {
1580 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1583 rxq = bp->rx_queues[i];
1587 rc = bnxt_hwrm_stat_clear(bp, cpr);
1594 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1598 struct bnxt_cp_ring_info *cpr;
1600 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1602 if (i >= bp->rx_cp_nr_rings) {
1603 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1605 cpr = bp->rx_queues[i]->cp_ring;
1606 bp->grp_info[i].fw_stats_ctx = -1;
1608 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1609 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1610 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1618 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1623 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1624 struct bnxt_tx_queue *txq;
1625 struct bnxt_rx_queue *rxq;
1626 struct bnxt_cp_ring_info *cpr;
1628 if (i >= bp->rx_cp_nr_rings) {
1629 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1632 rxq = bp->rx_queues[i];
1636 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1644 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1649 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1651 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1654 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1662 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1663 unsigned int idx __rte_unused)
1665 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1667 bnxt_hwrm_ring_free(bp, cp_ring,
1668 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1669 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1670 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1671 sizeof(*cpr->cp_desc_ring));
1672 cpr->cp_raw_cons = 0;
1675 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1680 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1681 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1682 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1683 struct bnxt_ring *ring = txr->tx_ring_struct;
1684 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1685 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1687 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1688 bnxt_hwrm_ring_free(bp, ring,
1689 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1690 ring->fw_ring_id = INVALID_HW_RING_ID;
1691 memset(txr->tx_desc_ring, 0,
1692 txr->tx_ring_struct->ring_size *
1693 sizeof(*txr->tx_desc_ring));
1694 memset(txr->tx_buf_ring, 0,
1695 txr->tx_ring_struct->ring_size *
1696 sizeof(*txr->tx_buf_ring));
1700 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1701 bnxt_free_cp_ring(bp, cpr, idx);
1702 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1706 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1707 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1708 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1709 struct bnxt_ring *ring = rxr->rx_ring_struct;
1710 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1711 unsigned int idx = i + 1;
1713 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1714 bnxt_hwrm_ring_free(bp, ring,
1715 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1716 ring->fw_ring_id = INVALID_HW_RING_ID;
1717 bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1718 memset(rxr->rx_desc_ring, 0,
1719 rxr->rx_ring_struct->ring_size *
1720 sizeof(*rxr->rx_desc_ring));
1721 memset(rxr->rx_buf_ring, 0,
1722 rxr->rx_ring_struct->ring_size *
1723 sizeof(*rxr->rx_buf_ring));
1726 ring = rxr->ag_ring_struct;
1727 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1728 bnxt_hwrm_ring_free(bp, ring,
1729 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1730 ring->fw_ring_id = INVALID_HW_RING_ID;
1731 memset(rxr->ag_buf_ring, 0,
1732 rxr->ag_ring_struct->ring_size *
1733 sizeof(*rxr->ag_buf_ring));
1735 bp->grp_info[i].ag_fw_ring_id = INVALID_HW_RING_ID;
1737 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1738 bnxt_free_cp_ring(bp, cpr, idx);
1739 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1740 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1744 /* Default completion ring */
1746 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1748 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1749 bnxt_free_cp_ring(bp, cpr, 0);
1750 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1757 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1762 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1763 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1770 void bnxt_free_hwrm_resources(struct bnxt *bp)
1772 /* Release memzone */
1773 rte_free(bp->hwrm_cmd_resp_addr);
1774 rte_free(bp->hwrm_short_cmd_req_addr);
1775 bp->hwrm_cmd_resp_addr = NULL;
1776 bp->hwrm_short_cmd_req_addr = NULL;
1777 bp->hwrm_cmd_resp_dma_addr = 0;
1778 bp->hwrm_short_cmd_req_dma_addr = 0;
1781 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1783 struct rte_pci_device *pdev = bp->pdev;
1784 char type[RTE_MEMZONE_NAMESIZE];
1786 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1787 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1788 bp->max_resp_len = HWRM_MAX_RESP_LEN;
1789 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1790 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1791 if (bp->hwrm_cmd_resp_addr == NULL)
1793 bp->hwrm_cmd_resp_dma_addr =
1794 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1795 if (bp->hwrm_cmd_resp_dma_addr == 0) {
1797 "unable to map response address to physical memory\n");
1800 rte_spinlock_init(&bp->hwrm_lock);
1805 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1807 struct bnxt_filter_info *filter;
1810 STAILQ_FOREACH(filter, &vnic->filter, next) {
1811 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1812 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1813 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1814 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1816 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1817 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
1825 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1827 struct bnxt_filter_info *filter;
1828 struct rte_flow *flow;
1831 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1832 filter = flow->filter;
1833 RTE_LOG(ERR, PMD, "filter type %d\n", filter->filter_type);
1834 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1835 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1836 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1837 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1839 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1841 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1849 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1851 struct bnxt_filter_info *filter;
1854 STAILQ_FOREACH(filter, &vnic->filter, next) {
1855 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1856 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1858 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1859 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1862 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1870 void bnxt_free_tunnel_ports(struct bnxt *bp)
1872 if (bp->vxlan_port_cnt)
1873 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1874 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1876 if (bp->geneve_port_cnt)
1877 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1878 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1879 bp->geneve_port = 0;
1882 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1886 if (bp->vnic_info == NULL)
1890 * Cleanup VNICs in reverse order, to make sure the L2 filter
1891 * from vnic0 is last to be cleaned up.
1893 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1894 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1896 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1898 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1900 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1902 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1904 bnxt_hwrm_vnic_free(bp, vnic);
1906 rte_free(vnic->fw_grp_ids);
1908 /* Ring resources */
1909 bnxt_free_all_hwrm_rings(bp);
1910 bnxt_free_all_hwrm_ring_grps(bp);
1911 bnxt_free_all_hwrm_stat_ctxs(bp);
1912 bnxt_free_tunnel_ports(bp);
1915 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1917 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1919 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1920 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1922 switch (conf_link_speed) {
1923 case ETH_LINK_SPEED_10M_HD:
1924 case ETH_LINK_SPEED_100M_HD:
1925 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1927 return hw_link_duplex;
1930 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
1932 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
1935 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1937 uint16_t eth_link_speed = 0;
1939 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1940 return ETH_LINK_SPEED_AUTONEG;
1942 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1943 case ETH_LINK_SPEED_100M:
1944 case ETH_LINK_SPEED_100M_HD:
1946 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1948 case ETH_LINK_SPEED_1G:
1950 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1952 case ETH_LINK_SPEED_2_5G:
1954 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1956 case ETH_LINK_SPEED_10G:
1958 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1960 case ETH_LINK_SPEED_20G:
1962 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1964 case ETH_LINK_SPEED_25G:
1966 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1968 case ETH_LINK_SPEED_40G:
1970 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1972 case ETH_LINK_SPEED_50G:
1974 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1978 "Unsupported link speed %d; default to AUTO\n",
1982 return eth_link_speed;
1985 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1986 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1987 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1988 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1990 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
1994 if (link_speed == ETH_LINK_SPEED_AUTONEG)
1997 if (link_speed & ETH_LINK_SPEED_FIXED) {
1998 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2000 if (one_speed & (one_speed - 1)) {
2002 "Invalid advertised speeds (%u) for port %u\n",
2003 link_speed, port_id);
2006 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2008 "Unsupported advertised speed (%u) for port %u\n",
2009 link_speed, port_id);
2013 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2015 "Unsupported advertised speeds (%u) for port %u\n",
2016 link_speed, port_id);
2024 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2028 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2029 if (bp->link_info.support_speeds)
2030 return bp->link_info.support_speeds;
2031 link_speed = BNXT_SUPPORTED_SPEEDS;
2034 if (link_speed & ETH_LINK_SPEED_100M)
2035 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2036 if (link_speed & ETH_LINK_SPEED_100M_HD)
2037 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2038 if (link_speed & ETH_LINK_SPEED_1G)
2039 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2040 if (link_speed & ETH_LINK_SPEED_2_5G)
2041 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2042 if (link_speed & ETH_LINK_SPEED_10G)
2043 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2044 if (link_speed & ETH_LINK_SPEED_20G)
2045 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2046 if (link_speed & ETH_LINK_SPEED_25G)
2047 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2048 if (link_speed & ETH_LINK_SPEED_40G)
2049 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2050 if (link_speed & ETH_LINK_SPEED_50G)
2051 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2055 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2057 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2059 switch (hw_link_speed) {
2060 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2061 eth_link_speed = ETH_SPEED_NUM_100M;
2063 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2064 eth_link_speed = ETH_SPEED_NUM_1G;
2066 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2067 eth_link_speed = ETH_SPEED_NUM_2_5G;
2069 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2070 eth_link_speed = ETH_SPEED_NUM_10G;
2072 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2073 eth_link_speed = ETH_SPEED_NUM_20G;
2075 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2076 eth_link_speed = ETH_SPEED_NUM_25G;
2078 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2079 eth_link_speed = ETH_SPEED_NUM_40G;
2081 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2082 eth_link_speed = ETH_SPEED_NUM_50G;
2084 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2086 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
2090 return eth_link_speed;
2093 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2095 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2097 switch (hw_link_duplex) {
2098 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2099 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2100 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2102 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2103 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2106 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
2110 return eth_link_duplex;
2113 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2116 struct bnxt_link_info *link_info = &bp->link_info;
2118 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2121 "Get link config failed with rc %d\n", rc);
2124 if (link_info->link_speed)
2126 bnxt_parse_hw_link_speed(link_info->link_speed);
2128 link->link_speed = ETH_SPEED_NUM_NONE;
2129 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2130 link->link_status = link_info->link_up;
2131 link->link_autoneg = link_info->auto_mode ==
2132 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2133 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2138 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2141 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2142 struct bnxt_link_info link_req;
2143 uint16_t speed, autoneg;
2145 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
2148 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2149 bp->eth_dev->data->port_id);
2153 memset(&link_req, 0, sizeof(link_req));
2154 link_req.link_up = link_up;
2158 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2159 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2160 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2161 /* Autoneg can be done only when the FW allows */
2162 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2163 bp->link_info.force_link_speed)) {
2164 link_req.phy_flags |=
2165 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2166 link_req.auto_link_speed_mask =
2167 bnxt_parse_eth_link_speed_mask(bp,
2168 dev_conf->link_speeds);
2170 if (bp->link_info.phy_type ==
2171 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2172 bp->link_info.phy_type ==
2173 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2174 bp->link_info.media_type ==
2175 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2176 RTE_LOG(ERR, PMD, "10GBase-T devices must autoneg\n");
2180 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2181 /* If user wants a particular speed try that first. */
2183 link_req.link_speed = speed;
2184 else if (bp->link_info.force_link_speed)
2185 link_req.link_speed = bp->link_info.force_link_speed;
2187 link_req.link_speed = bp->link_info.auto_link_speed;
2189 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2190 link_req.auto_pause = bp->link_info.auto_pause;
2191 link_req.force_pause = bp->link_info.force_pause;
2194 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2197 "Set link config failed with rc %d\n", rc);
2205 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2207 struct hwrm_func_qcfg_input req = {0};
2208 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2211 HWRM_PREP(req, FUNC_QCFG);
2212 req.fid = rte_cpu_to_le_16(0xffff);
2214 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2216 HWRM_CHECK_RESULT();
2218 /* Hard Coded.. 0xfff VLAN ID mask */
2219 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2221 switch (resp->port_partition_type) {
2222 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2223 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2224 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2225 bp->port_partition_type = resp->port_partition_type;
2228 bp->port_partition_type = 0;
2237 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2238 struct hwrm_func_qcaps_output *qcaps)
2240 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2241 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2242 sizeof(qcaps->mac_address));
2243 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2244 qcaps->max_rx_rings = fcfg->num_rx_rings;
2245 qcaps->max_tx_rings = fcfg->num_tx_rings;
2246 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2247 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2249 qcaps->first_vf_id = 0;
2250 qcaps->max_vnics = fcfg->num_vnics;
2251 qcaps->max_decap_records = 0;
2252 qcaps->max_encap_records = 0;
2253 qcaps->max_tx_wm_flows = 0;
2254 qcaps->max_tx_em_flows = 0;
2255 qcaps->max_rx_wm_flows = 0;
2256 qcaps->max_rx_em_flows = 0;
2257 qcaps->max_flow_id = 0;
2258 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2259 qcaps->max_sp_tx_rings = 0;
2260 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2263 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2265 struct hwrm_func_cfg_input req = {0};
2266 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2269 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2270 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2271 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2272 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2273 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2274 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2275 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2276 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2277 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2278 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2279 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2280 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2281 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2282 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2283 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2284 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2285 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2286 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2287 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2288 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2289 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2290 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2291 req.fid = rte_cpu_to_le_16(0xffff);
2293 HWRM_PREP(req, FUNC_CFG);
2295 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2297 HWRM_CHECK_RESULT();
2303 static void populate_vf_func_cfg_req(struct bnxt *bp,
2304 struct hwrm_func_cfg_input *req,
2307 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2308 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2309 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2310 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2311 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2312 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2313 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2314 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2315 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2316 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2318 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2319 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2320 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2321 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2322 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2324 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2325 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2327 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2328 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2329 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2330 /* TODO: For now, do not support VMDq/RFS on VFs. */
2331 req->num_vnics = rte_cpu_to_le_16(1);
2332 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2336 static void add_random_mac_if_needed(struct bnxt *bp,
2337 struct hwrm_func_cfg_input *cfg_req,
2340 struct ether_addr mac;
2342 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2345 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2347 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2348 eth_random_addr(cfg_req->dflt_mac_addr);
2349 bp->pf.vf_info[vf].random_mac = true;
2351 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2355 static void reserve_resources_from_vf(struct bnxt *bp,
2356 struct hwrm_func_cfg_input *cfg_req,
2359 struct hwrm_func_qcaps_input req = {0};
2360 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2363 /* Get the actual allocated values now */
2364 HWRM_PREP(req, FUNC_QCAPS);
2365 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2366 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2369 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2370 copy_func_cfg_to_qcaps(cfg_req, resp);
2371 } else if (resp->error_code) {
2372 rc = rte_le_to_cpu_16(resp->error_code);
2373 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2374 copy_func_cfg_to_qcaps(cfg_req, resp);
2377 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2378 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2379 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2380 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2381 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2382 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2384 * TODO: While not supporting VMDq with VFs, max_vnics is always
2385 * forced to 1 in this case
2387 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2388 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2393 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2395 struct hwrm_func_qcfg_input req = {0};
2396 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2399 /* Check for zero MAC address */
2400 HWRM_PREP(req, FUNC_QCFG);
2401 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2402 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2404 RTE_LOG(ERR, PMD, "hwrm_func_qcfg failed rc:%d\n", rc);
2406 } else if (resp->error_code) {
2407 rc = rte_le_to_cpu_16(resp->error_code);
2408 RTE_LOG(ERR, PMD, "hwrm_func_qcfg error %d\n", rc);
2411 rc = rte_le_to_cpu_16(resp->vlan);
2418 static int update_pf_resource_max(struct bnxt *bp)
2420 struct hwrm_func_qcfg_input req = {0};
2421 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2424 /* And copy the allocated numbers into the pf struct */
2425 HWRM_PREP(req, FUNC_QCFG);
2426 req.fid = rte_cpu_to_le_16(0xffff);
2427 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2428 HWRM_CHECK_RESULT();
2430 /* Only TX ring value reflects actual allocation? TODO */
2431 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2432 bp->pf.evb_mode = resp->evb_mode;
2439 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2444 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2448 rc = bnxt_hwrm_func_qcaps(bp);
2452 bp->pf.func_cfg_flags &=
2453 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2454 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2455 bp->pf.func_cfg_flags |=
2456 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2457 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2461 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2463 struct hwrm_func_cfg_input req = {0};
2464 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2471 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2475 rc = bnxt_hwrm_func_qcaps(bp);
2480 bp->pf.active_vfs = num_vfs;
2483 * First, configure the PF to only use one TX ring. This ensures that
2484 * there are enough rings for all VFs.
2486 * If we don't do this, when we call func_alloc() later, we will lock
2487 * extra rings to the PF that won't be available during func_cfg() of
2490 * This has been fixed with firmware versions above 20.6.54
2492 bp->pf.func_cfg_flags &=
2493 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2494 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2495 bp->pf.func_cfg_flags |=
2496 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2497 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2502 * Now, create and register a buffer to hold forwarded VF requests
2504 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2505 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2506 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2507 if (bp->pf.vf_req_buf == NULL) {
2511 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2512 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2513 for (i = 0; i < num_vfs; i++)
2514 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2515 (i * HWRM_MAX_REQ_LEN);
2517 rc = bnxt_hwrm_func_buf_rgtr(bp);
2521 populate_vf_func_cfg_req(bp, &req, num_vfs);
2523 bp->pf.active_vfs = 0;
2524 for (i = 0; i < num_vfs; i++) {
2525 add_random_mac_if_needed(bp, &req, i);
2527 HWRM_PREP(req, FUNC_CFG);
2528 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2529 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2530 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2532 /* Clear enable flag for next pass */
2533 req.enables &= ~rte_cpu_to_le_32(
2534 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2536 if (rc || resp->error_code) {
2538 "Failed to initizlie VF %d\n", i);
2540 "Not all VFs available. (%d, %d)\n",
2541 rc, resp->error_code);
2548 reserve_resources_from_vf(bp, &req, i);
2549 bp->pf.active_vfs++;
2550 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2554 * Now configure the PF to use "the rest" of the resources
2555 * We're using STD_TX_RING_MODE here though which will limit the TX
2556 * rings. This will allow QoS to function properly. Not setting this
2557 * will cause PF rings to break bandwidth settings.
2559 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2563 rc = update_pf_resource_max(bp);
2570 bnxt_hwrm_func_buf_unrgtr(bp);
2574 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2576 struct hwrm_func_cfg_input req = {0};
2577 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2580 HWRM_PREP(req, FUNC_CFG);
2582 req.fid = rte_cpu_to_le_16(0xffff);
2583 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2584 req.evb_mode = bp->pf.evb_mode;
2586 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2587 HWRM_CHECK_RESULT();
2593 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2594 uint8_t tunnel_type)
2596 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2597 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2600 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2601 req.tunnel_type = tunnel_type;
2602 req.tunnel_dst_port_val = port;
2603 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2604 HWRM_CHECK_RESULT();
2606 switch (tunnel_type) {
2607 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2608 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2609 bp->vxlan_port = port;
2611 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2612 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2613 bp->geneve_port = port;
2624 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2625 uint8_t tunnel_type)
2627 struct hwrm_tunnel_dst_port_free_input req = {0};
2628 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2631 HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2633 req.tunnel_type = tunnel_type;
2634 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2635 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2637 HWRM_CHECK_RESULT();
2643 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2646 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2647 struct hwrm_func_cfg_input req = {0};
2650 HWRM_PREP(req, FUNC_CFG);
2652 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2653 req.flags = rte_cpu_to_le_32(flags);
2654 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2656 HWRM_CHECK_RESULT();
2662 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2664 uint32_t *flag = flagp;
2666 vnic->flags = *flag;
2669 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2671 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2674 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2677 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2678 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2680 HWRM_PREP(req, FUNC_BUF_RGTR);
2682 req.req_buf_num_pages = rte_cpu_to_le_16(1);
2683 req.req_buf_page_size = rte_cpu_to_le_16(
2684 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2685 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2686 req.req_buf_page_addr[0] =
2687 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2688 if (req.req_buf_page_addr[0] == 0) {
2690 "unable to map buffer address to physical memory\n");
2694 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2696 HWRM_CHECK_RESULT();
2702 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2705 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2706 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2708 HWRM_PREP(req, FUNC_BUF_UNRGTR);
2710 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2712 HWRM_CHECK_RESULT();
2718 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2720 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2721 struct hwrm_func_cfg_input req = {0};
2724 HWRM_PREP(req, FUNC_CFG);
2726 req.fid = rte_cpu_to_le_16(0xffff);
2727 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2728 req.enables = rte_cpu_to_le_32(
2729 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2730 req.async_event_cr = rte_cpu_to_le_16(
2731 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2732 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2734 HWRM_CHECK_RESULT();
2740 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2742 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2743 struct hwrm_func_vf_cfg_input req = {0};
2746 HWRM_PREP(req, FUNC_VF_CFG);
2748 req.enables = rte_cpu_to_le_32(
2749 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2750 req.async_event_cr = rte_cpu_to_le_16(
2751 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2752 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2754 HWRM_CHECK_RESULT();
2760 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2762 struct hwrm_func_cfg_input req = {0};
2763 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2764 uint16_t dflt_vlan, fid;
2765 uint32_t func_cfg_flags;
2768 HWRM_PREP(req, FUNC_CFG);
2771 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2772 fid = bp->pf.vf_info[vf].fid;
2773 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2775 fid = rte_cpu_to_le_16(0xffff);
2776 func_cfg_flags = bp->pf.func_cfg_flags;
2777 dflt_vlan = bp->vlan;
2780 req.flags = rte_cpu_to_le_32(func_cfg_flags);
2781 req.fid = rte_cpu_to_le_16(fid);
2782 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2783 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2785 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2787 HWRM_CHECK_RESULT();
2793 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2794 uint16_t max_bw, uint16_t enables)
2796 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2797 struct hwrm_func_cfg_input req = {0};
2800 HWRM_PREP(req, FUNC_CFG);
2802 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2803 req.enables |= rte_cpu_to_le_32(enables);
2804 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2805 req.max_bw = rte_cpu_to_le_32(max_bw);
2806 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2808 HWRM_CHECK_RESULT();
2814 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2816 struct hwrm_func_cfg_input req = {0};
2817 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2820 HWRM_PREP(req, FUNC_CFG);
2822 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2823 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2824 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2825 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2827 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2829 HWRM_CHECK_RESULT();
2835 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2836 void *encaped, size_t ec_size)
2839 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2840 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2842 if (ec_size > sizeof(req.encap_request))
2845 HWRM_PREP(req, REJECT_FWD_RESP);
2847 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2848 memcpy(req.encap_request, encaped, ec_size);
2850 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2852 HWRM_CHECK_RESULT();
2858 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2859 struct ether_addr *mac)
2861 struct hwrm_func_qcfg_input req = {0};
2862 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2865 HWRM_PREP(req, FUNC_QCFG);
2867 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2868 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2870 HWRM_CHECK_RESULT();
2872 memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2879 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2880 void *encaped, size_t ec_size)
2883 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2884 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2886 if (ec_size > sizeof(req.encap_request))
2889 HWRM_PREP(req, EXEC_FWD_RESP);
2891 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2892 memcpy(req.encap_request, encaped, ec_size);
2894 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2896 HWRM_CHECK_RESULT();
2902 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2903 struct rte_eth_stats *stats, uint8_t rx)
2906 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2907 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2909 HWRM_PREP(req, STAT_CTX_QUERY);
2911 req.stat_ctx_id = rte_cpu_to_le_32(cid);
2913 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2915 HWRM_CHECK_RESULT();
2918 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2919 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2920 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2921 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2922 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2923 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2924 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2925 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2927 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2928 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2929 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2930 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2931 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2932 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2933 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2942 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2944 struct hwrm_port_qstats_input req = {0};
2945 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2946 struct bnxt_pf_info *pf = &bp->pf;
2949 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2952 HWRM_PREP(req, PORT_QSTATS);
2954 req.port_id = rte_cpu_to_le_16(pf->port_id);
2955 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2956 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2957 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2959 HWRM_CHECK_RESULT();
2965 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2967 struct hwrm_port_clr_stats_input req = {0};
2968 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2969 struct bnxt_pf_info *pf = &bp->pf;
2972 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2975 HWRM_PREP(req, PORT_CLR_STATS);
2977 req.port_id = rte_cpu_to_le_16(pf->port_id);
2978 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2980 HWRM_CHECK_RESULT();
2986 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
2988 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2989 struct hwrm_port_led_qcaps_input req = {0};
2995 HWRM_PREP(req, PORT_LED_QCAPS);
2996 req.port_id = bp->pf.port_id;
2997 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2999 HWRM_CHECK_RESULT();
3001 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3004 bp->num_leds = resp->num_leds;
3005 memcpy(bp->leds, &resp->led0_id,
3006 sizeof(bp->leds[0]) * bp->num_leds);
3007 for (i = 0; i < bp->num_leds; i++) {
3008 struct bnxt_led_info *led = &bp->leds[i];
3010 uint16_t caps = led->led_state_caps;
3012 if (!led->led_group_id ||
3013 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3025 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3027 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3028 struct hwrm_port_led_cfg_input req = {0};
3029 struct bnxt_led_cfg *led_cfg;
3030 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3031 uint16_t duration = 0;
3034 if (!bp->num_leds || BNXT_VF(bp))
3037 HWRM_PREP(req, PORT_LED_CFG);
3040 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3041 duration = rte_cpu_to_le_16(500);
3043 req.port_id = bp->pf.port_id;
3044 req.num_leds = bp->num_leds;
3045 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3046 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3047 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3048 led_cfg->led_id = bp->leds[i].led_id;
3049 led_cfg->led_state = led_state;
3050 led_cfg->led_blink_on = duration;
3051 led_cfg->led_blink_off = duration;
3052 led_cfg->led_group_id = bp->leds[i].led_group_id;
3055 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3057 HWRM_CHECK_RESULT();
3063 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3067 struct hwrm_nvm_get_dir_info_input req = {0};
3068 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3070 HWRM_PREP(req, NVM_GET_DIR_INFO);
3072 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3074 HWRM_CHECK_RESULT();
3078 *entries = rte_le_to_cpu_32(resp->entries);
3079 *length = rte_le_to_cpu_32(resp->entry_length);
3084 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3087 uint32_t dir_entries;
3088 uint32_t entry_length;
3091 rte_iova_t dma_handle;
3092 struct hwrm_nvm_get_dir_entries_input req = {0};
3093 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3095 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3099 *data++ = dir_entries;
3100 *data++ = entry_length;
3102 memset(data, 0xff, len);
3104 buflen = dir_entries * entry_length;
3105 buf = rte_malloc("nvm_dir", buflen, 0);
3106 rte_mem_lock_page(buf);
3109 dma_handle = rte_mem_virt2iova(buf);
3110 if (dma_handle == 0) {
3112 "unable to map response address to physical memory\n");
3115 HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3116 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3117 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3120 memcpy(data, buf, len > buflen ? buflen : len);
3123 HWRM_CHECK_RESULT();
3129 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3130 uint32_t offset, uint32_t length,
3135 rte_iova_t dma_handle;
3136 struct hwrm_nvm_read_input req = {0};
3137 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3139 buf = rte_malloc("nvm_item", length, 0);
3140 rte_mem_lock_page(buf);
3144 dma_handle = rte_mem_virt2iova(buf);
3145 if (dma_handle == 0) {
3147 "unable to map response address to physical memory\n");
3150 HWRM_PREP(req, NVM_READ);
3151 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3152 req.dir_idx = rte_cpu_to_le_16(index);
3153 req.offset = rte_cpu_to_le_32(offset);
3154 req.len = rte_cpu_to_le_32(length);
3155 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3157 memcpy(data, buf, length);
3160 HWRM_CHECK_RESULT();
3166 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3169 struct hwrm_nvm_erase_dir_entry_input req = {0};
3170 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3172 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3173 req.dir_idx = rte_cpu_to_le_16(index);
3174 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3175 HWRM_CHECK_RESULT();
3182 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3183 uint16_t dir_ordinal, uint16_t dir_ext,
3184 uint16_t dir_attr, const uint8_t *data,
3188 struct hwrm_nvm_write_input req = {0};
3189 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3190 rte_iova_t dma_handle;
3193 buf = rte_malloc("nvm_write", data_len, 0);
3194 rte_mem_lock_page(buf);
3198 dma_handle = rte_mem_virt2iova(buf);
3199 if (dma_handle == 0) {
3201 "unable to map response address to physical memory\n");
3204 memcpy(buf, data, data_len);
3206 HWRM_PREP(req, NVM_WRITE);
3208 req.dir_type = rte_cpu_to_le_16(dir_type);
3209 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3210 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3211 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3212 req.dir_data_length = rte_cpu_to_le_32(data_len);
3213 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3215 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3218 HWRM_CHECK_RESULT();
3225 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3227 uint32_t *count = cbdata;
3229 *count = *count + 1;
3232 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3233 struct bnxt_vnic_info *vnic __rte_unused)
3238 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3242 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3243 &count, bnxt_vnic_count_hwrm_stub);
3248 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3251 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3252 struct hwrm_func_vf_vnic_ids_query_output *resp =
3253 bp->hwrm_cmd_resp_addr;
3256 /* First query all VNIC ids */
3257 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3259 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3260 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3261 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3263 if (req.vnic_id_tbl_addr == 0) {
3266 "unable to map VNIC ID table address to physical memory\n");
3269 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3272 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3274 } else if (resp->error_code) {
3275 rc = rte_le_to_cpu_16(resp->error_code);
3277 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
3280 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3288 * This function queries the VNIC IDs for a specified VF. It then calls
3289 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3290 * Then it calls the hwrm_cb function to program this new vnic configuration.
3292 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3293 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3294 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3296 struct bnxt_vnic_info vnic;
3298 int i, num_vnic_ids;
3303 /* First query all VNIC ids */
3304 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3305 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3306 RTE_CACHE_LINE_SIZE);
3307 if (vnic_ids == NULL) {
3311 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3312 rte_mem_lock_page(((char *)vnic_ids) + sz);
3314 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3316 if (num_vnic_ids < 0)
3317 return num_vnic_ids;
3319 /* Retrieve VNIC, update bd_stall then update */
3321 for (i = 0; i < num_vnic_ids; i++) {
3322 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3323 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3324 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3327 if (vnic.mru <= 4) /* Indicates unallocated */
3330 vnic_cb(&vnic, cbdata);
3332 rc = hwrm_cb(bp, &vnic);
3342 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3345 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3346 struct hwrm_func_cfg_input req = {0};
3349 HWRM_PREP(req, FUNC_CFG);
3351 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3352 req.enables |= rte_cpu_to_le_32(
3353 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3354 req.vlan_antispoof_mode = on ?
3355 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3356 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3357 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3359 HWRM_CHECK_RESULT();
3365 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3367 struct bnxt_vnic_info vnic;
3370 int num_vnic_ids, i;
3374 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3375 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3376 RTE_CACHE_LINE_SIZE);
3377 if (vnic_ids == NULL) {
3382 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3383 rte_mem_lock_page(((char *)vnic_ids) + sz);
3385 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3391 * Loop through to find the default VNIC ID.
3392 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3393 * by sending the hwrm_func_qcfg command to the firmware.
3395 for (i = 0; i < num_vnic_ids; i++) {
3396 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3397 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3398 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3399 bp->pf.first_vf_id + vf);
3402 if (vnic.func_default) {
3404 return vnic.fw_vnic_id;
3407 /* Could not find a default VNIC. */
3408 RTE_LOG(ERR, PMD, "No default VNIC\n");
3414 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3416 struct bnxt_filter_info *filter)
3419 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3420 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3421 uint32_t enables = 0;
3423 if (filter->fw_em_filter_id != UINT64_MAX)
3424 bnxt_hwrm_clear_em_filter(bp, filter);
3426 HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3428 req.flags = rte_cpu_to_le_32(filter->flags);
3430 enables = filter->enables |
3431 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3432 req.dst_id = rte_cpu_to_le_16(dst_id);
3434 if (filter->ip_addr_type) {
3435 req.ip_addr_type = filter->ip_addr_type;
3436 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3439 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3440 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3442 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3443 memcpy(req.src_macaddr, filter->src_macaddr,
3446 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3447 memcpy(req.dst_macaddr, filter->dst_macaddr,
3450 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3451 req.ovlan_vid = filter->l2_ovlan;
3453 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3454 req.ivlan_vid = filter->l2_ivlan;
3456 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3457 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3459 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3460 req.ip_protocol = filter->ip_protocol;
3462 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3463 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3465 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3466 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3468 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3469 req.src_port = rte_cpu_to_be_16(filter->src_port);
3471 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3472 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3474 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3475 req.mirror_vnic_id = filter->mirror_vnic_id;
3477 req.enables = rte_cpu_to_le_32(enables);
3479 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3481 HWRM_CHECK_RESULT();
3483 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3489 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3492 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3493 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3495 if (filter->fw_em_filter_id == UINT64_MAX)
3498 RTE_LOG(ERR, PMD, "Clear EM filter\n");
3499 HWRM_PREP(req, CFA_EM_FLOW_FREE);
3501 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3503 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3505 HWRM_CHECK_RESULT();
3508 filter->fw_em_filter_id = -1;
3509 filter->fw_l2_filter_id = -1;
3514 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3516 struct bnxt_filter_info *filter)
3519 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3520 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3521 bp->hwrm_cmd_resp_addr;
3522 uint32_t enables = 0;
3524 if (filter->fw_ntuple_filter_id != UINT64_MAX)
3525 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3527 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3529 req.flags = rte_cpu_to_le_32(filter->flags);
3531 enables = filter->enables |
3532 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3533 req.dst_id = rte_cpu_to_le_16(dst_id);
3536 if (filter->ip_addr_type) {
3537 req.ip_addr_type = filter->ip_addr_type;
3539 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3542 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3543 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3545 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3546 memcpy(req.src_macaddr, filter->src_macaddr,
3549 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3550 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3553 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3554 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3556 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3557 req.ip_protocol = filter->ip_protocol;
3559 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3560 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3562 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3563 req.src_ipaddr_mask[0] =
3564 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3566 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3567 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3569 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3570 req.dst_ipaddr_mask[0] =
3571 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3573 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3574 req.src_port = rte_cpu_to_le_16(filter->src_port);
3576 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3577 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3579 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3580 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3582 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3583 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3585 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3586 req.mirror_vnic_id = filter->mirror_vnic_id;
3588 req.enables = rte_cpu_to_le_32(enables);
3590 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3592 HWRM_CHECK_RESULT();
3594 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3600 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3601 struct bnxt_filter_info *filter)
3604 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3605 struct hwrm_cfa_ntuple_filter_free_output *resp =
3606 bp->hwrm_cmd_resp_addr;
3608 if (filter->fw_ntuple_filter_id == UINT64_MAX)
3611 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3613 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3615 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3617 HWRM_CHECK_RESULT();
3620 filter->fw_ntuple_filter_id = -1;