4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <rte_byteorder.h>
37 #include <rte_common.h>
38 #include <rte_cycles.h>
39 #include <rte_malloc.h>
40 #include <rte_memzone.h>
41 #include <rte_version.h>
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
49 #include "bnxt_ring.h"
52 #include "bnxt_vnic.h"
53 #include "hsi_struct_def_dpdk.h"
57 #define HWRM_CMD_TIMEOUT 10000
59 struct bnxt_plcmodes_cfg {
61 uint16_t jumbo_thresh;
63 uint16_t hds_threshold;
66 static int page_getenum(size_t size)
82 RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
83 return sizeof(void *) * 8 - 1;
86 static int page_roundup(size_t size)
88 return 1 << page_getenum(size);
92 * HWRM Functions (sent to HWRM)
93 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
94 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
95 * command was failed by the ChiMP.
98 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
102 struct input *req = msg;
103 struct output *resp = bp->hwrm_cmd_resp_addr;
104 uint32_t *data = msg;
107 uint16_t max_req_len = bp->max_req_len;
108 struct hwrm_short_input short_input = { 0 };
110 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
111 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
113 memset(short_cmd_req, 0, bp->max_req_len);
114 memcpy(short_cmd_req, req, msg_len);
116 short_input.req_type = rte_cpu_to_le_16(req->req_type);
117 short_input.signature = rte_cpu_to_le_16(
118 HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
119 short_input.size = rte_cpu_to_le_16(msg_len);
120 short_input.req_addr =
121 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
123 data = (uint32_t *)&short_input;
124 msg_len = sizeof(short_input);
126 /* Sync memory write before updating doorbell */
129 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
132 /* Write request msg to hwrm channel */
133 for (i = 0; i < msg_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + i;
135 rte_write32(*data, bar);
139 /* Zero the rest of the request space */
140 for (; i < max_req_len; i += 4) {
141 bar = (uint8_t *)bp->bar0 + i;
145 /* Ring channel doorbell */
146 bar = (uint8_t *)bp->bar0 + 0x100;
149 /* Poll for the valid bit */
150 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
151 /* Sanity check on the resp->resp_len */
153 if (resp->resp_len && resp->resp_len <=
155 /* Last byte of resp contains the valid key */
156 valid = (uint8_t *)resp + resp->resp_len - 1;
157 if (*valid == HWRM_RESP_VALID_KEY)
163 if (i >= HWRM_CMD_TIMEOUT) {
164 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
175 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
176 * spinlock, and does initial processing.
178 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
179 * releases the spinlock only if it returns. If the regular int return codes
180 * are not used by the function, HWRM_CHECK_RESULT() should not be used
181 * directly, rather it should be copied and modified to suit the function.
183 * HWRM_UNLOCK() must be called after all response processing is completed.
185 #define HWRM_PREP(req, type) do { \
186 rte_spinlock_lock(&bp->hwrm_lock); \
187 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
188 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
189 req.cmpl_ring = rte_cpu_to_le_16(-1); \
190 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
191 req.target_id = rte_cpu_to_le_16(0xffff); \
192 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
195 #define HWRM_CHECK_RESULT() do {\
197 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
199 rte_spinlock_unlock(&bp->hwrm_lock); \
202 if (resp->error_code) { \
203 rc = rte_le_to_cpu_16(resp->error_code); \
204 if (resp->resp_len >= 16) { \
205 struct hwrm_err_output *tmp_hwrm_err_op = \
208 "%s error %d:%d:%08x:%04x\n", \
210 rc, tmp_hwrm_err_op->cmd_err, \
212 tmp_hwrm_err_op->opaque_0), \
214 tmp_hwrm_err_op->opaque_1)); \
218 "%s error %d\n", __func__, rc); \
220 rte_spinlock_unlock(&bp->hwrm_lock); \
225 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
227 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
230 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
231 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
233 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
234 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
237 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
245 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
246 struct bnxt_vnic_info *vnic,
248 struct bnxt_vlan_table_entry *vlan_table)
251 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
252 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
255 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
256 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
258 /* FIXME add multicast flag, when multicast adding options is supported
261 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
262 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
263 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
264 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
265 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
266 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
267 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
268 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
269 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
270 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
271 if (vnic->mc_addr_cnt) {
272 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
273 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
274 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
277 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
278 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
279 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
280 rte_mem_virt2iova(vlan_table));
281 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
283 req.mask = rte_cpu_to_le_32(mask);
285 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
293 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
295 struct bnxt_vlan_antispoof_table_entry *vlan_table)
298 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
299 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
300 bp->hwrm_cmd_resp_addr;
303 * Older HWRM versions did not support this command, and the set_rx_mask
304 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
305 * removed from set_rx_mask call, and this command was added.
307 * This command is also present from 1.7.8.11 and higher,
310 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
311 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
312 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
317 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
318 req.fid = rte_cpu_to_le_16(fid);
320 req.vlan_tag_mask_tbl_addr =
321 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
322 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
324 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
332 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
333 struct bnxt_filter_info *filter)
336 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
337 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
339 if (filter->fw_l2_filter_id == UINT64_MAX)
342 HWRM_PREP(req, CFA_L2_FILTER_FREE);
344 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
346 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
351 filter->fw_l2_filter_id = -1;
356 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
358 struct bnxt_filter_info *filter)
361 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
362 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
363 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
364 const struct rte_eth_vmdq_rx_conf *conf =
365 &dev_conf->rx_adv_conf.vmdq_rx_conf;
366 uint32_t enables = 0;
367 uint16_t j = dst_id - 1;
369 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
370 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
371 conf->pool_map[j].pools & (1UL << j)) {
373 "Add vlan %u to vmdq pool %u\n",
374 conf->pool_map[j].vlan_id, j);
376 filter->l2_ivlan = conf->pool_map[j].vlan_id;
378 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
379 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
382 if (filter->fw_l2_filter_id != UINT64_MAX)
383 bnxt_hwrm_clear_l2_filter(bp, filter);
385 HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
387 req.flags = rte_cpu_to_le_32(filter->flags);
389 enables = filter->enables |
390 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
391 req.dst_id = rte_cpu_to_le_16(dst_id);
394 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
395 memcpy(req.l2_addr, filter->l2_addr,
398 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
399 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
402 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
403 req.l2_ovlan = filter->l2_ovlan;
405 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
406 req.l2_ovlan = filter->l2_ivlan;
408 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
409 req.l2_ovlan_mask = filter->l2_ovlan_mask;
411 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
412 req.l2_ovlan_mask = filter->l2_ivlan_mask;
413 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
414 req.src_id = rte_cpu_to_le_32(filter->src_id);
415 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
416 req.src_type = filter->src_type;
418 req.enables = rte_cpu_to_le_32(enables);
420 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
424 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
430 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
433 struct hwrm_func_qcaps_input req = {.req_type = 0 };
434 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
435 uint16_t new_max_vfs;
438 HWRM_PREP(req, FUNC_QCAPS);
440 req.fid = rte_cpu_to_le_16(0xffff);
442 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
446 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
448 bp->pf.port_id = resp->port_id;
449 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
450 new_max_vfs = bp->pdev->max_vfs;
451 if (new_max_vfs != bp->pf.max_vfs) {
453 rte_free(bp->pf.vf_info);
454 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
455 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
456 bp->pf.max_vfs = new_max_vfs;
457 for (i = 0; i < new_max_vfs; i++) {
458 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
459 bp->pf.vf_info[i].vlan_table =
460 rte_zmalloc("VF VLAN table",
463 if (bp->pf.vf_info[i].vlan_table == NULL)
465 "Fail to alloc VLAN table for VF %d\n",
469 bp->pf.vf_info[i].vlan_table);
470 bp->pf.vf_info[i].vlan_as_table =
471 rte_zmalloc("VF VLAN AS table",
474 if (bp->pf.vf_info[i].vlan_as_table == NULL)
476 "Alloc VLAN AS table for VF %d fail\n",
480 bp->pf.vf_info[i].vlan_as_table);
481 STAILQ_INIT(&bp->pf.vf_info[i].filter);
486 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
487 memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
488 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
489 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
490 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
491 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
492 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
493 /* TODO: For now, do not support VMDq/RFS on VFs. */
498 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
502 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
504 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
510 int bnxt_hwrm_func_reset(struct bnxt *bp)
513 struct hwrm_func_reset_input req = {.req_type = 0 };
514 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
516 HWRM_PREP(req, FUNC_RESET);
518 req.enables = rte_cpu_to_le_32(0);
520 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
528 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
531 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
532 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
534 if (bp->flags & BNXT_FLAG_REGISTERED)
537 HWRM_PREP(req, FUNC_DRV_RGTR);
538 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
539 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
540 req.ver_maj = RTE_VER_YEAR;
541 req.ver_min = RTE_VER_MONTH;
542 req.ver_upd = RTE_VER_MINOR;
545 req.enables |= rte_cpu_to_le_32(
546 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
547 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
548 RTE_MIN(sizeof(req.vf_req_fwd),
549 sizeof(bp->pf.vf_req_fwd)));
552 req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1); /* TODO: Use MACRO */
553 //memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
555 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
560 bp->flags |= BNXT_FLAG_REGISTERED;
565 int bnxt_hwrm_ver_get(struct bnxt *bp)
568 struct hwrm_ver_get_input req = {.req_type = 0 };
569 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
572 uint16_t max_resp_len;
573 char type[RTE_MEMZONE_NAMESIZE];
574 uint32_t dev_caps_cfg;
576 bp->max_req_len = HWRM_MAX_REQ_LEN;
577 HWRM_PREP(req, VER_GET);
579 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
580 req.hwrm_intf_min = HWRM_VERSION_MINOR;
581 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
583 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
587 RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
588 resp->hwrm_intf_maj, resp->hwrm_intf_min,
590 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
591 bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
592 (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
593 RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
594 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
596 my_version = HWRM_VERSION_MAJOR << 16;
597 my_version |= HWRM_VERSION_MINOR << 8;
598 my_version |= HWRM_VERSION_UPDATE;
600 fw_version = resp->hwrm_intf_maj << 16;
601 fw_version |= resp->hwrm_intf_min << 8;
602 fw_version |= resp->hwrm_intf_upd;
604 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
605 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
610 if (my_version != fw_version) {
611 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
612 if (my_version < fw_version) {
614 "Firmware API version is newer than driver.\n");
616 "The driver may be missing features.\n");
619 "Firmware API version is older than driver.\n");
621 "Not all driver features may be functional.\n");
625 if (bp->max_req_len > resp->max_req_win_len) {
626 RTE_LOG(ERR, PMD, "Unsupported request length\n");
629 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
630 max_resp_len = resp->max_resp_len;
631 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
633 if (bp->max_resp_len != max_resp_len) {
634 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
635 bp->pdev->addr.domain, bp->pdev->addr.bus,
636 bp->pdev->addr.devid, bp->pdev->addr.function);
638 rte_free(bp->hwrm_cmd_resp_addr);
640 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
641 if (bp->hwrm_cmd_resp_addr == NULL) {
645 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
646 bp->hwrm_cmd_resp_dma_addr =
647 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
648 if (bp->hwrm_cmd_resp_dma_addr == 0) {
650 "Unable to map response buffer to physical memory.\n");
654 bp->max_resp_len = max_resp_len;
658 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
660 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
661 RTE_LOG(DEBUG, PMD, "Short command supported\n");
663 rte_free(bp->hwrm_short_cmd_req_addr);
665 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
667 if (bp->hwrm_short_cmd_req_addr == NULL) {
671 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
672 bp->hwrm_short_cmd_req_dma_addr =
673 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
674 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
675 rte_free(bp->hwrm_short_cmd_req_addr);
677 "Unable to map buffer to physical memory.\n");
682 bp->flags |= BNXT_FLAG_SHORT_CMD;
690 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
693 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
694 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
696 if (!(bp->flags & BNXT_FLAG_REGISTERED))
699 HWRM_PREP(req, FUNC_DRV_UNRGTR);
702 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
707 bp->flags &= ~BNXT_FLAG_REGISTERED;
712 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
715 struct hwrm_port_phy_cfg_input req = {0};
716 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
717 uint32_t enables = 0;
719 HWRM_PREP(req, PORT_PHY_CFG);
722 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
723 if (bp->link_info.auto_mode && conf->link_speed) {
724 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
725 RTE_LOG(DEBUG, PMD, "Disabling AutoNeg\n");
728 req.flags = rte_cpu_to_le_32(conf->phy_flags);
729 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
730 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
732 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
733 * any auto mode, even "none".
735 if (!conf->link_speed) {
736 /* No speeds specified. Enable AutoNeg - all speeds */
738 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
740 /* AutoNeg - Advertise speeds specified. */
741 if (conf->auto_link_speed_mask &&
742 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
744 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
745 req.auto_link_speed_mask =
746 conf->auto_link_speed_mask;
748 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
751 req.auto_duplex = conf->duplex;
752 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
753 req.auto_pause = conf->auto_pause;
754 req.force_pause = conf->force_pause;
755 /* Set force_pause if there is no auto or if there is a force */
756 if (req.auto_pause && !req.force_pause)
757 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
759 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
761 req.enables = rte_cpu_to_le_32(enables);
764 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
765 RTE_LOG(INFO, PMD, "Force Link Down\n");
768 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
776 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
777 struct bnxt_link_info *link_info)
780 struct hwrm_port_phy_qcfg_input req = {0};
781 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
783 HWRM_PREP(req, PORT_PHY_QCFG);
785 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
789 link_info->phy_link_status = resp->link;
791 (link_info->phy_link_status ==
792 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
793 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
794 link_info->duplex = resp->duplex_cfg;
795 link_info->pause = resp->pause;
796 link_info->auto_pause = resp->auto_pause;
797 link_info->force_pause = resp->force_pause;
798 link_info->auto_mode = resp->auto_mode;
799 link_info->phy_type = resp->phy_type;
800 link_info->media_type = resp->media_type;
802 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
803 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
804 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
805 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
806 link_info->phy_ver[0] = resp->phy_maj;
807 link_info->phy_ver[1] = resp->phy_min;
808 link_info->phy_ver[2] = resp->phy_bld;
812 RTE_LOG(DEBUG, PMD, "Link Speed %d\n", link_info->link_speed);
813 RTE_LOG(DEBUG, PMD, "Auto Mode %d\n", link_info->auto_mode);
814 RTE_LOG(DEBUG, PMD, "Support Speeds %x\n", link_info->support_speeds);
815 RTE_LOG(DEBUG, PMD, "Auto Link Speed %x\n", link_info->auto_link_speed);
816 RTE_LOG(DEBUG, PMD, "Auto Link Speed Mask %x\n",
817 link_info->auto_link_speed_mask);
818 RTE_LOG(DEBUG, PMD, "Forced Link Speed %x\n",
819 link_info->force_link_speed);
824 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
827 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
828 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
830 HWRM_PREP(req, QUEUE_QPORTCFG);
832 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
836 #define GET_QUEUE_INFO(x) \
837 bp->cos_queue[x].id = resp->queue_id##x; \
838 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
854 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
855 struct bnxt_ring *ring,
856 uint32_t ring_type, uint32_t map_index,
857 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
860 uint32_t enables = 0;
861 struct hwrm_ring_alloc_input req = {.req_type = 0 };
862 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
864 HWRM_PREP(req, RING_ALLOC);
866 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
867 req.fbo = rte_cpu_to_le_32(0);
868 /* Association of ring index with doorbell index */
869 req.logical_id = rte_cpu_to_le_16(map_index);
870 req.length = rte_cpu_to_le_32(ring->ring_size);
873 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
874 req.queue_id = bp->cos_queue[0].id;
876 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
877 req.ring_type = ring_type;
878 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
879 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
880 if (stats_ctx_id != INVALID_STATS_CTX_ID)
882 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
884 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
885 req.ring_type = ring_type;
887 * TODO: Some HWRM versions crash with
888 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
890 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
893 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
898 req.enables = rte_cpu_to_le_32(enables);
900 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
902 if (rc || resp->error_code) {
903 if (rc == 0 && resp->error_code)
904 rc = rte_le_to_cpu_16(resp->error_code);
906 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
908 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
911 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
913 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
916 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
918 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
922 RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
928 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
933 int bnxt_hwrm_ring_free(struct bnxt *bp,
934 struct bnxt_ring *ring, uint32_t ring_type)
937 struct hwrm_ring_free_input req = {.req_type = 0 };
938 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
940 HWRM_PREP(req, RING_FREE);
942 req.ring_type = ring_type;
943 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
945 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
947 if (rc || resp->error_code) {
948 if (rc == 0 && resp->error_code)
949 rc = rte_le_to_cpu_16(resp->error_code);
953 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
954 RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
957 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
958 RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
961 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
962 RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
966 RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
974 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
977 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
978 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
980 HWRM_PREP(req, RING_GRP_ALLOC);
982 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
983 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
984 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
985 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
987 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
991 bp->grp_info[idx].fw_grp_id =
992 rte_le_to_cpu_16(resp->ring_group_id);
999 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1002 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1003 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1005 HWRM_PREP(req, RING_GRP_FREE);
1007 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1009 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1011 HWRM_CHECK_RESULT();
1014 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1018 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1021 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1022 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1024 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1027 HWRM_PREP(req, STAT_CTX_CLR_STATS);
1029 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1031 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1033 HWRM_CHECK_RESULT();
1039 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1040 unsigned int idx __rte_unused)
1043 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1044 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1046 HWRM_PREP(req, STAT_CTX_ALLOC);
1048 req.update_period_ms = rte_cpu_to_le_32(0);
1050 req.stats_dma_addr =
1051 rte_cpu_to_le_64(cpr->hw_stats_map);
1053 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1055 HWRM_CHECK_RESULT();
1057 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1064 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1065 unsigned int idx __rte_unused)
1068 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1069 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1071 HWRM_PREP(req, STAT_CTX_FREE);
1073 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1075 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1077 HWRM_CHECK_RESULT();
1083 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1086 struct hwrm_vnic_alloc_input req = { 0 };
1087 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1089 /* map ring groups to this vnic */
1090 RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
1091 vnic->start_grp_id, vnic->end_grp_id);
1092 for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1093 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1094 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1095 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1096 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1097 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1098 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1099 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1100 HWRM_PREP(req, VNIC_ALLOC);
1102 if (vnic->func_default)
1103 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
1104 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1106 HWRM_CHECK_RESULT();
1108 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1110 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1114 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1115 struct bnxt_vnic_info *vnic,
1116 struct bnxt_plcmodes_cfg *pmode)
1119 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1120 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1122 HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1124 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1126 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1128 HWRM_CHECK_RESULT();
1130 pmode->flags = rte_le_to_cpu_32(resp->flags);
1131 /* dflt_vnic bit doesn't exist in the _cfg command */
1132 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1133 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1134 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1135 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1142 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1143 struct bnxt_vnic_info *vnic,
1144 struct bnxt_plcmodes_cfg *pmode)
1147 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1148 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1150 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1152 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1153 req.flags = rte_cpu_to_le_32(pmode->flags);
1154 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1155 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1156 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1157 req.enables = rte_cpu_to_le_32(
1158 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1159 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1160 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1163 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1165 HWRM_CHECK_RESULT();
1171 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1174 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1175 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1176 uint32_t ctx_enable_flag = 0;
1177 struct bnxt_plcmodes_cfg pmodes;
1179 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1180 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1184 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1188 HWRM_PREP(req, VNIC_CFG);
1190 /* Only RSS support for now TBD: COS & LB */
1192 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1193 if (vnic->lb_rule != 0xffff)
1194 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1195 if (vnic->cos_rule != 0xffff)
1196 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1197 if (vnic->rss_rule != 0xffff) {
1198 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1199 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1201 req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1202 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1203 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1204 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1205 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1206 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1207 req.mru = rte_cpu_to_le_16(vnic->mru);
1208 if (vnic->func_default)
1210 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1211 if (vnic->vlan_strip)
1213 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1216 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1217 if (vnic->roce_dual)
1218 req.flags |= rte_cpu_to_le_32(
1219 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1220 if (vnic->roce_only)
1221 req.flags |= rte_cpu_to_le_32(
1222 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1223 if (vnic->rss_dflt_cr)
1224 req.flags |= rte_cpu_to_le_32(
1225 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1227 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1229 HWRM_CHECK_RESULT();
1232 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1237 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1241 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1242 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1244 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1245 RTE_LOG(DEBUG, PMD, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1248 HWRM_PREP(req, VNIC_QCFG);
1251 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1252 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1253 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1255 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1257 HWRM_CHECK_RESULT();
1259 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1260 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1261 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1262 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1263 vnic->mru = rte_le_to_cpu_16(resp->mru);
1264 vnic->func_default = rte_le_to_cpu_32(
1265 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1266 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1267 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1268 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1269 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1270 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1271 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1272 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1273 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1274 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1275 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1282 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1285 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1286 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1287 bp->hwrm_cmd_resp_addr;
1289 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1291 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1293 HWRM_CHECK_RESULT();
1295 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1297 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1302 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1305 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1306 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1307 bp->hwrm_cmd_resp_addr;
1309 if (vnic->rss_rule == 0xffff) {
1310 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1313 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1315 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1317 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1319 HWRM_CHECK_RESULT();
1322 vnic->rss_rule = INVALID_HW_RING_ID;
1327 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1330 struct hwrm_vnic_free_input req = {.req_type = 0 };
1331 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1333 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1334 RTE_LOG(DEBUG, PMD, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1338 HWRM_PREP(req, VNIC_FREE);
1340 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1342 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1344 HWRM_CHECK_RESULT();
1347 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1351 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1352 struct bnxt_vnic_info *vnic)
1355 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1356 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1358 HWRM_PREP(req, VNIC_RSS_CFG);
1360 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1362 req.ring_grp_tbl_addr =
1363 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1364 req.hash_key_tbl_addr =
1365 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1366 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1368 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1370 HWRM_CHECK_RESULT();
1376 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1377 struct bnxt_vnic_info *vnic)
1380 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1381 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1384 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1386 req.flags = rte_cpu_to_le_32(
1387 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1389 req.enables = rte_cpu_to_le_32(
1390 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1392 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1393 size -= RTE_PKTMBUF_HEADROOM;
1395 req.jumbo_thresh = rte_cpu_to_le_16(size);
1396 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1398 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1400 HWRM_CHECK_RESULT();
1406 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1407 struct bnxt_vnic_info *vnic, bool enable)
1410 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1411 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1413 HWRM_PREP(req, VNIC_TPA_CFG);
1416 req.enables = rte_cpu_to_le_32(
1417 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1418 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1419 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1420 req.flags = rte_cpu_to_le_32(
1421 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1422 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1423 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1424 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1425 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1426 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1427 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1428 req.max_agg_segs = rte_cpu_to_le_16(5);
1430 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1431 req.min_agg_len = rte_cpu_to_le_32(512);
1434 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1436 HWRM_CHECK_RESULT();
1442 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1444 struct hwrm_func_cfg_input req = {0};
1445 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1448 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1449 req.enables = rte_cpu_to_le_32(
1450 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1451 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1452 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1454 HWRM_PREP(req, FUNC_CFG);
1456 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1457 HWRM_CHECK_RESULT();
1460 bp->pf.vf_info[vf].random_mac = false;
1465 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1469 struct hwrm_func_qstats_input req = {.req_type = 0};
1470 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1472 HWRM_PREP(req, FUNC_QSTATS);
1474 req.fid = rte_cpu_to_le_16(fid);
1476 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1478 HWRM_CHECK_RESULT();
1481 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1488 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1489 struct rte_eth_stats *stats)
1492 struct hwrm_func_qstats_input req = {.req_type = 0};
1493 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1495 HWRM_PREP(req, FUNC_QSTATS);
1497 req.fid = rte_cpu_to_le_16(fid);
1499 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1501 HWRM_CHECK_RESULT();
1503 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1504 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1505 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1506 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1507 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1508 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1510 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1511 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1512 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1513 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1514 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1515 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1517 stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1518 stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1520 stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1527 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1530 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1531 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1533 HWRM_PREP(req, FUNC_CLR_STATS);
1535 req.fid = rte_cpu_to_le_16(fid);
1537 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1539 HWRM_CHECK_RESULT();
1546 * HWRM utility functions
1549 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1554 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1555 struct bnxt_tx_queue *txq;
1556 struct bnxt_rx_queue *rxq;
1557 struct bnxt_cp_ring_info *cpr;
1559 if (i >= bp->rx_cp_nr_rings) {
1560 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1563 rxq = bp->rx_queues[i];
1567 rc = bnxt_hwrm_stat_clear(bp, cpr);
1574 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1578 struct bnxt_cp_ring_info *cpr;
1580 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1582 if (i >= bp->rx_cp_nr_rings) {
1583 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1585 cpr = bp->rx_queues[i]->cp_ring;
1586 bp->grp_info[i].fw_stats_ctx = -1;
1588 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1589 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1590 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1598 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1603 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1604 struct bnxt_tx_queue *txq;
1605 struct bnxt_rx_queue *rxq;
1606 struct bnxt_cp_ring_info *cpr;
1608 if (i >= bp->rx_cp_nr_rings) {
1609 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1612 rxq = bp->rx_queues[i];
1616 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1624 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1629 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1631 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1634 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1642 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1643 unsigned int idx __rte_unused)
1645 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1647 bnxt_hwrm_ring_free(bp, cp_ring,
1648 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1649 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1650 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1651 sizeof(*cpr->cp_desc_ring));
1652 cpr->cp_raw_cons = 0;
1655 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1660 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1661 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1662 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1663 struct bnxt_ring *ring = txr->tx_ring_struct;
1664 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1665 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1667 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1668 bnxt_hwrm_ring_free(bp, ring,
1669 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1670 ring->fw_ring_id = INVALID_HW_RING_ID;
1671 memset(txr->tx_desc_ring, 0,
1672 txr->tx_ring_struct->ring_size *
1673 sizeof(*txr->tx_desc_ring));
1674 memset(txr->tx_buf_ring, 0,
1675 txr->tx_ring_struct->ring_size *
1676 sizeof(*txr->tx_buf_ring));
1680 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1681 bnxt_free_cp_ring(bp, cpr, idx);
1682 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1686 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1687 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1688 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1689 struct bnxt_ring *ring = rxr->rx_ring_struct;
1690 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1691 unsigned int idx = i + 1;
1693 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1694 bnxt_hwrm_ring_free(bp, ring,
1695 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1696 ring->fw_ring_id = INVALID_HW_RING_ID;
1697 bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1698 memset(rxr->rx_desc_ring, 0,
1699 rxr->rx_ring_struct->ring_size *
1700 sizeof(*rxr->rx_desc_ring));
1701 memset(rxr->rx_buf_ring, 0,
1702 rxr->rx_ring_struct->ring_size *
1703 sizeof(*rxr->rx_buf_ring));
1706 ring = rxr->ag_ring_struct;
1707 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1708 bnxt_hwrm_ring_free(bp, ring,
1709 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1710 ring->fw_ring_id = INVALID_HW_RING_ID;
1711 memset(rxr->ag_buf_ring, 0,
1712 rxr->ag_ring_struct->ring_size *
1713 sizeof(*rxr->ag_buf_ring));
1715 bp->grp_info[i].ag_fw_ring_id = INVALID_HW_RING_ID;
1717 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1718 bnxt_free_cp_ring(bp, cpr, idx);
1719 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1720 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1724 /* Default completion ring */
1726 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1728 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1729 bnxt_free_cp_ring(bp, cpr, 0);
1730 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1737 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1742 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1743 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1750 void bnxt_free_hwrm_resources(struct bnxt *bp)
1752 /* Release memzone */
1753 rte_free(bp->hwrm_cmd_resp_addr);
1754 rte_free(bp->hwrm_short_cmd_req_addr);
1755 bp->hwrm_cmd_resp_addr = NULL;
1756 bp->hwrm_short_cmd_req_addr = NULL;
1757 bp->hwrm_cmd_resp_dma_addr = 0;
1758 bp->hwrm_short_cmd_req_dma_addr = 0;
1761 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1763 struct rte_pci_device *pdev = bp->pdev;
1764 char type[RTE_MEMZONE_NAMESIZE];
1766 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1767 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1768 bp->max_resp_len = HWRM_MAX_RESP_LEN;
1769 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1770 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1771 if (bp->hwrm_cmd_resp_addr == NULL)
1773 bp->hwrm_cmd_resp_dma_addr =
1774 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1775 if (bp->hwrm_cmd_resp_dma_addr == 0) {
1777 "unable to map response address to physical memory\n");
1780 rte_spinlock_init(&bp->hwrm_lock);
1785 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1787 struct bnxt_filter_info *filter;
1790 STAILQ_FOREACH(filter, &vnic->filter, next) {
1791 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1792 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1793 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1794 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1796 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1804 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1806 struct bnxt_filter_info *filter;
1807 struct rte_flow *flow;
1810 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1811 filter = flow->filter;
1812 RTE_LOG(ERR, PMD, "filter type %d\n", filter->filter_type);
1813 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1814 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1815 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1816 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1818 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1820 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1828 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1830 struct bnxt_filter_info *filter;
1833 STAILQ_FOREACH(filter, &vnic->filter, next) {
1834 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1835 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1837 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1838 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1841 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1849 void bnxt_free_tunnel_ports(struct bnxt *bp)
1851 if (bp->vxlan_port_cnt)
1852 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1853 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1855 if (bp->geneve_port_cnt)
1856 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1857 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1858 bp->geneve_port = 0;
1861 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1865 if (bp->vnic_info == NULL)
1869 * Cleanup VNICs in reverse order, to make sure the L2 filter
1870 * from vnic0 is last to be cleaned up.
1872 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1873 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1875 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1877 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1879 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1881 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1883 bnxt_hwrm_vnic_free(bp, vnic);
1885 /* Ring resources */
1886 bnxt_free_all_hwrm_rings(bp);
1887 bnxt_free_all_hwrm_ring_grps(bp);
1888 bnxt_free_all_hwrm_stat_ctxs(bp);
1889 bnxt_free_tunnel_ports(bp);
1892 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1894 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1896 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1897 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1899 switch (conf_link_speed) {
1900 case ETH_LINK_SPEED_10M_HD:
1901 case ETH_LINK_SPEED_100M_HD:
1902 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1904 return hw_link_duplex;
1907 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
1909 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
1912 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1914 uint16_t eth_link_speed = 0;
1916 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1917 return ETH_LINK_SPEED_AUTONEG;
1919 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1920 case ETH_LINK_SPEED_100M:
1921 case ETH_LINK_SPEED_100M_HD:
1923 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1925 case ETH_LINK_SPEED_1G:
1927 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1929 case ETH_LINK_SPEED_2_5G:
1931 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1933 case ETH_LINK_SPEED_10G:
1935 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1937 case ETH_LINK_SPEED_20G:
1939 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1941 case ETH_LINK_SPEED_25G:
1943 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1945 case ETH_LINK_SPEED_40G:
1947 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1949 case ETH_LINK_SPEED_50G:
1951 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1955 "Unsupported link speed %d; default to AUTO\n",
1959 return eth_link_speed;
1962 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1963 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1964 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1965 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1967 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
1971 if (link_speed == ETH_LINK_SPEED_AUTONEG)
1974 if (link_speed & ETH_LINK_SPEED_FIXED) {
1975 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1977 if (one_speed & (one_speed - 1)) {
1979 "Invalid advertised speeds (%u) for port %u\n",
1980 link_speed, port_id);
1983 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1985 "Unsupported advertised speed (%u) for port %u\n",
1986 link_speed, port_id);
1990 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1992 "Unsupported advertised speeds (%u) for port %u\n",
1993 link_speed, port_id);
2001 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2005 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2006 if (bp->link_info.support_speeds)
2007 return bp->link_info.support_speeds;
2008 link_speed = BNXT_SUPPORTED_SPEEDS;
2011 if (link_speed & ETH_LINK_SPEED_100M)
2012 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2013 if (link_speed & ETH_LINK_SPEED_100M_HD)
2014 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2015 if (link_speed & ETH_LINK_SPEED_1G)
2016 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2017 if (link_speed & ETH_LINK_SPEED_2_5G)
2018 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2019 if (link_speed & ETH_LINK_SPEED_10G)
2020 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2021 if (link_speed & ETH_LINK_SPEED_20G)
2022 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2023 if (link_speed & ETH_LINK_SPEED_25G)
2024 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2025 if (link_speed & ETH_LINK_SPEED_40G)
2026 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2027 if (link_speed & ETH_LINK_SPEED_50G)
2028 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2032 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2034 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2036 switch (hw_link_speed) {
2037 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2038 eth_link_speed = ETH_SPEED_NUM_100M;
2040 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2041 eth_link_speed = ETH_SPEED_NUM_1G;
2043 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2044 eth_link_speed = ETH_SPEED_NUM_2_5G;
2046 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2047 eth_link_speed = ETH_SPEED_NUM_10G;
2049 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2050 eth_link_speed = ETH_SPEED_NUM_20G;
2052 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2053 eth_link_speed = ETH_SPEED_NUM_25G;
2055 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2056 eth_link_speed = ETH_SPEED_NUM_40G;
2058 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2059 eth_link_speed = ETH_SPEED_NUM_50G;
2061 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2063 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
2067 return eth_link_speed;
2070 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2072 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2074 switch (hw_link_duplex) {
2075 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2076 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2077 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2079 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2080 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2083 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
2087 return eth_link_duplex;
2090 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2093 struct bnxt_link_info *link_info = &bp->link_info;
2095 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2098 "Get link config failed with rc %d\n", rc);
2101 if (link_info->link_speed)
2103 bnxt_parse_hw_link_speed(link_info->link_speed);
2105 link->link_speed = ETH_SPEED_NUM_NONE;
2106 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2107 link->link_status = link_info->link_up;
2108 link->link_autoneg = link_info->auto_mode ==
2109 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2110 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2115 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2118 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2119 struct bnxt_link_info link_req;
2120 uint16_t speed, autoneg;
2122 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
2125 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2126 bp->eth_dev->data->port_id);
2130 memset(&link_req, 0, sizeof(link_req));
2131 link_req.link_up = link_up;
2135 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2136 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2137 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2138 /* Autoneg can be done only when the FW allows */
2139 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2140 bp->link_info.force_link_speed)) {
2141 link_req.phy_flags |=
2142 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2143 link_req.auto_link_speed_mask =
2144 bnxt_parse_eth_link_speed_mask(bp,
2145 dev_conf->link_speeds);
2147 if (bp->link_info.phy_type ==
2148 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2149 bp->link_info.phy_type ==
2150 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2151 bp->link_info.media_type ==
2152 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2153 RTE_LOG(ERR, PMD, "10GBase-T devices must autoneg\n");
2157 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2158 /* If user wants a particular speed try that first. */
2160 link_req.link_speed = speed;
2161 else if (bp->link_info.force_link_speed)
2162 link_req.link_speed = bp->link_info.force_link_speed;
2164 link_req.link_speed = bp->link_info.auto_link_speed;
2166 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2167 link_req.auto_pause = bp->link_info.auto_pause;
2168 link_req.force_pause = bp->link_info.force_pause;
2171 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2174 "Set link config failed with rc %d\n", rc);
2182 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2184 struct hwrm_func_qcfg_input req = {0};
2185 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2188 HWRM_PREP(req, FUNC_QCFG);
2189 req.fid = rte_cpu_to_le_16(0xffff);
2191 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2193 HWRM_CHECK_RESULT();
2195 /* Hard Coded.. 0xfff VLAN ID mask */
2196 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2198 switch (resp->port_partition_type) {
2199 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2200 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2201 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2202 bp->port_partition_type = resp->port_partition_type;
2205 bp->port_partition_type = 0;
2214 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2215 struct hwrm_func_qcaps_output *qcaps)
2217 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2218 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2219 sizeof(qcaps->mac_address));
2220 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2221 qcaps->max_rx_rings = fcfg->num_rx_rings;
2222 qcaps->max_tx_rings = fcfg->num_tx_rings;
2223 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2224 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2226 qcaps->first_vf_id = 0;
2227 qcaps->max_vnics = fcfg->num_vnics;
2228 qcaps->max_decap_records = 0;
2229 qcaps->max_encap_records = 0;
2230 qcaps->max_tx_wm_flows = 0;
2231 qcaps->max_tx_em_flows = 0;
2232 qcaps->max_rx_wm_flows = 0;
2233 qcaps->max_rx_em_flows = 0;
2234 qcaps->max_flow_id = 0;
2235 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2236 qcaps->max_sp_tx_rings = 0;
2237 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2240 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2242 struct hwrm_func_cfg_input req = {0};
2243 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2246 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2247 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2248 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2249 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2250 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2251 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2252 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2253 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2254 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2255 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2256 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2257 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2258 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2259 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2260 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2261 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2262 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2263 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2264 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2265 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2266 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2267 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2268 req.fid = rte_cpu_to_le_16(0xffff);
2270 HWRM_PREP(req, FUNC_CFG);
2272 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2274 HWRM_CHECK_RESULT();
2280 static void populate_vf_func_cfg_req(struct bnxt *bp,
2281 struct hwrm_func_cfg_input *req,
2284 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2285 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2286 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2287 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2288 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2289 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2290 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2291 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2292 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2293 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2295 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2296 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2297 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2298 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2299 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2301 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2302 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2304 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2305 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2306 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2307 /* TODO: For now, do not support VMDq/RFS on VFs. */
2308 req->num_vnics = rte_cpu_to_le_16(1);
2309 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2313 static void add_random_mac_if_needed(struct bnxt *bp,
2314 struct hwrm_func_cfg_input *cfg_req,
2317 struct ether_addr mac;
2319 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2322 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2324 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2325 eth_random_addr(cfg_req->dflt_mac_addr);
2326 bp->pf.vf_info[vf].random_mac = true;
2328 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2332 static void reserve_resources_from_vf(struct bnxt *bp,
2333 struct hwrm_func_cfg_input *cfg_req,
2336 struct hwrm_func_qcaps_input req = {0};
2337 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2340 /* Get the actual allocated values now */
2341 HWRM_PREP(req, FUNC_QCAPS);
2342 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2343 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2346 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2347 copy_func_cfg_to_qcaps(cfg_req, resp);
2348 } else if (resp->error_code) {
2349 rc = rte_le_to_cpu_16(resp->error_code);
2350 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2351 copy_func_cfg_to_qcaps(cfg_req, resp);
2354 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2355 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2356 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2357 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2358 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2359 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2361 * TODO: While not supporting VMDq with VFs, max_vnics is always
2362 * forced to 1 in this case
2364 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2365 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2370 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2372 struct hwrm_func_qcfg_input req = {0};
2373 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2376 /* Check for zero MAC address */
2377 HWRM_PREP(req, FUNC_QCFG);
2378 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2379 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2381 RTE_LOG(ERR, PMD, "hwrm_func_qcfg failed rc:%d\n", rc);
2383 } else if (resp->error_code) {
2384 rc = rte_le_to_cpu_16(resp->error_code);
2385 RTE_LOG(ERR, PMD, "hwrm_func_qcfg error %d\n", rc);
2388 rc = rte_le_to_cpu_16(resp->vlan);
2395 static int update_pf_resource_max(struct bnxt *bp)
2397 struct hwrm_func_qcfg_input req = {0};
2398 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2401 /* And copy the allocated numbers into the pf struct */
2402 HWRM_PREP(req, FUNC_QCFG);
2403 req.fid = rte_cpu_to_le_16(0xffff);
2404 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2405 HWRM_CHECK_RESULT();
2407 /* Only TX ring value reflects actual allocation? TODO */
2408 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2409 bp->pf.evb_mode = resp->evb_mode;
2416 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2421 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2425 rc = bnxt_hwrm_func_qcaps(bp);
2429 bp->pf.func_cfg_flags &=
2430 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2431 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2432 bp->pf.func_cfg_flags |=
2433 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2434 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2438 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2440 struct hwrm_func_cfg_input req = {0};
2441 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2448 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2452 rc = bnxt_hwrm_func_qcaps(bp);
2457 bp->pf.active_vfs = num_vfs;
2460 * First, configure the PF to only use one TX ring. This ensures that
2461 * there are enough rings for all VFs.
2463 * If we don't do this, when we call func_alloc() later, we will lock
2464 * extra rings to the PF that won't be available during func_cfg() of
2467 * This has been fixed with firmware versions above 20.6.54
2469 bp->pf.func_cfg_flags &=
2470 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2471 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2472 bp->pf.func_cfg_flags |=
2473 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2474 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2479 * Now, create and register a buffer to hold forwarded VF requests
2481 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2482 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2483 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2484 if (bp->pf.vf_req_buf == NULL) {
2488 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2489 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2490 for (i = 0; i < num_vfs; i++)
2491 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2492 (i * HWRM_MAX_REQ_LEN);
2494 rc = bnxt_hwrm_func_buf_rgtr(bp);
2498 populate_vf_func_cfg_req(bp, &req, num_vfs);
2500 bp->pf.active_vfs = 0;
2501 for (i = 0; i < num_vfs; i++) {
2502 add_random_mac_if_needed(bp, &req, i);
2504 HWRM_PREP(req, FUNC_CFG);
2505 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2506 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2507 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2509 /* Clear enable flag for next pass */
2510 req.enables &= ~rte_cpu_to_le_32(
2511 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2513 if (rc || resp->error_code) {
2515 "Failed to initizlie VF %d\n", i);
2517 "Not all VFs available. (%d, %d)\n",
2518 rc, resp->error_code);
2525 reserve_resources_from_vf(bp, &req, i);
2526 bp->pf.active_vfs++;
2527 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2531 * Now configure the PF to use "the rest" of the resources
2532 * We're using STD_TX_RING_MODE here though which will limit the TX
2533 * rings. This will allow QoS to function properly. Not setting this
2534 * will cause PF rings to break bandwidth settings.
2536 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2540 rc = update_pf_resource_max(bp);
2547 bnxt_hwrm_func_buf_unrgtr(bp);
2551 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2553 struct hwrm_func_cfg_input req = {0};
2554 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2557 HWRM_PREP(req, FUNC_CFG);
2559 req.fid = rte_cpu_to_le_16(0xffff);
2560 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2561 req.evb_mode = bp->pf.evb_mode;
2563 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2564 HWRM_CHECK_RESULT();
2570 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2571 uint8_t tunnel_type)
2573 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2574 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2577 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2578 req.tunnel_type = tunnel_type;
2579 req.tunnel_dst_port_val = port;
2580 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2581 HWRM_CHECK_RESULT();
2583 switch (tunnel_type) {
2584 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2585 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2586 bp->vxlan_port = port;
2588 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2589 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2590 bp->geneve_port = port;
2601 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2602 uint8_t tunnel_type)
2604 struct hwrm_tunnel_dst_port_free_input req = {0};
2605 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2608 HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2610 req.tunnel_type = tunnel_type;
2611 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2612 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2614 HWRM_CHECK_RESULT();
2620 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2623 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2624 struct hwrm_func_cfg_input req = {0};
2627 HWRM_PREP(req, FUNC_CFG);
2629 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2630 req.flags = rte_cpu_to_le_32(flags);
2631 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2633 HWRM_CHECK_RESULT();
2639 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2641 uint32_t *flag = flagp;
2643 vnic->flags = *flag;
2646 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2648 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2651 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2654 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2655 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2657 HWRM_PREP(req, FUNC_BUF_RGTR);
2659 req.req_buf_num_pages = rte_cpu_to_le_16(1);
2660 req.req_buf_page_size = rte_cpu_to_le_16(
2661 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2662 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2663 req.req_buf_page_addr[0] =
2664 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2665 if (req.req_buf_page_addr[0] == 0) {
2667 "unable to map buffer address to physical memory\n");
2671 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2673 HWRM_CHECK_RESULT();
2679 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2682 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2683 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2685 HWRM_PREP(req, FUNC_BUF_UNRGTR);
2687 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2689 HWRM_CHECK_RESULT();
2695 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2697 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2698 struct hwrm_func_cfg_input req = {0};
2701 HWRM_PREP(req, FUNC_CFG);
2703 req.fid = rte_cpu_to_le_16(0xffff);
2704 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2705 req.enables = rte_cpu_to_le_32(
2706 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2707 req.async_event_cr = rte_cpu_to_le_16(
2708 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2709 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2711 HWRM_CHECK_RESULT();
2717 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2719 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2720 struct hwrm_func_vf_cfg_input req = {0};
2723 HWRM_PREP(req, FUNC_VF_CFG);
2725 req.enables = rte_cpu_to_le_32(
2726 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2727 req.async_event_cr = rte_cpu_to_le_16(
2728 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2729 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2731 HWRM_CHECK_RESULT();
2737 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2739 struct hwrm_func_cfg_input req = {0};
2740 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2741 uint16_t dflt_vlan, fid;
2742 uint32_t func_cfg_flags;
2745 HWRM_PREP(req, FUNC_CFG);
2748 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2749 fid = bp->pf.vf_info[vf].fid;
2750 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2752 fid = rte_cpu_to_le_16(0xffff);
2753 func_cfg_flags = bp->pf.func_cfg_flags;
2754 dflt_vlan = bp->vlan;
2757 req.flags = rte_cpu_to_le_32(func_cfg_flags);
2758 req.fid = rte_cpu_to_le_16(fid);
2759 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2760 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2762 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2764 HWRM_CHECK_RESULT();
2770 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2771 uint16_t max_bw, uint16_t enables)
2773 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2774 struct hwrm_func_cfg_input req = {0};
2777 HWRM_PREP(req, FUNC_CFG);
2779 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2780 req.enables |= rte_cpu_to_le_32(enables);
2781 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2782 req.max_bw = rte_cpu_to_le_32(max_bw);
2783 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2785 HWRM_CHECK_RESULT();
2791 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2793 struct hwrm_func_cfg_input req = {0};
2794 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2797 HWRM_PREP(req, FUNC_CFG);
2799 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2800 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2801 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2802 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2804 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2806 HWRM_CHECK_RESULT();
2812 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2813 void *encaped, size_t ec_size)
2816 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2817 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2819 if (ec_size > sizeof(req.encap_request))
2822 HWRM_PREP(req, REJECT_FWD_RESP);
2824 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2825 memcpy(req.encap_request, encaped, ec_size);
2827 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2829 HWRM_CHECK_RESULT();
2835 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2836 struct ether_addr *mac)
2838 struct hwrm_func_qcfg_input req = {0};
2839 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2842 HWRM_PREP(req, FUNC_QCFG);
2844 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2845 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2847 HWRM_CHECK_RESULT();
2849 memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2856 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2857 void *encaped, size_t ec_size)
2860 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2861 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2863 if (ec_size > sizeof(req.encap_request))
2866 HWRM_PREP(req, EXEC_FWD_RESP);
2868 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2869 memcpy(req.encap_request, encaped, ec_size);
2871 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2873 HWRM_CHECK_RESULT();
2879 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2880 struct rte_eth_stats *stats, uint8_t rx)
2883 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2884 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2886 HWRM_PREP(req, STAT_CTX_QUERY);
2888 req.stat_ctx_id = rte_cpu_to_le_32(cid);
2890 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2892 HWRM_CHECK_RESULT();
2895 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2896 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2897 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2898 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2899 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2900 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2901 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2902 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2904 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2905 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2906 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2907 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2908 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2909 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2910 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2919 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2921 struct hwrm_port_qstats_input req = {0};
2922 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2923 struct bnxt_pf_info *pf = &bp->pf;
2926 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2929 HWRM_PREP(req, PORT_QSTATS);
2931 req.port_id = rte_cpu_to_le_16(pf->port_id);
2932 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2933 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2934 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2936 HWRM_CHECK_RESULT();
2942 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2944 struct hwrm_port_clr_stats_input req = {0};
2945 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2946 struct bnxt_pf_info *pf = &bp->pf;
2949 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2952 HWRM_PREP(req, PORT_CLR_STATS);
2954 req.port_id = rte_cpu_to_le_16(pf->port_id);
2955 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2957 HWRM_CHECK_RESULT();
2963 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
2965 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2966 struct hwrm_port_led_qcaps_input req = {0};
2972 HWRM_PREP(req, PORT_LED_QCAPS);
2973 req.port_id = bp->pf.port_id;
2974 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2976 HWRM_CHECK_RESULT();
2978 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
2981 bp->num_leds = resp->num_leds;
2982 memcpy(bp->leds, &resp->led0_id,
2983 sizeof(bp->leds[0]) * bp->num_leds);
2984 for (i = 0; i < bp->num_leds; i++) {
2985 struct bnxt_led_info *led = &bp->leds[i];
2987 uint16_t caps = led->led_state_caps;
2989 if (!led->led_group_id ||
2990 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3002 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3004 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3005 struct hwrm_port_led_cfg_input req = {0};
3006 struct bnxt_led_cfg *led_cfg;
3007 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3008 uint16_t duration = 0;
3011 if (!bp->num_leds || BNXT_VF(bp))
3014 HWRM_PREP(req, PORT_LED_CFG);
3017 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3018 duration = rte_cpu_to_le_16(500);
3020 req.port_id = bp->pf.port_id;
3021 req.num_leds = bp->num_leds;
3022 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3023 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3024 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3025 led_cfg->led_id = bp->leds[i].led_id;
3026 led_cfg->led_state = led_state;
3027 led_cfg->led_blink_on = duration;
3028 led_cfg->led_blink_off = duration;
3029 led_cfg->led_group_id = bp->leds[i].led_group_id;
3032 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3034 HWRM_CHECK_RESULT();
3040 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3044 struct hwrm_nvm_get_dir_info_input req = {0};
3045 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3047 HWRM_PREP(req, NVM_GET_DIR_INFO);
3049 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3051 HWRM_CHECK_RESULT();
3055 *entries = rte_le_to_cpu_32(resp->entries);
3056 *length = rte_le_to_cpu_32(resp->entry_length);
3061 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3064 uint32_t dir_entries;
3065 uint32_t entry_length;
3068 rte_iova_t dma_handle;
3069 struct hwrm_nvm_get_dir_entries_input req = {0};
3070 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3072 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3076 *data++ = dir_entries;
3077 *data++ = entry_length;
3079 memset(data, 0xff, len);
3081 buflen = dir_entries * entry_length;
3082 buf = rte_malloc("nvm_dir", buflen, 0);
3083 rte_mem_lock_page(buf);
3086 dma_handle = rte_mem_virt2iova(buf);
3087 if (dma_handle == 0) {
3089 "unable to map response address to physical memory\n");
3092 HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3093 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3094 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3096 HWRM_CHECK_RESULT();
3100 memcpy(data, buf, len > buflen ? buflen : len);
3107 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3108 uint32_t offset, uint32_t length,
3113 rte_iova_t dma_handle;
3114 struct hwrm_nvm_read_input req = {0};
3115 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3117 buf = rte_malloc("nvm_item", length, 0);
3118 rte_mem_lock_page(buf);
3122 dma_handle = rte_mem_virt2iova(buf);
3123 if (dma_handle == 0) {
3125 "unable to map response address to physical memory\n");
3128 HWRM_PREP(req, NVM_READ);
3129 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3130 req.dir_idx = rte_cpu_to_le_16(index);
3131 req.offset = rte_cpu_to_le_32(offset);
3132 req.len = rte_cpu_to_le_32(length);
3133 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3134 HWRM_CHECK_RESULT();
3137 memcpy(data, buf, length);
3143 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3146 struct hwrm_nvm_erase_dir_entry_input req = {0};
3147 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3149 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3150 req.dir_idx = rte_cpu_to_le_16(index);
3151 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3152 HWRM_CHECK_RESULT();
3159 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3160 uint16_t dir_ordinal, uint16_t dir_ext,
3161 uint16_t dir_attr, const uint8_t *data,
3165 struct hwrm_nvm_write_input req = {0};
3166 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3167 rte_iova_t dma_handle;
3170 HWRM_PREP(req, NVM_WRITE);
3172 req.dir_type = rte_cpu_to_le_16(dir_type);
3173 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3174 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3175 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3176 req.dir_data_length = rte_cpu_to_le_32(data_len);
3178 buf = rte_malloc("nvm_write", data_len, 0);
3179 rte_mem_lock_page(buf);
3183 dma_handle = rte_mem_virt2iova(buf);
3184 if (dma_handle == 0) {
3186 "unable to map response address to physical memory\n");
3189 memcpy(buf, data, data_len);
3190 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3192 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3194 HWRM_CHECK_RESULT();
3202 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3204 uint32_t *count = cbdata;
3206 *count = *count + 1;
3209 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3210 struct bnxt_vnic_info *vnic __rte_unused)
3215 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3219 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3220 &count, bnxt_vnic_count_hwrm_stub);
3225 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3228 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3229 struct hwrm_func_vf_vnic_ids_query_output *resp =
3230 bp->hwrm_cmd_resp_addr;
3233 /* First query all VNIC ids */
3234 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3236 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3237 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3238 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3240 if (req.vnic_id_tbl_addr == 0) {
3243 "unable to map VNIC ID table address to physical memory\n");
3246 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3249 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3251 } else if (resp->error_code) {
3252 rc = rte_le_to_cpu_16(resp->error_code);
3254 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
3257 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3265 * This function queries the VNIC IDs for a specified VF. It then calls
3266 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3267 * Then it calls the hwrm_cb function to program this new vnic configuration.
3269 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3270 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3271 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3273 struct bnxt_vnic_info vnic;
3275 int i, num_vnic_ids;
3280 /* First query all VNIC ids */
3281 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3282 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3283 RTE_CACHE_LINE_SIZE);
3284 if (vnic_ids == NULL) {
3288 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3289 rte_mem_lock_page(((char *)vnic_ids) + sz);
3291 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3293 if (num_vnic_ids < 0)
3294 return num_vnic_ids;
3296 /* Retrieve VNIC, update bd_stall then update */
3298 for (i = 0; i < num_vnic_ids; i++) {
3299 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3300 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3301 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3304 if (vnic.mru <= 4) /* Indicates unallocated */
3307 vnic_cb(&vnic, cbdata);
3309 rc = hwrm_cb(bp, &vnic);
3319 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3322 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3323 struct hwrm_func_cfg_input req = {0};
3326 HWRM_PREP(req, FUNC_CFG);
3328 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3329 req.enables |= rte_cpu_to_le_32(
3330 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3331 req.vlan_antispoof_mode = on ?
3332 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3333 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3334 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3336 HWRM_CHECK_RESULT();
3342 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3344 struct bnxt_vnic_info vnic;
3347 int num_vnic_ids, i;
3351 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3352 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3353 RTE_CACHE_LINE_SIZE);
3354 if (vnic_ids == NULL) {
3359 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3360 rte_mem_lock_page(((char *)vnic_ids) + sz);
3362 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3368 * Loop through to find the default VNIC ID.
3369 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3370 * by sending the hwrm_func_qcfg command to the firmware.
3372 for (i = 0; i < num_vnic_ids; i++) {
3373 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3374 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3375 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3376 bp->pf.first_vf_id + vf);
3379 if (vnic.func_default) {
3381 return vnic.fw_vnic_id;
3384 /* Could not find a default VNIC. */
3385 RTE_LOG(ERR, PMD, "No default VNIC\n");
3391 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3393 struct bnxt_filter_info *filter)
3396 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3397 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3398 uint32_t enables = 0;
3400 if (filter->fw_em_filter_id != UINT64_MAX)
3401 bnxt_hwrm_clear_em_filter(bp, filter);
3403 HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3405 req.flags = rte_cpu_to_le_32(filter->flags);
3407 enables = filter->enables |
3408 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3409 req.dst_id = rte_cpu_to_le_16(dst_id);
3411 if (filter->ip_addr_type) {
3412 req.ip_addr_type = filter->ip_addr_type;
3413 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3416 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3417 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3419 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3420 memcpy(req.src_macaddr, filter->src_macaddr,
3423 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3424 memcpy(req.dst_macaddr, filter->dst_macaddr,
3427 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3428 req.ovlan_vid = filter->l2_ovlan;
3430 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3431 req.ivlan_vid = filter->l2_ivlan;
3433 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3434 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3436 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3437 req.ip_protocol = filter->ip_protocol;
3439 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3440 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3442 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3443 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3445 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3446 req.src_port = rte_cpu_to_be_16(filter->src_port);
3448 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3449 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3451 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3452 req.mirror_vnic_id = filter->mirror_vnic_id;
3454 req.enables = rte_cpu_to_le_32(enables);
3456 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3458 HWRM_CHECK_RESULT();
3460 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3466 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3469 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3470 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3472 if (filter->fw_em_filter_id == UINT64_MAX)
3475 RTE_LOG(ERR, PMD, "Clear EM filter\n");
3476 HWRM_PREP(req, CFA_EM_FLOW_FREE);
3478 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3480 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3482 HWRM_CHECK_RESULT();
3485 filter->fw_em_filter_id = -1;
3486 filter->fw_l2_filter_id = -1;
3491 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3493 struct bnxt_filter_info *filter)
3496 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3497 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3498 bp->hwrm_cmd_resp_addr;
3499 uint32_t enables = 0;
3501 if (filter->fw_ntuple_filter_id != UINT64_MAX)
3502 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3504 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3506 req.flags = rte_cpu_to_le_32(filter->flags);
3508 enables = filter->enables |
3509 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3510 req.dst_id = rte_cpu_to_le_16(dst_id);
3513 if (filter->ip_addr_type) {
3514 req.ip_addr_type = filter->ip_addr_type;
3516 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3519 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3520 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3522 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3523 memcpy(req.src_macaddr, filter->src_macaddr,
3526 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3527 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3530 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3531 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3533 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3534 req.ip_protocol = filter->ip_protocol;
3536 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3537 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3539 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3540 req.src_ipaddr_mask[0] =
3541 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3543 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3544 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3546 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3547 req.dst_ipaddr_mask[0] =
3548 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3550 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3551 req.src_port = rte_cpu_to_le_16(filter->src_port);
3553 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3554 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3556 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3557 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3559 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3560 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3562 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3563 req.mirror_vnic_id = filter->mirror_vnic_id;
3565 req.enables = rte_cpu_to_le_32(enables);
3567 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3569 HWRM_CHECK_RESULT();
3571 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3577 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3578 struct bnxt_filter_info *filter)
3581 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3582 struct hwrm_cfa_ntuple_filter_free_output *resp =
3583 bp->hwrm_cmd_resp_addr;
3585 if (filter->fw_ntuple_filter_id == UINT64_MAX)
3588 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3590 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3592 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3594 HWRM_CHECK_RESULT();
3597 filter->fw_ntuple_filter_id = -1;