4 * Copyright(c) Broadcom Limited.
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8 * modification, are permitted provided that the following conditions
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15 * the documentation and/or other materials provided with the
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_byteorder.h>
35 #include <rte_common.h>
36 #include <rte_cycles.h>
37 #include <rte_malloc.h>
38 #include <rte_memzone.h>
39 #include <rte_version.h>
43 #include "bnxt_filter.h"
44 #include "bnxt_hwrm.h"
47 #include "bnxt_ring.h"
50 #include "bnxt_vnic.h"
51 #include "hsi_struct_def_dpdk.h"
53 #define HWRM_CMD_TIMEOUT 2000
56 * HWRM Functions (sent to HWRM)
57 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
58 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
59 * command was failed by the ChiMP.
62 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
66 struct input *req = msg;
67 struct output *resp = bp->hwrm_cmd_resp_addr;
72 /* Write request msg to hwrm channel */
73 for (i = 0; i < msg_len; i += 4) {
74 bar = (uint8_t *)bp->bar0 + i;
75 *(volatile uint32_t *)bar = *data;
79 /* Zero the rest of the request space */
80 for (; i < bp->max_req_len; i += 4) {
81 bar = (uint8_t *)bp->bar0 + i;
82 *(volatile uint32_t *)bar = 0;
85 /* Ring channel doorbell */
86 bar = (uint8_t *)bp->bar0 + 0x100;
87 *(volatile uint32_t *)bar = 1;
89 /* Poll for the valid bit */
90 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
91 /* Sanity check on the resp->resp_len */
93 if (resp->resp_len && resp->resp_len <=
95 /* Last byte of resp contains the valid key */
96 valid = (uint8_t *)resp + resp->resp_len - 1;
97 if (*valid == HWRM_RESP_VALID_KEY)
103 if (i >= HWRM_CMD_TIMEOUT) {
104 RTE_LOG(ERR, PMD, "Error sending msg %x\n",
114 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
118 rte_spinlock_lock(&bp->hwrm_lock);
119 rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
120 rte_spinlock_unlock(&bp->hwrm_lock);
124 #define HWRM_PREP(req, type, cr, resp) \
125 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
126 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
127 req.cmpl_ring = rte_cpu_to_le_16(cr); \
128 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
129 req.target_id = rte_cpu_to_le_16(0xffff); \
130 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
132 #define HWRM_CHECK_RESULT \
135 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
139 if (resp->error_code) { \
140 rc = rte_le_to_cpu_16(resp->error_code); \
141 RTE_LOG(ERR, PMD, "%s error %d\n", __func__, rc); \
146 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
149 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
150 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
152 HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
153 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
156 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
163 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
166 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
167 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
170 HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
171 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
173 /* FIXME add multicast flag, when multicast adding options is supported
176 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
177 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
178 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
179 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
180 req.mask = rte_cpu_to_le_32(mask);
182 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
189 int bnxt_hwrm_clear_filter(struct bnxt *bp,
190 struct bnxt_filter_info *filter)
193 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
194 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
196 if (filter->fw_l2_filter_id == UINT64_MAX)
199 HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
201 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
203 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
207 filter->fw_l2_filter_id = -1;
212 int bnxt_hwrm_set_filter(struct bnxt *bp,
213 struct bnxt_vnic_info *vnic,
214 struct bnxt_filter_info *filter)
217 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
218 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
219 uint32_t enables = 0;
221 if (filter->fw_l2_filter_id != UINT64_MAX)
222 bnxt_hwrm_clear_filter(bp, filter);
224 HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
226 req.flags = rte_cpu_to_le_32(filter->flags);
228 enables = filter->enables |
229 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
230 req.dst_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
233 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
234 memcpy(req.l2_addr, filter->l2_addr,
237 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
238 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
241 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
242 req.l2_ovlan = filter->l2_ovlan;
244 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
245 req.l2_ovlan_mask = filter->l2_ovlan_mask;
247 req.enables = rte_cpu_to_le_32(enables);
249 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
253 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
258 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, void *fwd_cmd)
261 struct hwrm_exec_fwd_resp_input req = {.req_type = 0 };
262 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
264 HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
266 memcpy(req.encap_request, fwd_cmd,
267 sizeof(req.encap_request));
269 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
276 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
279 struct hwrm_func_qcaps_input req = {.req_type = 0 };
280 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
282 HWRM_PREP(req, FUNC_QCAPS, -1, resp);
284 req.fid = rte_cpu_to_le_16(0xffff);
286 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
290 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
292 struct bnxt_pf_info *pf = &bp->pf;
294 pf->fw_fid = rte_le_to_cpu_32(resp->fid);
295 pf->port_id = resp->port_id;
296 memcpy(pf->mac_addr, resp->mac_address, ETHER_ADDR_LEN);
297 pf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
298 pf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
299 pf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
300 pf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
301 pf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
302 pf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
303 pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
304 pf->max_vfs = rte_le_to_cpu_16(resp->max_vfs);
306 struct bnxt_vf_info *vf = &bp->vf;
308 vf->fw_fid = rte_le_to_cpu_32(resp->fid);
309 memcpy(vf->mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
310 vf->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
311 vf->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
312 vf->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
313 vf->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
314 vf->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
315 vf->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
321 int bnxt_hwrm_func_reset(struct bnxt *bp)
324 struct hwrm_func_reset_input req = {.req_type = 0 };
325 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
327 HWRM_PREP(req, FUNC_RESET, -1, resp);
329 req.enables = rte_cpu_to_le_32(0);
331 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
338 int bnxt_hwrm_func_driver_register(struct bnxt *bp, uint32_t flags,
339 uint32_t *vf_req_fwd)
342 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
343 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
345 if (bp->flags & BNXT_FLAG_REGISTERED)
348 HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
350 req.enables = HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
351 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD;
352 req.ver_maj = RTE_VER_YEAR;
353 req.ver_min = RTE_VER_MONTH;
354 req.ver_upd = RTE_VER_MINOR;
356 memcpy(req.vf_req_fwd, vf_req_fwd, sizeof(req.vf_req_fwd));
358 req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1); /* TODO: Use MACRO */
360 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
364 bp->flags |= BNXT_FLAG_REGISTERED;
369 int bnxt_hwrm_ver_get(struct bnxt *bp)
372 struct hwrm_ver_get_input req = {.req_type = 0 };
373 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
376 uint16_t max_resp_len;
377 char type[RTE_MEMZONE_NAMESIZE];
379 HWRM_PREP(req, VER_GET, -1, resp);
381 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
382 req.hwrm_intf_min = HWRM_VERSION_MINOR;
383 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
386 * Hold the lock since we may be adjusting the response pointers.
388 rte_spinlock_lock(&bp->hwrm_lock);
389 rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
393 RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
394 resp->hwrm_intf_maj, resp->hwrm_intf_min,
396 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
397 RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
398 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
400 my_version = HWRM_VERSION_MAJOR << 16;
401 my_version |= HWRM_VERSION_MINOR << 8;
402 my_version |= HWRM_VERSION_UPDATE;
404 fw_version = resp->hwrm_intf_maj << 16;
405 fw_version |= resp->hwrm_intf_min << 8;
406 fw_version |= resp->hwrm_intf_upd;
408 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
409 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
414 if (my_version != fw_version) {
415 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
416 if (my_version < fw_version) {
418 "Firmware API version is newer than driver.\n");
420 "The driver may be missing features.\n");
423 "Firmware API version is older than driver.\n");
425 "Not all driver features may be functional.\n");
429 if (bp->max_req_len > resp->max_req_win_len) {
430 RTE_LOG(ERR, PMD, "Unsupported request length\n");
433 bp->max_req_len = resp->max_req_win_len;
434 max_resp_len = resp->max_resp_len;
435 if (bp->max_resp_len != max_resp_len) {
436 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
437 bp->pdev->addr.domain, bp->pdev->addr.bus,
438 bp->pdev->addr.devid, bp->pdev->addr.function);
440 rte_free(bp->hwrm_cmd_resp_addr);
442 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
443 if (bp->hwrm_cmd_resp_addr == NULL) {
447 bp->hwrm_cmd_resp_dma_addr =
448 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
449 bp->max_resp_len = max_resp_len;
453 rte_spinlock_unlock(&bp->hwrm_lock);
457 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
460 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
461 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
463 if (!(bp->flags & BNXT_FLAG_REGISTERED))
466 HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
469 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
473 bp->flags &= ~BNXT_FLAG_REGISTERED;
478 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
481 struct hwrm_port_phy_cfg_input req = {0};
482 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
483 uint32_t enables = 0;
485 HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
488 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
489 if (bp->link_info.auto_mode && conf->link_speed) {
490 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
491 RTE_LOG(DEBUG, PMD, "Disabling AutoNeg\n");
494 req.flags = rte_cpu_to_le_32(conf->phy_flags);
495 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
496 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
498 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
499 * any auto mode, even "none".
501 if (!conf->link_speed) {
502 /* No speeds specified. Enable AutoNeg - all speeds */
504 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
506 /* AutoNeg - Advertise speeds specified. */
507 if (conf->auto_link_speed_mask &&
508 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
510 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
511 req.auto_link_speed_mask =
512 conf->auto_link_speed_mask;
514 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
517 req.auto_duplex = conf->duplex;
518 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
519 req.auto_pause = conf->auto_pause;
520 req.force_pause = conf->force_pause;
521 /* Set force_pause if there is no auto or if there is a force */
522 if (req.auto_pause && !req.force_pause)
523 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
525 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
527 req.enables = rte_cpu_to_le_32(enables);
530 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN);
531 RTE_LOG(INFO, PMD, "Force Link Down\n");
534 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
541 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
542 struct bnxt_link_info *link_info)
545 struct hwrm_port_phy_qcfg_input req = {0};
546 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
548 HWRM_PREP(req, PORT_PHY_QCFG, -1, resp);
550 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
554 link_info->phy_link_status = resp->link;
556 (link_info->phy_link_status ==
557 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
558 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
559 link_info->duplex = resp->duplex;
560 link_info->pause = resp->pause;
561 link_info->auto_pause = resp->auto_pause;
562 link_info->force_pause = resp->force_pause;
563 link_info->auto_mode = resp->auto_mode;
564 link_info->phy_type = resp->phy_type;
565 link_info->media_type = resp->media_type;
567 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
568 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
569 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
570 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
571 link_info->phy_ver[0] = resp->phy_maj;
572 link_info->phy_ver[1] = resp->phy_min;
573 link_info->phy_ver[2] = resp->phy_bld;
578 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
581 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
582 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
584 HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
586 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
590 #define GET_QUEUE_INFO(x) \
591 bp->cos_queue[x].id = resp->queue_id##x; \
592 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
606 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
607 struct bnxt_ring *ring,
608 uint32_t ring_type, uint32_t map_index,
609 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
612 struct hwrm_ring_alloc_input req = {.req_type = 0 };
613 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
615 HWRM_PREP(req, RING_ALLOC, -1, resp);
617 req.enables = rte_cpu_to_le_32(0);
619 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
620 req.fbo = rte_cpu_to_le_32(0);
621 /* Association of ring index with doorbell index */
622 req.logical_id = rte_cpu_to_le_16(map_index);
625 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
626 req.queue_id = bp->cos_queue[0].id;
628 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
629 req.ring_type = ring_type;
630 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
631 req.length = rte_cpu_to_le_32(ring->ring_size);
632 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
633 if (stats_ctx_id != INVALID_STATS_CTX_ID)
635 rte_cpu_to_le_32(rte_le_to_cpu_32(req.enables) |
636 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID);
638 case HWRM_RING_ALLOC_INPUT_RING_TYPE_CMPL:
639 req.ring_type = ring_type;
641 * TODO: Some HWRM versions crash with
642 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
644 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
645 req.length = rte_cpu_to_le_32(ring->ring_size);
648 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
653 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
655 if (rc || resp->error_code) {
656 if (rc == 0 && resp->error_code)
657 rc = rte_le_to_cpu_16(resp->error_code);
659 case HWRM_RING_FREE_INPUT_RING_TYPE_CMPL:
661 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
663 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
665 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
667 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
669 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
672 RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
677 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
681 int bnxt_hwrm_ring_free(struct bnxt *bp,
682 struct bnxt_ring *ring, uint32_t ring_type)
685 struct hwrm_ring_free_input req = {.req_type = 0 };
686 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
688 HWRM_PREP(req, RING_FREE, -1, resp);
690 req.ring_type = ring_type;
691 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
693 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
695 if (rc || resp->error_code) {
696 if (rc == 0 && resp->error_code)
697 rc = rte_le_to_cpu_16(resp->error_code);
700 case HWRM_RING_FREE_INPUT_RING_TYPE_CMPL:
701 RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
704 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
705 RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
708 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
709 RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
713 RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
720 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
723 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
724 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
726 HWRM_PREP(req, RING_GRP_ALLOC, -1, resp);
728 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
729 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
730 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
731 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
733 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
737 bp->grp_info[idx].fw_grp_id =
738 rte_le_to_cpu_16(resp->ring_group_id);
743 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
746 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
747 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
749 HWRM_PREP(req, RING_GRP_FREE, -1, resp);
751 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
753 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
757 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
761 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
764 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
765 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
767 HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
769 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
772 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
773 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
775 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
782 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp,
783 struct bnxt_cp_ring_info *cpr, unsigned int idx)
786 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
787 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
789 HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
791 req.update_period_ms = rte_cpu_to_le_32(1000);
793 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
795 rte_cpu_to_le_64(cpr->hw_stats_map);
797 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
801 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
802 //Tx rings don't need grp_info entry. It is a Rx only attribute.
804 bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
809 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp,
810 struct bnxt_cp_ring_info *cpr, unsigned int idx)
813 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
814 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
816 HWRM_PREP(req, STAT_CTX_FREE, -1, resp);
818 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
819 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++);
821 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
825 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
826 //Tx rings don't have a grp_info entry. It is a Rx only attribute.
828 bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
833 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
836 struct hwrm_vnic_alloc_input req = { 0 };
837 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
839 /* map ring groups to this vnic */
840 for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++) {
841 if (bp->grp_info[i].fw_grp_id == (uint16_t)HWRM_NA_SIGNATURE) {
843 "Not enough ring groups avail:%x req:%x\n", j,
844 (vnic->end_grp_id - vnic->start_grp_id) + 1);
847 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
850 vnic->fw_rss_cos_lb_ctx = (uint16_t)HWRM_NA_SIGNATURE;
851 vnic->ctx_is_rss_cos_lb = HW_CONTEXT_NONE;
853 HWRM_PREP(req, VNIC_ALLOC, -1, resp);
855 if (vnic->func_default)
857 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
858 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
862 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
863 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
867 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
870 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
871 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
873 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
874 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
878 HWRM_PREP(req, VNIC_CFG, -1, resp);
880 /* Only RSS support for now TBD: COS & LB */
882 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
883 HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE |
884 HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
885 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
887 rte_cpu_to_le_16(bp->grp_info[vnic->start_grp_id].fw_grp_id);
888 req.rss_rule = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
889 req.cos_rule = rte_cpu_to_le_16(0xffff);
890 req.lb_rule = rte_cpu_to_le_16(0xffff);
891 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
892 ETHER_CRC_LEN + VLAN_TAG_SIZE);
893 if (vnic->func_default)
895 if (vnic->vlan_strip)
897 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
899 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
906 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
909 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
910 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
911 bp->hwrm_cmd_resp_addr;
913 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
915 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
919 vnic->fw_rss_cos_lb_ctx = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
920 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->fw_rss_cos_lb_ctx);
925 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
928 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
929 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
930 bp->hwrm_cmd_resp_addr;
932 if (vnic->fw_rss_cos_lb_ctx == 0xffff) {
934 "VNIC RSS Rule %x\n", vnic->fw_rss_cos_lb_ctx);
938 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
940 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
942 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
946 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
951 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
954 struct hwrm_vnic_free_input req = {.req_type = 0 };
955 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
957 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
958 RTE_LOG(DEBUG, PMD, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
962 HWRM_PREP(req, VNIC_FREE, -1, resp);
964 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
966 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
970 vnic->fw_vnic_id = INVALID_HW_RING_ID;
974 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
975 struct bnxt_vnic_info *vnic)
978 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
979 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
981 HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
983 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
985 req.ring_grp_tbl_addr =
986 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
987 req.hash_key_tbl_addr =
988 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
989 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_rss_cos_lb_ctx);
991 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
999 * HWRM utility functions
1002 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1007 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1008 struct bnxt_tx_queue *txq;
1009 struct bnxt_rx_queue *rxq;
1010 struct bnxt_cp_ring_info *cpr;
1012 if (i >= bp->rx_cp_nr_rings) {
1013 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1016 rxq = bp->rx_queues[i];
1020 rc = bnxt_hwrm_stat_clear(bp, cpr);
1027 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1031 struct bnxt_cp_ring_info *cpr;
1033 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1034 unsigned int idx = i + 1;
1036 if (i >= bp->rx_cp_nr_rings) {
1037 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1038 //Tx rings don't have a grp_info entry.
1041 cpr = bp->rx_queues[i]->cp_ring;
1043 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1044 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, idx);
1052 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1057 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1058 struct bnxt_tx_queue *txq;
1059 struct bnxt_rx_queue *rxq;
1060 struct bnxt_cp_ring_info *cpr;
1061 unsigned int idx = i + 1;
1063 if (i >= bp->rx_cp_nr_rings) {
1064 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1066 //Tx rings don't need grp_info entry.
1069 rxq = bp->rx_queues[i];
1073 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, idx);
1081 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1086 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1087 unsigned int idx = i + 1;
1089 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID) {
1091 "Attempt to free invalid ring group %d\n",
1096 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1104 static void bnxt_free_cp_ring(struct bnxt *bp,
1105 struct bnxt_cp_ring_info *cpr)
1107 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1109 bnxt_hwrm_ring_free(bp, cp_ring,
1110 HWRM_RING_FREE_INPUT_RING_TYPE_CMPL);
1111 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1112 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1113 sizeof(*cpr->cp_desc_ring));
1114 cpr->cp_raw_cons = 0;
1117 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1122 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1123 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1124 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1125 struct bnxt_ring *ring = txr->tx_ring_struct;
1126 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1128 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1129 bnxt_hwrm_ring_free(bp, ring,
1130 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1131 ring->fw_ring_id = INVALID_HW_RING_ID;
1132 memset(txr->tx_desc_ring, 0,
1133 txr->tx_ring_struct->ring_size *
1134 sizeof(*txr->tx_desc_ring));
1135 memset(txr->tx_buf_ring, 0,
1136 txr->tx_ring_struct->ring_size *
1137 sizeof(*txr->tx_buf_ring));
1141 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1142 bnxt_free_cp_ring(bp, cpr);
1145 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1146 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1147 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1148 struct bnxt_ring *ring = rxr->rx_ring_struct;
1149 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1150 unsigned int idx = i + 1;
1152 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1153 bnxt_hwrm_ring_free(bp, ring,
1154 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1155 ring->fw_ring_id = INVALID_HW_RING_ID;
1156 bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1157 memset(rxr->rx_desc_ring, 0,
1158 rxr->rx_ring_struct->ring_size *
1159 sizeof(*rxr->rx_desc_ring));
1160 memset(rxr->rx_buf_ring, 0,
1161 rxr->rx_ring_struct->ring_size *
1162 sizeof(*rxr->rx_buf_ring));
1165 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1166 bnxt_free_cp_ring(bp, cpr);
1167 bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1170 /* Default completion ring */
1172 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1174 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
1175 bnxt_free_cp_ring(bp, cpr);
1176 bp->grp_info[0].cp_fw_ring_id = INVALID_HW_RING_ID;
1182 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1187 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1188 unsigned int idx = i + 1;
1190 if (bp->grp_info[idx].cp_fw_ring_id == INVALID_HW_RING_ID ||
1191 bp->grp_info[idx].rx_fw_ring_id == INVALID_HW_RING_ID)
1194 rc = bnxt_hwrm_ring_grp_alloc(bp, idx);
1202 void bnxt_free_hwrm_resources(struct bnxt *bp)
1204 /* Release memzone */
1205 rte_free(bp->hwrm_cmd_resp_addr);
1206 bp->hwrm_cmd_resp_addr = NULL;
1207 bp->hwrm_cmd_resp_dma_addr = 0;
1210 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1212 struct rte_pci_device *pdev = bp->pdev;
1213 char type[RTE_MEMZONE_NAMESIZE];
1215 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1216 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1217 bp->max_req_len = HWRM_MAX_REQ_LEN;
1218 bp->max_resp_len = HWRM_MAX_RESP_LEN;
1219 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1220 if (bp->hwrm_cmd_resp_addr == NULL)
1222 bp->hwrm_cmd_resp_dma_addr =
1223 rte_malloc_virt2phy(bp->hwrm_cmd_resp_addr);
1224 rte_spinlock_init(&bp->hwrm_lock);
1229 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1231 struct bnxt_filter_info *filter;
1234 STAILQ_FOREACH(filter, &vnic->filter, next) {
1235 rc = bnxt_hwrm_clear_filter(bp, filter);
1242 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1244 struct bnxt_filter_info *filter;
1247 STAILQ_FOREACH(filter, &vnic->filter, next) {
1248 rc = bnxt_hwrm_set_filter(bp, vnic, filter);
1255 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1257 struct bnxt_vnic_info *vnic;
1260 if (bp->vnic_info == NULL)
1263 vnic = &bp->vnic_info[0];
1264 bnxt_hwrm_cfa_l2_clear_rx_mask(bp, vnic);
1266 /* VNIC resources */
1267 for (i = 0; i < bp->nr_vnics; i++) {
1268 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1270 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1272 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1273 bnxt_hwrm_vnic_free(bp, vnic);
1275 /* Ring resources */
1276 bnxt_free_all_hwrm_rings(bp);
1277 bnxt_free_all_hwrm_ring_grps(bp);
1278 bnxt_free_all_hwrm_stat_ctxs(bp);
1281 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1283 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1285 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1286 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1288 switch (conf_link_speed) {
1289 case ETH_LINK_SPEED_10M_HD:
1290 case ETH_LINK_SPEED_100M_HD:
1291 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1293 return hw_link_duplex;
1296 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
1298 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
1301 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1303 uint16_t eth_link_speed = 0;
1305 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1306 return ETH_LINK_SPEED_AUTONEG;
1308 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1309 case ETH_LINK_SPEED_100M:
1310 case ETH_LINK_SPEED_100M_HD:
1312 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1314 case ETH_LINK_SPEED_1G:
1316 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1318 case ETH_LINK_SPEED_2_5G:
1320 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1322 case ETH_LINK_SPEED_10G:
1324 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1326 case ETH_LINK_SPEED_20G:
1328 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1330 case ETH_LINK_SPEED_25G:
1332 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1334 case ETH_LINK_SPEED_40G:
1336 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1338 case ETH_LINK_SPEED_50G:
1340 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1344 "Unsupported link speed %d; default to AUTO\n",
1348 return eth_link_speed;
1351 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1352 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1353 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1354 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1356 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
1360 if (link_speed == ETH_LINK_SPEED_AUTONEG)
1363 if (link_speed & ETH_LINK_SPEED_FIXED) {
1364 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1366 if (one_speed & (one_speed - 1)) {
1368 "Invalid advertised speeds (%u) for port %u\n",
1369 link_speed, port_id);
1372 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1374 "Unsupported advertised speed (%u) for port %u\n",
1375 link_speed, port_id);
1379 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1381 "Unsupported advertised speeds (%u) for port %u\n",
1382 link_speed, port_id);
1390 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
1394 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
1395 if (bp->link_info.support_speeds)
1396 return bp->link_info.support_speeds;
1397 link_speed = BNXT_SUPPORTED_SPEEDS;
1400 if (link_speed & ETH_LINK_SPEED_100M)
1401 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1402 if (link_speed & ETH_LINK_SPEED_100M_HD)
1403 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1404 if (link_speed & ETH_LINK_SPEED_1G)
1405 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1406 if (link_speed & ETH_LINK_SPEED_2_5G)
1407 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1408 if (link_speed & ETH_LINK_SPEED_10G)
1409 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1410 if (link_speed & ETH_LINK_SPEED_20G)
1411 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1412 if (link_speed & ETH_LINK_SPEED_25G)
1413 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1414 if (link_speed & ETH_LINK_SPEED_40G)
1415 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1416 if (link_speed & ETH_LINK_SPEED_50G)
1417 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1421 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
1423 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
1425 switch (hw_link_speed) {
1426 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
1427 eth_link_speed = ETH_SPEED_NUM_100M;
1429 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
1430 eth_link_speed = ETH_SPEED_NUM_1G;
1432 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
1433 eth_link_speed = ETH_SPEED_NUM_2_5G;
1435 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
1436 eth_link_speed = ETH_SPEED_NUM_10G;
1438 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
1439 eth_link_speed = ETH_SPEED_NUM_20G;
1441 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
1442 eth_link_speed = ETH_SPEED_NUM_25G;
1444 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
1445 eth_link_speed = ETH_SPEED_NUM_40G;
1447 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
1448 eth_link_speed = ETH_SPEED_NUM_50G;
1450 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
1452 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
1456 return eth_link_speed;
1459 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
1461 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1463 switch (hw_link_duplex) {
1464 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
1465 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
1466 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1468 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
1469 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
1472 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
1476 return eth_link_duplex;
1479 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
1482 struct bnxt_link_info *link_info = &bp->link_info;
1484 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
1487 "Get link config failed with rc %d\n", rc);
1490 if (link_info->link_speed)
1492 bnxt_parse_hw_link_speed(link_info->link_speed);
1494 link->link_speed = ETH_SPEED_NUM_NONE;
1495 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
1496 link->link_status = link_info->link_up;
1497 link->link_autoneg = link_info->auto_mode ==
1498 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
1499 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
1504 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
1507 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1508 struct bnxt_link_info link_req;
1509 uint16_t speed, autoneg;
1511 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
1514 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
1515 bp->eth_dev->data->port_id);
1519 memset(&link_req, 0, sizeof(link_req));
1520 link_req.link_up = link_up;
1524 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
1525 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
1526 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
1527 /* Autoneg can be done only when the FW allows */
1528 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
1529 bp->link_info.force_link_speed)) {
1530 link_req.phy_flags |=
1531 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
1532 link_req.auto_link_speed_mask =
1533 bnxt_parse_eth_link_speed_mask(bp,
1534 dev_conf->link_speeds);
1536 if (bp->link_info.phy_type ==
1537 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
1538 bp->link_info.phy_type ==
1539 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
1540 bp->link_info.media_type ==
1541 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
1542 RTE_LOG(ERR, PMD, "10GBase-T devices must autoneg\n");
1546 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
1547 /* If user wants a particular speed try that first. */
1549 link_req.link_speed = speed;
1550 else if (bp->link_info.force_link_speed)
1551 link_req.link_speed = bp->link_info.force_link_speed;
1553 link_req.link_speed = bp->link_info.auto_link_speed;
1555 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
1556 link_req.auto_pause = bp->link_info.auto_pause;
1557 link_req.force_pause = bp->link_info.force_pause;
1560 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
1563 "Set link config failed with rc %d\n", rc);
1571 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
1573 struct hwrm_func_qcfg_input req = {0};
1574 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1577 HWRM_PREP(req, FUNC_QCFG, -1, resp);
1578 req.fid = rte_cpu_to_le_16(0xffff);
1580 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1585 struct bnxt_vf_info *vf = &bp->vf;
1587 /* Hard Coded.. 0xfff VLAN ID mask */
1588 vf->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
1591 switch (resp->port_partition_type) {
1592 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
1593 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
1594 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
1595 bp->port_partition_type = resp->port_partition_type;
1598 bp->port_partition_type = 0;