4 * Copyright(c) 2014-2016 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <netinet/in.h>
36 #include <rte_interrupts.h>
38 #include <rte_debug.h>
40 #include <rte_atomic.h>
41 #include <rte_branch_prediction.h>
42 #include <rte_memory.h>
43 #include <rte_memzone.h>
44 #include <rte_tailq.h>
46 #include <rte_alarm.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_atomic.h>
50 #include <rte_malloc.h>
51 #include <rte_random.h>
53 #include <rte_byteorder.h>
57 #include "t4_regs_values.h"
58 #include "t4fw_interface.h"
60 static void init_link_config(struct link_config *lc, unsigned int caps);
63 * t4_read_mtu_tbl - returns the values in the HW path MTU table
65 * @mtus: where to store the MTU values
66 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
68 * Reads the HW path MTU table.
70 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
75 for (i = 0; i < NMTUS; ++i) {
76 t4_write_reg(adap, A_TP_MTU_TABLE,
77 V_MTUINDEX(0xff) | V_MTUVALUE(i));
78 v = t4_read_reg(adap, A_TP_MTU_TABLE);
79 mtus[i] = G_MTUVALUE(v);
81 mtu_log[i] = G_MTUWIDTH(v);
86 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
88 * @addr: the indirect TP register address
89 * @mask: specifies the field within the register to modify
90 * @val: new value for the field
92 * Sets a field of an indirect TP register to the given value.
94 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
95 unsigned int mask, unsigned int val)
97 t4_write_reg(adap, A_TP_PIO_ADDR, addr);
98 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
99 t4_write_reg(adap, A_TP_PIO_DATA, val);
102 /* The minimum additive increment value for the congestion control table */
103 #define CC_MIN_INCR 2U
106 * t4_load_mtus - write the MTU and congestion control HW tables
108 * @mtus: the values for the MTU table
109 * @alpha: the values for the congestion control alpha parameter
110 * @beta: the values for the congestion control beta parameter
112 * Write the HW MTU table with the supplied MTUs and the high-speed
113 * congestion control table with the supplied alpha, beta, and MTUs.
114 * We write the two tables together because the additive increments
115 * depend on the MTUs.
117 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
118 const unsigned short *alpha, const unsigned short *beta)
120 static const unsigned int avg_pkts[NCCTRL_WIN] = {
121 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
122 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
123 28672, 40960, 57344, 81920, 114688, 163840, 229376
128 for (i = 0; i < NMTUS; ++i) {
129 unsigned int mtu = mtus[i];
130 unsigned int log2 = cxgbe_fls(mtu);
132 if (!(mtu & ((1 << log2) >> 2))) /* round */
134 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
135 V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
137 for (w = 0; w < NCCTRL_WIN; ++w) {
140 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
143 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
144 (w << 16) | (beta[w] << 13) | inc);
150 * t4_wait_op_done_val - wait until an operation is completed
151 * @adapter: the adapter performing the operation
152 * @reg: the register to check for completion
153 * @mask: a single-bit field within @reg that indicates completion
154 * @polarity: the value of the field when the operation is completed
155 * @attempts: number of check iterations
156 * @delay: delay in usecs between iterations
157 * @valp: where to store the value of the register at completion time
159 * Wait until an operation is completed by checking a bit in a register
160 * up to @attempts times. If @valp is not NULL the value of the register
161 * at the time it indicated completion is stored there. Returns 0 if the
162 * operation completes and -EAGAIN otherwise.
164 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
165 int polarity, int attempts, int delay, u32 *valp)
168 u32 val = t4_read_reg(adapter, reg);
170 if (!!(val & mask) == polarity) {
183 * t4_set_reg_field - set a register field to a value
184 * @adapter: the adapter to program
185 * @addr: the register address
186 * @mask: specifies the portion of the register to modify
187 * @val: the new value for the register field
189 * Sets a register field specified by the supplied mask to the
192 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
195 u32 v = t4_read_reg(adapter, addr) & ~mask;
197 t4_write_reg(adapter, addr, v | val);
198 (void)t4_read_reg(adapter, addr); /* flush */
202 * t4_read_indirect - read indirectly addressed registers
204 * @addr_reg: register holding the indirect address
205 * @data_reg: register holding the value of the indirect register
206 * @vals: where the read register values are stored
207 * @nregs: how many indirect registers to read
208 * @start_idx: index of first indirect register to read
210 * Reads registers that are accessed indirectly through an address/data
213 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
214 unsigned int data_reg, u32 *vals, unsigned int nregs,
215 unsigned int start_idx)
218 t4_write_reg(adap, addr_reg, start_idx);
219 *vals++ = t4_read_reg(adap, data_reg);
225 * t4_write_indirect - write indirectly addressed registers
227 * @addr_reg: register holding the indirect addresses
228 * @data_reg: register holding the value for the indirect registers
229 * @vals: values to write
230 * @nregs: how many indirect registers to write
231 * @start_idx: address of first indirect register to write
233 * Writes a sequential block of registers that are accessed indirectly
234 * through an address/data register pair.
236 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
237 unsigned int data_reg, const u32 *vals,
238 unsigned int nregs, unsigned int start_idx)
241 t4_write_reg(adap, addr_reg, start_idx++);
242 t4_write_reg(adap, data_reg, *vals++);
247 * t4_report_fw_error - report firmware error
250 * The adapter firmware can indicate error conditions to the host.
251 * If the firmware has indicated an error, print out the reason for
252 * the firmware error.
254 static void t4_report_fw_error(struct adapter *adap)
256 static const char * const reason[] = {
257 "Crash", /* PCIE_FW_EVAL_CRASH */
258 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
259 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
260 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
261 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
262 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
263 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
264 "Reserved", /* reserved */
268 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
269 if (pcie_fw & F_PCIE_FW_ERR)
270 pr_err("%s: Firmware reports adapter error: %s\n",
271 __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
275 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
277 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
280 for ( ; nflit; nflit--, mbox_addr += 8)
281 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
285 * Handle a FW assertion reported in a mailbox.
287 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
289 struct fw_debug_cmd asrt;
291 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
292 pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
293 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
294 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
297 #define X_CIM_PF_NOACCESS 0xeeeeeeee
300 * If the Host OS Driver needs locking arround accesses to the mailbox, this
301 * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
303 /* makes single-statement usage a bit cleaner ... */
304 #ifdef T4_OS_NEEDS_MBOX_LOCKING
305 #define T4_OS_MBOX_LOCKING(x) x
307 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
311 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
313 * @mbox: index of the mailbox to use
314 * @cmd: the command to write
315 * @size: command length in bytes
316 * @rpl: where to optionally store the reply
317 * @sleep_ok: if true we may sleep while awaiting command completion
318 * @timeout: time to wait for command to finish before timing out
319 * (negative implies @sleep_ok=false)
321 * Sends the given command to FW through the selected mailbox and waits
322 * for the FW to execute the command. If @rpl is not %NULL it is used to
323 * store the FW's reply to the command. The command and its optional
324 * reply are of the same length. Some FW commands like RESET and
325 * INITIALIZE can take a considerable amount of time to execute.
326 * @sleep_ok determines whether we may sleep while awaiting the response.
327 * If sleeping is allowed we use progressive backoff otherwise we spin.
328 * Note that passing in a negative @timeout is an alternate mechanism
329 * for specifying @sleep_ok=false. This is useful when a higher level
330 * interface allows for specification of @timeout but not @sleep_ok ...
332 * Returns 0 on success or a negative errno on failure. A
333 * failure can happen either because we are not able to execute the
334 * command or FW executes it but signals an error. In the latter case
335 * the return value is the error code indicated by FW (negated).
337 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
338 const void __attribute__((__may_alias__)) *cmd,
339 int size, void *rpl, bool sleep_ok, int timeout)
342 * We delay in small increments at first in an effort to maintain
343 * responsiveness for simple, fast executing commands but then back
344 * off to larger delays to a maximum retry delay.
346 static const int delay[] = {
347 1, 1, 3, 5, 10, 10, 20, 50, 100
353 unsigned int delay_idx;
354 __be64 *temp = (__be64 *)malloc(size * sizeof(char));
356 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
357 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
359 struct mbox_entry entry;
365 if ((size & 15) || size > MBOX_LEN) {
371 memcpy(p, (const __be64 *)cmd, size);
374 * If we have a negative timeout, that implies that we can't sleep.
381 #ifdef T4_OS_NEEDS_MBOX_LOCKING
383 * Queue ourselves onto the mailbox access list. When our entry is at
384 * the front of the list, we have rights to access the mailbox. So we
385 * wait [for a while] till we're at the front [or bail out with an
388 t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
393 for (i = 0; ; i += ms) {
395 * If we've waited too long, return a busy indication. This
396 * really ought to be based on our initial position in the
397 * mailbox access list but this is a start. We very rarely
398 * contend on access to the mailbox ... Also check for a
399 * firmware error which we'll report as a device error.
401 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
402 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
403 t4_os_atomic_list_del(&entry, &adap->mbox_list,
405 t4_report_fw_error(adap);
407 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
411 * If we're at the head, break out and start the mailbox
414 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
418 * Delay for a bit before checking again ...
421 ms = delay[delay_idx]; /* last element may repeat */
422 if (delay_idx < ARRAY_SIZE(delay) - 1)
429 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
432 * Attempt to gain access to the mailbox.
434 for (i = 0; i < 4; i++) {
435 ctl = t4_read_reg(adap, ctl_reg);
437 if (v != X_MBOWNER_NONE)
442 * If we were unable to gain access, dequeue ourselves from the
443 * mailbox atomic access list and report the error to our caller.
445 if (v != X_MBOWNER_PL) {
446 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
449 t4_report_fw_error(adap);
451 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
455 * If we gain ownership of the mailbox and there's a "valid" message
456 * in it, this is likely an asynchronous error message from the
457 * firmware. So we'll report that and then proceed on with attempting
458 * to issue our own command ... which may well fail if the error
459 * presaged the firmware crashing ...
461 if (ctl & F_MBMSGVALID) {
462 dev_err(adap, "found VALID command in mbox %u: "
463 "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
464 (unsigned long long)t4_read_reg64(adap, data_reg),
465 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
466 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
467 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
468 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
469 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
470 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
471 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
475 * Copy in the new mailbox command and send it on its way ...
477 for (i = 0; i < size; i += 8, p++)
478 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
480 CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
481 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
482 (unsigned long long)t4_read_reg64(adap, data_reg),
483 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
484 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
485 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
486 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
487 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
488 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
489 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
491 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
492 t4_read_reg(adap, ctl_reg); /* flush write */
498 * Loop waiting for the reply; bail out if we time out or the firmware
501 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
502 for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
504 ms = delay[delay_idx]; /* last element may repeat */
505 if (delay_idx < ARRAY_SIZE(delay) - 1)
512 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
513 v = t4_read_reg(adap, ctl_reg);
514 if (v == X_CIM_PF_NOACCESS)
516 if (G_MBOWNER(v) == X_MBOWNER_PL) {
517 if (!(v & F_MBMSGVALID)) {
518 t4_write_reg(adap, ctl_reg,
519 V_MBOWNER(X_MBOWNER_NONE));
523 CXGBE_DEBUG_MBOX(adap,
524 "%s: mbox %u: %016llx %016llx %016llx %016llx "
525 "%016llx %016llx %016llx %016llx\n", __func__, (mbox),
526 (unsigned long long)t4_read_reg64(adap, data_reg),
527 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
528 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
529 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
530 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
531 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
532 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
533 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
535 CXGBE_DEBUG_MBOX(adap,
536 "command %#x completed in %d ms (%ssleeping)\n",
538 i + ms, sleep_ok ? "" : "non-");
540 res = t4_read_reg64(adap, data_reg);
541 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
542 fw_asrt(adap, data_reg);
543 res = V_FW_CMD_RETVAL(EIO);
545 get_mbox_rpl(adap, rpl, size / 8, data_reg);
547 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
549 t4_os_atomic_list_del(&entry, &adap->mbox_list,
552 return -G_FW_CMD_RETVAL((int)res);
557 * We timed out waiting for a reply to our mailbox command. Report
558 * the error and also check to see if the firmware reported any
561 dev_err(adap, "command %#x in mailbox %d timed out\n",
562 *(const u8 *)cmd, mbox);
563 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
566 t4_report_fw_error(adap);
568 return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
571 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
572 void *rpl, bool sleep_ok)
574 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
579 * t4_get_regs_len - return the size of the chips register set
580 * @adapter: the adapter
582 * Returns the size of the chip's BAR0 register space.
584 unsigned int t4_get_regs_len(struct adapter *adapter)
586 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
588 switch (chip_version) {
590 return T5_REGMAP_SIZE;
594 "Unsupported chip version %d\n", chip_version);
599 * t4_get_regs - read chip registers into provided buffer
601 * @buf: register buffer
602 * @buf_size: size (in bytes) of register buffer
604 * If the provided register buffer isn't large enough for the chip's
605 * full register range, the register dump will be truncated to the
606 * register buffer's size.
608 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
610 static const unsigned int t5_reg_ranges[] = {
1385 u32 *buf_end = (u32 *)((char *)buf + buf_size);
1386 const unsigned int *reg_ranges;
1387 int reg_ranges_size, range;
1388 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1390 /* Select the right set of register ranges to dump depending on the
1391 * adapter chip type.
1393 switch (chip_version) {
1395 reg_ranges = t5_reg_ranges;
1396 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1401 "Unsupported chip version %d\n", chip_version);
1405 /* Clear the register buffer and insert the appropriate register
1406 * values selected by the above register ranges.
1408 memset(buf, 0, buf_size);
1409 for (range = 0; range < reg_ranges_size; range += 2) {
1410 unsigned int reg = reg_ranges[range];
1411 unsigned int last_reg = reg_ranges[range + 1];
1412 u32 *bufp = (u32 *)((char *)buf + reg);
1414 /* Iterate across the register range filling in the register
1415 * buffer but don't write past the end of the register buffer.
1417 while (reg <= last_reg && bufp < buf_end) {
1418 *bufp++ = t4_read_reg(adap, reg);
1424 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1425 #define EEPROM_DELAY 10 /* 10us per poll spin */
1426 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */
1428 #define EEPROM_STAT_ADDR 0x7bfc
1431 * Small utility function to wait till any outstanding VPD Access is complete.
1432 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1433 * VPD Access in flight. This allows us to handle the problem of having a
1434 * previous VPD Access time out and prevent an attempt to inject a new VPD
1435 * Request before any in-flight VPD request has completed.
1437 static int t4_seeprom_wait(struct adapter *adapter)
1439 unsigned int base = adapter->params.pci.vpd_cap_addr;
1442 /* If no VPD Access is in flight, we can just return success right
1445 if (!adapter->vpd_busy)
1448 /* Poll the VPD Capability Address/Flag register waiting for it
1449 * to indicate that the operation is complete.
1451 max_poll = EEPROM_MAX_POLL;
1455 udelay(EEPROM_DELAY);
1456 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
1458 /* If the operation is complete, mark the VPD as no longer
1459 * busy and return success.
1461 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
1462 adapter->vpd_busy = 0;
1465 } while (--max_poll);
1467 /* Failure! Note that we leave the VPD Busy status set in order to
1468 * avoid pushing a new VPD Access request into the VPD Capability till
1469 * the current operation eventually succeeds. It's a bug to issue a
1470 * new request when an existing request is in flight and will result
1471 * in corrupt hardware state.
1477 * t4_seeprom_read - read a serial EEPROM location
1478 * @adapter: adapter to read
1479 * @addr: EEPROM virtual address
1480 * @data: where to store the read data
1482 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
1483 * VPD capability. Note that this function must be called with a virtual
1486 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
1488 unsigned int base = adapter->params.pci.vpd_cap_addr;
1491 /* VPD Accesses must alway be 4-byte aligned!
1493 if (addr >= EEPROMVSIZE || (addr & 3))
1496 /* Wait for any previous operation which may still be in flight to
1499 ret = t4_seeprom_wait(adapter);
1501 dev_err(adapter, "VPD still busy from previous operation\n");
1505 /* Issue our new VPD Read request, mark the VPD as being busy and wait
1506 * for our request to complete. If it doesn't complete, note the
1507 * error and return it to our caller. Note that we do not reset the
1510 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
1511 adapter->vpd_busy = 1;
1512 adapter->vpd_flag = PCI_VPD_ADDR_F;
1513 ret = t4_seeprom_wait(adapter);
1515 dev_err(adapter, "VPD read of address %#x failed\n", addr);
1519 /* Grab the returned data, swizzle it into our endianness and
1522 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
1523 *data = le32_to_cpu(*data);
1528 * t4_seeprom_write - write a serial EEPROM location
1529 * @adapter: adapter to write
1530 * @addr: virtual EEPROM address
1531 * @data: value to write
1533 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
1534 * VPD capability. Note that this function must be called with a virtual
1537 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
1539 unsigned int base = adapter->params.pci.vpd_cap_addr;
1544 /* VPD Accesses must alway be 4-byte aligned!
1546 if (addr >= EEPROMVSIZE || (addr & 3))
1549 /* Wait for any previous operation which may still be in flight to
1552 ret = t4_seeprom_wait(adapter);
1554 dev_err(adapter, "VPD still busy from previous operation\n");
1558 /* Issue our new VPD Read request, mark the VPD as being busy and wait
1559 * for our request to complete. If it doesn't complete, note the
1560 * error and return it to our caller. Note that we do not reset the
1563 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
1565 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
1566 (u16)addr | PCI_VPD_ADDR_F);
1567 adapter->vpd_busy = 1;
1568 adapter->vpd_flag = 0;
1569 ret = t4_seeprom_wait(adapter);
1571 dev_err(adapter, "VPD write of address %#x failed\n", addr);
1575 /* Reset PCI_VPD_DATA register after a transaction and wait for our
1576 * request to complete. If it doesn't complete, return error.
1578 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
1579 max_poll = EEPROM_MAX_POLL;
1581 udelay(EEPROM_DELAY);
1582 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
1583 } while ((stats_reg & 0x1) && --max_poll);
1587 /* Return success! */
1592 * t4_seeprom_wp - enable/disable EEPROM write protection
1593 * @adapter: the adapter
1594 * @enable: whether to enable or disable write protection
1596 * Enables or disables write protection on the serial EEPROM.
1598 int t4_seeprom_wp(struct adapter *adapter, int enable)
1600 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
1604 * t4_config_rss_range - configure a portion of the RSS mapping table
1605 * @adapter: the adapter
1606 * @mbox: mbox to use for the FW command
1607 * @viid: virtual interface whose RSS subtable is to be written
1608 * @start: start entry in the table to write
1609 * @n: how many table entries to write
1610 * @rspq: values for the "response queue" (Ingress Queue) lookup table
1611 * @nrspq: number of values in @rspq
1613 * Programs the selected part of the VI's RSS mapping table with the
1614 * provided values. If @nrspq < @n the supplied values are used repeatedly
1615 * until the full table range is populated.
1617 * The caller must ensure the values in @rspq are in the range allowed for
1620 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1621 int start, int n, const u16 *rspq, unsigned int nrspq)
1624 const u16 *rsp = rspq;
1625 const u16 *rsp_end = rspq + nrspq;
1626 struct fw_rss_ind_tbl_cmd cmd;
1628 memset(&cmd, 0, sizeof(cmd));
1629 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
1630 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
1631 V_FW_RSS_IND_TBL_CMD_VIID(viid));
1632 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1635 * Each firmware RSS command can accommodate up to 32 RSS Ingress
1636 * Queue Identifiers. These Ingress Queue IDs are packed three to
1637 * a 32-bit word as 10-bit values with the upper remaining 2 bits
1641 int nq = min(n, 32);
1643 __be32 *qp = &cmd.iq0_to_iq2;
1646 * Set up the firmware RSS command header to send the next
1647 * "nq" Ingress Queue IDs to the firmware.
1649 cmd.niqid = cpu_to_be16(nq);
1650 cmd.startidx = cpu_to_be16(start);
1653 * "nq" more done for the start of the next loop.
1659 * While there are still Ingress Queue IDs to stuff into the
1660 * current firmware RSS command, retrieve them from the
1661 * Ingress Queue ID array and insert them into the command.
1665 * Grab up to the next 3 Ingress Queue IDs (wrapping
1666 * around the Ingress Queue ID array if necessary) and
1667 * insert them into the firmware RSS command at the
1668 * current 3-tuple position within the commad.
1672 int nqbuf = min(3, nq);
1678 while (nqbuf && nq_packed < 32) {
1685 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
1686 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
1687 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
1691 * Send this portion of the RRS table update to the firmware;
1692 * bail out on any errors.
1694 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
1703 * t4_config_vi_rss - configure per VI RSS settings
1704 * @adapter: the adapter
1705 * @mbox: mbox to use for the FW command
1708 * @defq: id of the default RSS queue for the VI.
1710 * Configures VI-specific RSS properties.
1712 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1713 unsigned int flags, unsigned int defq)
1715 struct fw_rss_vi_config_cmd c;
1717 memset(&c, 0, sizeof(c));
1718 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
1719 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
1720 V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
1721 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
1722 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
1723 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
1724 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
1728 * init_cong_ctrl - initialize congestion control parameters
1729 * @a: the alpha values for congestion control
1730 * @b: the beta values for congestion control
1732 * Initialize the congestion control parameters.
1734 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
1738 for (i = 0; i < 9; i++) {
1792 #define INIT_CMD(var, cmd, rd_wr) do { \
1793 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
1794 F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
1795 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
1798 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
1800 u32 cclk_param, cclk_val;
1804 * Ask firmware for the Core Clock since it knows how to translate the
1805 * Reference Clock ('V2') VPD field into a Core Clock value ...
1807 cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1808 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
1809 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
1810 1, &cclk_param, &cclk_val);
1812 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
1818 dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
1822 /* serial flash and firmware constants and flash config file constants */
1824 SF_ATTEMPTS = 10, /* max retries for SF operations */
1826 /* flash command opcodes */
1827 SF_PROG_PAGE = 2, /* program page */
1828 SF_WR_DISABLE = 4, /* disable writes */
1829 SF_RD_STATUS = 5, /* read status register */
1830 SF_WR_ENABLE = 6, /* enable writes */
1831 SF_RD_DATA_FAST = 0xb, /* read flash */
1832 SF_RD_ID = 0x9f, /* read ID */
1833 SF_ERASE_SECTOR = 0xd8, /* erase sector */
1837 * sf1_read - read data from the serial flash
1838 * @adapter: the adapter
1839 * @byte_cnt: number of bytes to read
1840 * @cont: whether another operation will be chained
1841 * @lock: whether to lock SF for PL access only
1842 * @valp: where to store the read data
1844 * Reads up to 4 bytes of data from the serial flash. The location of
1845 * the read needs to be specified prior to calling this by issuing the
1846 * appropriate commands to the serial flash.
1848 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
1849 int lock, u32 *valp)
1853 if (!byte_cnt || byte_cnt > 4)
1855 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
1857 t4_write_reg(adapter, A_SF_OP,
1858 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
1859 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
1861 *valp = t4_read_reg(adapter, A_SF_DATA);
1866 * sf1_write - write data to the serial flash
1867 * @adapter: the adapter
1868 * @byte_cnt: number of bytes to write
1869 * @cont: whether another operation will be chained
1870 * @lock: whether to lock SF for PL access only
1871 * @val: value to write
1873 * Writes up to 4 bytes of data to the serial flash. The location of
1874 * the write needs to be specified prior to calling this by issuing the
1875 * appropriate commands to the serial flash.
1877 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
1880 if (!byte_cnt || byte_cnt > 4)
1882 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
1884 t4_write_reg(adapter, A_SF_DATA, val);
1885 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
1886 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
1887 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
1891 * t4_read_flash - read words from serial flash
1892 * @adapter: the adapter
1893 * @addr: the start address for the read
1894 * @nwords: how many 32-bit words to read
1895 * @data: where to store the read data
1896 * @byte_oriented: whether to store data as bytes or as words
1898 * Read the specified number of 32-bit words from the serial flash.
1899 * If @byte_oriented is set the read data is stored as a byte array
1900 * (i.e., big-endian), otherwise as 32-bit words in the platform's
1901 * natural endianness.
1903 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1904 unsigned int nwords, u32 *data, int byte_oriented)
1908 if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
1912 addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
1914 ret = sf1_write(adapter, 4, 1, 0, addr);
1918 ret = sf1_read(adapter, 1, 1, 0, data);
1922 for ( ; nwords; nwords--, data++) {
1923 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
1925 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
1929 *data = cpu_to_be32(*data);
1935 * t4_get_fw_version - read the firmware version
1936 * @adapter: the adapter
1937 * @vers: where to place the version
1939 * Reads the FW version from flash.
1941 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
1943 return t4_read_flash(adapter, FLASH_FW_START +
1944 offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
1948 * t4_get_tp_version - read the TP microcode version
1949 * @adapter: the adapter
1950 * @vers: where to place the version
1952 * Reads the TP microcode version from flash.
1954 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
1956 return t4_read_flash(adapter, FLASH_FW_START +
1957 offsetof(struct fw_hdr, tp_microcode_ver),
1961 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
1962 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
1963 FW_PORT_CAP_SPEED_100G | FW_PORT_CAP_ANEG)
1966 * t4_link_l1cfg - apply link configuration to MAC/PHY
1967 * @phy: the PHY to setup
1968 * @mac: the MAC to setup
1969 * @lc: the requested link configuration
1971 * Set up a port's MAC and PHY according to a desired link configuration.
1972 * - If the PHY can auto-negotiate first decide what to advertise, then
1973 * enable/disable auto-negotiation as desired, and reset.
1974 * - If the PHY does not auto-negotiate just reset it.
1975 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
1976 * otherwise do it later based on the outcome of auto-negotiation.
1978 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
1979 struct link_config *lc)
1981 struct fw_port_cmd c;
1982 unsigned int fc = 0, mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
1985 if (lc->requested_fc & PAUSE_RX)
1986 fc |= FW_PORT_CAP_FC_RX;
1987 if (lc->requested_fc & PAUSE_TX)
1988 fc |= FW_PORT_CAP_FC_TX;
1990 memset(&c, 0, sizeof(c));
1991 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
1992 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
1993 V_FW_PORT_CMD_PORTID(port));
1995 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
1998 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
1999 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
2001 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
2002 } else if (lc->autoneg == AUTONEG_DISABLE) {
2003 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
2004 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
2006 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
2009 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2013 * t4_flash_cfg_addr - return the address of the flash configuration file
2014 * @adapter: the adapter
2016 * Return the address within the flash where the Firmware Configuration
2017 * File is stored, or an error if the device FLASH is too small to contain
2018 * a Firmware Configuration File.
2020 int t4_flash_cfg_addr(struct adapter *adapter)
2023 * If the device FLASH isn't large enough to hold a Firmware
2024 * Configuration File, return an error.
2026 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2029 return FLASH_CFG_START;
2032 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
2035 * t4_intr_enable - enable interrupts
2036 * @adapter: the adapter whose interrupts should be enabled
2038 * Enable PF-specific interrupts for the calling function and the top-level
2039 * interrupt concentrator for global interrupts. Interrupts are already
2040 * enabled at each module, here we just enable the roots of the interrupt
2043 * Note: this function should be called only when the driver manages
2044 * non PF-specific interrupts from the various HW modules. Only one PCI
2045 * function at a time should be doing this.
2047 void t4_intr_enable(struct adapter *adapter)
2050 u32 pf = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI));
2052 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2053 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2054 t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2055 F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2056 F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2057 F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2058 F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
2059 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
2060 F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
2061 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
2062 t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
2066 * t4_intr_disable - disable interrupts
2067 * @adapter: the adapter whose interrupts should be disabled
2069 * Disable interrupts. We only disable the top-level interrupt
2070 * concentrators. The caller must be a PCI function managing global
2073 void t4_intr_disable(struct adapter *adapter)
2075 u32 pf = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI));
2077 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
2078 t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
2082 * t4_get_port_type_description - return Port Type string description
2083 * @port_type: firmware Port Type enumeration
2085 const char *t4_get_port_type_description(enum fw_port_type port_type)
2087 static const char * const port_type_description[] = {
2106 if (port_type < ARRAY_SIZE(port_type_description))
2107 return port_type_description[port_type];
2112 * t4_get_mps_bg_map - return the buffer groups associated with a port
2113 * @adap: the adapter
2114 * @idx: the port index
2116 * Returns a bitmap indicating which MPS buffer groups are associated
2117 * with the given port. Bit i is set if buffer group i is used by the
2120 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
2122 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
2125 return idx == 0 ? 0xf : 0;
2127 return idx < 2 ? (3 << (2 * idx)) : 0;
2132 * t4_get_port_stats - collect port statistics
2133 * @adap: the adapter
2134 * @idx: the port index
2135 * @p: the stats structure to fill
2137 * Collect statistics related to the given port from HW.
2139 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2141 u32 bgmap = t4_get_mps_bg_map(adap, idx);
2142 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
2144 #define GET_STAT(name) \
2145 t4_read_reg64(adap, \
2146 (is_t4(adap->params.chip) ? \
2147 PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
2148 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
2149 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
2151 p->tx_octets = GET_STAT(TX_PORT_BYTES);
2152 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
2153 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
2154 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
2155 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
2156 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
2157 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
2158 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
2159 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
2160 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
2161 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
2162 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2163 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
2164 p->tx_drop = GET_STAT(TX_PORT_DROP);
2165 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
2166 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
2167 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
2168 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
2169 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
2170 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
2171 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
2172 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
2173 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
2175 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
2176 if (stat_ctl & F_COUNTPAUSESTATTX) {
2177 p->tx_frames -= p->tx_pause;
2178 p->tx_octets -= p->tx_pause * 64;
2180 if (stat_ctl & F_COUNTPAUSEMCTX)
2181 p->tx_mcast_frames -= p->tx_pause;
2184 p->rx_octets = GET_STAT(RX_PORT_BYTES);
2185 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
2186 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
2187 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
2188 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
2189 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
2190 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2191 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
2192 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
2193 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
2194 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
2195 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
2196 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
2197 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
2198 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
2199 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
2200 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
2201 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
2202 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
2203 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
2204 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
2205 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
2206 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
2207 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
2208 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
2209 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
2210 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
2212 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
2213 if (stat_ctl & F_COUNTPAUSESTATRX) {
2214 p->rx_frames -= p->rx_pause;
2215 p->rx_octets -= p->rx_pause * 64;
2217 if (stat_ctl & F_COUNTPAUSEMCRX)
2218 p->rx_mcast_frames -= p->rx_pause;
2221 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
2222 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
2223 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
2224 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
2225 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
2226 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
2227 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
2228 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
2235 * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
2236 * @adap: The adapter
2238 * @stats: Current stats to fill
2239 * @offset: Previous stats snapshot
2241 void t4_get_port_stats_offset(struct adapter *adap, int idx,
2242 struct port_stats *stats,
2243 struct port_stats *offset)
2248 t4_get_port_stats(adap, idx, stats);
2249 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
2250 i < (sizeof(struct port_stats) / sizeof(u64));
2256 * t4_clr_port_stats - clear port statistics
2257 * @adap: the adapter
2258 * @idx: the port index
2260 * Clear HW statistics for the given port.
2262 void t4_clr_port_stats(struct adapter *adap, int idx)
2265 u32 bgmap = t4_get_mps_bg_map(adap, idx);
2268 if (is_t4(adap->params.chip))
2269 port_base_addr = PORT_BASE(idx);
2271 port_base_addr = T5_PORT_BASE(idx);
2273 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
2274 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
2275 t4_write_reg(adap, port_base_addr + i, 0);
2276 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
2277 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
2278 t4_write_reg(adap, port_base_addr + i, 0);
2279 for (i = 0; i < 4; i++)
2280 if (bgmap & (1 << i)) {
2282 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
2285 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
2291 * t4_fw_hello - establish communication with FW
2292 * @adap: the adapter
2293 * @mbox: mailbox to use for the FW command
2294 * @evt_mbox: mailbox to receive async FW events
2295 * @master: specifies the caller's willingness to be the device master
2296 * @state: returns the current device state (if non-NULL)
2298 * Issues a command to establish communication with FW. Returns either
2299 * an error (negative integer) or the mailbox of the Master PF.
2301 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
2302 enum dev_master master, enum dev_state *state)
2305 struct fw_hello_cmd c;
2307 unsigned int master_mbox;
2308 int retries = FW_CMD_HELLO_RETRIES;
2311 memset(&c, 0, sizeof(c));
2312 INIT_CMD(c, HELLO, WRITE);
2313 c.err_to_clearinit = cpu_to_be32(
2314 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
2315 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
2316 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
2317 M_FW_HELLO_CMD_MBMASTER) |
2318 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
2319 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
2320 F_FW_HELLO_CMD_CLEARINIT);
2323 * Issue the HELLO command to the firmware. If it's not successful
2324 * but indicates that we got a "busy" or "timeout" condition, retry
2325 * the HELLO until we exhaust our retry limit. If we do exceed our
2326 * retry limit, check to see if the firmware left us any error
2327 * information and report that if so ...
2329 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2330 if (ret != FW_SUCCESS) {
2331 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
2333 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
2334 t4_report_fw_error(adap);
2338 v = be32_to_cpu(c.err_to_clearinit);
2339 master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
2341 if (v & F_FW_HELLO_CMD_ERR)
2342 *state = DEV_STATE_ERR;
2343 else if (v & F_FW_HELLO_CMD_INIT)
2344 *state = DEV_STATE_INIT;
2346 *state = DEV_STATE_UNINIT;
2350 * If we're not the Master PF then we need to wait around for the
2351 * Master PF Driver to finish setting up the adapter.
2353 * Note that we also do this wait if we're a non-Master-capable PF and
2354 * there is no current Master PF; a Master PF may show up momentarily
2355 * and we wouldn't want to fail pointlessly. (This can happen when an
2356 * OS loads lots of different drivers rapidly at the same time). In
2357 * this case, the Master PF returned by the firmware will be
2358 * M_PCIE_FW_MASTER so the test below will work ...
2360 if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
2361 master_mbox != mbox) {
2362 int waiting = FW_CMD_HELLO_TIMEOUT;
2365 * Wait for the firmware to either indicate an error or
2366 * initialized state. If we see either of these we bail out
2367 * and report the issue to the caller. If we exhaust the
2368 * "hello timeout" and we haven't exhausted our retries, try
2369 * again. Otherwise bail with a timeout error.
2378 * If neither Error nor Initialialized are indicated
2379 * by the firmware keep waiting till we exaust our
2380 * timeout ... and then retry if we haven't exhausted
2383 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
2384 if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
2395 * We either have an Error or Initialized condition
2396 * report errors preferentially.
2399 if (pcie_fw & F_PCIE_FW_ERR)
2400 *state = DEV_STATE_ERR;
2401 else if (pcie_fw & F_PCIE_FW_INIT)
2402 *state = DEV_STATE_INIT;
2406 * If we arrived before a Master PF was selected and
2407 * there's not a valid Master PF, grab its identity
2410 if (master_mbox == M_PCIE_FW_MASTER &&
2411 (pcie_fw & F_PCIE_FW_MASTER_VLD))
2412 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
2421 * t4_fw_bye - end communication with FW
2422 * @adap: the adapter
2423 * @mbox: mailbox to use for the FW command
2425 * Issues a command to terminate communication with FW.
2427 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
2429 struct fw_bye_cmd c;
2431 memset(&c, 0, sizeof(c));
2432 INIT_CMD(c, BYE, WRITE);
2433 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2437 * t4_fw_reset - issue a reset to FW
2438 * @adap: the adapter
2439 * @mbox: mailbox to use for the FW command
2440 * @reset: specifies the type of reset to perform
2442 * Issues a reset command of the specified type to FW.
2444 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
2446 struct fw_reset_cmd c;
2448 memset(&c, 0, sizeof(c));
2449 INIT_CMD(c, RESET, WRITE);
2450 c.val = cpu_to_be32(reset);
2451 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2455 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
2456 * @adap: the adapter
2457 * @mbox: mailbox to use for the FW RESET command (if desired)
2458 * @force: force uP into RESET even if FW RESET command fails
2460 * Issues a RESET command to firmware (if desired) with a HALT indication
2461 * and then puts the microprocessor into RESET state. The RESET command
2462 * will only be issued if a legitimate mailbox is provided (mbox <=
2463 * M_PCIE_FW_MASTER).
2465 * This is generally used in order for the host to safely manipulate the
2466 * adapter without fear of conflicting with whatever the firmware might
2467 * be doing. The only way out of this state is to RESTART the firmware
2470 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
2475 * If a legitimate mailbox is provided, issue a RESET command
2476 * with a HALT indication.
2478 if (mbox <= M_PCIE_FW_MASTER) {
2479 struct fw_reset_cmd c;
2481 memset(&c, 0, sizeof(c));
2482 INIT_CMD(c, RESET, WRITE);
2483 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
2484 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
2485 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2489 * Normally we won't complete the operation if the firmware RESET
2490 * command fails but if our caller insists we'll go ahead and put the
2491 * uP into RESET. This can be useful if the firmware is hung or even
2492 * missing ... We'll have to take the risk of putting the uP into
2493 * RESET without the cooperation of firmware in that case.
2495 * We also force the firmware's HALT flag to be on in case we bypassed
2496 * the firmware RESET command above or we're dealing with old firmware
2497 * which doesn't have the HALT capability. This will serve as a flag
2498 * for the incoming firmware to know that it's coming out of a HALT
2499 * rather than a RESET ... if it's new enough to understand that ...
2501 if (ret == 0 || force) {
2502 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
2503 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
2508 * And we always return the result of the firmware RESET command
2509 * even when we force the uP into RESET ...
2515 * t4_fw_restart - restart the firmware by taking the uP out of RESET
2516 * @adap: the adapter
2517 * @mbox: mailbox to use for the FW RESET command (if desired)
2518 * @reset: if we want to do a RESET to restart things
2520 * Restart firmware previously halted by t4_fw_halt(). On successful
2521 * return the previous PF Master remains as the new PF Master and there
2522 * is no need to issue a new HELLO command, etc.
2524 * We do this in two ways:
2526 * 1. If we're dealing with newer firmware we'll simply want to take
2527 * the chip's microprocessor out of RESET. This will cause the
2528 * firmware to start up from its start vector. And then we'll loop
2529 * until the firmware indicates it's started again (PCIE_FW.HALT
2530 * reset to 0) or we timeout.
2532 * 2. If we're dealing with older firmware then we'll need to RESET
2533 * the chip since older firmware won't recognize the PCIE_FW.HALT
2534 * flag and automatically RESET itself on startup.
2536 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
2540 * Since we're directing the RESET instead of the firmware
2541 * doing it automatically, we need to clear the PCIE_FW.HALT
2544 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
2547 * If we've been given a valid mailbox, first try to get the
2548 * firmware to do the RESET. If that works, great and we can
2549 * return success. Otherwise, if we haven't been given a
2550 * valid mailbox or the RESET command failed, fall back to
2551 * hitting the chip with a hammer.
2553 if (mbox <= M_PCIE_FW_MASTER) {
2554 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
2556 if (t4_fw_reset(adap, mbox,
2557 F_PIORST | F_PIORSTMODE) == 0)
2561 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
2566 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
2567 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
2568 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
2579 * t4_fixup_host_params_compat - fix up host-dependent parameters
2580 * @adap: the adapter
2581 * @page_size: the host's Base Page Size
2582 * @cache_line_size: the host's Cache Line Size
2583 * @chip_compat: maintain compatibility with designated chip
2585 * Various registers in the chip contain values which are dependent on the
2586 * host's Base Page and Cache Line Sizes. This function will fix all of
2587 * those registers with the appropriate values as passed in ...
2589 * @chip_compat is used to limit the set of changes that are made
2590 * to be compatible with the indicated chip release. This is used by
2591 * drivers to maintain compatibility with chip register settings when
2592 * the drivers haven't [yet] been updated with new chip support.
2594 int t4_fixup_host_params_compat(struct adapter *adap,
2595 unsigned int page_size,
2596 unsigned int cache_line_size,
2597 enum chip_type chip_compat)
2599 unsigned int page_shift = cxgbe_fls(page_size) - 1;
2600 unsigned int sge_hps = page_shift - 10;
2601 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
2602 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
2603 unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
2605 t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
2606 V_HOSTPAGESIZEPF0(sge_hps) |
2607 V_HOSTPAGESIZEPF1(sge_hps) |
2608 V_HOSTPAGESIZEPF2(sge_hps) |
2609 V_HOSTPAGESIZEPF3(sge_hps) |
2610 V_HOSTPAGESIZEPF4(sge_hps) |
2611 V_HOSTPAGESIZEPF5(sge_hps) |
2612 V_HOSTPAGESIZEPF6(sge_hps) |
2613 V_HOSTPAGESIZEPF7(sge_hps));
2615 if (is_t4(adap->params.chip) || is_t4(chip_compat))
2616 t4_set_reg_field(adap, A_SGE_CONTROL,
2617 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
2618 F_EGRSTATUSPAGESIZE,
2619 V_INGPADBOUNDARY(fl_align_log -
2620 X_INGPADBOUNDARY_SHIFT) |
2621 V_EGRSTATUSPAGESIZE(stat_len != 64));
2624 * T5 introduced the separation of the Free List Padding and
2625 * Packing Boundaries. Thus, we can select a smaller Padding
2626 * Boundary to avoid uselessly chewing up PCIe Link and Memory
2627 * Bandwidth, and use a Packing Boundary which is large enough
2628 * to avoid false sharing between CPUs, etc.
2630 * For the PCI Link, the smaller the Padding Boundary the
2631 * better. For the Memory Controller, a smaller Padding
2632 * Boundary is better until we cross under the Memory Line
2633 * Size (the minimum unit of transfer to/from Memory). If we
2634 * have a Padding Boundary which is smaller than the Memory
2635 * Line Size, that'll involve a Read-Modify-Write cycle on the
2636 * Memory Controller which is never good. For T5 the smallest
2637 * Padding Boundary which we can select is 32 bytes which is
2638 * larger than any known Memory Controller Line Size so we'll
2643 * N.B. T5 has a different interpretation of the "0" value for
2644 * the Packing Boundary. This corresponds to 16 bytes instead
2645 * of the expected 32 bytes. We never have a Packing Boundary
2646 * less than 32 bytes so we can't use that special value but
2647 * on the other hand, if we wanted 32 bytes, the best we can
2648 * really do is 64 bytes ...
2650 if (fl_align <= 32) {
2654 t4_set_reg_field(adap, A_SGE_CONTROL,
2655 V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
2656 F_EGRSTATUSPAGESIZE,
2657 V_INGPADBOUNDARY(X_INGPCIEBOUNDARY_32B) |
2658 V_EGRSTATUSPAGESIZE(stat_len != 64));
2659 t4_set_reg_field(adap, A_SGE_CONTROL2,
2660 V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
2661 V_INGPACKBOUNDARY(fl_align_log -
2662 X_INGPACKBOUNDARY_SHIFT));
2666 * Adjust various SGE Free List Host Buffer Sizes.
2668 * The first four entries are:
2672 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
2673 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
2675 * For the single-MTU buffers in unpacked mode we need to include
2676 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
2677 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
2678 * Padding boundary. All of these are accommodated in the Factory
2679 * Default Firmware Configuration File but we need to adjust it for
2680 * this host's cache line size.
2682 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
2683 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
2684 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
2686 t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
2687 (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
2690 t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
2696 * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
2697 * @adap: the adapter
2698 * @page_size: the host's Base Page Size
2699 * @cache_line_size: the host's Cache Line Size
2701 * Various registers in T4 contain values which are dependent on the
2702 * host's Base Page and Cache Line Sizes. This function will fix all of
2703 * those registers with the appropriate values as passed in ...
2705 * This routine makes changes which are compatible with T4 chips.
2707 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
2708 unsigned int cache_line_size)
2710 return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
2715 * t4_fw_initialize - ask FW to initialize the device
2716 * @adap: the adapter
2717 * @mbox: mailbox to use for the FW command
2719 * Issues a command to FW to partially initialize the device. This
2720 * performs initialization that generally doesn't depend on user input.
2722 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
2724 struct fw_initialize_cmd c;
2726 memset(&c, 0, sizeof(c));
2727 INIT_CMD(c, INITIALIZE, WRITE);
2728 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2732 * t4_query_params_rw - query FW or device parameters
2733 * @adap: the adapter
2734 * @mbox: mailbox to use for the FW command
2737 * @nparams: the number of parameters
2738 * @params: the parameter names
2739 * @val: the parameter values
2740 * @rw: Write and read flag
2742 * Reads the value of FW or device parameters. Up to 7 parameters can be
2745 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
2746 unsigned int pf, unsigned int vf,
2747 unsigned int nparams, const u32 *params,
2752 struct fw_params_cmd c;
2753 __be32 *p = &c.param[0].mnem;
2758 memset(&c, 0, sizeof(c));
2759 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
2760 F_FW_CMD_REQUEST | F_FW_CMD_READ |
2761 V_FW_PARAMS_CMD_PFN(pf) |
2762 V_FW_PARAMS_CMD_VFN(vf));
2763 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2765 for (i = 0; i < nparams; i++) {
2766 *p++ = cpu_to_be32(*params++);
2768 *p = cpu_to_be32(*(val + i));
2772 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2774 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
2775 *val++ = be32_to_cpu(*p);
2779 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
2780 unsigned int vf, unsigned int nparams, const u32 *params,
2783 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
2787 * t4_set_params_timeout - sets FW or device parameters
2788 * @adap: the adapter
2789 * @mbox: mailbox to use for the FW command
2792 * @nparams: the number of parameters
2793 * @params: the parameter names
2794 * @val: the parameter values
2795 * @timeout: the timeout time
2797 * Sets the value of FW or device parameters. Up to 7 parameters can be
2798 * specified at once.
2800 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
2801 unsigned int pf, unsigned int vf,
2802 unsigned int nparams, const u32 *params,
2803 const u32 *val, int timeout)
2805 struct fw_params_cmd c;
2806 __be32 *p = &c.param[0].mnem;
2811 memset(&c, 0, sizeof(c));
2812 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
2813 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2814 V_FW_PARAMS_CMD_PFN(pf) |
2815 V_FW_PARAMS_CMD_VFN(vf));
2816 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2819 *p++ = cpu_to_be32(*params++);
2820 *p++ = cpu_to_be32(*val++);
2823 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
2826 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
2827 unsigned int vf, unsigned int nparams, const u32 *params,
2830 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
2831 FW_CMD_MAX_TIMEOUT);
2835 * t4_alloc_vi_func - allocate a virtual interface
2836 * @adap: the adapter
2837 * @mbox: mailbox to use for the FW command
2838 * @port: physical port associated with the VI
2839 * @pf: the PF owning the VI
2840 * @vf: the VF owning the VI
2841 * @nmac: number of MAC addresses needed (1 to 5)
2842 * @mac: the MAC addresses of the VI
2843 * @rss_size: size of RSS table slice associated with this VI
2844 * @portfunc: which Port Application Function MAC Address is desired
2845 * @idstype: Intrusion Detection Type
2847 * Allocates a virtual interface for the given physical port. If @mac is
2848 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
2849 * @mac should be large enough to hold @nmac Ethernet addresses, they are
2850 * stored consecutively so the space needed is @nmac * 6 bytes.
2851 * Returns a negative error number or the non-negative VI id.
2853 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
2854 unsigned int port, unsigned int pf, unsigned int vf,
2855 unsigned int nmac, u8 *mac, unsigned int *rss_size,
2856 unsigned int portfunc, unsigned int idstype)
2861 memset(&c, 0, sizeof(c));
2862 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
2863 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
2864 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
2865 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
2866 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
2867 V_FW_VI_CMD_FUNC(portfunc));
2868 c.portid_pkd = V_FW_VI_CMD_PORTID(port);
2871 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2876 memcpy(mac, c.mac, sizeof(c.mac));
2879 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
2882 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
2885 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
2888 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
2893 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
2894 return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
2898 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
2899 * @adap: the adapter
2900 * @mbox: mailbox to use for the FW command
2901 * @port: physical port associated with the VI
2902 * @pf: the PF owning the VI
2903 * @vf: the VF owning the VI
2904 * @nmac: number of MAC addresses needed (1 to 5)
2905 * @mac: the MAC addresses of the VI
2906 * @rss_size: size of RSS table slice associated with this VI
2908 * Backwards compatible and convieniance routine to allocate a Virtual
2909 * Interface with a Ethernet Port Application Function and Intrustion
2910 * Detection System disabled.
2912 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
2913 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
2914 unsigned int *rss_size)
2916 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
2921 * t4_free_vi - free a virtual interface
2922 * @adap: the adapter
2923 * @mbox: mailbox to use for the FW command
2924 * @pf: the PF owning the VI
2925 * @vf: the VF owning the VI
2926 * @viid: virtual interface identifiler
2928 * Free a previously allocated virtual interface.
2930 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
2931 unsigned int vf, unsigned int viid)
2935 memset(&c, 0, sizeof(c));
2936 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
2937 F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
2938 V_FW_VI_CMD_VFN(vf));
2939 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
2940 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
2942 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2946 * t4_set_rxmode - set Rx properties of a virtual interface
2947 * @adap: the adapter
2948 * @mbox: mailbox to use for the FW command
2950 * @mtu: the new MTU or -1
2951 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
2952 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
2953 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
2954 * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
2956 * @sleep_ok: if true we may sleep while awaiting command completion
2958 * Sets Rx properties of a virtual interface.
2960 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
2961 int mtu, int promisc, int all_multi, int bcast, int vlanex,
2964 struct fw_vi_rxmode_cmd c;
2966 /* convert to FW values */
2968 mtu = M_FW_VI_RXMODE_CMD_MTU;
2970 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
2972 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
2974 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
2976 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
2978 memset(&c, 0, sizeof(c));
2979 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
2980 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2981 V_FW_VI_RXMODE_CMD_VIID(viid));
2982 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2983 c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
2984 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
2985 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
2986 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
2987 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
2988 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
2992 * t4_change_mac - modifies the exact-match filter for a MAC address
2993 * @adap: the adapter
2994 * @mbox: mailbox to use for the FW command
2996 * @idx: index of existing filter for old value of MAC address, or -1
2997 * @addr: the new MAC address value
2998 * @persist: whether a new MAC allocation should be persistent
2999 * @add_smt: if true also add the address to the HW SMT
3001 * Modifies an exact-match filter and sets it to the new MAC address if
3002 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
3003 * latter case the address is added persistently if @persist is %true.
3005 * Note that in general it is not possible to modify the value of a given
3006 * filter so the generic way to modify an address filter is to free the one
3007 * being used by the old address value and allocate a new filter for the
3008 * new address value.
3010 * Returns a negative error number or the index of the filter with the new
3011 * MAC value. Note that this index may differ from @idx.
3013 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
3014 int idx, const u8 *addr, bool persist, bool add_smt)
3017 struct fw_vi_mac_cmd c;
3018 struct fw_vi_mac_exact *p = c.u.exact;
3019 int max_mac_addr = adap->params.arch.mps_tcam_size;
3021 if (idx < 0) /* new allocation */
3022 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3023 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3025 memset(&c, 0, sizeof(c));
3026 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
3027 F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3028 V_FW_VI_MAC_CMD_VIID(viid));
3029 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
3030 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
3031 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3032 V_FW_VI_MAC_CMD_IDX(idx));
3033 memcpy(p->macaddr, addr, sizeof(p->macaddr));
3035 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3037 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
3038 if (ret >= max_mac_addr)
3045 * t4_enable_vi_params - enable/disable a virtual interface
3046 * @adap: the adapter
3047 * @mbox: mailbox to use for the FW command
3049 * @rx_en: 1=enable Rx, 0=disable Rx
3050 * @tx_en: 1=enable Tx, 0=disable Tx
3051 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
3053 * Enables/disables a virtual interface. Note that setting DCB Enable
3054 * only makes sense when enabling a Virtual Interface ...
3056 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
3057 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
3059 struct fw_vi_enable_cmd c;
3061 memset(&c, 0, sizeof(c));
3062 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
3063 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3064 V_FW_VI_ENABLE_CMD_VIID(viid));
3065 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
3066 V_FW_VI_ENABLE_CMD_EEN(tx_en) |
3067 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
3069 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3073 * t4_enable_vi - enable/disable a virtual interface
3074 * @adap: the adapter
3075 * @mbox: mailbox to use for the FW command
3077 * @rx_en: 1=enable Rx, 0=disable Rx
3078 * @tx_en: 1=enable Tx, 0=disable Tx
3080 * Enables/disables a virtual interface. Note that setting DCB Enable
3081 * only makes sense when enabling a Virtual Interface ...
3083 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3084 bool rx_en, bool tx_en)
3086 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
3090 * t4_iq_start_stop - enable/disable an ingress queue and its FLs
3091 * @adap: the adapter
3092 * @mbox: mailbox to use for the FW command
3093 * @start: %true to enable the queues, %false to disable them
3094 * @pf: the PF owning the queues
3095 * @vf: the VF owning the queues
3096 * @iqid: ingress queue id
3097 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3098 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3100 * Starts or stops an ingress queue and its associated FLs, if any.
3102 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
3103 unsigned int pf, unsigned int vf, unsigned int iqid,
3104 unsigned int fl0id, unsigned int fl1id)
3108 memset(&c, 0, sizeof(c));
3109 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3110 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3111 V_FW_IQ_CMD_VFN(vf));
3112 c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
3113 V_FW_IQ_CMD_IQSTOP(!start) |
3115 c.iqid = cpu_to_be16(iqid);
3116 c.fl0id = cpu_to_be16(fl0id);
3117 c.fl1id = cpu_to_be16(fl1id);
3118 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3122 * t4_iq_free - free an ingress queue and its FLs
3123 * @adap: the adapter
3124 * @mbox: mailbox to use for the FW command
3125 * @pf: the PF owning the queues
3126 * @vf: the VF owning the queues
3127 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
3128 * @iqid: ingress queue id
3129 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3130 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3132 * Frees an ingress queue and its associated FLs, if any.
3134 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3135 unsigned int vf, unsigned int iqtype, unsigned int iqid,
3136 unsigned int fl0id, unsigned int fl1id)
3140 memset(&c, 0, sizeof(c));
3141 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3142 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3143 V_FW_IQ_CMD_VFN(vf));
3144 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
3145 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
3146 c.iqid = cpu_to_be16(iqid);
3147 c.fl0id = cpu_to_be16(fl0id);
3148 c.fl1id = cpu_to_be16(fl1id);
3149 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3153 * t4_eth_eq_free - free an Ethernet egress queue
3154 * @adap: the adapter
3155 * @mbox: mailbox to use for the FW command
3156 * @pf: the PF owning the queue
3157 * @vf: the VF owning the queue
3158 * @eqid: egress queue id
3160 * Frees an Ethernet egress queue.
3162 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3163 unsigned int vf, unsigned int eqid)
3165 struct fw_eq_eth_cmd c;
3167 memset(&c, 0, sizeof(c));
3168 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
3169 F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3170 V_FW_EQ_ETH_CMD_PFN(pf) |
3171 V_FW_EQ_ETH_CMD_VFN(vf));
3172 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
3173 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
3174 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3178 * t4_handle_fw_rpl - process a FW reply message
3179 * @adap: the adapter
3180 * @rpl: start of the FW message
3182 * Processes a FW message, such as link state change messages.
3184 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
3186 u8 opcode = *(const u8 *)rpl;
3189 * This might be a port command ... this simplifies the following
3190 * conditionals ... We can get away with pre-dereferencing
3191 * action_to_len16 because it's in the first 16 bytes and all messages
3192 * will be at least that long.
3194 const struct fw_port_cmd *p = (const void *)rpl;
3195 unsigned int action =
3196 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
3198 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
3199 /* link/module state change message */
3200 int speed = 0, fc = 0, i;
3201 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
3202 struct port_info *pi = NULL;
3203 struct link_config *lc;
3204 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
3205 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
3206 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
3208 if (stat & F_FW_PORT_CMD_RXPAUSE)
3210 if (stat & F_FW_PORT_CMD_TXPAUSE)
3212 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
3213 speed = ETH_SPEED_NUM_100M;
3214 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
3215 speed = ETH_SPEED_NUM_1G;
3216 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
3217 speed = ETH_SPEED_NUM_10G;
3218 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
3219 speed = ETH_SPEED_NUM_40G;
3221 for_each_port(adap, i) {
3222 pi = adap2pinfo(adap, i);
3223 if (pi->tx_chan == chan)
3228 if (mod != pi->mod_type) {
3230 t4_os_portmod_changed(adap, i);
3232 if (link_ok != lc->link_ok || speed != lc->speed ||
3233 fc != lc->fc) { /* something changed */
3234 if (!link_ok && lc->link_ok) {
3235 static const char * const reason[] = {
3238 "Auto-negotiation Failure",
3240 "Insufficient Airflow",
3241 "Unable To Determine Reason",
3242 "No RX Signal Detected",
3245 unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
3247 dev_warn(adap, "Port %d link down, reason: %s\n",
3250 lc->link_ok = link_ok;
3253 lc->supported = be16_to_cpu(p->u.info.pcap);
3256 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
3262 void t4_reset_link_config(struct adapter *adap, int idx)
3264 struct port_info *pi = adap2pinfo(adap, idx);
3265 struct link_config *lc = &pi->link_cfg;
3268 lc->requested_speed = 0;
3269 lc->requested_fc = 0;
3275 * init_link_config - initialize a link's SW state
3276 * @lc: structure holding the link state
3277 * @caps: link capabilities
3279 * Initializes the SW state maintained for each link, including the link's
3280 * capabilities and default speed/flow-control/autonegotiation settings.
3282 static void init_link_config(struct link_config *lc,
3285 lc->supported = caps;
3286 lc->requested_speed = 0;
3288 lc->requested_fc = 0;
3290 if (lc->supported & FW_PORT_CAP_ANEG) {
3291 lc->advertising = lc->supported & ADVERT_MASK;
3292 lc->autoneg = AUTONEG_ENABLE;
3294 lc->advertising = 0;
3295 lc->autoneg = AUTONEG_DISABLE;
3300 * t4_wait_dev_ready - wait till to reads of registers work
3302 * Right after the device is RESET is can take a small amount of time
3303 * for it to respond to register reads. Until then, all reads will
3304 * return either 0xff...ff or 0xee...ee. Return an error if reads
3305 * don't work within a reasonable time frame.
3307 static int t4_wait_dev_ready(struct adapter *adapter)
3311 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3313 if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
3317 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
3318 return (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS
3323 u32 vendor_and_model_id;
3327 int t4_get_flash_params(struct adapter *adapter)
3330 * Table for non-Numonix supported flash parts. Numonix parts are left
3331 * to the preexisting well-tested code. All flash parts have 64KB
3334 static struct flash_desc supported_flash[] = {
3335 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
3342 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
3344 ret = sf1_read(adapter, 3, 0, 1, &info);
3345 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */
3349 for (i = 0; i < ARRAY_SIZE(supported_flash); ++i)
3350 if (supported_flash[i].vendor_and_model_id == info) {
3351 adapter->params.sf_size = supported_flash[i].size_mb;
3352 adapter->params.sf_nsec =
3353 adapter->params.sf_size / SF_SEC_SIZE;
3357 if ((info & 0xff) != 0x20) /* not a Numonix flash */
3359 info >>= 16; /* log2 of size */
3360 if (info >= 0x14 && info < 0x18)
3361 adapter->params.sf_nsec = 1 << (info - 16);
3362 else if (info == 0x18)
3363 adapter->params.sf_nsec = 64;
3366 adapter->params.sf_size = 1 << info;
3369 * We should reject adapters with FLASHes which are too small. So, emit
3372 if (adapter->params.sf_size < FLASH_MIN_SIZE) {
3373 dev_warn(adapter, "WARNING!!! FLASH size %#x < %#x!!!\n",
3374 adapter->params.sf_size, FLASH_MIN_SIZE);
3380 static void set_pcie_completion_timeout(struct adapter *adapter,
3386 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
3388 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
3391 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
3396 * t4_prep_adapter - prepare SW and HW for operation
3397 * @adapter: the adapter
3399 * Initialize adapter SW state for the various HW modules, set initial
3400 * values for some adapter tunables, take PHYs out of reset, and
3401 * initialize the MDIO interface.
3403 int t4_prep_adapter(struct adapter *adapter)
3408 ret = t4_wait_dev_ready(adapter);
3412 pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
3413 adapter->params.pci.device_id = adapter->pdev->id.device_id;
3414 adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
3417 * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
3418 * ADAPTER (VERSION << 4 | REVISION)
3420 ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
3421 adapter->params.chip = 0;
3424 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
3425 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
3426 adapter->params.arch.mps_tcam_size =
3427 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
3428 adapter->params.arch.mps_rplc_size = 128;
3429 adapter->params.arch.nchan = NCHAN;
3430 adapter->params.arch.vfcount = 128;
3433 dev_err(adapter, "%s: Device %d is not supported\n",
3434 __func__, adapter->params.pci.device_id);
3438 adapter->params.pci.vpd_cap_addr =
3439 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
3441 ret = t4_get_flash_params(adapter);
3445 adapter->params.cim_la_size = CIMLA_SIZE;
3447 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3450 * Default port and clock for debugging in case we can't reach FW.
3452 adapter->params.nports = 1;
3453 adapter->params.portvec = 1;
3454 adapter->params.vpd.cclk = 50000;
3456 /* Set pci completion timeout value to 4 seconds. */
3457 set_pcie_completion_timeout(adapter, 0xd);
3462 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
3463 * @adapter: the adapter
3464 * @qid: the Queue ID
3465 * @qtype: the Ingress or Egress type for @qid
3466 * @pbar2_qoffset: BAR2 Queue Offset
3467 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
3469 * Returns the BAR2 SGE Queue Registers information associated with the
3470 * indicated Absolute Queue ID. These are passed back in return value
3471 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
3472 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
3474 * This may return an error which indicates that BAR2 SGE Queue
3475 * registers aren't available. If an error is not returned, then the
3476 * following values are returned:
3478 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
3479 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
3481 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
3482 * require the "Inferred Queue ID" ability may be used. E.g. the
3483 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
3484 * then these "Inferred Queue ID" register may not be used.
3486 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
3487 enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
3488 unsigned int *pbar2_qid)
3490 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
3491 u64 bar2_page_offset, bar2_qoffset;
3492 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
3495 * T4 doesn't support BAR2 SGE Queue registers.
3497 if (is_t4(adapter->params.chip))
3501 * Get our SGE Page Size parameters.
3503 page_shift = adapter->params.sge.hps + 10;
3504 page_size = 1 << page_shift;
3507 * Get the right Queues per Page parameters for our Queue.
3509 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
3510 adapter->params.sge.eq_qpp :
3511 adapter->params.sge.iq_qpp);
3512 qpp_mask = (1 << qpp_shift) - 1;
3515 * Calculate the basics of the BAR2 SGE Queue register area:
3516 * o The BAR2 page the Queue registers will be in.
3517 * o The BAR2 Queue ID.
3518 * o The BAR2 Queue ID Offset into the BAR2 page.
3520 bar2_page_offset = ((qid >> qpp_shift) << page_shift);
3521 bar2_qid = qid & qpp_mask;
3522 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
3525 * If the BAR2 Queue ID Offset is less than the Page Size, then the
3526 * hardware will infer the Absolute Queue ID simply from the writes to
3527 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
3528 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
3529 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
3530 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
3531 * from the BAR2 Page and BAR2 Queue ID.
3533 * One important censequence of this is that some BAR2 SGE registers
3534 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
3535 * there. But other registers synthesize the SGE Queue ID purely
3536 * from the writes to the registers -- the Write Combined Doorbell
3537 * Buffer is a good example. These BAR2 SGE Registers are only
3538 * available for those BAR2 SGE Register areas where the SGE Absolute
3539 * Queue ID can be inferred from simple writes.
3541 bar2_qoffset = bar2_page_offset;
3542 bar2_qinferred = (bar2_qid_offset < page_size);
3543 if (bar2_qinferred) {
3544 bar2_qoffset += bar2_qid_offset;
3548 *pbar2_qoffset = bar2_qoffset;
3549 *pbar2_qid = bar2_qid;
3554 * t4_init_sge_params - initialize adap->params.sge
3555 * @adapter: the adapter
3557 * Initialize various fields of the adapter's SGE Parameters structure.
3559 int t4_init_sge_params(struct adapter *adapter)
3561 struct sge_params *sge_params = &adapter->params.sge;
3563 unsigned int s_hps, s_qpp;
3566 * Extract the SGE Page Size for our PF.
3568 hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
3569 s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
3571 sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
3574 * Extract the SGE Egress and Ingess Queues Per Page for our PF.
3576 s_qpp = (S_QUEUESPERPAGEPF0 +
3577 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
3578 qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
3579 sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
3580 qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
3581 sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
3587 * t4_init_tp_params - initialize adap->params.tp
3588 * @adap: the adapter
3590 * Initialize various fields of the adapter's TP Parameters structure.
3592 int t4_init_tp_params(struct adapter *adap)
3597 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
3598 adap->params.tp.tre = G_TIMERRESOLUTION(v);
3599 adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
3601 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
3602 for (chan = 0; chan < NCHAN; chan++)
3603 adap->params.tp.tx_modq[chan] = chan;
3606 * Cache the adapter's Compressed Filter Mode and global Incress
3609 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
3610 &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
3611 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
3612 &adap->params.tp.ingress_config, 1,
3613 A_TP_INGRESS_CONFIG);
3616 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
3617 * shift positions of several elements of the Compressed Filter Tuple
3618 * for this adapter which we need frequently ...
3620 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
3621 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
3622 adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
3623 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
3627 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
3628 * represents the presense of an Outer VLAN instead of a VNIC ID.
3630 if ((adap->params.tp.ingress_config & F_VNIC) == 0)
3631 adap->params.tp.vnic_shift = -1;
3637 * t4_filter_field_shift - calculate filter field shift
3638 * @adap: the adapter
3639 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
3641 * Return the shift position of a filter field within the Compressed
3642 * Filter Tuple. The filter field is specified via its selection bit
3643 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
3645 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
3647 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
3651 if ((filter_mode & filter_sel) == 0)
3654 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
3655 switch (filter_mode & sel) {
3657 field_shift += W_FT_FCOE;
3660 field_shift += W_FT_PORT;
3663 field_shift += W_FT_VNIC_ID;
3666 field_shift += W_FT_VLAN;
3669 field_shift += W_FT_TOS;
3672 field_shift += W_FT_PROTOCOL;
3675 field_shift += W_FT_ETHERTYPE;
3678 field_shift += W_FT_MACMATCH;
3681 field_shift += W_FT_MPSHITTYPE;
3683 case F_FRAGMENTATION:
3684 field_shift += W_FT_FRAGMENTATION;
3691 int t4_init_rss_mode(struct adapter *adap, int mbox)
3694 struct fw_rss_vi_config_cmd rvc;
3696 memset(&rvc, 0, sizeof(rvc));
3698 for_each_port(adap, i) {
3699 struct port_info *p = adap2pinfo(adap, i);
3701 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
3702 F_FW_CMD_REQUEST | F_FW_CMD_READ |
3703 V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
3704 rvc.retval_len16 = htonl(FW_LEN16(rvc));
3705 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
3708 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
3713 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
3717 struct fw_port_cmd c;
3719 memset(&c, 0, sizeof(c));
3721 for_each_port(adap, i) {
3722 unsigned int rss_size = 0;
3723 struct port_info *p = adap2pinfo(adap, i);
3725 while ((adap->params.portvec & (1 << j)) == 0)
3728 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3729 F_FW_CMD_REQUEST | F_FW_CMD_READ |
3730 V_FW_PORT_CMD_PORTID(j));
3731 c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
3732 FW_PORT_ACTION_GET_PORT_INFO) |
3734 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3738 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
3744 p->rss_size = rss_size;
3745 t4_os_set_hw_addr(adap, i, addr);
3747 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
3748 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
3749 G_FW_PORT_CMD_MDIOADDR(ret) : -1;
3750 p->port_type = G_FW_PORT_CMD_PTYPE(ret);
3751 p->mod_type = FW_PORT_MOD_TYPE_NA;
3753 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));