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34 #include <sys/queue.h>
44 #include <rte_interrupts.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
48 #include <rte_debug.h>
50 #include <rte_memory.h>
51 #include <rte_memcpy.h>
52 #include <rte_memzone.h>
53 #include <rte_launch.h>
55 #include <rte_per_lcore.h>
56 #include <rte_lcore.h>
57 #include <rte_atomic.h>
58 #include <rte_branch_prediction.h>
59 #include <rte_mempool.h>
60 #include <rte_malloc.h>
62 #include <rte_ether.h>
63 #include <rte_ethdev.h>
64 #include <rte_prefetch.h>
69 #include <rte_string_fns.h>
71 #include "e1000_logs.h"
72 #include "base/e1000_api.h"
73 #include "e1000_ethdev.h"
74 #include "base/e1000_osdep.h"
76 #define E1000_TXD_VLAN_SHIFT 16
78 #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
81 * Structure associated with each descriptor of the RX ring of a RX queue.
84 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
88 * Structure associated with each descriptor of the TX ring of a TX queue.
91 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
92 uint16_t next_id; /**< Index of next descriptor in ring. */
93 uint16_t last_id; /**< Index of last scattered descriptor. */
97 * Structure associated with each RX queue.
100 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
101 volatile struct e1000_rx_desc *rx_ring; /**< RX ring virtual address. */
102 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
103 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
104 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
105 struct em_rx_entry *sw_ring; /**< address of RX software ring. */
106 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
107 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
108 uint16_t nb_rx_desc; /**< number of RX descriptors. */
109 uint16_t rx_tail; /**< current value of RDT register. */
110 uint16_t nb_rx_hold; /**< number of held free RX desc. */
111 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
112 uint16_t queue_id; /**< RX queue index. */
113 uint8_t port_id; /**< Device port identifier. */
114 uint8_t pthresh; /**< Prefetch threshold register. */
115 uint8_t hthresh; /**< Host threshold register. */
116 uint8_t wthresh; /**< Write-back threshold register. */
117 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
121 * Hardware context number
124 EM_CTX_0 = 0, /**< CTX0 */
125 EM_CTX_NUM = 1, /**< CTX NUM */
128 /** Offload features */
129 union em_vlan_macip {
132 uint16_t l3_len:9; /**< L3 (IP) Header Length. */
133 uint16_t l2_len:7; /**< L2 (MAC) Header Length. */
135 /**< VLAN Tag Control Identifier (CPU order). */
140 * Compare mask for vlan_macip_len.data,
141 * should be in sync with em_vlan_macip.f layout.
143 #define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */
144 #define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */
145 #define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */
146 /** MAC+IP length. */
147 #define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK)
150 * Structure to check if new context need be built
153 uint64_t flags; /**< ol_flags related to context build. */
154 uint32_t cmp_mask; /**< compare mask */
155 union em_vlan_macip hdrlen; /**< L2 and L3 header lenghts */
159 * Structure associated with each TX queue.
162 volatile struct e1000_data_desc *tx_ring; /**< TX ring address */
163 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
164 struct em_tx_entry *sw_ring; /**< virtual address of SW ring. */
165 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
166 uint16_t nb_tx_desc; /**< number of TX descriptors. */
167 uint16_t tx_tail; /**< Current value of TDT register. */
168 /**< Start freeing TX buffers if there are less free descriptors than
170 uint16_t tx_free_thresh;
171 /**< Number of TX descriptors to use before RS bit is set. */
172 uint16_t tx_rs_thresh;
173 /** Number of TX descriptors used since RS bit was set. */
175 /** Index to last TX descriptor to have been cleaned. */
176 uint16_t last_desc_cleaned;
177 /** Total number of TX descriptors ready to be allocated. */
179 uint16_t queue_id; /**< TX queue index. */
180 uint8_t port_id; /**< Device port identifier. */
181 uint8_t pthresh; /**< Prefetch threshold register. */
182 uint8_t hthresh; /**< Host threshold register. */
183 uint8_t wthresh; /**< Write-back threshold register. */
184 struct em_ctx_info ctx_cache;
185 /**< Hardware context history.*/
189 #define RTE_PMD_USE_PREFETCH
192 #ifdef RTE_PMD_USE_PREFETCH
193 #define rte_em_prefetch(p) rte_prefetch0(p)
195 #define rte_em_prefetch(p) do {} while(0)
198 #ifdef RTE_PMD_PACKET_PREFETCH
199 #define rte_packet_prefetch(p) rte_prefetch1(p)
201 #define rte_packet_prefetch(p) do {} while(0)
204 #ifndef DEFAULT_TX_FREE_THRESH
205 #define DEFAULT_TX_FREE_THRESH 32
206 #endif /* DEFAULT_TX_FREE_THRESH */
208 #ifndef DEFAULT_TX_RS_THRESH
209 #define DEFAULT_TX_RS_THRESH 32
210 #endif /* DEFAULT_TX_RS_THRESH */
213 /*********************************************************************
217 **********************************************************************/
220 * Populates TX context descriptor.
223 em_set_xmit_ctx(struct em_tx_queue* txq,
224 volatile struct e1000_context_desc *ctx_txd,
226 union em_vlan_macip hdrlen)
228 uint32_t cmp_mask, cmd_len;
229 uint16_t ipcse, l2len;
230 struct e1000_context_desc ctx;
233 cmd_len = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C;
235 l2len = hdrlen.f.l2_len;
236 ipcse = (uint16_t)(l2len + hdrlen.f.l3_len);
238 /* setup IPCS* fields */
239 ctx.lower_setup.ip_fields.ipcss = (uint8_t)l2len;
240 ctx.lower_setup.ip_fields.ipcso = (uint8_t)(l2len +
241 offsetof(struct ipv4_hdr, hdr_checksum));
244 * When doing checksum or TCP segmentation with IPv6 headers,
245 * IPCSE field should be set t0 0.
247 if (flags & PKT_TX_IP_CKSUM) {
248 ctx.lower_setup.ip_fields.ipcse =
249 (uint16_t)rte_cpu_to_le_16(ipcse - 1);
250 cmd_len |= E1000_TXD_CMD_IP;
251 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
253 ctx.lower_setup.ip_fields.ipcse = 0;
256 /* setup TUCS* fields */
257 ctx.upper_setup.tcp_fields.tucss = (uint8_t)ipcse;
258 ctx.upper_setup.tcp_fields.tucse = 0;
260 switch (flags & PKT_TX_L4_MASK) {
261 case PKT_TX_UDP_CKSUM:
262 ctx.upper_setup.tcp_fields.tucso = (uint8_t)(ipcse +
263 offsetof(struct udp_hdr, dgram_cksum));
264 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
266 case PKT_TX_TCP_CKSUM:
267 ctx.upper_setup.tcp_fields.tucso = (uint8_t)(ipcse +
268 offsetof(struct tcp_hdr, cksum));
269 cmd_len |= E1000_TXD_CMD_TCP;
270 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
273 ctx.upper_setup.tcp_fields.tucso = 0;
276 ctx.cmd_and_length = rte_cpu_to_le_32(cmd_len);
277 ctx.tcp_seg_setup.data = 0;
281 txq->ctx_cache.flags = flags;
282 txq->ctx_cache.cmp_mask = cmp_mask;
283 txq->ctx_cache.hdrlen = hdrlen;
287 * Check which hardware context can be used. Use the existing match
288 * or create a new context descriptor.
290 static inline uint32_t
291 what_ctx_update(struct em_tx_queue *txq, uint64_t flags,
292 union em_vlan_macip hdrlen)
294 /* If match with the current context */
295 if (likely (txq->ctx_cache.flags == flags &&
296 ((txq->ctx_cache.hdrlen.data ^ hdrlen.data) &
297 txq->ctx_cache.cmp_mask) == 0))
304 /* Reset transmit descriptors after they have been used */
306 em_xmit_cleanup(struct em_tx_queue *txq)
308 struct em_tx_entry *sw_ring = txq->sw_ring;
309 volatile struct e1000_data_desc *txr = txq->tx_ring;
310 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
311 uint16_t nb_tx_desc = txq->nb_tx_desc;
312 uint16_t desc_to_clean_to;
313 uint16_t nb_tx_to_clean;
315 /* Determine the last descriptor needing to be cleaned */
316 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
317 if (desc_to_clean_to >= nb_tx_desc)
318 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
320 /* Check to make sure the last descriptor to clean is done */
321 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
322 if (! (txr[desc_to_clean_to].upper.fields.status & E1000_TXD_STAT_DD))
324 PMD_TX_FREE_LOG(DEBUG,
325 "TX descriptor %4u is not done"
326 "(port=%d queue=%d)", desc_to_clean_to,
327 txq->port_id, txq->queue_id);
328 /* Failed to clean any descriptors, better luck next time */
332 /* Figure out how many descriptors will be cleaned */
333 if (last_desc_cleaned > desc_to_clean_to)
334 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
337 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
340 PMD_TX_FREE_LOG(DEBUG,
341 "Cleaning %4u TX descriptors: %4u to %4u "
342 "(port=%d queue=%d)", nb_tx_to_clean,
343 last_desc_cleaned, desc_to_clean_to, txq->port_id,
347 * The last descriptor to clean is done, so that means all the
348 * descriptors from the last descriptor that was cleaned
349 * up to the last descriptor with the RS bit set
350 * are done. Only reset the threshold descriptor.
352 txr[desc_to_clean_to].upper.fields.status = 0;
354 /* Update the txq to reflect the last descriptor that was cleaned */
355 txq->last_desc_cleaned = desc_to_clean_to;
356 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
362 static inline uint32_t
363 tx_desc_cksum_flags_to_upper(uint64_t ol_flags)
365 static const uint32_t l4_olinfo[2] = {0, E1000_TXD_POPTS_TXSM << 8};
366 static const uint32_t l3_olinfo[2] = {0, E1000_TXD_POPTS_IXSM << 8};
369 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
370 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
375 eth_em_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
378 struct em_tx_queue *txq;
379 struct em_tx_entry *sw_ring;
380 struct em_tx_entry *txe, *txn;
381 volatile struct e1000_data_desc *txr;
382 volatile struct e1000_data_desc *txd;
383 struct rte_mbuf *tx_pkt;
384 struct rte_mbuf *m_seg;
385 uint64_t buf_dma_addr;
387 uint32_t cmd_type_len;
397 union em_vlan_macip hdrlen;
400 sw_ring = txq->sw_ring;
402 tx_id = txq->tx_tail;
403 txe = &sw_ring[tx_id];
405 /* Determine if the descriptor ring needs to be cleaned. */
406 if (txq->nb_tx_free < txq->tx_free_thresh)
407 em_xmit_cleanup(txq);
410 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
414 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
417 * Determine how many (if any) context descriptors
418 * are needed for offload functionality.
420 ol_flags = tx_pkt->ol_flags;
422 /* If hardware offload required */
423 tx_ol_req = (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK));
425 hdrlen.f.vlan_tci = tx_pkt->vlan_tci;
426 hdrlen.f.l2_len = tx_pkt->l2_len;
427 hdrlen.f.l3_len = tx_pkt->l3_len;
428 /* If new context to be built or reuse the exist ctx. */
429 ctx = what_ctx_update(txq, tx_ol_req, hdrlen);
431 /* Only allocate context descriptor if required*/
432 new_ctx = (ctx == EM_CTX_NUM);
436 * Keep track of how many descriptors are used this loop
437 * This will always be the number of segments + the number of
438 * Context descriptors required to transmit the packet
440 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
443 * The number of descriptors that must be allocated for a
444 * packet is the number of segments of that packet, plus 1
445 * Context Descriptor for the hardware offload, if any.
446 * Determine the last TX descriptor to allocate in the TX ring
447 * for the packet, starting from the current position (tx_id)
450 tx_last = (uint16_t) (tx_id + nb_used - 1);
453 if (tx_last >= txq->nb_tx_desc)
454 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
456 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
457 " tx_first=%u tx_last=%u",
458 (unsigned) txq->port_id,
459 (unsigned) txq->queue_id,
460 (unsigned) tx_pkt->pkt_len,
465 * Make sure there are enough TX descriptors available to
466 * transmit the entire packet.
467 * nb_used better be less than or equal to txq->tx_rs_thresh
469 while (unlikely (nb_used > txq->nb_tx_free)) {
470 PMD_TX_FREE_LOG(DEBUG, "Not enough free TX descriptors "
471 "nb_used=%4u nb_free=%4u "
472 "(port=%d queue=%d)",
473 nb_used, txq->nb_tx_free,
474 txq->port_id, txq->queue_id);
476 if (em_xmit_cleanup(txq) != 0) {
477 /* Could not clean any descriptors */
485 * By now there are enough free TX descriptors to transmit
490 * Set common flags of all TX Data Descriptors.
492 * The following bits must be set in all Data Descriptors:
493 * - E1000_TXD_DTYP_DATA
494 * - E1000_TXD_DTYP_DEXT
496 * The following bits must be set in the first Data Descriptor
497 * and are ignored in the other ones:
498 * - E1000_TXD_POPTS_IXSM
499 * - E1000_TXD_POPTS_TXSM
501 * The following bits must be set in the last Data Descriptor
502 * and are ignored in the other ones:
503 * - E1000_TXD_CMD_VLE
504 * - E1000_TXD_CMD_IFCS
506 * The following bits must only be set in the last Data
508 * - E1000_TXD_CMD_EOP
510 * The following bits can be set in any Data Descriptor, but
511 * are only set in the last Data Descriptor:
514 cmd_type_len = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
518 /* Set VLAN Tag offload fields. */
519 if (ol_flags & PKT_TX_VLAN_PKT) {
520 cmd_type_len |= E1000_TXD_CMD_VLE;
521 popts_spec = tx_pkt->vlan_tci << E1000_TXD_VLAN_SHIFT;
526 * Setup the TX Context Descriptor if required
529 volatile struct e1000_context_desc *ctx_txd;
531 ctx_txd = (volatile struct e1000_context_desc *)
534 txn = &sw_ring[txe->next_id];
535 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
537 if (txe->mbuf != NULL) {
538 rte_pktmbuf_free_seg(txe->mbuf);
542 em_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
545 txe->last_id = tx_last;
546 tx_id = txe->next_id;
551 * Setup the TX Data Descriptor,
552 * This path will go through
553 * whatever new/reuse the context descriptor
555 popts_spec |= tx_desc_cksum_flags_to_upper(ol_flags);
561 txn = &sw_ring[txe->next_id];
563 if (txe->mbuf != NULL)
564 rte_pktmbuf_free_seg(txe->mbuf);
568 * Set up Transmit Data Descriptor.
570 slen = m_seg->data_len;
571 buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
573 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
574 txd->lower.data = rte_cpu_to_le_32(cmd_type_len | slen);
575 txd->upper.data = rte_cpu_to_le_32(popts_spec);
577 txe->last_id = tx_last;
578 tx_id = txe->next_id;
581 } while (m_seg != NULL);
584 * The last packet data descriptor needs End Of Packet (EOP)
586 cmd_type_len |= E1000_TXD_CMD_EOP;
587 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
588 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
590 /* Set RS bit only on threshold packets' last descriptor */
591 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
592 PMD_TX_FREE_LOG(DEBUG,
593 "Setting RS bit on TXD id=%4u "
594 "(port=%d queue=%d)",
595 tx_last, txq->port_id, txq->queue_id);
597 cmd_type_len |= E1000_TXD_CMD_RS;
599 /* Update txq RS bit counters */
602 txd->lower.data |= rte_cpu_to_le_32(cmd_type_len);
608 * Set the Transmit Descriptor Tail (TDT)
610 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
611 (unsigned) txq->port_id, (unsigned) txq->queue_id,
612 (unsigned) tx_id, (unsigned) nb_tx);
613 E1000_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
614 txq->tx_tail = tx_id;
619 /*********************************************************************
623 **********************************************************************/
625 static inline uint64_t
626 rx_desc_status_to_pkt_flags(uint32_t rx_status)
630 /* Check if VLAN present */
631 pkt_flags = ((rx_status & E1000_RXD_STAT_VP) ?
632 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED : 0);
637 static inline uint64_t
638 rx_desc_error_to_pkt_flags(uint32_t rx_error)
640 uint64_t pkt_flags = 0;
642 if (rx_error & E1000_RXD_ERR_IPE)
643 pkt_flags |= PKT_RX_IP_CKSUM_BAD;
644 if (rx_error & E1000_RXD_ERR_TCPE)
645 pkt_flags |= PKT_RX_L4_CKSUM_BAD;
650 eth_em_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
653 volatile struct e1000_rx_desc *rx_ring;
654 volatile struct e1000_rx_desc *rxdp;
655 struct em_rx_queue *rxq;
656 struct em_rx_entry *sw_ring;
657 struct em_rx_entry *rxe;
658 struct rte_mbuf *rxm;
659 struct rte_mbuf *nmb;
660 struct e1000_rx_desc rxd;
672 rx_id = rxq->rx_tail;
673 rx_ring = rxq->rx_ring;
674 sw_ring = rxq->sw_ring;
675 while (nb_rx < nb_pkts) {
677 * The order of operations here is important as the DD status
678 * bit must not be read after any other descriptor fields.
679 * rx_ring and rxdp are pointing to volatile data so the order
680 * of accesses cannot be reordered by the compiler. If they were
681 * not volatile, they could be reordered which could lead to
682 * using invalid descriptor fields when read from rxd.
684 rxdp = &rx_ring[rx_id];
685 status = rxdp->status;
686 if (! (status & E1000_RXD_STAT_DD))
693 * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is
694 * likely to be invalid and to be dropped by the various
695 * validation checks performed by the network stack.
697 * Allocate a new mbuf to replenish the RX ring descriptor.
698 * If the allocation fails:
699 * - arrange for that RX descriptor to be the first one
700 * being parsed the next time the receive function is
701 * invoked [on the same queue].
703 * - Stop parsing the RX ring and return immediately.
705 * This policy do not drop the packet received in the RX
706 * descriptor for which the allocation of a new mbuf failed.
707 * Thus, it allows that packet to be later retrieved if
708 * mbuf have been freed in the mean time.
709 * As a side effect, holding RX descriptors instead of
710 * systematically giving them back to the NIC may lead to
711 * RX ring exhaustion situations.
712 * However, the NIC can gracefully prevent such situations
713 * to happen by sending specific "back-pressure" flow control
714 * frames to its peer(s).
716 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
717 "status=0x%x pkt_len=%u",
718 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
719 (unsigned) rx_id, (unsigned) status,
720 (unsigned) rte_le_to_cpu_16(rxd.length));
722 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
724 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
726 (unsigned) rxq->port_id,
727 (unsigned) rxq->queue_id);
728 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
733 rxe = &sw_ring[rx_id];
735 if (rx_id == rxq->nb_rx_desc)
738 /* Prefetch next mbuf while processing current one. */
739 rte_em_prefetch(sw_ring[rx_id].mbuf);
742 * When next RX descriptor is on a cache-line boundary,
743 * prefetch the next 4 RX descriptors and the next 8 pointers
746 if ((rx_id & 0x3) == 0) {
747 rte_em_prefetch(&rx_ring[rx_id]);
748 rte_em_prefetch(&sw_ring[rx_id]);
751 /* Rearm RXD: attach new mbuf and reset status to zero. */
756 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
757 rxdp->buffer_addr = dma_addr;
761 * Initialize the returned mbuf.
762 * 1) setup generic mbuf fields:
763 * - number of segments,
766 * - RX port identifier.
767 * 2) integrate hardware offload data, if any:
769 * - IP checksum flag,
770 * - VLAN TCI, if any,
773 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.length) -
775 rxm->data_off = RTE_PKTMBUF_HEADROOM;
776 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
779 rxm->pkt_len = pkt_len;
780 rxm->data_len = pkt_len;
781 rxm->port = rxq->port_id;
783 rxm->ol_flags = rx_desc_status_to_pkt_flags(status);
784 rxm->ol_flags = rxm->ol_flags |
785 rx_desc_error_to_pkt_flags(rxd.errors);
787 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
788 rxm->vlan_tci = rte_le_to_cpu_16(rxd.special);
791 * Store the mbuf address into the next entry of the array
792 * of returned packets.
794 rx_pkts[nb_rx++] = rxm;
796 rxq->rx_tail = rx_id;
799 * If the number of free RX descriptors is greater than the RX free
800 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
802 * Update the RDT with the value of the last processed RX descriptor
803 * minus 1, to guarantee that the RDT register is never equal to the
804 * RDH register, which creates a "full" ring situtation from the
805 * hardware point of view...
807 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
808 if (nb_hold > rxq->rx_free_thresh) {
809 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
810 "nb_hold=%u nb_rx=%u",
811 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
812 (unsigned) rx_id, (unsigned) nb_hold,
814 rx_id = (uint16_t) ((rx_id == 0) ?
815 (rxq->nb_rx_desc - 1) : (rx_id - 1));
816 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
819 rxq->nb_rx_hold = nb_hold;
824 eth_em_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
827 struct em_rx_queue *rxq;
828 volatile struct e1000_rx_desc *rx_ring;
829 volatile struct e1000_rx_desc *rxdp;
830 struct em_rx_entry *sw_ring;
831 struct em_rx_entry *rxe;
832 struct rte_mbuf *first_seg;
833 struct rte_mbuf *last_seg;
834 struct rte_mbuf *rxm;
835 struct rte_mbuf *nmb;
836 struct e1000_rx_desc rxd;
837 uint64_t dma; /* Physical address of mbuf data buffer */
848 rx_id = rxq->rx_tail;
849 rx_ring = rxq->rx_ring;
850 sw_ring = rxq->sw_ring;
853 * Retrieve RX context of current packet, if any.
855 first_seg = rxq->pkt_first_seg;
856 last_seg = rxq->pkt_last_seg;
858 while (nb_rx < nb_pkts) {
861 * The order of operations here is important as the DD status
862 * bit must not be read after any other descriptor fields.
863 * rx_ring and rxdp are pointing to volatile data so the order
864 * of accesses cannot be reordered by the compiler. If they were
865 * not volatile, they could be reordered which could lead to
866 * using invalid descriptor fields when read from rxd.
868 rxdp = &rx_ring[rx_id];
869 status = rxdp->status;
870 if (! (status & E1000_RXD_STAT_DD))
877 * Allocate a new mbuf to replenish the RX ring descriptor.
878 * If the allocation fails:
879 * - arrange for that RX descriptor to be the first one
880 * being parsed the next time the receive function is
881 * invoked [on the same queue].
883 * - Stop parsing the RX ring and return immediately.
885 * This policy does not drop the packet received in the RX
886 * descriptor for which the allocation of a new mbuf failed.
887 * Thus, it allows that packet to be later retrieved if
888 * mbuf have been freed in the mean time.
889 * As a side effect, holding RX descriptors instead of
890 * systematically giving them back to the NIC may lead to
891 * RX ring exhaustion situations.
892 * However, the NIC can gracefully prevent such situations
893 * to happen by sending specific "back-pressure" flow control
894 * frames to its peer(s).
896 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
897 "status=0x%x data_len=%u",
898 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
899 (unsigned) rx_id, (unsigned) status,
900 (unsigned) rte_le_to_cpu_16(rxd.length));
902 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
904 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
905 "queue_id=%u", (unsigned) rxq->port_id,
906 (unsigned) rxq->queue_id);
907 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
912 rxe = &sw_ring[rx_id];
914 if (rx_id == rxq->nb_rx_desc)
917 /* Prefetch next mbuf while processing current one. */
918 rte_em_prefetch(sw_ring[rx_id].mbuf);
921 * When next RX descriptor is on a cache-line boundary,
922 * prefetch the next 4 RX descriptors and the next 8 pointers
925 if ((rx_id & 0x3) == 0) {
926 rte_em_prefetch(&rx_ring[rx_id]);
927 rte_em_prefetch(&sw_ring[rx_id]);
931 * Update RX descriptor with the physical address of the new
932 * data buffer of the new allocated mbuf.
936 dma = rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
937 rxdp->buffer_addr = dma;
941 * Set data length & data buffer address of mbuf.
943 data_len = rte_le_to_cpu_16(rxd.length);
944 rxm->data_len = data_len;
945 rxm->data_off = RTE_PKTMBUF_HEADROOM;
948 * If this is the first buffer of the received packet,
949 * set the pointer to the first mbuf of the packet and
950 * initialize its context.
951 * Otherwise, update the total length and the number of segments
952 * of the current scattered packet, and update the pointer to
953 * the last mbuf of the current packet.
955 if (first_seg == NULL) {
957 first_seg->pkt_len = data_len;
958 first_seg->nb_segs = 1;
960 first_seg->pkt_len += data_len;
961 first_seg->nb_segs++;
962 last_seg->next = rxm;
966 * If this is not the last buffer of the received packet,
967 * update the pointer to the last mbuf of the current scattered
968 * packet and continue to parse the RX ring.
970 if (! (status & E1000_RXD_STAT_EOP)) {
976 * This is the last buffer of the received packet.
977 * If the CRC is not stripped by the hardware:
978 * - Subtract the CRC length from the total packet length.
979 * - If the last buffer only contains the whole CRC or a part
980 * of it, free the mbuf associated to the last buffer.
981 * If part of the CRC is also contained in the previous
982 * mbuf, subtract the length of that CRC part from the
983 * data length of the previous mbuf.
986 if (unlikely(rxq->crc_len > 0)) {
987 first_seg->pkt_len -= ETHER_CRC_LEN;
988 if (data_len <= ETHER_CRC_LEN) {
989 rte_pktmbuf_free_seg(rxm);
990 first_seg->nb_segs--;
991 last_seg->data_len = (uint16_t)
992 (last_seg->data_len -
993 (ETHER_CRC_LEN - data_len));
994 last_seg->next = NULL;
997 (uint16_t) (data_len - ETHER_CRC_LEN);
1001 * Initialize the first mbuf of the returned packet:
1002 * - RX port identifier,
1003 * - hardware offload data, if any:
1004 * - IP checksum flag,
1007 first_seg->port = rxq->port_id;
1009 first_seg->ol_flags = rx_desc_status_to_pkt_flags(status);
1010 first_seg->ol_flags = first_seg->ol_flags |
1011 rx_desc_error_to_pkt_flags(rxd.errors);
1013 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1014 rxm->vlan_tci = rte_le_to_cpu_16(rxd.special);
1016 /* Prefetch data of first segment, if configured to do so. */
1017 rte_packet_prefetch((char *)first_seg->buf_addr +
1018 first_seg->data_off);
1021 * Store the mbuf address into the next entry of the array
1022 * of returned packets.
1024 rx_pkts[nb_rx++] = first_seg;
1027 * Setup receipt context for a new packet.
1033 * Record index of the next RX descriptor to probe.
1035 rxq->rx_tail = rx_id;
1038 * Save receive context.
1040 rxq->pkt_first_seg = first_seg;
1041 rxq->pkt_last_seg = last_seg;
1044 * If the number of free RX descriptors is greater than the RX free
1045 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1047 * Update the RDT with the value of the last processed RX descriptor
1048 * minus 1, to guarantee that the RDT register is never equal to the
1049 * RDH register, which creates a "full" ring situtation from the
1050 * hardware point of view...
1052 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1053 if (nb_hold > rxq->rx_free_thresh) {
1054 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1055 "nb_hold=%u nb_rx=%u",
1056 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1057 (unsigned) rx_id, (unsigned) nb_hold,
1059 rx_id = (uint16_t) ((rx_id == 0) ?
1060 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1061 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1064 rxq->nb_rx_hold = nb_hold;
1068 #define EM_MAX_BUF_SIZE 16384
1069 #define EM_RCTL_FLXBUF_STEP 1024
1072 em_tx_queue_release_mbufs(struct em_tx_queue *txq)
1076 if (txq->sw_ring != NULL) {
1077 for (i = 0; i != txq->nb_tx_desc; i++) {
1078 if (txq->sw_ring[i].mbuf != NULL) {
1079 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1080 txq->sw_ring[i].mbuf = NULL;
1087 em_tx_queue_release(struct em_tx_queue *txq)
1090 em_tx_queue_release_mbufs(txq);
1091 rte_free(txq->sw_ring);
1097 eth_em_tx_queue_release(void *txq)
1099 em_tx_queue_release(txq);
1102 /* (Re)set dynamic em_tx_queue fields to defaults */
1104 em_reset_tx_queue(struct em_tx_queue *txq)
1106 uint16_t i, nb_desc, prev;
1107 static const struct e1000_data_desc txd_init = {
1108 .upper.fields = {.status = E1000_TXD_STAT_DD},
1111 nb_desc = txq->nb_tx_desc;
1113 /* Initialize ring entries */
1115 prev = (uint16_t) (nb_desc - 1);
1117 for (i = 0; i < nb_desc; i++) {
1118 txq->tx_ring[i] = txd_init;
1119 txq->sw_ring[i].mbuf = NULL;
1120 txq->sw_ring[i].last_id = i;
1121 txq->sw_ring[prev].next_id = i;
1126 * Always allow 1 descriptor to be un-allocated to avoid
1127 * a H/W race condition
1129 txq->nb_tx_free = (uint16_t)(nb_desc - 1);
1130 txq->last_desc_cleaned = (uint16_t)(nb_desc - 1);
1131 txq->nb_tx_used = 0;
1134 memset((void*)&txq->ctx_cache, 0, sizeof (txq->ctx_cache));
1138 eth_em_tx_queue_setup(struct rte_eth_dev *dev,
1141 unsigned int socket_id,
1142 const struct rte_eth_txconf *tx_conf)
1144 const struct rte_memzone *tz;
1145 struct em_tx_queue *txq;
1146 struct e1000_hw *hw;
1148 uint16_t tx_rs_thresh, tx_free_thresh;
1150 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1153 * Validate number of transmit descriptors.
1154 * It must not exceed hardware maximum, and must be multiple
1157 if (nb_desc % EM_TXD_ALIGN != 0 ||
1158 (nb_desc > E1000_MAX_RING_DESC) ||
1159 (nb_desc < E1000_MIN_RING_DESC)) {
1163 tx_free_thresh = tx_conf->tx_free_thresh;
1164 if (tx_free_thresh == 0)
1165 tx_free_thresh = (uint16_t)RTE_MIN(nb_desc / 4,
1166 DEFAULT_TX_FREE_THRESH);
1168 tx_rs_thresh = tx_conf->tx_rs_thresh;
1169 if (tx_rs_thresh == 0)
1170 tx_rs_thresh = (uint16_t)RTE_MIN(tx_free_thresh,
1171 DEFAULT_TX_RS_THRESH);
1173 if (tx_free_thresh >= (nb_desc - 3)) {
1174 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
1175 "number of TX descriptors minus 3. "
1176 "(tx_free_thresh=%u port=%d queue=%d)",
1177 (unsigned int)tx_free_thresh,
1178 (int)dev->data->port_id, (int)queue_idx);
1181 if (tx_rs_thresh > tx_free_thresh) {
1182 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
1183 "tx_free_thresh. (tx_free_thresh=%u "
1184 "tx_rs_thresh=%u port=%d queue=%d)",
1185 (unsigned int)tx_free_thresh,
1186 (unsigned int)tx_rs_thresh,
1187 (int)dev->data->port_id,
1193 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1194 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1195 * by the NIC and all descriptors are written back after the NIC
1196 * accumulates WTHRESH descriptors.
1198 if (tx_conf->tx_thresh.wthresh != 0 && tx_rs_thresh != 1) {
1199 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1200 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1201 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1202 (int)dev->data->port_id, (int)queue_idx);
1206 /* Free memory prior to re-allocation if needed... */
1207 if (dev->data->tx_queues[queue_idx] != NULL) {
1208 em_tx_queue_release(dev->data->tx_queues[queue_idx]);
1209 dev->data->tx_queues[queue_idx] = NULL;
1213 * Allocate TX ring hardware descriptors. A memzone large enough to
1214 * handle the maximum ring size is allocated in order to allow for
1215 * resizing in later calls to the queue setup function.
1217 tsize = sizeof(txq->tx_ring[0]) * E1000_MAX_RING_DESC;
1218 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx, tsize,
1219 RTE_CACHE_LINE_SIZE, socket_id);
1223 /* Allocate the tx queue data structure. */
1224 if ((txq = rte_zmalloc("ethdev TX queue", sizeof(*txq),
1225 RTE_CACHE_LINE_SIZE)) == NULL)
1228 /* Allocate software ring */
1229 if ((txq->sw_ring = rte_zmalloc("txq->sw_ring",
1230 sizeof(txq->sw_ring[0]) * nb_desc,
1231 RTE_CACHE_LINE_SIZE)) == NULL) {
1232 em_tx_queue_release(txq);
1236 txq->nb_tx_desc = nb_desc;
1237 txq->tx_free_thresh = tx_free_thresh;
1238 txq->tx_rs_thresh = tx_rs_thresh;
1239 txq->pthresh = tx_conf->tx_thresh.pthresh;
1240 txq->hthresh = tx_conf->tx_thresh.hthresh;
1241 txq->wthresh = tx_conf->tx_thresh.wthresh;
1242 txq->queue_id = queue_idx;
1243 txq->port_id = dev->data->port_id;
1245 txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(queue_idx));
1246 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1247 txq->tx_ring = (struct e1000_data_desc *) tz->addr;
1249 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1250 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1252 em_reset_tx_queue(txq);
1254 dev->data->tx_queues[queue_idx] = txq;
1259 em_rx_queue_release_mbufs(struct em_rx_queue *rxq)
1263 if (rxq->sw_ring != NULL) {
1264 for (i = 0; i != rxq->nb_rx_desc; i++) {
1265 if (rxq->sw_ring[i].mbuf != NULL) {
1266 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1267 rxq->sw_ring[i].mbuf = NULL;
1274 em_rx_queue_release(struct em_rx_queue *rxq)
1277 em_rx_queue_release_mbufs(rxq);
1278 rte_free(rxq->sw_ring);
1284 eth_em_rx_queue_release(void *rxq)
1286 em_rx_queue_release(rxq);
1289 /* Reset dynamic em_rx_queue fields back to defaults */
1291 em_reset_rx_queue(struct em_rx_queue *rxq)
1294 rxq->nb_rx_hold = 0;
1295 rxq->pkt_first_seg = NULL;
1296 rxq->pkt_last_seg = NULL;
1300 eth_em_rx_queue_setup(struct rte_eth_dev *dev,
1303 unsigned int socket_id,
1304 const struct rte_eth_rxconf *rx_conf,
1305 struct rte_mempool *mp)
1307 const struct rte_memzone *rz;
1308 struct em_rx_queue *rxq;
1309 struct e1000_hw *hw;
1312 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1315 * Validate number of receive descriptors.
1316 * It must not exceed hardware maximum, and must be multiple
1319 if (nb_desc % EM_RXD_ALIGN != 0 ||
1320 (nb_desc > E1000_MAX_RING_DESC) ||
1321 (nb_desc < E1000_MIN_RING_DESC)) {
1326 * EM devices don't support drop_en functionality.
1327 * It's an optimization that does nothing on single-queue devices,
1328 * so just log the issue and carry on.
1330 if (rx_conf->rx_drop_en) {
1331 PMD_INIT_LOG(NOTICE, "drop_en functionality not supported by "
1335 /* Free memory prior to re-allocation if needed. */
1336 if (dev->data->rx_queues[queue_idx] != NULL) {
1337 em_rx_queue_release(dev->data->rx_queues[queue_idx]);
1338 dev->data->rx_queues[queue_idx] = NULL;
1341 /* Allocate RX ring for max possible mumber of hardware descriptors. */
1342 rsize = sizeof(rxq->rx_ring[0]) * E1000_MAX_RING_DESC;
1343 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, rsize,
1344 RTE_CACHE_LINE_SIZE, socket_id);
1348 /* Allocate the RX queue data structure. */
1349 if ((rxq = rte_zmalloc("ethdev RX queue", sizeof(*rxq),
1350 RTE_CACHE_LINE_SIZE)) == NULL)
1353 /* Allocate software ring. */
1354 if ((rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
1355 sizeof (rxq->sw_ring[0]) * nb_desc,
1356 RTE_CACHE_LINE_SIZE)) == NULL) {
1357 em_rx_queue_release(rxq);
1362 rxq->nb_rx_desc = nb_desc;
1363 rxq->pthresh = rx_conf->rx_thresh.pthresh;
1364 rxq->hthresh = rx_conf->rx_thresh.hthresh;
1365 rxq->wthresh = rx_conf->rx_thresh.wthresh;
1366 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1367 rxq->queue_id = queue_idx;
1368 rxq->port_id = dev->data->port_id;
1369 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1372 rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(queue_idx));
1373 rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(queue_idx));
1374 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1375 rxq->rx_ring = (struct e1000_rx_desc *) rz->addr;
1377 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1378 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
1380 dev->data->rx_queues[queue_idx] = rxq;
1381 em_reset_rx_queue(rxq);
1387 eth_em_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1389 #define EM_RXQ_SCAN_INTERVAL 4
1390 volatile struct e1000_rx_desc *rxdp;
1391 struct em_rx_queue *rxq;
1394 if (rx_queue_id >= dev->data->nb_rx_queues) {
1395 PMD_RX_LOG(DEBUG, "Invalid RX queue_id=%d", rx_queue_id);
1399 rxq = dev->data->rx_queues[rx_queue_id];
1400 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1402 while ((desc < rxq->nb_rx_desc) &&
1403 (rxdp->status & E1000_RXD_STAT_DD)) {
1404 desc += EM_RXQ_SCAN_INTERVAL;
1405 rxdp += EM_RXQ_SCAN_INTERVAL;
1406 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1407 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1408 desc - rxq->nb_rx_desc]);
1415 eth_em_rx_descriptor_done(void *rx_queue, uint16_t offset)
1417 volatile struct e1000_rx_desc *rxdp;
1418 struct em_rx_queue *rxq = rx_queue;
1421 if (unlikely(offset >= rxq->nb_rx_desc))
1423 desc = rxq->rx_tail + offset;
1424 if (desc >= rxq->nb_rx_desc)
1425 desc -= rxq->nb_rx_desc;
1427 rxdp = &rxq->rx_ring[desc];
1428 return !!(rxdp->status & E1000_RXD_STAT_DD);
1432 em_dev_clear_queues(struct rte_eth_dev *dev)
1435 struct em_tx_queue *txq;
1436 struct em_rx_queue *rxq;
1438 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1439 txq = dev->data->tx_queues[i];
1441 em_tx_queue_release_mbufs(txq);
1442 em_reset_tx_queue(txq);
1446 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1447 rxq = dev->data->rx_queues[i];
1449 em_rx_queue_release_mbufs(rxq);
1450 em_reset_rx_queue(rxq);
1456 em_dev_free_queues(struct rte_eth_dev *dev)
1460 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1461 eth_em_rx_queue_release(dev->data->rx_queues[i]);
1462 dev->data->rx_queues[i] = NULL;
1464 dev->data->nb_rx_queues = 0;
1466 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1467 eth_em_tx_queue_release(dev->data->tx_queues[i]);
1468 dev->data->tx_queues[i] = NULL;
1470 dev->data->nb_tx_queues = 0;
1474 * Takes as input/output parameter RX buffer size.
1475 * Returns (BSIZE | BSEX | FLXBUF) fields of RCTL register.
1478 em_rctl_bsize(__rte_unused enum e1000_mac_type hwtyp, uint32_t *bufsz)
1481 * For BSIZE & BSEX all configurable sizes are:
1482 * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);
1483 * 8192: rctl |= (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX);
1484 * 4096: rctl |= (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX);
1485 * 2048: rctl |= E1000_RCTL_SZ_2048;
1486 * 1024: rctl |= E1000_RCTL_SZ_1024;
1487 * 512: rctl |= E1000_RCTL_SZ_512;
1488 * 256: rctl |= E1000_RCTL_SZ_256;
1490 static const struct {
1493 } bufsz_to_rctl[] = {
1494 {16384, (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX)},
1495 {8192, (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX)},
1496 {4096, (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX)},
1497 {2048, E1000_RCTL_SZ_2048},
1498 {1024, E1000_RCTL_SZ_1024},
1499 {512, E1000_RCTL_SZ_512},
1500 {256, E1000_RCTL_SZ_256},
1504 uint32_t rctl_bsize;
1506 rctl_bsize = *bufsz;
1509 * Starting from 82571 it is possible to specify RX buffer size
1510 * by RCTL.FLXBUF. When this field is different from zero, the
1511 * RX buffer size = RCTL.FLXBUF * 1K
1512 * (e.g. t is possible to specify RX buffer size 1,2,...,15KB).
1513 * It is working ok on real HW, but by some reason doesn't work
1514 * on VMware emulated 82574L.
1515 * So for now, always use BSIZE/BSEX to setup RX buffer size.
1516 * If you don't plan to use it on VMware emulated 82574L and
1517 * would like to specify RX buffer size in 1K granularity,
1518 * uncomment the following lines:
1519 * ***************************************************************
1520 * if (hwtyp >= e1000_82571 && hwtyp <= e1000_82574 &&
1521 * rctl_bsize >= EM_RCTL_FLXBUF_STEP) {
1522 * rctl_bsize /= EM_RCTL_FLXBUF_STEP;
1523 * *bufsz = rctl_bsize;
1524 * return (rctl_bsize << E1000_RCTL_FLXBUF_SHIFT &
1525 * E1000_RCTL_FLXBUF_MASK);
1527 * ***************************************************************
1530 for (i = 0; i != sizeof(bufsz_to_rctl) / sizeof(bufsz_to_rctl[0]);
1532 if (rctl_bsize >= bufsz_to_rctl[i].bufsz) {
1533 *bufsz = bufsz_to_rctl[i].bufsz;
1534 return bufsz_to_rctl[i].rctl;
1538 /* Should never happen. */
1543 em_alloc_rx_queue_mbufs(struct em_rx_queue *rxq)
1545 struct em_rx_entry *rxe = rxq->sw_ring;
1548 static const struct e1000_rx_desc rxd_init = {
1552 /* Initialize software ring entries */
1553 for (i = 0; i < rxq->nb_rx_desc; i++) {
1554 volatile struct e1000_rx_desc *rxd;
1555 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
1558 PMD_INIT_LOG(ERR, "RX mbuf alloc failed "
1559 "queue_id=%hu", rxq->queue_id);
1564 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
1566 /* Clear HW ring memory */
1567 rxq->rx_ring[i] = rxd_init;
1569 rxd = &rxq->rx_ring[i];
1570 rxd->buffer_addr = dma_addr;
1577 /*********************************************************************
1579 * Enable receive unit.
1581 **********************************************************************/
1583 eth_em_rx_init(struct rte_eth_dev *dev)
1585 struct e1000_hw *hw;
1586 struct em_rx_queue *rxq;
1590 uint32_t rctl_bsize;
1594 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1597 * Make sure receives are disabled while setting
1598 * up the descriptor ring.
1600 rctl = E1000_READ_REG(hw, E1000_RCTL);
1601 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
1603 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
1605 /* Disable extended descriptor type. */
1606 rfctl &= ~E1000_RFCTL_EXTEN;
1607 /* Disable accelerated acknowledge */
1608 if (hw->mac.type == e1000_82574)
1609 rfctl |= E1000_RFCTL_ACK_DIS;
1611 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
1614 * XXX TEMPORARY WORKAROUND: on some systems with 82573
1615 * long latencies are observed, like Lenovo X60. This
1616 * change eliminates the problem, but since having positive
1617 * values in RDTR is a known source of problems on other
1618 * platforms another solution is being sought.
1620 if (hw->mac.type == e1000_82573)
1621 E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
1623 dev->rx_pkt_burst = (eth_rx_burst_t)eth_em_recv_pkts;
1625 /* Determine RX bufsize. */
1626 rctl_bsize = EM_MAX_BUF_SIZE;
1627 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1630 rxq = dev->data->rx_queues[i];
1631 buf_size = rte_pktmbuf_data_room_size(rxq->mb_pool) -
1632 RTE_PKTMBUF_HEADROOM;
1633 rctl_bsize = RTE_MIN(rctl_bsize, buf_size);
1636 rctl |= em_rctl_bsize(hw->mac.type, &rctl_bsize);
1638 /* Configure and enable each RX queue. */
1639 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1643 rxq = dev->data->rx_queues[i];
1645 /* Allocate buffers for descriptor rings and setup queue */
1646 ret = em_alloc_rx_queue_mbufs(rxq);
1651 * Reset crc_len in case it was changed after queue setup by a
1655 (uint8_t)(dev->data->dev_conf.rxmode.hw_strip_crc ?
1658 bus_addr = rxq->rx_ring_phys_addr;
1659 E1000_WRITE_REG(hw, E1000_RDLEN(i),
1661 sizeof(*rxq->rx_ring));
1662 E1000_WRITE_REG(hw, E1000_RDBAH(i),
1663 (uint32_t)(bus_addr >> 32));
1664 E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
1666 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
1667 E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
1669 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
1670 rxdctl &= 0xFE000000;
1671 rxdctl |= rxq->pthresh & 0x3F;
1672 rxdctl |= (rxq->hthresh & 0x3F) << 8;
1673 rxdctl |= (rxq->wthresh & 0x3F) << 16;
1674 rxdctl |= E1000_RXDCTL_GRAN;
1675 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
1678 * Due to EM devices not having any sort of hardware
1679 * limit for packet length, jumbo frame of any size
1680 * can be accepted, thus we have to enable scattered
1681 * rx if jumbo frames are enabled (or if buffer size
1682 * is too small to accommodate non-jumbo packets)
1683 * to avoid splitting packets that don't fit into
1686 if (dev->data->dev_conf.rxmode.jumbo_frame ||
1687 rctl_bsize < ETHER_MAX_LEN) {
1688 if (!dev->data->scattered_rx)
1689 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
1691 (eth_rx_burst_t)eth_em_recv_scattered_pkts;
1692 dev->data->scattered_rx = 1;
1696 if (dev->data->dev_conf.rxmode.enable_scatter) {
1697 if (!dev->data->scattered_rx)
1698 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
1699 dev->rx_pkt_burst = eth_em_recv_scattered_pkts;
1700 dev->data->scattered_rx = 1;
1704 * Setup the Checksum Register.
1705 * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.
1707 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
1709 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
1710 rxcsum |= E1000_RXCSUM_IPOFL;
1712 rxcsum &= ~E1000_RXCSUM_IPOFL;
1713 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
1715 /* No MRQ or RSS support for now */
1717 /* Set early receive threshold on appropriate hw */
1718 if ((hw->mac.type == e1000_ich9lan ||
1719 hw->mac.type == e1000_pch2lan ||
1720 hw->mac.type == e1000_ich10lan) &&
1721 dev->data->dev_conf.rxmode.jumbo_frame == 1) {
1722 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
1723 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
1724 E1000_WRITE_REG(hw, E1000_ERT, 0x100 | (1 << 13));
1727 if (hw->mac.type == e1000_pch2lan) {
1728 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1729 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE);
1731 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE);
1734 /* Setup the Receive Control Register. */
1735 if (dev->data->dev_conf.rxmode.hw_strip_crc)
1736 rctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */
1738 rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */
1740 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1741 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
1742 E1000_RCTL_RDMTS_HALF |
1743 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1745 /* Make sure VLAN Filters are off. */
1746 rctl &= ~E1000_RCTL_VFE;
1747 /* Don't store bad packets. */
1748 rctl &= ~E1000_RCTL_SBP;
1749 /* Legacy descriptor type. */
1750 rctl &= ~E1000_RCTL_DTYP_MASK;
1753 * Configure support of jumbo frames, if any.
1755 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1756 rctl |= E1000_RCTL_LPE;
1758 rctl &= ~E1000_RCTL_LPE;
1760 /* Enable Receives. */
1761 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1766 /*********************************************************************
1768 * Enable transmit unit.
1770 **********************************************************************/
1772 eth_em_tx_init(struct rte_eth_dev *dev)
1774 struct e1000_hw *hw;
1775 struct em_tx_queue *txq;
1780 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1782 /* Setup the Base and Length of the Tx Descriptor Rings. */
1783 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1786 txq = dev->data->tx_queues[i];
1787 bus_addr = txq->tx_ring_phys_addr;
1788 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1790 sizeof(*txq->tx_ring));
1791 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1792 (uint32_t)(bus_addr >> 32));
1793 E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
1795 /* Setup the HW Tx Head and Tail descriptor pointers. */
1796 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1797 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1799 /* Setup Transmit threshold registers. */
1800 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
1802 * bit 22 is reserved, on some models should always be 0,
1803 * on others - always 1.
1805 txdctl &= E1000_TXDCTL_COUNT_DESC;
1806 txdctl |= txq->pthresh & 0x3F;
1807 txdctl |= (txq->hthresh & 0x3F) << 8;
1808 txdctl |= (txq->wthresh & 0x3F) << 16;
1809 txdctl |= E1000_TXDCTL_GRAN;
1810 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1813 /* Program the Transmit Control Register. */
1814 tctl = E1000_READ_REG(hw, E1000_TCTL);
1815 tctl &= ~E1000_TCTL_CT;
1816 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1817 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1819 /* This write will effectively turn on the transmit unit. */
1820 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1824 em_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1825 struct rte_eth_rxq_info *qinfo)
1827 struct em_rx_queue *rxq;
1829 rxq = dev->data->rx_queues[queue_id];
1831 qinfo->mp = rxq->mb_pool;
1832 qinfo->scattered_rx = dev->data->scattered_rx;
1833 qinfo->nb_desc = rxq->nb_rx_desc;
1834 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1838 em_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1839 struct rte_eth_txq_info *qinfo)
1841 struct em_tx_queue *txq;
1843 txq = dev->data->tx_queues[queue_id];
1845 qinfo->nb_desc = txq->nb_tx_desc;
1847 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1848 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1849 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1850 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1851 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;