4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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18 * contributors may be used to endorse or promote products derived
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
61 * Default values for port configuration
63 #define IGB_DEFAULT_RX_FREE_THRESH 32
65 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
66 #define IGB_DEFAULT_RX_HTHRESH 8
67 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
69 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
70 #define IGB_DEFAULT_TX_HTHRESH 1
71 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
73 #define IGB_HKEY_MAX_INDEX 10
75 /* Bit shift and mask */
76 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
77 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
78 #define IGB_8_BIT_WIDTH CHAR_BIT
79 #define IGB_8_BIT_MASK UINT8_MAX
81 /* Additional timesync values. */
82 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
83 #define E1000_ETQF_FILTER_1588 3
84 #define IGB_82576_TSYNC_SHIFT 16
85 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
86 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
89 #define E1000_VTIVAR_MISC 0x01740
90 #define E1000_VTIVAR_MISC_MASK 0xFF
91 #define E1000_VTIVAR_VALID 0x80
92 #define E1000_VTIVAR_MISC_MAILBOX 0
93 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
95 /* External VLAN Enable bit mask */
96 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
98 /* External VLAN Ether Type bit mask and shift */
99 #define E1000_VET_VET_EXT 0xFFFF0000
100 #define E1000_VET_VET_EXT_SHIFT 16
102 static int eth_igb_configure(struct rte_eth_dev *dev);
103 static int eth_igb_start(struct rte_eth_dev *dev);
104 static void eth_igb_stop(struct rte_eth_dev *dev);
105 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
106 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
107 static void eth_igb_close(struct rte_eth_dev *dev);
108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
112 static int eth_igb_link_update(struct rte_eth_dev *dev,
113 int wait_to_complete);
114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
115 struct rte_eth_stats *rte_stats);
116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
117 struct rte_eth_xstat *xstats, unsigned n);
118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
119 struct rte_eth_xstat_name *xstats_names,
121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
123 static void eth_igb_infos_get(struct rte_eth_dev *dev,
124 struct rte_eth_dev_info *dev_info);
125 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
126 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
127 struct rte_eth_dev_info *dev_info);
128 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
129 struct rte_eth_fc_conf *fc_conf);
130 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
131 struct rte_eth_fc_conf *fc_conf);
132 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
133 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
134 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
135 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
136 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
138 static int igb_hardware_init(struct e1000_hw *hw);
139 static void igb_hw_control_acquire(struct e1000_hw *hw);
140 static void igb_hw_control_release(struct e1000_hw *hw);
141 static void igb_init_manageability(struct e1000_hw *hw);
142 static void igb_release_manageability(struct e1000_hw *hw);
144 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
146 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
147 uint16_t vlan_id, int on);
148 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
149 enum rte_vlan_type vlan_type,
151 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
153 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
154 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
155 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
156 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
157 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
158 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
160 static int eth_igb_led_on(struct rte_eth_dev *dev);
161 static int eth_igb_led_off(struct rte_eth_dev *dev);
163 static void igb_intr_disable(struct e1000_hw *hw);
164 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
165 static void eth_igb_rar_set(struct rte_eth_dev *dev,
166 struct ether_addr *mac_addr,
167 uint32_t index, uint32_t pool);
168 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
169 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
170 struct ether_addr *addr);
172 static void igbvf_intr_disable(struct e1000_hw *hw);
173 static int igbvf_dev_configure(struct rte_eth_dev *dev);
174 static int igbvf_dev_start(struct rte_eth_dev *dev);
175 static void igbvf_dev_stop(struct rte_eth_dev *dev);
176 static void igbvf_dev_close(struct rte_eth_dev *dev);
177 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
178 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
179 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
180 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
181 static int eth_igbvf_link_update(struct e1000_hw *hw);
182 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
183 struct rte_eth_stats *rte_stats);
184 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
185 struct rte_eth_xstat *xstats, unsigned n);
186 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
187 struct rte_eth_xstat_name *xstats_names,
189 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
190 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
191 uint16_t vlan_id, int on);
192 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
193 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
194 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
195 struct ether_addr *addr);
196 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
197 static int igbvf_get_regs(struct rte_eth_dev *dev,
198 struct rte_dev_reg_info *regs);
200 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
201 struct rte_eth_rss_reta_entry64 *reta_conf,
203 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
204 struct rte_eth_rss_reta_entry64 *reta_conf,
207 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
208 struct rte_eth_syn_filter *filter,
210 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
211 struct rte_eth_syn_filter *filter);
212 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
213 enum rte_filter_op filter_op,
215 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
216 struct rte_eth_ntuple_filter *ntuple_filter);
217 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
218 struct rte_eth_ntuple_filter *ntuple_filter);
219 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
220 struct rte_eth_flex_filter *filter,
222 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
223 struct rte_eth_flex_filter *filter);
224 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
225 enum rte_filter_op filter_op,
227 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
228 struct rte_eth_ntuple_filter *ntuple_filter);
229 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
230 struct rte_eth_ntuple_filter *ntuple_filter);
231 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
232 struct rte_eth_ntuple_filter *filter,
234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
235 struct rte_eth_ntuple_filter *filter);
236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
237 enum rte_filter_op filter_op,
239 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
240 struct rte_eth_ethertype_filter *filter,
242 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
243 enum rte_filter_op filter_op,
245 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
246 struct rte_eth_ethertype_filter *filter);
247 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
248 enum rte_filter_type filter_type,
249 enum rte_filter_op filter_op,
251 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
252 static int eth_igb_get_regs(struct rte_eth_dev *dev,
253 struct rte_dev_reg_info *regs);
254 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
255 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
256 struct rte_dev_eeprom_info *eeprom);
257 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
258 struct rte_dev_eeprom_info *eeprom);
259 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
260 struct ether_addr *mc_addr_set,
261 uint32_t nb_mc_addr);
262 static int igb_timesync_enable(struct rte_eth_dev *dev);
263 static int igb_timesync_disable(struct rte_eth_dev *dev);
264 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
265 struct timespec *timestamp,
267 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
268 struct timespec *timestamp);
269 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
270 static int igb_timesync_read_time(struct rte_eth_dev *dev,
271 struct timespec *timestamp);
272 static int igb_timesync_write_time(struct rte_eth_dev *dev,
273 const struct timespec *timestamp);
274 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
276 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
278 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
279 uint8_t queue, uint8_t msix_vector);
280 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
281 uint8_t index, uint8_t offset);
282 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
283 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
285 static void igbvf_mbx_process(struct rte_eth_dev *dev);
288 * Define VF Stats MACRO for Non "cleared on read" register
290 #define UPDATE_VF_STAT(reg, last, cur) \
292 u32 latest = E1000_READ_REG(hw, reg); \
293 cur += (latest - last) & UINT_MAX; \
297 #define IGB_FC_PAUSE_TIME 0x0680
298 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
299 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
301 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
303 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
306 * The set of PCI devices this driver supports
308 static const struct rte_pci_id pci_id_igb_map[] = {
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
324 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
325 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
326 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
327 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
329 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
330 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
335 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
336 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
337 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
338 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
339 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
340 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
341 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
342 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
343 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
344 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
345 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
346 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
347 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
348 { .vendor_id = 0, /* sentinel */ },
352 * The set of PCI devices this driver supports (for 82576&I350 VF)
354 static const struct rte_pci_id pci_id_igbvf_map[] = {
355 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
356 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
357 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
358 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
359 { .vendor_id = 0, /* sentinel */ },
362 static const struct rte_eth_desc_lim rx_desc_lim = {
363 .nb_max = E1000_MAX_RING_DESC,
364 .nb_min = E1000_MIN_RING_DESC,
365 .nb_align = IGB_RXD_ALIGN,
368 static const struct rte_eth_desc_lim tx_desc_lim = {
369 .nb_max = E1000_MAX_RING_DESC,
370 .nb_min = E1000_MIN_RING_DESC,
371 .nb_align = IGB_RXD_ALIGN,
374 static const struct eth_dev_ops eth_igb_ops = {
375 .dev_configure = eth_igb_configure,
376 .dev_start = eth_igb_start,
377 .dev_stop = eth_igb_stop,
378 .dev_set_link_up = eth_igb_dev_set_link_up,
379 .dev_set_link_down = eth_igb_dev_set_link_down,
380 .dev_close = eth_igb_close,
381 .promiscuous_enable = eth_igb_promiscuous_enable,
382 .promiscuous_disable = eth_igb_promiscuous_disable,
383 .allmulticast_enable = eth_igb_allmulticast_enable,
384 .allmulticast_disable = eth_igb_allmulticast_disable,
385 .link_update = eth_igb_link_update,
386 .stats_get = eth_igb_stats_get,
387 .xstats_get = eth_igb_xstats_get,
388 .xstats_get_names = eth_igb_xstats_get_names,
389 .stats_reset = eth_igb_stats_reset,
390 .xstats_reset = eth_igb_xstats_reset,
391 .dev_infos_get = eth_igb_infos_get,
392 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
393 .mtu_set = eth_igb_mtu_set,
394 .vlan_filter_set = eth_igb_vlan_filter_set,
395 .vlan_tpid_set = eth_igb_vlan_tpid_set,
396 .vlan_offload_set = eth_igb_vlan_offload_set,
397 .rx_queue_setup = eth_igb_rx_queue_setup,
398 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
399 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
400 .rx_queue_release = eth_igb_rx_queue_release,
401 .rx_queue_count = eth_igb_rx_queue_count,
402 .rx_descriptor_done = eth_igb_rx_descriptor_done,
403 .tx_queue_setup = eth_igb_tx_queue_setup,
404 .tx_queue_release = eth_igb_tx_queue_release,
405 .dev_led_on = eth_igb_led_on,
406 .dev_led_off = eth_igb_led_off,
407 .flow_ctrl_get = eth_igb_flow_ctrl_get,
408 .flow_ctrl_set = eth_igb_flow_ctrl_set,
409 .mac_addr_add = eth_igb_rar_set,
410 .mac_addr_remove = eth_igb_rar_clear,
411 .mac_addr_set = eth_igb_default_mac_addr_set,
412 .reta_update = eth_igb_rss_reta_update,
413 .reta_query = eth_igb_rss_reta_query,
414 .rss_hash_update = eth_igb_rss_hash_update,
415 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
416 .filter_ctrl = eth_igb_filter_ctrl,
417 .set_mc_addr_list = eth_igb_set_mc_addr_list,
418 .rxq_info_get = igb_rxq_info_get,
419 .txq_info_get = igb_txq_info_get,
420 .timesync_enable = igb_timesync_enable,
421 .timesync_disable = igb_timesync_disable,
422 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
423 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
424 .get_reg = eth_igb_get_regs,
425 .get_eeprom_length = eth_igb_get_eeprom_length,
426 .get_eeprom = eth_igb_get_eeprom,
427 .set_eeprom = eth_igb_set_eeprom,
428 .timesync_adjust_time = igb_timesync_adjust_time,
429 .timesync_read_time = igb_timesync_read_time,
430 .timesync_write_time = igb_timesync_write_time,
434 * dev_ops for virtual function, bare necessities for basic vf
435 * operation have been implemented
437 static const struct eth_dev_ops igbvf_eth_dev_ops = {
438 .dev_configure = igbvf_dev_configure,
439 .dev_start = igbvf_dev_start,
440 .dev_stop = igbvf_dev_stop,
441 .dev_close = igbvf_dev_close,
442 .promiscuous_enable = igbvf_promiscuous_enable,
443 .promiscuous_disable = igbvf_promiscuous_disable,
444 .allmulticast_enable = igbvf_allmulticast_enable,
445 .allmulticast_disable = igbvf_allmulticast_disable,
446 .link_update = eth_igb_link_update,
447 .stats_get = eth_igbvf_stats_get,
448 .xstats_get = eth_igbvf_xstats_get,
449 .xstats_get_names = eth_igbvf_xstats_get_names,
450 .stats_reset = eth_igbvf_stats_reset,
451 .xstats_reset = eth_igbvf_stats_reset,
452 .vlan_filter_set = igbvf_vlan_filter_set,
453 .dev_infos_get = eth_igbvf_infos_get,
454 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
455 .rx_queue_setup = eth_igb_rx_queue_setup,
456 .rx_queue_release = eth_igb_rx_queue_release,
457 .tx_queue_setup = eth_igb_tx_queue_setup,
458 .tx_queue_release = eth_igb_tx_queue_release,
459 .set_mc_addr_list = eth_igb_set_mc_addr_list,
460 .rxq_info_get = igb_rxq_info_get,
461 .txq_info_get = igb_txq_info_get,
462 .mac_addr_set = igbvf_default_mac_addr_set,
463 .get_reg = igbvf_get_regs,
466 /* store statistics names and its offset in stats structure */
467 struct rte_igb_xstats_name_off {
468 char name[RTE_ETH_XSTATS_NAME_SIZE];
472 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
473 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
474 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
475 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
476 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
477 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
478 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
479 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
481 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
482 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
483 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
484 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
485 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
486 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
487 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
488 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
489 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
490 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
491 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
493 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
494 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
495 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
496 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
497 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
499 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
501 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
502 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
503 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
504 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
505 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
506 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
507 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
508 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
509 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
510 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
511 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
512 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
513 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
514 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
515 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
516 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
517 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
518 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
520 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
522 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
523 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
524 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
525 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
526 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
527 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
528 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
530 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
533 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
534 sizeof(rte_igb_stats_strings[0]))
536 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
537 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
538 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
539 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
540 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
541 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
544 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
545 sizeof(rte_igbvf_stats_strings[0]))
548 * Atomically reads the link status information from global
549 * structure rte_eth_dev.
552 * - Pointer to the structure rte_eth_dev to read from.
553 * - Pointer to the buffer to be saved with the link status.
556 * - On success, zero.
557 * - On failure, negative value.
560 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
561 struct rte_eth_link *link)
563 struct rte_eth_link *dst = link;
564 struct rte_eth_link *src = &(dev->data->dev_link);
566 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
567 *(uint64_t *)src) == 0)
574 * Atomically writes the link status information into global
575 * structure rte_eth_dev.
578 * - Pointer to the structure rte_eth_dev to read from.
579 * - Pointer to the buffer to be saved with the link status.
582 * - On success, zero.
583 * - On failure, negative value.
586 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
587 struct rte_eth_link *link)
589 struct rte_eth_link *dst = &(dev->data->dev_link);
590 struct rte_eth_link *src = link;
592 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
593 *(uint64_t *)src) == 0)
600 igb_intr_enable(struct rte_eth_dev *dev)
602 struct e1000_interrupt *intr =
603 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
604 struct e1000_hw *hw =
605 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
607 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
608 E1000_WRITE_FLUSH(hw);
612 igb_intr_disable(struct e1000_hw *hw)
614 E1000_WRITE_REG(hw, E1000_IMC, ~0);
615 E1000_WRITE_FLUSH(hw);
619 igbvf_intr_enable(struct rte_eth_dev *dev)
621 struct e1000_hw *hw =
622 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
624 /* only for mailbox */
625 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
626 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
627 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
628 E1000_WRITE_FLUSH(hw);
631 /* only for mailbox now. If RX/TX needed, should extend this function. */
633 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
638 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
639 tmp |= E1000_VTIVAR_VALID;
640 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
644 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
646 struct e1000_hw *hw =
647 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
649 /* Configure VF other cause ivar */
650 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
653 static inline int32_t
654 igb_pf_reset_hw(struct e1000_hw *hw)
659 status = e1000_reset_hw(hw);
661 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
662 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
663 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
664 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
665 E1000_WRITE_FLUSH(hw);
671 igb_identify_hardware(struct rte_eth_dev *dev)
673 struct e1000_hw *hw =
674 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
676 hw->vendor_id = dev->pci_dev->id.vendor_id;
677 hw->device_id = dev->pci_dev->id.device_id;
678 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
679 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
681 e1000_set_mac_type(hw);
683 /* need to check if it is a vf device below */
687 igb_reset_swfw_lock(struct e1000_hw *hw)
692 * Do mac ops initialization manually here, since we will need
693 * some function pointers set by this call.
695 ret_val = e1000_init_mac_params(hw);
700 * SMBI lock should not fail in this early stage. If this is the case,
701 * it is due to an improper exit of the application.
702 * So force the release of the faulty lock.
704 if (e1000_get_hw_semaphore_generic(hw) < 0) {
705 PMD_DRV_LOG(DEBUG, "SMBI lock released");
707 e1000_put_hw_semaphore_generic(hw);
709 if (hw->mac.ops.acquire_swfw_sync != NULL) {
713 * Phy lock should not fail in this early stage. If this is the case,
714 * it is due to an improper exit of the application.
715 * So force the release of the faulty lock.
717 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
718 if (hw->bus.func > E1000_FUNC_1)
720 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
721 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
724 hw->mac.ops.release_swfw_sync(hw, mask);
727 * This one is more tricky since it is common to all ports; but
728 * swfw_sync retries last long enough (1s) to be almost sure that if
729 * lock can not be taken it is due to an improper lock of the
732 mask = E1000_SWFW_EEP_SM;
733 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
734 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
736 hw->mac.ops.release_swfw_sync(hw, mask);
739 return E1000_SUCCESS;
743 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
746 struct rte_pci_device *pci_dev;
747 struct e1000_hw *hw =
748 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
749 struct e1000_vfta * shadow_vfta =
750 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
751 struct e1000_filter_info *filter_info =
752 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
753 struct e1000_adapter *adapter =
754 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
758 pci_dev = eth_dev->pci_dev;
760 eth_dev->dev_ops = ð_igb_ops;
761 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
762 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
764 /* for secondary processes, we don't initialise any further as primary
765 * has already done this work. Only check we don't need a different
767 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
768 if (eth_dev->data->scattered_rx)
769 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
773 rte_eth_copy_pci_info(eth_dev, pci_dev);
775 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
777 igb_identify_hardware(eth_dev);
778 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
783 e1000_get_bus_info(hw);
785 /* Reset any pending lock */
786 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
791 /* Finish initialization */
792 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
798 hw->phy.autoneg_wait_to_complete = 0;
799 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
802 if (hw->phy.media_type == e1000_media_type_copper) {
803 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
804 hw->phy.disable_polarity_correction = 0;
805 hw->phy.ms_type = e1000_ms_hw_default;
809 * Start from a known state, this is important in reading the nvm
814 /* Make sure we have a good EEPROM before we read from it */
815 if (e1000_validate_nvm_checksum(hw) < 0) {
817 * Some PCI-E parts fail the first check due to
818 * the link being in sleep state, call it again,
819 * if it fails a second time its a real issue.
821 if (e1000_validate_nvm_checksum(hw) < 0) {
822 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
828 /* Read the permanent MAC address out of the EEPROM */
829 if (e1000_read_mac_addr(hw) != 0) {
830 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
835 /* Allocate memory for storing MAC addresses */
836 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
837 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
838 if (eth_dev->data->mac_addrs == NULL) {
839 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
840 "store MAC addresses",
841 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
846 /* Copy the permanent MAC address */
847 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
849 /* initialize the vfta */
850 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
852 /* Now initialize the hardware */
853 if (igb_hardware_init(hw) != 0) {
854 PMD_INIT_LOG(ERR, "Hardware initialization failed");
855 rte_free(eth_dev->data->mac_addrs);
856 eth_dev->data->mac_addrs = NULL;
860 hw->mac.get_link_status = 1;
861 adapter->stopped = 0;
863 /* Indicate SOL/IDER usage */
864 if (e1000_check_reset_block(hw) < 0) {
865 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
869 /* initialize PF if max_vfs not zero */
870 igb_pf_host_init(eth_dev);
872 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
873 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
874 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
875 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
876 E1000_WRITE_FLUSH(hw);
878 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
879 eth_dev->data->port_id, pci_dev->id.vendor_id,
880 pci_dev->id.device_id);
882 rte_intr_callback_register(&pci_dev->intr_handle,
883 eth_igb_interrupt_handler,
886 /* enable uio/vfio intr/eventfd mapping */
887 rte_intr_enable(&pci_dev->intr_handle);
889 /* enable support intr */
890 igb_intr_enable(eth_dev);
892 TAILQ_INIT(&filter_info->flex_list);
893 filter_info->flex_mask = 0;
894 TAILQ_INIT(&filter_info->twotuple_list);
895 filter_info->twotuple_mask = 0;
896 TAILQ_INIT(&filter_info->fivetuple_list);
897 filter_info->fivetuple_mask = 0;
902 igb_hw_control_release(hw);
908 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
910 struct rte_pci_device *pci_dev;
912 struct e1000_adapter *adapter =
913 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
915 PMD_INIT_FUNC_TRACE();
917 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
920 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
921 pci_dev = eth_dev->pci_dev;
923 if (adapter->stopped == 0)
924 eth_igb_close(eth_dev);
926 eth_dev->dev_ops = NULL;
927 eth_dev->rx_pkt_burst = NULL;
928 eth_dev->tx_pkt_burst = NULL;
930 /* Reset any pending lock */
931 igb_reset_swfw_lock(hw);
933 rte_free(eth_dev->data->mac_addrs);
934 eth_dev->data->mac_addrs = NULL;
936 /* uninitialize PF if max_vfs not zero */
937 igb_pf_host_uninit(eth_dev);
939 /* disable uio intr before callback unregister */
940 rte_intr_disable(&(pci_dev->intr_handle));
941 rte_intr_callback_unregister(&(pci_dev->intr_handle),
942 eth_igb_interrupt_handler, (void *)eth_dev);
948 * Virtual Function device init
951 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
953 struct rte_pci_device *pci_dev;
954 struct e1000_adapter *adapter =
955 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
956 struct e1000_hw *hw =
957 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
959 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
961 PMD_INIT_FUNC_TRACE();
963 eth_dev->dev_ops = &igbvf_eth_dev_ops;
964 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
965 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
967 /* for secondary processes, we don't initialise any further as primary
968 * has already done this work. Only check we don't need a different
970 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
971 if (eth_dev->data->scattered_rx)
972 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
976 pci_dev = eth_dev->pci_dev;
978 rte_eth_copy_pci_info(eth_dev, pci_dev);
980 hw->device_id = pci_dev->id.device_id;
981 hw->vendor_id = pci_dev->id.vendor_id;
982 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
983 adapter->stopped = 0;
985 /* Initialize the shared code (base driver) */
986 diag = e1000_setup_init_funcs(hw, TRUE);
988 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
993 /* init_mailbox_params */
994 hw->mbx.ops.init_params(hw);
996 /* Disable the interrupts for VF */
997 igbvf_intr_disable(hw);
999 diag = hw->mac.ops.reset_hw(hw);
1001 /* Allocate memory for storing MAC addresses */
1002 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1003 hw->mac.rar_entry_count, 0);
1004 if (eth_dev->data->mac_addrs == NULL) {
1006 "Failed to allocate %d bytes needed to store MAC "
1008 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1012 /* Generate a random MAC address, if none was assigned by PF. */
1013 if (is_zero_ether_addr(perm_addr)) {
1014 eth_random_addr(perm_addr->addr_bytes);
1015 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1016 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1017 "%02x:%02x:%02x:%02x:%02x:%02x",
1018 perm_addr->addr_bytes[0],
1019 perm_addr->addr_bytes[1],
1020 perm_addr->addr_bytes[2],
1021 perm_addr->addr_bytes[3],
1022 perm_addr->addr_bytes[4],
1023 perm_addr->addr_bytes[5]);
1026 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1028 rte_free(eth_dev->data->mac_addrs);
1029 eth_dev->data->mac_addrs = NULL;
1032 /* Copy the permanent MAC address */
1033 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1034 ð_dev->data->mac_addrs[0]);
1036 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1038 eth_dev->data->port_id, pci_dev->id.vendor_id,
1039 pci_dev->id.device_id, "igb_mac_82576_vf");
1041 rte_intr_callback_register(&pci_dev->intr_handle,
1042 eth_igbvf_interrupt_handler,
1049 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1051 struct e1000_adapter *adapter =
1052 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1053 struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1055 PMD_INIT_FUNC_TRACE();
1057 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1060 if (adapter->stopped == 0)
1061 igbvf_dev_close(eth_dev);
1063 eth_dev->dev_ops = NULL;
1064 eth_dev->rx_pkt_burst = NULL;
1065 eth_dev->tx_pkt_burst = NULL;
1067 rte_free(eth_dev->data->mac_addrs);
1068 eth_dev->data->mac_addrs = NULL;
1070 /* disable uio intr before callback unregister */
1071 rte_intr_disable(&pci_dev->intr_handle);
1072 rte_intr_callback_unregister(&pci_dev->intr_handle,
1073 eth_igbvf_interrupt_handler,
1079 static struct eth_driver rte_igb_pmd = {
1081 .id_table = pci_id_igb_map,
1082 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1083 RTE_PCI_DRV_DETACHABLE,
1084 .probe = rte_eth_dev_pci_probe,
1085 .remove = rte_eth_dev_pci_remove,
1087 .eth_dev_init = eth_igb_dev_init,
1088 .eth_dev_uninit = eth_igb_dev_uninit,
1089 .dev_private_size = sizeof(struct e1000_adapter),
1093 * virtual function driver struct
1095 static struct eth_driver rte_igbvf_pmd = {
1097 .id_table = pci_id_igbvf_map,
1098 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1099 .probe = rte_eth_dev_pci_probe,
1100 .remove = rte_eth_dev_pci_remove,
1102 .eth_dev_init = eth_igbvf_dev_init,
1103 .eth_dev_uninit = eth_igbvf_dev_uninit,
1104 .dev_private_size = sizeof(struct e1000_adapter),
1108 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1110 struct e1000_hw *hw =
1111 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1112 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1113 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1114 rctl |= E1000_RCTL_VFE;
1115 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1119 igb_check_mq_mode(struct rte_eth_dev *dev)
1121 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1122 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1123 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1124 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1126 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1127 tx_mq_mode == ETH_MQ_TX_DCB ||
1128 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1129 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1132 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1133 /* Check multi-queue mode.
1134 * To no break software we accept ETH_MQ_RX_NONE as this might
1135 * be used to turn off VLAN filter.
1138 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1139 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1140 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1141 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1143 /* Only support one queue on VFs.
1144 * RSS together with SRIOV is not supported.
1146 PMD_INIT_LOG(ERR, "SRIOV is active,"
1147 " wrong mq_mode rx %d.",
1151 /* TX mode is not used here, so mode might be ignored.*/
1152 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1153 /* SRIOV only works in VMDq enable mode */
1154 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1155 " TX mode %d is not supported. "
1156 " Driver will behave as %d mode.",
1157 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1160 /* check valid queue number */
1161 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1162 PMD_INIT_LOG(ERR, "SRIOV is active,"
1163 " only support one queue on VFs.");
1167 /* To no break software that set invalid mode, only display
1168 * warning if invalid mode is used.
1170 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1171 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1172 rx_mq_mode != ETH_MQ_RX_RSS) {
1173 /* RSS together with VMDq not supported*/
1174 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1179 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1180 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1181 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1182 " Due to txmode is meaningless in this"
1183 " driver, just ignore.",
1191 eth_igb_configure(struct rte_eth_dev *dev)
1193 struct e1000_interrupt *intr =
1194 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1197 PMD_INIT_FUNC_TRACE();
1199 /* multipe queue mode checking */
1200 ret = igb_check_mq_mode(dev);
1202 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1207 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1208 PMD_INIT_FUNC_TRACE();
1214 eth_igb_start(struct rte_eth_dev *dev)
1216 struct e1000_hw *hw =
1217 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1218 struct e1000_adapter *adapter =
1219 E1000_DEV_PRIVATE(dev->data->dev_private);
1220 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1222 uint32_t intr_vector = 0;
1228 PMD_INIT_FUNC_TRACE();
1230 /* disable uio/vfio intr/eventfd mapping */
1231 rte_intr_disable(intr_handle);
1233 /* Power up the phy. Needed to make the link go Up */
1234 eth_igb_dev_set_link_up(dev);
1237 * Packet Buffer Allocation (PBA)
1238 * Writing PBA sets the receive portion of the buffer
1239 * the remainder is used for the transmit buffer.
1241 if (hw->mac.type == e1000_82575) {
1244 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1245 E1000_WRITE_REG(hw, E1000_PBA, pba);
1248 /* Put the address into the Receive Address Array */
1249 e1000_rar_set(hw, hw->mac.addr, 0);
1251 /* Initialize the hardware */
1252 if (igb_hardware_init(hw)) {
1253 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1256 adapter->stopped = 0;
1258 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1260 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1261 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1262 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1263 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1264 E1000_WRITE_FLUSH(hw);
1266 /* configure PF module if SRIOV enabled */
1267 igb_pf_host_configure(dev);
1269 /* check and configure queue intr-vector mapping */
1270 if ((rte_intr_cap_multiple(intr_handle) ||
1271 !RTE_ETH_DEV_SRIOV(dev).active) &&
1272 dev->data->dev_conf.intr_conf.rxq != 0) {
1273 intr_vector = dev->data->nb_rx_queues;
1274 if (rte_intr_efd_enable(intr_handle, intr_vector))
1278 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1279 intr_handle->intr_vec =
1280 rte_zmalloc("intr_vec",
1281 dev->data->nb_rx_queues * sizeof(int), 0);
1282 if (intr_handle->intr_vec == NULL) {
1283 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1284 " intr_vec\n", dev->data->nb_rx_queues);
1289 /* confiugre msix for rx interrupt */
1290 eth_igb_configure_msix_intr(dev);
1292 /* Configure for OS presence */
1293 igb_init_manageability(hw);
1295 eth_igb_tx_init(dev);
1297 /* This can fail when allocating mbufs for descriptor rings */
1298 ret = eth_igb_rx_init(dev);
1300 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1301 igb_dev_clear_queues(dev);
1305 e1000_clear_hw_cntrs_base_generic(hw);
1308 * VLAN Offload Settings
1310 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1311 ETH_VLAN_EXTEND_MASK;
1312 eth_igb_vlan_offload_set(dev, mask);
1314 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1315 /* Enable VLAN filter since VMDq always use VLAN filter */
1316 igb_vmdq_vlan_hw_filter_enable(dev);
1319 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1320 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1321 (hw->mac.type == e1000_i211)) {
1322 /* Configure EITR with the maximum possible value (0xFFFF) */
1323 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1326 /* Setup link speed and duplex */
1327 speeds = &dev->data->dev_conf.link_speeds;
1328 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1329 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1330 hw->mac.autoneg = 1;
1333 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1336 hw->phy.autoneg_advertised = 0;
1338 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1339 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1340 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1342 goto error_invalid_config;
1344 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1345 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1348 if (*speeds & ETH_LINK_SPEED_10M) {
1349 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1352 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1353 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1356 if (*speeds & ETH_LINK_SPEED_100M) {
1357 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1360 if (*speeds & ETH_LINK_SPEED_1G) {
1361 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1364 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1365 goto error_invalid_config;
1367 /* Set/reset the mac.autoneg based on the link speed,
1371 hw->mac.autoneg = 0;
1372 hw->mac.forced_speed_duplex =
1373 hw->phy.autoneg_advertised;
1375 hw->mac.autoneg = 1;
1379 e1000_setup_link(hw);
1381 if (rte_intr_allow_others(intr_handle)) {
1382 /* check if lsc interrupt is enabled */
1383 if (dev->data->dev_conf.intr_conf.lsc != 0)
1384 eth_igb_lsc_interrupt_setup(dev);
1386 rte_intr_callback_unregister(intr_handle,
1387 eth_igb_interrupt_handler,
1389 if (dev->data->dev_conf.intr_conf.lsc != 0)
1390 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1391 " no intr multiplex\n");
1394 /* check if rxq interrupt is enabled */
1395 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1396 rte_intr_dp_is_en(intr_handle))
1397 eth_igb_rxq_interrupt_setup(dev);
1399 /* enable uio/vfio intr/eventfd mapping */
1400 rte_intr_enable(intr_handle);
1402 /* resume enabled intr since hw reset */
1403 igb_intr_enable(dev);
1405 PMD_INIT_LOG(DEBUG, "<<");
1409 error_invalid_config:
1410 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1411 dev->data->dev_conf.link_speeds, dev->data->port_id);
1412 igb_dev_clear_queues(dev);
1416 /*********************************************************************
1418 * This routine disables all traffic on the adapter by issuing a
1419 * global reset on the MAC.
1421 **********************************************************************/
1423 eth_igb_stop(struct rte_eth_dev *dev)
1425 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426 struct e1000_filter_info *filter_info =
1427 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1428 struct rte_eth_link link;
1429 struct e1000_flex_filter *p_flex;
1430 struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1431 struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1432 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1434 igb_intr_disable(hw);
1436 /* disable intr eventfd mapping */
1437 rte_intr_disable(intr_handle);
1439 igb_pf_reset_hw(hw);
1440 E1000_WRITE_REG(hw, E1000_WUC, 0);
1442 /* Set bit for Go Link disconnect */
1443 if (hw->mac.type >= e1000_82580) {
1446 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1447 phpm_reg |= E1000_82580_PM_GO_LINKD;
1448 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1451 /* Power down the phy. Needed to make the link go Down */
1452 eth_igb_dev_set_link_down(dev);
1454 igb_dev_clear_queues(dev);
1456 /* clear the recorded link status */
1457 memset(&link, 0, sizeof(link));
1458 rte_igb_dev_atomic_write_link_status(dev, &link);
1460 /* Remove all flex filters of the device */
1461 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1462 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1465 filter_info->flex_mask = 0;
1467 /* Remove all ntuple filters of the device */
1468 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1469 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1470 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1471 TAILQ_REMOVE(&filter_info->fivetuple_list,
1475 filter_info->fivetuple_mask = 0;
1476 for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1477 p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1478 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1479 TAILQ_REMOVE(&filter_info->twotuple_list,
1483 filter_info->twotuple_mask = 0;
1485 if (!rte_intr_allow_others(intr_handle))
1486 /* resume to the default handler */
1487 rte_intr_callback_register(intr_handle,
1488 eth_igb_interrupt_handler,
1491 /* Clean datapath event and queue/vec mapping */
1492 rte_intr_efd_disable(intr_handle);
1493 if (intr_handle->intr_vec != NULL) {
1494 rte_free(intr_handle->intr_vec);
1495 intr_handle->intr_vec = NULL;
1500 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1502 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1504 if (hw->phy.media_type == e1000_media_type_copper)
1505 e1000_power_up_phy(hw);
1507 e1000_power_up_fiber_serdes_link(hw);
1513 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1515 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1517 if (hw->phy.media_type == e1000_media_type_copper)
1518 e1000_power_down_phy(hw);
1520 e1000_shutdown_fiber_serdes_link(hw);
1526 eth_igb_close(struct rte_eth_dev *dev)
1528 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1529 struct e1000_adapter *adapter =
1530 E1000_DEV_PRIVATE(dev->data->dev_private);
1531 struct rte_eth_link link;
1532 struct rte_pci_device *pci_dev;
1535 adapter->stopped = 1;
1537 e1000_phy_hw_reset(hw);
1538 igb_release_manageability(hw);
1539 igb_hw_control_release(hw);
1541 /* Clear bit for Go Link disconnect */
1542 if (hw->mac.type >= e1000_82580) {
1545 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1546 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1547 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1550 igb_dev_free_queues(dev);
1552 pci_dev = dev->pci_dev;
1553 if (pci_dev->intr_handle.intr_vec) {
1554 rte_free(pci_dev->intr_handle.intr_vec);
1555 pci_dev->intr_handle.intr_vec = NULL;
1558 memset(&link, 0, sizeof(link));
1559 rte_igb_dev_atomic_write_link_status(dev, &link);
1563 igb_get_rx_buffer_size(struct e1000_hw *hw)
1565 uint32_t rx_buf_size;
1566 if (hw->mac.type == e1000_82576) {
1567 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1568 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1569 /* PBS needs to be translated according to a lookup table */
1570 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1571 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1572 rx_buf_size = (rx_buf_size << 10);
1573 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1574 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1576 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1582 /*********************************************************************
1584 * Initialize the hardware
1586 **********************************************************************/
1588 igb_hardware_init(struct e1000_hw *hw)
1590 uint32_t rx_buf_size;
1593 /* Let the firmware know the OS is in control */
1594 igb_hw_control_acquire(hw);
1597 * These parameters control the automatic generation (Tx) and
1598 * response (Rx) to Ethernet PAUSE frames.
1599 * - High water mark should allow for at least two standard size (1518)
1600 * frames to be received after sending an XOFF.
1601 * - Low water mark works best when it is very near the high water mark.
1602 * This allows the receiver to restart by sending XON when it has
1603 * drained a bit. Here we use an arbitrary value of 1500 which will
1604 * restart after one full frame is pulled from the buffer. There
1605 * could be several smaller frames in the buffer and if so they will
1606 * not trigger the XON until their total number reduces the buffer
1608 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1610 rx_buf_size = igb_get_rx_buffer_size(hw);
1612 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1613 hw->fc.low_water = hw->fc.high_water - 1500;
1614 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1615 hw->fc.send_xon = 1;
1617 /* Set Flow control, use the tunable location if sane */
1618 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1619 hw->fc.requested_mode = igb_fc_setting;
1621 hw->fc.requested_mode = e1000_fc_none;
1623 /* Issue a global reset */
1624 igb_pf_reset_hw(hw);
1625 E1000_WRITE_REG(hw, E1000_WUC, 0);
1627 diag = e1000_init_hw(hw);
1631 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1632 e1000_get_phy_info(hw);
1633 e1000_check_for_link(hw);
1638 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1640 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1644 uint64_t old_gprc = stats->gprc;
1645 uint64_t old_gptc = stats->gptc;
1646 uint64_t old_tpr = stats->tpr;
1647 uint64_t old_tpt = stats->tpt;
1648 uint64_t old_rpthc = stats->rpthc;
1649 uint64_t old_hgptc = stats->hgptc;
1651 if(hw->phy.media_type == e1000_media_type_copper ||
1652 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1654 E1000_READ_REG(hw,E1000_SYMERRS);
1655 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1658 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1659 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1660 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1661 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1663 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1664 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1665 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1666 stats->dc += E1000_READ_REG(hw, E1000_DC);
1667 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1668 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1669 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1671 ** For watchdog management we need to know if we have been
1672 ** paused during the last interval, so capture that here.
1674 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1675 stats->xoffrxc += pause_frames;
1676 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1677 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1678 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1679 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1680 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1681 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1682 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1683 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1684 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1685 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1686 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1687 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1689 /* For the 64-bit byte counters the low dword must be read first. */
1690 /* Both registers clear on the read of the high dword */
1692 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1693 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1694 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1695 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1696 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1697 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1698 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1700 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1701 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1702 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1703 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1704 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1706 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1707 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1709 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1710 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1711 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1712 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1713 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1714 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1716 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1717 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1718 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1719 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1720 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1721 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1722 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1723 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1725 /* Interrupt Counts */
1727 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1728 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1729 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1730 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1731 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1732 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1733 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1734 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1735 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1737 /* Host to Card Statistics */
1739 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1740 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1741 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1742 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1743 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1744 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1745 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1746 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1747 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1748 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1749 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1750 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1751 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1752 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1753 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1754 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1756 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1757 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1758 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1759 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1760 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1761 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1765 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1767 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1768 struct e1000_hw_stats *stats =
1769 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1771 igb_read_stats_registers(hw, stats);
1773 if (rte_stats == NULL)
1777 rte_stats->imissed = stats->mpc;
1778 rte_stats->ierrors = stats->crcerrs +
1779 stats->rlec + stats->ruc + stats->roc +
1780 stats->rxerrc + stats->algnerrc + stats->cexterr;
1783 rte_stats->oerrors = stats->ecol + stats->latecol;
1785 rte_stats->ipackets = stats->gprc;
1786 rte_stats->opackets = stats->gptc;
1787 rte_stats->ibytes = stats->gorc;
1788 rte_stats->obytes = stats->gotc;
1792 eth_igb_stats_reset(struct rte_eth_dev *dev)
1794 struct e1000_hw_stats *hw_stats =
1795 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1797 /* HW registers are cleared on read */
1798 eth_igb_stats_get(dev, NULL);
1800 /* Reset software totals */
1801 memset(hw_stats, 0, sizeof(*hw_stats));
1805 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1807 struct e1000_hw_stats *stats =
1808 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1810 /* HW registers are cleared on read */
1811 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1813 /* Reset software totals */
1814 memset(stats, 0, sizeof(*stats));
1817 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1818 struct rte_eth_xstat_name *xstats_names,
1819 __rte_unused unsigned limit)
1823 if (xstats_names == NULL)
1824 return IGB_NB_XSTATS;
1826 /* Note: limit checked in rte_eth_xstats_names() */
1828 for (i = 0; i < IGB_NB_XSTATS; i++) {
1829 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1830 "%s", rte_igb_stats_strings[i].name);
1833 return IGB_NB_XSTATS;
1837 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1840 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1841 struct e1000_hw_stats *hw_stats =
1842 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1845 if (n < IGB_NB_XSTATS)
1846 return IGB_NB_XSTATS;
1848 igb_read_stats_registers(hw, hw_stats);
1850 /* If this is a reset xstats is NULL, and we have cleared the
1851 * registers by reading them.
1856 /* Extended stats */
1857 for (i = 0; i < IGB_NB_XSTATS; i++) {
1859 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1860 rte_igb_stats_strings[i].offset);
1863 return IGB_NB_XSTATS;
1867 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1869 /* Good Rx packets, include VF loopback */
1870 UPDATE_VF_STAT(E1000_VFGPRC,
1871 hw_stats->last_gprc, hw_stats->gprc);
1873 /* Good Rx octets, include VF loopback */
1874 UPDATE_VF_STAT(E1000_VFGORC,
1875 hw_stats->last_gorc, hw_stats->gorc);
1877 /* Good Tx packets, include VF loopback */
1878 UPDATE_VF_STAT(E1000_VFGPTC,
1879 hw_stats->last_gptc, hw_stats->gptc);
1881 /* Good Tx octets, include VF loopback */
1882 UPDATE_VF_STAT(E1000_VFGOTC,
1883 hw_stats->last_gotc, hw_stats->gotc);
1885 /* Rx Multicst packets */
1886 UPDATE_VF_STAT(E1000_VFMPRC,
1887 hw_stats->last_mprc, hw_stats->mprc);
1889 /* Good Rx loopback packets */
1890 UPDATE_VF_STAT(E1000_VFGPRLBC,
1891 hw_stats->last_gprlbc, hw_stats->gprlbc);
1893 /* Good Rx loopback octets */
1894 UPDATE_VF_STAT(E1000_VFGORLBC,
1895 hw_stats->last_gorlbc, hw_stats->gorlbc);
1897 /* Good Tx loopback packets */
1898 UPDATE_VF_STAT(E1000_VFGPTLBC,
1899 hw_stats->last_gptlbc, hw_stats->gptlbc);
1901 /* Good Tx loopback octets */
1902 UPDATE_VF_STAT(E1000_VFGOTLBC,
1903 hw_stats->last_gotlbc, hw_stats->gotlbc);
1906 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1907 struct rte_eth_xstat_name *xstats_names,
1908 __rte_unused unsigned limit)
1912 if (xstats_names != NULL)
1913 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1914 snprintf(xstats_names[i].name,
1915 sizeof(xstats_names[i].name), "%s",
1916 rte_igbvf_stats_strings[i].name);
1918 return IGBVF_NB_XSTATS;
1922 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1925 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1927 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1930 if (n < IGBVF_NB_XSTATS)
1931 return IGBVF_NB_XSTATS;
1933 igbvf_read_stats_registers(hw, hw_stats);
1938 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1940 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1941 rte_igbvf_stats_strings[i].offset);
1944 return IGBVF_NB_XSTATS;
1948 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1950 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1952 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1954 igbvf_read_stats_registers(hw, hw_stats);
1956 if (rte_stats == NULL)
1959 rte_stats->ipackets = hw_stats->gprc;
1960 rte_stats->ibytes = hw_stats->gorc;
1961 rte_stats->opackets = hw_stats->gptc;
1962 rte_stats->obytes = hw_stats->gotc;
1966 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1968 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1969 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1971 /* Sync HW register to the last stats */
1972 eth_igbvf_stats_get(dev, NULL);
1974 /* reset HW current stats*/
1975 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1976 offsetof(struct e1000_vf_stats, gprc));
1980 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1982 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1984 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1985 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1986 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1987 dev_info->rx_offload_capa =
1988 DEV_RX_OFFLOAD_VLAN_STRIP |
1989 DEV_RX_OFFLOAD_IPV4_CKSUM |
1990 DEV_RX_OFFLOAD_UDP_CKSUM |
1991 DEV_RX_OFFLOAD_TCP_CKSUM;
1992 dev_info->tx_offload_capa =
1993 DEV_TX_OFFLOAD_VLAN_INSERT |
1994 DEV_TX_OFFLOAD_IPV4_CKSUM |
1995 DEV_TX_OFFLOAD_UDP_CKSUM |
1996 DEV_TX_OFFLOAD_TCP_CKSUM |
1997 DEV_TX_OFFLOAD_SCTP_CKSUM |
1998 DEV_TX_OFFLOAD_TCP_TSO;
2000 switch (hw->mac.type) {
2002 dev_info->max_rx_queues = 4;
2003 dev_info->max_tx_queues = 4;
2004 dev_info->max_vmdq_pools = 0;
2008 dev_info->max_rx_queues = 16;
2009 dev_info->max_tx_queues = 16;
2010 dev_info->max_vmdq_pools = ETH_8_POOLS;
2011 dev_info->vmdq_queue_num = 16;
2015 dev_info->max_rx_queues = 8;
2016 dev_info->max_tx_queues = 8;
2017 dev_info->max_vmdq_pools = ETH_8_POOLS;
2018 dev_info->vmdq_queue_num = 8;
2022 dev_info->max_rx_queues = 8;
2023 dev_info->max_tx_queues = 8;
2024 dev_info->max_vmdq_pools = ETH_8_POOLS;
2025 dev_info->vmdq_queue_num = 8;
2029 dev_info->max_rx_queues = 8;
2030 dev_info->max_tx_queues = 8;
2034 dev_info->max_rx_queues = 4;
2035 dev_info->max_tx_queues = 4;
2036 dev_info->max_vmdq_pools = 0;
2040 dev_info->max_rx_queues = 2;
2041 dev_info->max_tx_queues = 2;
2042 dev_info->max_vmdq_pools = 0;
2046 /* Should not happen */
2049 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2050 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2051 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2053 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2055 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2056 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2057 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2059 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2063 dev_info->default_txconf = (struct rte_eth_txconf) {
2065 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2066 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2067 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2072 dev_info->rx_desc_lim = rx_desc_lim;
2073 dev_info->tx_desc_lim = tx_desc_lim;
2075 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2076 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2080 static const uint32_t *
2081 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2083 static const uint32_t ptypes[] = {
2084 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2087 RTE_PTYPE_L3_IPV4_EXT,
2089 RTE_PTYPE_L3_IPV6_EXT,
2093 RTE_PTYPE_TUNNEL_IP,
2094 RTE_PTYPE_INNER_L3_IPV6,
2095 RTE_PTYPE_INNER_L3_IPV6_EXT,
2096 RTE_PTYPE_INNER_L4_TCP,
2097 RTE_PTYPE_INNER_L4_UDP,
2101 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2102 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2108 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2110 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2112 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2113 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2114 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2115 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2116 DEV_RX_OFFLOAD_IPV4_CKSUM |
2117 DEV_RX_OFFLOAD_UDP_CKSUM |
2118 DEV_RX_OFFLOAD_TCP_CKSUM;
2119 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2120 DEV_TX_OFFLOAD_IPV4_CKSUM |
2121 DEV_TX_OFFLOAD_UDP_CKSUM |
2122 DEV_TX_OFFLOAD_TCP_CKSUM |
2123 DEV_TX_OFFLOAD_SCTP_CKSUM |
2124 DEV_TX_OFFLOAD_TCP_TSO;
2125 switch (hw->mac.type) {
2127 dev_info->max_rx_queues = 2;
2128 dev_info->max_tx_queues = 2;
2130 case e1000_vfadapt_i350:
2131 dev_info->max_rx_queues = 1;
2132 dev_info->max_tx_queues = 1;
2135 /* Should not happen */
2139 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2141 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2142 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2143 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2145 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2149 dev_info->default_txconf = (struct rte_eth_txconf) {
2151 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2152 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2153 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2158 dev_info->rx_desc_lim = rx_desc_lim;
2159 dev_info->tx_desc_lim = tx_desc_lim;
2162 /* return 0 means link status changed, -1 means not changed */
2164 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2166 struct e1000_hw *hw =
2167 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2168 struct rte_eth_link link, old;
2169 int link_check, count;
2172 hw->mac.get_link_status = 1;
2174 /* possible wait-to-complete in up to 9 seconds */
2175 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2176 /* Read the real link status */
2177 switch (hw->phy.media_type) {
2178 case e1000_media_type_copper:
2179 /* Do the work to read phy */
2180 e1000_check_for_link(hw);
2181 link_check = !hw->mac.get_link_status;
2184 case e1000_media_type_fiber:
2185 e1000_check_for_link(hw);
2186 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2190 case e1000_media_type_internal_serdes:
2191 e1000_check_for_link(hw);
2192 link_check = hw->mac.serdes_has_link;
2195 /* VF device is type_unknown */
2196 case e1000_media_type_unknown:
2197 eth_igbvf_link_update(hw);
2198 link_check = !hw->mac.get_link_status;
2204 if (link_check || wait_to_complete == 0)
2206 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2208 memset(&link, 0, sizeof(link));
2209 rte_igb_dev_atomic_read_link_status(dev, &link);
2212 /* Now we check if a transition has happened */
2214 uint16_t duplex, speed;
2215 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2216 link.link_duplex = (duplex == FULL_DUPLEX) ?
2217 ETH_LINK_FULL_DUPLEX :
2218 ETH_LINK_HALF_DUPLEX;
2219 link.link_speed = speed;
2220 link.link_status = ETH_LINK_UP;
2221 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2222 ETH_LINK_SPEED_FIXED);
2223 } else if (!link_check) {
2224 link.link_speed = 0;
2225 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2226 link.link_status = ETH_LINK_DOWN;
2227 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2229 rte_igb_dev_atomic_write_link_status(dev, &link);
2232 if (old.link_status == link.link_status)
2240 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2241 * For ASF and Pass Through versions of f/w this means
2242 * that the driver is loaded.
2245 igb_hw_control_acquire(struct e1000_hw *hw)
2249 /* Let firmware know the driver has taken over */
2250 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2251 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2255 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2256 * For ASF and Pass Through versions of f/w this means that the
2257 * driver is no longer loaded.
2260 igb_hw_control_release(struct e1000_hw *hw)
2264 /* Let firmware taken over control of h/w */
2265 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2266 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2267 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2271 * Bit of a misnomer, what this really means is
2272 * to enable OS management of the system... aka
2273 * to disable special hardware management features.
2276 igb_init_manageability(struct e1000_hw *hw)
2278 if (e1000_enable_mng_pass_thru(hw)) {
2279 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2280 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2282 /* disable hardware interception of ARP */
2283 manc &= ~(E1000_MANC_ARP_EN);
2285 /* enable receiving management packets to the host */
2286 manc |= E1000_MANC_EN_MNG2HOST;
2287 manc2h |= 1 << 5; /* Mng Port 623 */
2288 manc2h |= 1 << 6; /* Mng Port 664 */
2289 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2290 E1000_WRITE_REG(hw, E1000_MANC, manc);
2295 igb_release_manageability(struct e1000_hw *hw)
2297 if (e1000_enable_mng_pass_thru(hw)) {
2298 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2300 manc |= E1000_MANC_ARP_EN;
2301 manc &= ~E1000_MANC_EN_MNG2HOST;
2303 E1000_WRITE_REG(hw, E1000_MANC, manc);
2308 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2310 struct e1000_hw *hw =
2311 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2314 rctl = E1000_READ_REG(hw, E1000_RCTL);
2315 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2316 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2320 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2322 struct e1000_hw *hw =
2323 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2326 rctl = E1000_READ_REG(hw, E1000_RCTL);
2327 rctl &= (~E1000_RCTL_UPE);
2328 if (dev->data->all_multicast == 1)
2329 rctl |= E1000_RCTL_MPE;
2331 rctl &= (~E1000_RCTL_MPE);
2332 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2336 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2338 struct e1000_hw *hw =
2339 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2342 rctl = E1000_READ_REG(hw, E1000_RCTL);
2343 rctl |= E1000_RCTL_MPE;
2344 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2348 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2350 struct e1000_hw *hw =
2351 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354 if (dev->data->promiscuous == 1)
2355 return; /* must remain in all_multicast mode */
2356 rctl = E1000_READ_REG(hw, E1000_RCTL);
2357 rctl &= (~E1000_RCTL_MPE);
2358 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2362 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2364 struct e1000_hw *hw =
2365 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2366 struct e1000_vfta * shadow_vfta =
2367 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2372 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2373 E1000_VFTA_ENTRY_MASK);
2374 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2375 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2380 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2382 /* update local VFTA copy */
2383 shadow_vfta->vfta[vid_idx] = vfta;
2389 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2390 enum rte_vlan_type vlan_type,
2393 struct e1000_hw *hw =
2394 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2397 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2398 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2400 /* only outer TPID of double VLAN can be configured*/
2401 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2402 reg = E1000_READ_REG(hw, E1000_VET);
2403 reg = (reg & (~E1000_VET_VET_EXT)) |
2404 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2405 E1000_WRITE_REG(hw, E1000_VET, reg);
2410 /* all other TPID values are read-only*/
2411 PMD_DRV_LOG(ERR, "Not supported");
2417 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2419 struct e1000_hw *hw =
2420 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423 /* Filter Table Disable */
2424 reg = E1000_READ_REG(hw, E1000_RCTL);
2425 reg &= ~E1000_RCTL_CFIEN;
2426 reg &= ~E1000_RCTL_VFE;
2427 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2431 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2433 struct e1000_hw *hw =
2434 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435 struct e1000_vfta * shadow_vfta =
2436 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2440 /* Filter Table Enable, CFI not used for packet acceptance */
2441 reg = E1000_READ_REG(hw, E1000_RCTL);
2442 reg &= ~E1000_RCTL_CFIEN;
2443 reg |= E1000_RCTL_VFE;
2444 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2446 /* restore VFTA table */
2447 for (i = 0; i < IGB_VFTA_SIZE; i++)
2448 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2452 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2454 struct e1000_hw *hw =
2455 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2458 /* VLAN Mode Disable */
2459 reg = E1000_READ_REG(hw, E1000_CTRL);
2460 reg &= ~E1000_CTRL_VME;
2461 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2465 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2467 struct e1000_hw *hw =
2468 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2471 /* VLAN Mode Enable */
2472 reg = E1000_READ_REG(hw, E1000_CTRL);
2473 reg |= E1000_CTRL_VME;
2474 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2478 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2480 struct e1000_hw *hw =
2481 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2484 /* CTRL_EXT: Extended VLAN */
2485 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2486 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2487 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2489 /* Update maximum packet length */
2490 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2491 E1000_WRITE_REG(hw, E1000_RLPML,
2492 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2497 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2499 struct e1000_hw *hw =
2500 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2503 /* CTRL_EXT: Extended VLAN */
2504 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2505 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2506 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2508 /* Update maximum packet length */
2509 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2510 E1000_WRITE_REG(hw, E1000_RLPML,
2511 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2516 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2518 if(mask & ETH_VLAN_STRIP_MASK){
2519 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2520 igb_vlan_hw_strip_enable(dev);
2522 igb_vlan_hw_strip_disable(dev);
2525 if(mask & ETH_VLAN_FILTER_MASK){
2526 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2527 igb_vlan_hw_filter_enable(dev);
2529 igb_vlan_hw_filter_disable(dev);
2532 if(mask & ETH_VLAN_EXTEND_MASK){
2533 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2534 igb_vlan_hw_extend_enable(dev);
2536 igb_vlan_hw_extend_disable(dev);
2542 * It enables the interrupt mask and then enable the interrupt.
2545 * Pointer to struct rte_eth_dev.
2548 * - On success, zero.
2549 * - On failure, a negative value.
2552 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2554 struct e1000_interrupt *intr =
2555 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2557 intr->mask |= E1000_ICR_LSC;
2562 /* It clears the interrupt causes and enables the interrupt.
2563 * It will be called once only during nic initialized.
2566 * Pointer to struct rte_eth_dev.
2569 * - On success, zero.
2570 * - On failure, a negative value.
2572 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2574 uint32_t mask, regval;
2575 struct e1000_hw *hw =
2576 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2577 struct rte_eth_dev_info dev_info;
2579 memset(&dev_info, 0, sizeof(dev_info));
2580 eth_igb_infos_get(dev, &dev_info);
2582 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2583 regval = E1000_READ_REG(hw, E1000_EIMS);
2584 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2590 * It reads ICR and gets interrupt causes, check it and set a bit flag
2591 * to update link status.
2594 * Pointer to struct rte_eth_dev.
2597 * - On success, zero.
2598 * - On failure, a negative value.
2601 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2604 struct e1000_hw *hw =
2605 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2606 struct e1000_interrupt *intr =
2607 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2609 igb_intr_disable(hw);
2611 /* read-on-clear nic registers here */
2612 icr = E1000_READ_REG(hw, E1000_ICR);
2615 if (icr & E1000_ICR_LSC) {
2616 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2619 if (icr & E1000_ICR_VMMB)
2620 intr->flags |= E1000_FLAG_MAILBOX;
2626 * It executes link_update after knowing an interrupt is prsent.
2629 * Pointer to struct rte_eth_dev.
2632 * - On success, zero.
2633 * - On failure, a negative value.
2636 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2638 struct e1000_hw *hw =
2639 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640 struct e1000_interrupt *intr =
2641 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2642 uint32_t tctl, rctl;
2643 struct rte_eth_link link;
2646 if (intr->flags & E1000_FLAG_MAILBOX) {
2647 igb_pf_mbx_process(dev);
2648 intr->flags &= ~E1000_FLAG_MAILBOX;
2651 igb_intr_enable(dev);
2652 rte_intr_enable(&(dev->pci_dev->intr_handle));
2654 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2655 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2657 /* set get_link_status to check register later */
2658 hw->mac.get_link_status = 1;
2659 ret = eth_igb_link_update(dev, 0);
2661 /* check if link has changed */
2665 memset(&link, 0, sizeof(link));
2666 rte_igb_dev_atomic_read_link_status(dev, &link);
2667 if (link.link_status) {
2669 " Port %d: Link Up - speed %u Mbps - %s",
2671 (unsigned)link.link_speed,
2672 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2673 "full-duplex" : "half-duplex");
2675 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2676 dev->data->port_id);
2679 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2680 dev->pci_dev->addr.domain,
2681 dev->pci_dev->addr.bus,
2682 dev->pci_dev->addr.devid,
2683 dev->pci_dev->addr.function);
2684 tctl = E1000_READ_REG(hw, E1000_TCTL);
2685 rctl = E1000_READ_REG(hw, E1000_RCTL);
2686 if (link.link_status) {
2688 tctl |= E1000_TCTL_EN;
2689 rctl |= E1000_RCTL_EN;
2692 tctl &= ~E1000_TCTL_EN;
2693 rctl &= ~E1000_RCTL_EN;
2695 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2696 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2697 E1000_WRITE_FLUSH(hw);
2698 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2705 * Interrupt handler which shall be registered at first.
2708 * Pointer to interrupt handle.
2710 * The address of parameter (struct rte_eth_dev *) regsitered before.
2716 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2719 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2721 eth_igb_interrupt_get_status(dev);
2722 eth_igb_interrupt_action(dev);
2726 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2729 struct e1000_hw *hw =
2730 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2731 struct e1000_interrupt *intr =
2732 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2734 igbvf_intr_disable(hw);
2736 /* read-on-clear nic registers here */
2737 eicr = E1000_READ_REG(hw, E1000_EICR);
2740 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2741 intr->flags |= E1000_FLAG_MAILBOX;
2746 void igbvf_mbx_process(struct rte_eth_dev *dev)
2748 struct e1000_hw *hw =
2749 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2750 struct e1000_mbx_info *mbx = &hw->mbx;
2753 if (mbx->ops.read(hw, &in_msg, 1, 0))
2756 /* PF reset VF event */
2757 if (in_msg == E1000_PF_CONTROL_MSG)
2758 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2762 eth_igbvf_interrupt_action(struct rte_eth_dev *dev)
2764 struct e1000_interrupt *intr =
2765 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2767 if (intr->flags & E1000_FLAG_MAILBOX) {
2768 igbvf_mbx_process(dev);
2769 intr->flags &= ~E1000_FLAG_MAILBOX;
2772 igbvf_intr_enable(dev);
2773 rte_intr_enable(&dev->pci_dev->intr_handle);
2779 eth_igbvf_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2782 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2784 eth_igbvf_interrupt_get_status(dev);
2785 eth_igbvf_interrupt_action(dev);
2789 eth_igb_led_on(struct rte_eth_dev *dev)
2791 struct e1000_hw *hw;
2793 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2794 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2798 eth_igb_led_off(struct rte_eth_dev *dev)
2800 struct e1000_hw *hw;
2802 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2803 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2807 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2809 struct e1000_hw *hw;
2814 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2815 fc_conf->pause_time = hw->fc.pause_time;
2816 fc_conf->high_water = hw->fc.high_water;
2817 fc_conf->low_water = hw->fc.low_water;
2818 fc_conf->send_xon = hw->fc.send_xon;
2819 fc_conf->autoneg = hw->mac.autoneg;
2822 * Return rx_pause and tx_pause status according to actual setting of
2823 * the TFCE and RFCE bits in the CTRL register.
2825 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2826 if (ctrl & E1000_CTRL_TFCE)
2831 if (ctrl & E1000_CTRL_RFCE)
2836 if (rx_pause && tx_pause)
2837 fc_conf->mode = RTE_FC_FULL;
2839 fc_conf->mode = RTE_FC_RX_PAUSE;
2841 fc_conf->mode = RTE_FC_TX_PAUSE;
2843 fc_conf->mode = RTE_FC_NONE;
2849 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2851 struct e1000_hw *hw;
2853 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2859 uint32_t rx_buf_size;
2860 uint32_t max_high_water;
2863 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2864 if (fc_conf->autoneg != hw->mac.autoneg)
2866 rx_buf_size = igb_get_rx_buffer_size(hw);
2867 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2869 /* At least reserve one Ethernet frame for watermark */
2870 max_high_water = rx_buf_size - ETHER_MAX_LEN;
2871 if ((fc_conf->high_water > max_high_water) ||
2872 (fc_conf->high_water < fc_conf->low_water)) {
2873 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2874 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
2878 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2879 hw->fc.pause_time = fc_conf->pause_time;
2880 hw->fc.high_water = fc_conf->high_water;
2881 hw->fc.low_water = fc_conf->low_water;
2882 hw->fc.send_xon = fc_conf->send_xon;
2884 err = e1000_setup_link_generic(hw);
2885 if (err == E1000_SUCCESS) {
2887 /* check if we want to forward MAC frames - driver doesn't have native
2888 * capability to do that, so we'll write the registers ourselves */
2890 rctl = E1000_READ_REG(hw, E1000_RCTL);
2892 /* set or clear MFLCN.PMCF bit depending on configuration */
2893 if (fc_conf->mac_ctrl_frame_fwd != 0)
2894 rctl |= E1000_RCTL_PMCF;
2896 rctl &= ~E1000_RCTL_PMCF;
2898 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2899 E1000_WRITE_FLUSH(hw);
2904 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2908 #define E1000_RAH_POOLSEL_SHIFT (18)
2910 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2911 uint32_t index, __rte_unused uint32_t pool)
2913 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2916 e1000_rar_set(hw, mac_addr->addr_bytes, index);
2917 rah = E1000_READ_REG(hw, E1000_RAH(index));
2918 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2919 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2923 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2925 uint8_t addr[ETHER_ADDR_LEN];
2926 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2928 memset(addr, 0, sizeof(addr));
2930 e1000_rar_set(hw, addr, index);
2934 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2935 struct ether_addr *addr)
2937 eth_igb_rar_clear(dev, 0);
2939 eth_igb_rar_set(dev, (void *)addr, 0, 0);
2942 * Virtual Function operations
2945 igbvf_intr_disable(struct e1000_hw *hw)
2947 PMD_INIT_FUNC_TRACE();
2949 /* Clear interrupt mask to stop from interrupts being generated */
2950 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2952 E1000_WRITE_FLUSH(hw);
2956 igbvf_stop_adapter(struct rte_eth_dev *dev)
2960 struct rte_eth_dev_info dev_info;
2961 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2963 memset(&dev_info, 0, sizeof(dev_info));
2964 eth_igbvf_infos_get(dev, &dev_info);
2966 /* Clear interrupt mask to stop from interrupts being generated */
2967 igbvf_intr_disable(hw);
2969 /* Clear any pending interrupts, flush previous writes */
2970 E1000_READ_REG(hw, E1000_EICR);
2972 /* Disable the transmit unit. Each queue must be disabled. */
2973 for (i = 0; i < dev_info.max_tx_queues; i++)
2974 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2976 /* Disable the receive unit by stopping each queue */
2977 for (i = 0; i < dev_info.max_rx_queues; i++) {
2978 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2979 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2980 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2981 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2985 /* flush all queues disables */
2986 E1000_WRITE_FLUSH(hw);
2990 static int eth_igbvf_link_update(struct e1000_hw *hw)
2992 struct e1000_mbx_info *mbx = &hw->mbx;
2993 struct e1000_mac_info *mac = &hw->mac;
2994 int ret_val = E1000_SUCCESS;
2996 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2999 * We only want to run this if there has been a rst asserted.
3000 * in this case that could mean a link change, device reset,
3001 * or a virtual function reset
3004 /* If we were hit with a reset or timeout drop the link */
3005 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3006 mac->get_link_status = TRUE;
3008 if (!mac->get_link_status)
3011 /* if link status is down no point in checking to see if pf is up */
3012 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3015 /* if we passed all the tests above then the link is up and we no
3016 * longer need to check for link */
3017 mac->get_link_status = FALSE;
3025 igbvf_dev_configure(struct rte_eth_dev *dev)
3027 struct rte_eth_conf* conf = &dev->data->dev_conf;
3029 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3030 dev->data->port_id);
3033 * VF has no ability to enable/disable HW CRC
3034 * Keep the persistent behavior the same as Host PF
3036 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3037 if (!conf->rxmode.hw_strip_crc) {
3038 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3039 conf->rxmode.hw_strip_crc = 1;
3042 if (conf->rxmode.hw_strip_crc) {
3043 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3044 conf->rxmode.hw_strip_crc = 0;
3052 igbvf_dev_start(struct rte_eth_dev *dev)
3054 struct e1000_hw *hw =
3055 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3056 struct e1000_adapter *adapter =
3057 E1000_DEV_PRIVATE(dev->data->dev_private);
3059 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3060 uint32_t intr_vector = 0;
3062 PMD_INIT_FUNC_TRACE();
3064 hw->mac.ops.reset_hw(hw);
3065 adapter->stopped = 0;
3068 igbvf_set_vfta_all(dev,1);
3070 eth_igbvf_tx_init(dev);
3072 /* This can fail when allocating mbufs for descriptor rings */
3073 ret = eth_igbvf_rx_init(dev);
3075 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3076 igb_dev_clear_queues(dev);
3080 /* check and configure queue intr-vector mapping */
3081 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3082 intr_vector = dev->data->nb_rx_queues;
3083 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3088 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3089 intr_handle->intr_vec =
3090 rte_zmalloc("intr_vec",
3091 dev->data->nb_rx_queues * sizeof(int), 0);
3092 if (!intr_handle->intr_vec) {
3093 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3094 " intr_vec\n", dev->data->nb_rx_queues);
3099 eth_igbvf_configure_msix_intr(dev);
3101 /* enable uio/vfio intr/eventfd mapping */
3102 rte_intr_enable(intr_handle);
3104 /* resume enabled intr since hw reset */
3105 igbvf_intr_enable(dev);
3111 igbvf_dev_stop(struct rte_eth_dev *dev)
3113 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3115 PMD_INIT_FUNC_TRACE();
3117 igbvf_stop_adapter(dev);
3120 * Clear what we set, but we still keep shadow_vfta to
3121 * restore after device starts
3123 igbvf_set_vfta_all(dev,0);
3125 igb_dev_clear_queues(dev);
3127 /* disable intr eventfd mapping */
3128 rte_intr_disable(intr_handle);
3130 /* Clean datapath event and queue/vec mapping */
3131 rte_intr_efd_disable(intr_handle);
3132 if (intr_handle->intr_vec) {
3133 rte_free(intr_handle->intr_vec);
3134 intr_handle->intr_vec = NULL;
3139 igbvf_dev_close(struct rte_eth_dev *dev)
3141 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3142 struct e1000_adapter *adapter =
3143 E1000_DEV_PRIVATE(dev->data->dev_private);
3144 struct ether_addr addr;
3146 PMD_INIT_FUNC_TRACE();
3150 igbvf_dev_stop(dev);
3151 adapter->stopped = 1;
3152 igb_dev_free_queues(dev);
3155 * reprogram the RAR with a zero mac address,
3156 * to ensure that the VF traffic goes to the PF
3157 * after stop, close and detach of the VF.
3160 memset(&addr, 0, sizeof(addr));
3161 igbvf_default_mac_addr_set(dev, &addr);
3165 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3167 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3169 /* Set both unicast and multicast promisc */
3170 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3174 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3176 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3178 /* If in allmulticast mode leave multicast promisc */
3179 if (dev->data->all_multicast == 1)
3180 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3182 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3186 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3188 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3190 /* In promiscuous mode multicast promisc already set */
3191 if (dev->data->promiscuous == 0)
3192 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3196 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3198 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3200 /* In promiscuous mode leave multicast promisc enabled */
3201 if (dev->data->promiscuous == 0)
3202 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3205 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3207 struct e1000_mbx_info *mbx = &hw->mbx;
3211 /* After set vlan, vlan strip will also be enabled in igb driver*/
3212 msgbuf[0] = E1000_VF_SET_VLAN;
3214 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3216 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3218 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3222 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3226 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3227 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3234 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3236 struct e1000_hw *hw =
3237 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3238 struct e1000_vfta * shadow_vfta =
3239 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3240 int i = 0, j = 0, vfta = 0, mask = 1;
3242 for (i = 0; i < IGB_VFTA_SIZE; i++){
3243 vfta = shadow_vfta->vfta[i];
3246 for (j = 0; j < 32; j++){
3249 (uint16_t)((i<<5)+j), on);
3258 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3260 struct e1000_hw *hw =
3261 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3262 struct e1000_vfta * shadow_vfta =
3263 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3264 uint32_t vid_idx = 0;
3265 uint32_t vid_bit = 0;
3268 PMD_INIT_FUNC_TRACE();
3270 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3271 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3273 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3276 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3277 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3279 /*Save what we set and retore it after device reset*/
3281 shadow_vfta->vfta[vid_idx] |= vid_bit;
3283 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3289 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3291 struct e1000_hw *hw =
3292 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3294 /* index is not used by rar_set() */
3295 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3300 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3301 struct rte_eth_rss_reta_entry64 *reta_conf,
3306 uint16_t idx, shift;
3307 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3309 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3310 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3311 "(%d) doesn't match the number hardware can supported "
3312 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3316 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3317 idx = i / RTE_RETA_GROUP_SIZE;
3318 shift = i % RTE_RETA_GROUP_SIZE;
3319 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3323 if (mask == IGB_4_BIT_MASK)
3326 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3327 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3328 if (mask & (0x1 << j))
3329 reta |= reta_conf[idx].reta[shift + j] <<
3332 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3334 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3341 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3342 struct rte_eth_rss_reta_entry64 *reta_conf,
3347 uint16_t idx, shift;
3348 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3350 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3351 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3352 "(%d) doesn't match the number hardware can supported "
3353 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3357 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3358 idx = i / RTE_RETA_GROUP_SIZE;
3359 shift = i % RTE_RETA_GROUP_SIZE;
3360 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3364 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3365 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3366 if (mask & (0x1 << j))
3367 reta_conf[idx].reta[shift + j] =
3368 ((reta >> (CHAR_BIT * j)) &
3376 #define MAC_TYPE_FILTER_SUP(type) do {\
3377 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3378 (type) != e1000_82576)\
3383 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3384 struct rte_eth_syn_filter *filter,
3387 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3388 uint32_t synqf, rfctl;
3390 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3393 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3396 if (synqf & E1000_SYN_FILTER_ENABLE)
3399 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3400 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3402 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3403 if (filter->hig_pri)
3404 rfctl |= E1000_RFCTL_SYNQFP;
3406 rfctl &= ~E1000_RFCTL_SYNQFP;
3408 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3410 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3415 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3416 E1000_WRITE_FLUSH(hw);
3421 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3422 struct rte_eth_syn_filter *filter)
3424 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3425 uint32_t synqf, rfctl;
3427 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3428 if (synqf & E1000_SYN_FILTER_ENABLE) {
3429 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3430 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3431 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3432 E1000_SYN_FILTER_QUEUE_SHIFT);
3440 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3441 enum rte_filter_op filter_op,
3444 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3447 MAC_TYPE_FILTER_SUP(hw->mac.type);
3449 if (filter_op == RTE_ETH_FILTER_NOP)
3453 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3458 switch (filter_op) {
3459 case RTE_ETH_FILTER_ADD:
3460 ret = eth_igb_syn_filter_set(dev,
3461 (struct rte_eth_syn_filter *)arg,
3464 case RTE_ETH_FILTER_DELETE:
3465 ret = eth_igb_syn_filter_set(dev,
3466 (struct rte_eth_syn_filter *)arg,
3469 case RTE_ETH_FILTER_GET:
3470 ret = eth_igb_syn_filter_get(dev,
3471 (struct rte_eth_syn_filter *)arg);
3474 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3482 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
3483 if ((type) != e1000_82580 && (type) != e1000_i350)\
3487 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3489 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3490 struct e1000_2tuple_filter_info *filter_info)
3492 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3494 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3495 return -EINVAL; /* filter index is out of range. */
3496 if (filter->tcp_flags > TCP_FLAG_ALL)
3497 return -EINVAL; /* flags is invalid. */
3499 switch (filter->dst_port_mask) {
3501 filter_info->dst_port_mask = 0;
3502 filter_info->dst_port = filter->dst_port;
3505 filter_info->dst_port_mask = 1;
3508 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3512 switch (filter->proto_mask) {
3514 filter_info->proto_mask = 0;
3515 filter_info->proto = filter->proto;
3518 filter_info->proto_mask = 1;
3521 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3525 filter_info->priority = (uint8_t)filter->priority;
3526 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3527 filter_info->tcp_flags = filter->tcp_flags;
3529 filter_info->tcp_flags = 0;
3534 static inline struct e1000_2tuple_filter *
3535 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3536 struct e1000_2tuple_filter_info *key)
3538 struct e1000_2tuple_filter *it;
3540 TAILQ_FOREACH(it, filter_list, entries) {
3541 if (memcmp(key, &it->filter_info,
3542 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3550 * igb_add_2tuple_filter - add a 2tuple filter
3553 * dev: Pointer to struct rte_eth_dev.
3554 * ntuple_filter: ponter to the filter that will be added.
3557 * - On success, zero.
3558 * - On failure, a negative value.
3561 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3562 struct rte_eth_ntuple_filter *ntuple_filter)
3564 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3565 struct e1000_filter_info *filter_info =
3566 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3567 struct e1000_2tuple_filter *filter;
3568 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3569 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3572 filter = rte_zmalloc("e1000_2tuple_filter",
3573 sizeof(struct e1000_2tuple_filter), 0);
3577 ret = ntuple_filter_to_2tuple(ntuple_filter,
3578 &filter->filter_info);
3583 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3584 &filter->filter_info) != NULL) {
3585 PMD_DRV_LOG(ERR, "filter exists.");
3589 filter->queue = ntuple_filter->queue;
3592 * look for an unused 2tuple filter index,
3593 * and insert the filter to list.
3595 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3596 if (!(filter_info->twotuple_mask & (1 << i))) {
3597 filter_info->twotuple_mask |= 1 << i;
3599 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3605 if (i >= E1000_MAX_TTQF_FILTERS) {
3606 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3611 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3612 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3613 imir |= E1000_IMIR_PORT_BP;
3615 imir &= ~E1000_IMIR_PORT_BP;
3617 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3619 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3620 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3621 ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3622 if (filter->filter_info.proto_mask == 0)
3623 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3625 /* tcp flags bits setting. */
3626 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3627 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3628 imir_ext |= E1000_IMIREXT_CTRL_URG;
3629 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3630 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3631 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3632 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3633 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3634 imir_ext |= E1000_IMIREXT_CTRL_RST;
3635 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3636 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3637 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3638 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3640 imir_ext |= E1000_IMIREXT_CTRL_BP;
3641 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3642 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3643 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3648 * igb_remove_2tuple_filter - remove a 2tuple filter
3651 * dev: Pointer to struct rte_eth_dev.
3652 * ntuple_filter: ponter to the filter that will be removed.
3655 * - On success, zero.
3656 * - On failure, a negative value.
3659 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3660 struct rte_eth_ntuple_filter *ntuple_filter)
3662 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3663 struct e1000_filter_info *filter_info =
3664 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3665 struct e1000_2tuple_filter_info filter_2tuple;
3666 struct e1000_2tuple_filter *filter;
3669 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3670 ret = ntuple_filter_to_2tuple(ntuple_filter,
3675 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3677 if (filter == NULL) {
3678 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3682 filter_info->twotuple_mask &= ~(1 << filter->index);
3683 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3686 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3687 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3688 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3692 static inline struct e1000_flex_filter *
3693 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3694 struct e1000_flex_filter_info *key)
3696 struct e1000_flex_filter *it;
3698 TAILQ_FOREACH(it, filter_list, entries) {
3699 if (memcmp(key, &it->filter_info,
3700 sizeof(struct e1000_flex_filter_info)) == 0)
3708 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3709 struct rte_eth_flex_filter *filter,
3712 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3713 struct e1000_filter_info *filter_info =
3714 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3715 struct e1000_flex_filter *flex_filter, *it;
3716 uint32_t wufc, queueing, mask;
3718 uint8_t shift, i, j = 0;
3720 flex_filter = rte_zmalloc("e1000_flex_filter",
3721 sizeof(struct e1000_flex_filter), 0);
3722 if (flex_filter == NULL)
3725 flex_filter->filter_info.len = filter->len;
3726 flex_filter->filter_info.priority = filter->priority;
3727 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3728 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3730 /* reverse bits in flex filter's mask*/
3731 for (shift = 0; shift < CHAR_BIT; shift++) {
3732 if (filter->mask[i] & (0x01 << shift))
3733 mask |= (0x80 >> shift);
3735 flex_filter->filter_info.mask[i] = mask;
3738 wufc = E1000_READ_REG(hw, E1000_WUFC);
3739 if (flex_filter->index < E1000_MAX_FHFT)
3740 reg_off = E1000_FHFT(flex_filter->index);
3742 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3745 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3746 &flex_filter->filter_info) != NULL) {
3747 PMD_DRV_LOG(ERR, "filter exists.");
3748 rte_free(flex_filter);
3751 flex_filter->queue = filter->queue;
3753 * look for an unused flex filter index
3754 * and insert the filter into the list.
3756 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3757 if (!(filter_info->flex_mask & (1 << i))) {
3758 filter_info->flex_mask |= 1 << i;
3759 flex_filter->index = i;
3760 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3766 if (i >= E1000_MAX_FLEX_FILTERS) {
3767 PMD_DRV_LOG(ERR, "flex filters are full.");
3768 rte_free(flex_filter);
3772 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3773 (E1000_WUFC_FLX0 << flex_filter->index));
3774 queueing = filter->len |
3775 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3776 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3777 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3779 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3780 E1000_WRITE_REG(hw, reg_off,
3781 flex_filter->filter_info.dwords[j]);
3782 reg_off += sizeof(uint32_t);
3783 E1000_WRITE_REG(hw, reg_off,
3784 flex_filter->filter_info.dwords[++j]);
3785 reg_off += sizeof(uint32_t);
3786 E1000_WRITE_REG(hw, reg_off,
3787 (uint32_t)flex_filter->filter_info.mask[i]);
3788 reg_off += sizeof(uint32_t) * 2;
3792 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3793 &flex_filter->filter_info);
3795 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3796 rte_free(flex_filter);
3800 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3801 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3802 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3803 (~(E1000_WUFC_FLX0 << it->index)));
3805 filter_info->flex_mask &= ~(1 << it->index);
3806 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3808 rte_free(flex_filter);
3815 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3816 struct rte_eth_flex_filter *filter)
3818 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3819 struct e1000_filter_info *filter_info =
3820 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3821 struct e1000_flex_filter flex_filter, *it;
3822 uint32_t wufc, queueing, wufc_en = 0;
3824 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3825 flex_filter.filter_info.len = filter->len;
3826 flex_filter.filter_info.priority = filter->priority;
3827 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3828 memcpy(flex_filter.filter_info.mask, filter->mask,
3829 RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3831 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3832 &flex_filter.filter_info);
3834 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3838 wufc = E1000_READ_REG(hw, E1000_WUFC);
3839 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3841 if ((wufc & wufc_en) == wufc_en) {
3842 uint32_t reg_off = 0;
3843 if (it->index < E1000_MAX_FHFT)
3844 reg_off = E1000_FHFT(it->index);
3846 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3848 queueing = E1000_READ_REG(hw,
3849 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3850 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3851 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3852 E1000_FHFT_QUEUEING_PRIO_SHIFT;
3853 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3854 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3861 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3862 enum rte_filter_op filter_op,
3865 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3866 struct rte_eth_flex_filter *filter;
3869 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3871 if (filter_op == RTE_ETH_FILTER_NOP)
3875 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3880 filter = (struct rte_eth_flex_filter *)arg;
3881 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3882 || filter->len % sizeof(uint64_t) != 0) {
3883 PMD_DRV_LOG(ERR, "filter's length is out of range");
3886 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3887 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3891 switch (filter_op) {
3892 case RTE_ETH_FILTER_ADD:
3893 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3895 case RTE_ETH_FILTER_DELETE:
3896 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3898 case RTE_ETH_FILTER_GET:
3899 ret = eth_igb_get_flex_filter(dev, filter);
3902 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3910 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3912 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3913 struct e1000_5tuple_filter_info *filter_info)
3915 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3917 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3918 return -EINVAL; /* filter index is out of range. */
3919 if (filter->tcp_flags > TCP_FLAG_ALL)
3920 return -EINVAL; /* flags is invalid. */
3922 switch (filter->dst_ip_mask) {
3924 filter_info->dst_ip_mask = 0;
3925 filter_info->dst_ip = filter->dst_ip;
3928 filter_info->dst_ip_mask = 1;
3931 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3935 switch (filter->src_ip_mask) {
3937 filter_info->src_ip_mask = 0;
3938 filter_info->src_ip = filter->src_ip;
3941 filter_info->src_ip_mask = 1;
3944 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3948 switch (filter->dst_port_mask) {
3950 filter_info->dst_port_mask = 0;
3951 filter_info->dst_port = filter->dst_port;
3954 filter_info->dst_port_mask = 1;
3957 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3961 switch (filter->src_port_mask) {
3963 filter_info->src_port_mask = 0;
3964 filter_info->src_port = filter->src_port;
3967 filter_info->src_port_mask = 1;
3970 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3974 switch (filter->proto_mask) {
3976 filter_info->proto_mask = 0;
3977 filter_info->proto = filter->proto;
3980 filter_info->proto_mask = 1;
3983 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3987 filter_info->priority = (uint8_t)filter->priority;
3988 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3989 filter_info->tcp_flags = filter->tcp_flags;
3991 filter_info->tcp_flags = 0;
3996 static inline struct e1000_5tuple_filter *
3997 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3998 struct e1000_5tuple_filter_info *key)
4000 struct e1000_5tuple_filter *it;
4002 TAILQ_FOREACH(it, filter_list, entries) {
4003 if (memcmp(key, &it->filter_info,
4004 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4012 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4015 * dev: Pointer to struct rte_eth_dev.
4016 * ntuple_filter: ponter to the filter that will be added.
4019 * - On success, zero.
4020 * - On failure, a negative value.
4023 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4024 struct rte_eth_ntuple_filter *ntuple_filter)
4026 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4027 struct e1000_filter_info *filter_info =
4028 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4029 struct e1000_5tuple_filter *filter;
4030 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4031 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4035 filter = rte_zmalloc("e1000_5tuple_filter",
4036 sizeof(struct e1000_5tuple_filter), 0);
4040 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4041 &filter->filter_info);
4047 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4048 &filter->filter_info) != NULL) {
4049 PMD_DRV_LOG(ERR, "filter exists.");
4053 filter->queue = ntuple_filter->queue;
4056 * look for an unused 5tuple filter index,
4057 * and insert the filter to list.
4059 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4060 if (!(filter_info->fivetuple_mask & (1 << i))) {
4061 filter_info->fivetuple_mask |= 1 << i;
4063 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4069 if (i >= E1000_MAX_FTQF_FILTERS) {
4070 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4075 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4076 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4077 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4078 if (filter->filter_info.dst_ip_mask == 0)
4079 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4080 if (filter->filter_info.src_port_mask == 0)
4081 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4082 if (filter->filter_info.proto_mask == 0)
4083 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4084 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4085 E1000_FTQF_QUEUE_MASK;
4086 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4087 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4088 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4089 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4091 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4092 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4094 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4095 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4096 imir |= E1000_IMIR_PORT_BP;
4098 imir &= ~E1000_IMIR_PORT_BP;
4099 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4101 /* tcp flags bits setting. */
4102 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4103 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4104 imir_ext |= E1000_IMIREXT_CTRL_URG;
4105 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4106 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4107 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4108 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4109 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4110 imir_ext |= E1000_IMIREXT_CTRL_RST;
4111 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4112 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4113 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4114 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4116 imir_ext |= E1000_IMIREXT_CTRL_BP;
4117 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4118 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4123 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4126 * dev: Pointer to struct rte_eth_dev.
4127 * ntuple_filter: ponter to the filter that will be removed.
4130 * - On success, zero.
4131 * - On failure, a negative value.
4134 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4135 struct rte_eth_ntuple_filter *ntuple_filter)
4137 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4138 struct e1000_filter_info *filter_info =
4139 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4140 struct e1000_5tuple_filter_info filter_5tuple;
4141 struct e1000_5tuple_filter *filter;
4144 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4145 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4150 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4152 if (filter == NULL) {
4153 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4157 filter_info->fivetuple_mask &= ~(1 << filter->index);
4158 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4161 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4162 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4163 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4164 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4165 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4166 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4167 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4172 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4175 struct e1000_hw *hw;
4176 struct rte_eth_dev_info dev_info;
4177 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4180 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4182 #ifdef RTE_LIBRTE_82571_SUPPORT
4183 /* XXX: not bigger than max_rx_pktlen */
4184 if (hw->mac.type == e1000_82571)
4187 eth_igb_infos_get(dev, &dev_info);
4189 /* check that mtu is within the allowed range */
4190 if ((mtu < ETHER_MIN_MTU) ||
4191 (frame_size > dev_info.max_rx_pktlen))
4194 /* refuse mtu that requires the support of scattered packets when this
4195 * feature has not been enabled before. */
4196 if (!dev->data->scattered_rx &&
4197 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4200 rctl = E1000_READ_REG(hw, E1000_RCTL);
4202 /* switch to jumbo mode if needed */
4203 if (frame_size > ETHER_MAX_LEN) {
4204 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4205 rctl |= E1000_RCTL_LPE;
4207 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4208 rctl &= ~E1000_RCTL_LPE;
4210 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4212 /* update max frame size */
4213 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4215 E1000_WRITE_REG(hw, E1000_RLPML,
4216 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4222 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4225 * dev: Pointer to struct rte_eth_dev.
4226 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4227 * add: if true, add filter, if false, remove filter
4230 * - On success, zero.
4231 * - On failure, a negative value.
4234 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4235 struct rte_eth_ntuple_filter *ntuple_filter,
4238 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4241 switch (ntuple_filter->flags) {
4242 case RTE_5TUPLE_FLAGS:
4243 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4244 if (hw->mac.type != e1000_82576)
4247 ret = igb_add_5tuple_filter_82576(dev,
4250 ret = igb_remove_5tuple_filter_82576(dev,
4253 case RTE_2TUPLE_FLAGS:
4254 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4255 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4258 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4260 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4271 * igb_get_ntuple_filter - get a ntuple filter
4274 * dev: Pointer to struct rte_eth_dev.
4275 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4278 * - On success, zero.
4279 * - On failure, a negative value.
4282 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4283 struct rte_eth_ntuple_filter *ntuple_filter)
4285 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4286 struct e1000_filter_info *filter_info =
4287 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4288 struct e1000_5tuple_filter_info filter_5tuple;
4289 struct e1000_2tuple_filter_info filter_2tuple;
4290 struct e1000_5tuple_filter *p_5tuple_filter;
4291 struct e1000_2tuple_filter *p_2tuple_filter;
4294 switch (ntuple_filter->flags) {
4295 case RTE_5TUPLE_FLAGS:
4296 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4297 if (hw->mac.type != e1000_82576)
4299 memset(&filter_5tuple,
4301 sizeof(struct e1000_5tuple_filter_info));
4302 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4306 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4307 &filter_info->fivetuple_list,
4309 if (p_5tuple_filter == NULL) {
4310 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4313 ntuple_filter->queue = p_5tuple_filter->queue;
4315 case RTE_2TUPLE_FLAGS:
4316 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4317 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4319 memset(&filter_2tuple,
4321 sizeof(struct e1000_2tuple_filter_info));
4322 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4325 p_2tuple_filter = igb_2tuple_filter_lookup(
4326 &filter_info->twotuple_list,
4328 if (p_2tuple_filter == NULL) {
4329 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4332 ntuple_filter->queue = p_2tuple_filter->queue;
4343 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4344 * @dev: pointer to rte_eth_dev structure
4345 * @filter_op:operation will be taken.
4346 * @arg: a pointer to specific structure corresponding to the filter_op
4349 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4350 enum rte_filter_op filter_op,
4353 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4356 MAC_TYPE_FILTER_SUP(hw->mac.type);
4358 if (filter_op == RTE_ETH_FILTER_NOP)
4362 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4367 switch (filter_op) {
4368 case RTE_ETH_FILTER_ADD:
4369 ret = igb_add_del_ntuple_filter(dev,
4370 (struct rte_eth_ntuple_filter *)arg,
4373 case RTE_ETH_FILTER_DELETE:
4374 ret = igb_add_del_ntuple_filter(dev,
4375 (struct rte_eth_ntuple_filter *)arg,
4378 case RTE_ETH_FILTER_GET:
4379 ret = igb_get_ntuple_filter(dev,
4380 (struct rte_eth_ntuple_filter *)arg);
4383 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4391 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4396 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4397 if (filter_info->ethertype_filters[i] == ethertype &&
4398 (filter_info->ethertype_mask & (1 << i)))
4405 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4410 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4411 if (!(filter_info->ethertype_mask & (1 << i))) {
4412 filter_info->ethertype_mask |= 1 << i;
4413 filter_info->ethertype_filters[i] = ethertype;
4421 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4424 if (idx >= E1000_MAX_ETQF_FILTERS)
4426 filter_info->ethertype_mask &= ~(1 << idx);
4427 filter_info->ethertype_filters[idx] = 0;
4433 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4434 struct rte_eth_ethertype_filter *filter,
4437 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4438 struct e1000_filter_info *filter_info =
4439 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4443 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4444 filter->ether_type == ETHER_TYPE_IPv6) {
4445 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4446 " ethertype filter.", filter->ether_type);
4450 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4451 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4454 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4455 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4459 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4460 if (ret >= 0 && add) {
4461 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4462 filter->ether_type);
4465 if (ret < 0 && !add) {
4466 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4467 filter->ether_type);
4472 ret = igb_ethertype_filter_insert(filter_info,
4473 filter->ether_type);
4475 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4479 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4480 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4481 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4483 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4487 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4488 E1000_WRITE_FLUSH(hw);
4494 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4495 struct rte_eth_ethertype_filter *filter)
4497 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4498 struct e1000_filter_info *filter_info =
4499 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4503 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4505 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4506 filter->ether_type);
4510 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4511 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4512 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4514 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4515 E1000_ETQF_QUEUE_SHIFT;
4523 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4524 * @dev: pointer to rte_eth_dev structure
4525 * @filter_op:operation will be taken.
4526 * @arg: a pointer to specific structure corresponding to the filter_op
4529 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4530 enum rte_filter_op filter_op,
4533 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4536 MAC_TYPE_FILTER_SUP(hw->mac.type);
4538 if (filter_op == RTE_ETH_FILTER_NOP)
4542 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4547 switch (filter_op) {
4548 case RTE_ETH_FILTER_ADD:
4549 ret = igb_add_del_ethertype_filter(dev,
4550 (struct rte_eth_ethertype_filter *)arg,
4553 case RTE_ETH_FILTER_DELETE:
4554 ret = igb_add_del_ethertype_filter(dev,
4555 (struct rte_eth_ethertype_filter *)arg,
4558 case RTE_ETH_FILTER_GET:
4559 ret = igb_get_ethertype_filter(dev,
4560 (struct rte_eth_ethertype_filter *)arg);
4563 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4571 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4572 enum rte_filter_type filter_type,
4573 enum rte_filter_op filter_op,
4578 switch (filter_type) {
4579 case RTE_ETH_FILTER_NTUPLE:
4580 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4582 case RTE_ETH_FILTER_ETHERTYPE:
4583 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4585 case RTE_ETH_FILTER_SYN:
4586 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4588 case RTE_ETH_FILTER_FLEXIBLE:
4589 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4592 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4601 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4602 struct ether_addr *mc_addr_set,
4603 uint32_t nb_mc_addr)
4605 struct e1000_hw *hw;
4607 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4608 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4613 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4615 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4616 uint64_t systime_cycles;
4618 switch (hw->mac.type) {
4622 * Need to read System Time Residue Register to be able
4623 * to read the other two registers.
4625 E1000_READ_REG(hw, E1000_SYSTIMR);
4626 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4627 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4628 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4635 * Need to read System Time Residue Register to be able
4636 * to read the other two registers.
4638 E1000_READ_REG(hw, E1000_SYSTIMR);
4639 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4640 /* Only the 8 LSB are valid. */
4641 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4645 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4646 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4651 return systime_cycles;
4655 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4657 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4658 uint64_t rx_tstamp_cycles;
4660 switch (hw->mac.type) {
4663 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4664 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4665 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4671 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4672 /* Only the 8 LSB are valid. */
4673 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4677 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4678 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4683 return rx_tstamp_cycles;
4687 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4689 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4690 uint64_t tx_tstamp_cycles;
4692 switch (hw->mac.type) {
4695 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4696 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4697 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4703 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4704 /* Only the 8 LSB are valid. */
4705 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4709 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4710 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4715 return tx_tstamp_cycles;
4719 igb_start_timecounters(struct rte_eth_dev *dev)
4721 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4722 struct e1000_adapter *adapter =
4723 (struct e1000_adapter *)dev->data->dev_private;
4724 uint32_t incval = 1;
4726 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4728 switch (hw->mac.type) {
4732 /* 32 LSB bits + 8 MSB bits = 40 bits */
4733 mask = (1ULL << 40) - 1;
4738 * Start incrementing the register
4739 * used to timestamp PTP packets.
4741 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4744 incval = E1000_INCVALUE_82576;
4745 shift = IGB_82576_TSYNC_SHIFT;
4746 E1000_WRITE_REG(hw, E1000_TIMINCA,
4747 E1000_INCPERIOD_82576 | incval);
4754 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4755 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4756 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4758 adapter->systime_tc.cc_mask = mask;
4759 adapter->systime_tc.cc_shift = shift;
4760 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4762 adapter->rx_tstamp_tc.cc_mask = mask;
4763 adapter->rx_tstamp_tc.cc_shift = shift;
4764 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4766 adapter->tx_tstamp_tc.cc_mask = mask;
4767 adapter->tx_tstamp_tc.cc_shift = shift;
4768 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4772 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4774 struct e1000_adapter *adapter =
4775 (struct e1000_adapter *)dev->data->dev_private;
4777 adapter->systime_tc.nsec += delta;
4778 adapter->rx_tstamp_tc.nsec += delta;
4779 adapter->tx_tstamp_tc.nsec += delta;
4785 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4788 struct e1000_adapter *adapter =
4789 (struct e1000_adapter *)dev->data->dev_private;
4791 ns = rte_timespec_to_ns(ts);
4793 /* Set the timecounters to a new value. */
4794 adapter->systime_tc.nsec = ns;
4795 adapter->rx_tstamp_tc.nsec = ns;
4796 adapter->tx_tstamp_tc.nsec = ns;
4802 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4804 uint64_t ns, systime_cycles;
4805 struct e1000_adapter *adapter =
4806 (struct e1000_adapter *)dev->data->dev_private;
4808 systime_cycles = igb_read_systime_cyclecounter(dev);
4809 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4810 *ts = rte_ns_to_timespec(ns);
4816 igb_timesync_enable(struct rte_eth_dev *dev)
4818 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4822 /* Stop the timesync system time. */
4823 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4824 /* Reset the timesync system time value. */
4825 switch (hw->mac.type) {
4831 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4834 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4835 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4838 /* Not supported. */
4842 /* Enable system time for it isn't on by default. */
4843 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4844 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4845 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4847 igb_start_timecounters(dev);
4849 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4850 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4852 E1000_ETQF_FILTER_ENABLE |
4855 /* Enable timestamping of received PTP packets. */
4856 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4857 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4858 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4860 /* Enable Timestamping of transmitted PTP packets. */
4861 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4862 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4863 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4869 igb_timesync_disable(struct rte_eth_dev *dev)
4871 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4874 /* Disable timestamping of transmitted PTP packets. */
4875 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4876 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4877 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4879 /* Disable timestamping of received PTP packets. */
4880 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4881 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4882 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4884 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4885 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4887 /* Stop incrementating the System Time registers. */
4888 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4894 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4895 struct timespec *timestamp,
4896 uint32_t flags __rte_unused)
4898 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4899 struct e1000_adapter *adapter =
4900 (struct e1000_adapter *)dev->data->dev_private;
4901 uint32_t tsync_rxctl;
4902 uint64_t rx_tstamp_cycles;
4905 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4906 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4909 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4910 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4911 *timestamp = rte_ns_to_timespec(ns);
4917 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4918 struct timespec *timestamp)
4920 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4921 struct e1000_adapter *adapter =
4922 (struct e1000_adapter *)dev->data->dev_private;
4923 uint32_t tsync_txctl;
4924 uint64_t tx_tstamp_cycles;
4927 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4928 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4931 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4932 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4933 *timestamp = rte_ns_to_timespec(ns);
4939 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4943 const struct reg_info *reg_group;
4945 while ((reg_group = igb_regs[g_ind++]))
4946 count += igb_reg_group_count(reg_group);
4952 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4956 const struct reg_info *reg_group;
4958 while ((reg_group = igbvf_regs[g_ind++]))
4959 count += igb_reg_group_count(reg_group);
4965 eth_igb_get_regs(struct rte_eth_dev *dev,
4966 struct rte_dev_reg_info *regs)
4968 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4969 uint32_t *data = regs->data;
4972 const struct reg_info *reg_group;
4975 regs->length = eth_igb_get_reg_length(dev);
4976 regs->width = sizeof(uint32_t);
4980 /* Support only full register dump */
4981 if ((regs->length == 0) ||
4982 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4983 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4985 while ((reg_group = igb_regs[g_ind++]))
4986 count += igb_read_regs_group(dev, &data[count],
4995 igbvf_get_regs(struct rte_eth_dev *dev,
4996 struct rte_dev_reg_info *regs)
4998 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4999 uint32_t *data = regs->data;
5002 const struct reg_info *reg_group;
5005 regs->length = igbvf_get_reg_length(dev);
5006 regs->width = sizeof(uint32_t);
5010 /* Support only full register dump */
5011 if ((regs->length == 0) ||
5012 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5013 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5015 while ((reg_group = igbvf_regs[g_ind++]))
5016 count += igb_read_regs_group(dev, &data[count],
5025 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5027 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5029 /* Return unit is byte count */
5030 return hw->nvm.word_size * 2;
5034 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5035 struct rte_dev_eeprom_info *in_eeprom)
5037 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5038 struct e1000_nvm_info *nvm = &hw->nvm;
5039 uint16_t *data = in_eeprom->data;
5042 first = in_eeprom->offset >> 1;
5043 length = in_eeprom->length >> 1;
5044 if ((first >= hw->nvm.word_size) ||
5045 ((first + length) >= hw->nvm.word_size))
5048 in_eeprom->magic = hw->vendor_id |
5049 ((uint32_t)hw->device_id << 16);
5051 if ((nvm->ops.read) == NULL)
5054 return nvm->ops.read(hw, first, length, data);
5058 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5059 struct rte_dev_eeprom_info *in_eeprom)
5061 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5062 struct e1000_nvm_info *nvm = &hw->nvm;
5063 uint16_t *data = in_eeprom->data;
5066 first = in_eeprom->offset >> 1;
5067 length = in_eeprom->length >> 1;
5068 if ((first >= hw->nvm.word_size) ||
5069 ((first + length) >= hw->nvm.word_size))
5072 in_eeprom->magic = (uint32_t)hw->vendor_id |
5073 ((uint32_t)hw->device_id << 16);
5075 if ((nvm->ops.write) == NULL)
5077 return nvm->ops.write(hw, first, length, data);
5081 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5083 struct e1000_hw *hw =
5084 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5085 uint32_t mask = 1 << queue_id;
5087 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5088 E1000_WRITE_FLUSH(hw);
5094 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5096 struct e1000_hw *hw =
5097 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5098 uint32_t mask = 1 << queue_id;
5101 regval = E1000_READ_REG(hw, E1000_EIMS);
5102 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5103 E1000_WRITE_FLUSH(hw);
5105 rte_intr_enable(&dev->pci_dev->intr_handle);
5111 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5112 uint8_t index, uint8_t offset)
5114 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5117 val &= ~((uint32_t)0xFF << offset);
5119 /* write vector and valid bit */
5120 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5122 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5126 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5127 uint8_t queue, uint8_t msix_vector)
5131 if (hw->mac.type == e1000_82575) {
5133 tmp = E1000_EICR_RX_QUEUE0 << queue;
5134 else if (direction == 1)
5135 tmp = E1000_EICR_TX_QUEUE0 << queue;
5136 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5137 } else if (hw->mac.type == e1000_82576) {
5138 if ((direction == 0) || (direction == 1))
5139 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5140 ((queue & 0x8) << 1) +
5142 } else if ((hw->mac.type == e1000_82580) ||
5143 (hw->mac.type == e1000_i350) ||
5144 (hw->mac.type == e1000_i354) ||
5145 (hw->mac.type == e1000_i210) ||
5146 (hw->mac.type == e1000_i211)) {
5147 if ((direction == 0) || (direction == 1))
5148 eth_igb_write_ivar(hw, msix_vector,
5150 ((queue & 0x1) << 4) +
5155 /* Sets up the hardware to generate MSI-X interrupts properly
5157 * board private structure
5160 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5163 uint32_t tmpval, regval, intr_mask;
5164 struct e1000_hw *hw =
5165 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5166 uint32_t vec = E1000_MISC_VEC_ID;
5167 uint32_t base = E1000_MISC_VEC_ID;
5168 uint32_t misc_shift = 0;
5170 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5172 /* won't configure msix register if no mapping is done
5173 * between intr vector and event fd
5175 if (!rte_intr_dp_is_en(intr_handle))
5178 if (rte_intr_allow_others(intr_handle)) {
5179 vec = base = E1000_RX_VEC_START;
5183 /* set interrupt vector for other causes */
5184 if (hw->mac.type == e1000_82575) {
5185 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5186 /* enable MSI-X PBA support */
5187 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5189 /* Auto-Mask interrupts upon ICR read */
5190 tmpval |= E1000_CTRL_EXT_EIAME;
5191 tmpval |= E1000_CTRL_EXT_IRCA;
5193 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5195 /* enable msix_other interrupt */
5196 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5197 regval = E1000_READ_REG(hw, E1000_EIAC);
5198 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5199 regval = E1000_READ_REG(hw, E1000_EIAM);
5200 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5201 } else if ((hw->mac.type == e1000_82576) ||
5202 (hw->mac.type == e1000_82580) ||
5203 (hw->mac.type == e1000_i350) ||
5204 (hw->mac.type == e1000_i354) ||
5205 (hw->mac.type == e1000_i210) ||
5206 (hw->mac.type == e1000_i211)) {
5207 /* turn on MSI-X capability first */
5208 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5209 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5211 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5213 regval = E1000_READ_REG(hw, E1000_EIAC);
5214 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5216 /* enable msix_other interrupt */
5217 regval = E1000_READ_REG(hw, E1000_EIMS);
5218 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5219 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5220 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5223 /* use EIAM to auto-mask when MSI-X interrupt
5224 * is asserted, this saves a register write for every interrupt
5226 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5228 regval = E1000_READ_REG(hw, E1000_EIAM);
5229 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5231 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5232 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5233 intr_handle->intr_vec[queue_id] = vec;
5234 if (vec < base + intr_handle->nb_efd - 1)
5238 E1000_WRITE_FLUSH(hw);
5241 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd.pci_drv);
5242 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5243 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd.pci_drv);
5244 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);