4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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14 * notice, this list of conditions and the following disclaimer in
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34 #include <sys/queue.h>
40 #include <rte_common.h>
41 #include <rte_interrupts.h>
42 #include <rte_byteorder.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memory.h>
49 #include <rte_memzone.h>
51 #include <rte_atomic.h>
52 #include <rte_malloc.h>
55 #include "e1000_logs.h"
56 #include "base/e1000_api.h"
57 #include "e1000_ethdev.h"
61 * Default values for port configuration
63 #define IGB_DEFAULT_RX_FREE_THRESH 32
65 #define IGB_DEFAULT_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
66 #define IGB_DEFAULT_RX_HTHRESH 8
67 #define IGB_DEFAULT_RX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 4)
69 #define IGB_DEFAULT_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
70 #define IGB_DEFAULT_TX_HTHRESH 1
71 #define IGB_DEFAULT_TX_WTHRESH ((hw->mac.type == e1000_82576) ? 1 : 16)
73 #define IGB_HKEY_MAX_INDEX 10
75 /* Bit shift and mask */
76 #define IGB_4_BIT_WIDTH (CHAR_BIT / 2)
77 #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
78 #define IGB_8_BIT_WIDTH CHAR_BIT
79 #define IGB_8_BIT_MASK UINT8_MAX
81 /* Additional timesync values. */
82 #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL
83 #define E1000_ETQF_FILTER_1588 3
84 #define IGB_82576_TSYNC_SHIFT 16
85 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
86 #define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
89 #define E1000_VTIVAR_MISC 0x01740
90 #define E1000_VTIVAR_MISC_MASK 0xFF
91 #define E1000_VTIVAR_VALID 0x80
92 #define E1000_VTIVAR_MISC_MAILBOX 0
93 #define E1000_VTIVAR_MISC_INTR_MASK 0x3
95 /* External VLAN Enable bit mask */
96 #define E1000_CTRL_EXT_EXT_VLAN (1 << 26)
98 /* External VLAN Ether Type bit mask and shift */
99 #define E1000_VET_VET_EXT 0xFFFF0000
100 #define E1000_VET_VET_EXT_SHIFT 16
102 static int eth_igb_configure(struct rte_eth_dev *dev);
103 static int eth_igb_start(struct rte_eth_dev *dev);
104 static void eth_igb_stop(struct rte_eth_dev *dev);
105 static int eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
106 static int eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
107 static void eth_igb_close(struct rte_eth_dev *dev);
108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
112 static int eth_igb_link_update(struct rte_eth_dev *dev,
113 int wait_to_complete);
114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
115 struct rte_eth_stats *rte_stats);
116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
117 struct rte_eth_xstat *xstats, unsigned n);
118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
119 struct rte_eth_xstat_name *xstats_names,
121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
123 static void eth_igb_infos_get(struct rte_eth_dev *dev,
124 struct rte_eth_dev_info *dev_info);
125 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
126 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
127 struct rte_eth_dev_info *dev_info);
128 static int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
129 struct rte_eth_fc_conf *fc_conf);
130 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
131 struct rte_eth_fc_conf *fc_conf);
132 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
133 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
134 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
135 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
136 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
138 static int igb_hardware_init(struct e1000_hw *hw);
139 static void igb_hw_control_acquire(struct e1000_hw *hw);
140 static void igb_hw_control_release(struct e1000_hw *hw);
141 static void igb_init_manageability(struct e1000_hw *hw);
142 static void igb_release_manageability(struct e1000_hw *hw);
144 static int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
146 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
147 uint16_t vlan_id, int on);
148 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
149 enum rte_vlan_type vlan_type,
151 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
153 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
154 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
155 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
156 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
157 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
158 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
160 static int eth_igb_led_on(struct rte_eth_dev *dev);
161 static int eth_igb_led_off(struct rte_eth_dev *dev);
163 static void igb_intr_disable(struct e1000_hw *hw);
164 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
165 static void eth_igb_rar_set(struct rte_eth_dev *dev,
166 struct ether_addr *mac_addr,
167 uint32_t index, uint32_t pool);
168 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
169 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
170 struct ether_addr *addr);
172 static void igbvf_intr_disable(struct e1000_hw *hw);
173 static int igbvf_dev_configure(struct rte_eth_dev *dev);
174 static int igbvf_dev_start(struct rte_eth_dev *dev);
175 static void igbvf_dev_stop(struct rte_eth_dev *dev);
176 static void igbvf_dev_close(struct rte_eth_dev *dev);
177 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
178 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
179 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
180 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
181 static int eth_igbvf_link_update(struct e1000_hw *hw);
182 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
183 struct rte_eth_stats *rte_stats);
184 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
185 struct rte_eth_xstat *xstats, unsigned n);
186 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
187 struct rte_eth_xstat_name *xstats_names,
189 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
190 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
191 uint16_t vlan_id, int on);
192 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
193 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
194 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
195 struct ether_addr *addr);
196 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
197 static int igbvf_get_regs(struct rte_eth_dev *dev,
198 struct rte_dev_reg_info *regs);
200 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
201 struct rte_eth_rss_reta_entry64 *reta_conf,
203 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
204 struct rte_eth_rss_reta_entry64 *reta_conf,
207 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
208 struct rte_eth_syn_filter *filter,
210 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
211 struct rte_eth_syn_filter *filter);
212 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
213 enum rte_filter_op filter_op,
215 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
216 struct rte_eth_ntuple_filter *ntuple_filter);
217 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
218 struct rte_eth_ntuple_filter *ntuple_filter);
219 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
220 struct rte_eth_flex_filter *filter,
222 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
223 struct rte_eth_flex_filter *filter);
224 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
225 enum rte_filter_op filter_op,
227 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
228 struct rte_eth_ntuple_filter *ntuple_filter);
229 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
230 struct rte_eth_ntuple_filter *ntuple_filter);
231 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
232 struct rte_eth_ntuple_filter *filter,
234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
235 struct rte_eth_ntuple_filter *filter);
236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
237 enum rte_filter_op filter_op,
239 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
240 struct rte_eth_ethertype_filter *filter,
242 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
243 enum rte_filter_op filter_op,
245 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
246 struct rte_eth_ethertype_filter *filter);
247 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
248 enum rte_filter_type filter_type,
249 enum rte_filter_op filter_op,
251 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
252 static int eth_igb_get_regs(struct rte_eth_dev *dev,
253 struct rte_dev_reg_info *regs);
254 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
255 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
256 struct rte_dev_eeprom_info *eeprom);
257 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
258 struct rte_dev_eeprom_info *eeprom);
259 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
260 struct ether_addr *mc_addr_set,
261 uint32_t nb_mc_addr);
262 static int igb_timesync_enable(struct rte_eth_dev *dev);
263 static int igb_timesync_disable(struct rte_eth_dev *dev);
264 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
265 struct timespec *timestamp,
267 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
268 struct timespec *timestamp);
269 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
270 static int igb_timesync_read_time(struct rte_eth_dev *dev,
271 struct timespec *timestamp);
272 static int igb_timesync_write_time(struct rte_eth_dev *dev,
273 const struct timespec *timestamp);
274 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
276 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
278 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
279 uint8_t queue, uint8_t msix_vector);
280 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
281 uint8_t index, uint8_t offset);
282 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
283 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
285 static void igbvf_mbx_process(struct rte_eth_dev *dev);
288 * Define VF Stats MACRO for Non "cleared on read" register
290 #define UPDATE_VF_STAT(reg, last, cur) \
292 u32 latest = E1000_READ_REG(hw, reg); \
293 cur += (latest - last) & UINT_MAX; \
297 #define IGB_FC_PAUSE_TIME 0x0680
298 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
299 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
301 #define IGBVF_PMD_NAME "rte_igbvf_pmd" /* PMD name */
303 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
306 * The set of PCI devices this driver supports
308 static const struct rte_pci_id pci_id_igb_map[] = {
309 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
310 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
311 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
312 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
313 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
314 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
315 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
316 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
318 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
319 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
320 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
322 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
323 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
324 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
325 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
326 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
327 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
329 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
330 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
331 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
332 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
333 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
334 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
335 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
336 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
337 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
338 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
339 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
340 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
341 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
342 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
343 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
344 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
345 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
346 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
347 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
348 { .vendor_id = 0, /* sentinel */ },
352 * The set of PCI devices this driver supports (for 82576&I350 VF)
354 static const struct rte_pci_id pci_id_igbvf_map[] = {
355 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
356 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
357 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
358 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
359 { .vendor_id = 0, /* sentinel */ },
362 static const struct rte_eth_desc_lim rx_desc_lim = {
363 .nb_max = E1000_MAX_RING_DESC,
364 .nb_min = E1000_MIN_RING_DESC,
365 .nb_align = IGB_RXD_ALIGN,
368 static const struct rte_eth_desc_lim tx_desc_lim = {
369 .nb_max = E1000_MAX_RING_DESC,
370 .nb_min = E1000_MIN_RING_DESC,
371 .nb_align = IGB_RXD_ALIGN,
374 static const struct eth_dev_ops eth_igb_ops = {
375 .dev_configure = eth_igb_configure,
376 .dev_start = eth_igb_start,
377 .dev_stop = eth_igb_stop,
378 .dev_set_link_up = eth_igb_dev_set_link_up,
379 .dev_set_link_down = eth_igb_dev_set_link_down,
380 .dev_close = eth_igb_close,
381 .promiscuous_enable = eth_igb_promiscuous_enable,
382 .promiscuous_disable = eth_igb_promiscuous_disable,
383 .allmulticast_enable = eth_igb_allmulticast_enable,
384 .allmulticast_disable = eth_igb_allmulticast_disable,
385 .link_update = eth_igb_link_update,
386 .stats_get = eth_igb_stats_get,
387 .xstats_get = eth_igb_xstats_get,
388 .xstats_get_names = eth_igb_xstats_get_names,
389 .stats_reset = eth_igb_stats_reset,
390 .xstats_reset = eth_igb_xstats_reset,
391 .dev_infos_get = eth_igb_infos_get,
392 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
393 .mtu_set = eth_igb_mtu_set,
394 .vlan_filter_set = eth_igb_vlan_filter_set,
395 .vlan_tpid_set = eth_igb_vlan_tpid_set,
396 .vlan_offload_set = eth_igb_vlan_offload_set,
397 .rx_queue_setup = eth_igb_rx_queue_setup,
398 .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
399 .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
400 .rx_queue_release = eth_igb_rx_queue_release,
401 .rx_queue_count = eth_igb_rx_queue_count,
402 .rx_descriptor_done = eth_igb_rx_descriptor_done,
403 .tx_queue_setup = eth_igb_tx_queue_setup,
404 .tx_queue_release = eth_igb_tx_queue_release,
405 .dev_led_on = eth_igb_led_on,
406 .dev_led_off = eth_igb_led_off,
407 .flow_ctrl_get = eth_igb_flow_ctrl_get,
408 .flow_ctrl_set = eth_igb_flow_ctrl_set,
409 .mac_addr_add = eth_igb_rar_set,
410 .mac_addr_remove = eth_igb_rar_clear,
411 .mac_addr_set = eth_igb_default_mac_addr_set,
412 .reta_update = eth_igb_rss_reta_update,
413 .reta_query = eth_igb_rss_reta_query,
414 .rss_hash_update = eth_igb_rss_hash_update,
415 .rss_hash_conf_get = eth_igb_rss_hash_conf_get,
416 .filter_ctrl = eth_igb_filter_ctrl,
417 .set_mc_addr_list = eth_igb_set_mc_addr_list,
418 .rxq_info_get = igb_rxq_info_get,
419 .txq_info_get = igb_txq_info_get,
420 .timesync_enable = igb_timesync_enable,
421 .timesync_disable = igb_timesync_disable,
422 .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
423 .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
424 .get_reg = eth_igb_get_regs,
425 .get_eeprom_length = eth_igb_get_eeprom_length,
426 .get_eeprom = eth_igb_get_eeprom,
427 .set_eeprom = eth_igb_set_eeprom,
428 .timesync_adjust_time = igb_timesync_adjust_time,
429 .timesync_read_time = igb_timesync_read_time,
430 .timesync_write_time = igb_timesync_write_time,
434 * dev_ops for virtual function, bare necessities for basic vf
435 * operation have been implemented
437 static const struct eth_dev_ops igbvf_eth_dev_ops = {
438 .dev_configure = igbvf_dev_configure,
439 .dev_start = igbvf_dev_start,
440 .dev_stop = igbvf_dev_stop,
441 .dev_close = igbvf_dev_close,
442 .promiscuous_enable = igbvf_promiscuous_enable,
443 .promiscuous_disable = igbvf_promiscuous_disable,
444 .allmulticast_enable = igbvf_allmulticast_enable,
445 .allmulticast_disable = igbvf_allmulticast_disable,
446 .link_update = eth_igb_link_update,
447 .stats_get = eth_igbvf_stats_get,
448 .xstats_get = eth_igbvf_xstats_get,
449 .xstats_get_names = eth_igbvf_xstats_get_names,
450 .stats_reset = eth_igbvf_stats_reset,
451 .xstats_reset = eth_igbvf_stats_reset,
452 .vlan_filter_set = igbvf_vlan_filter_set,
453 .dev_infos_get = eth_igbvf_infos_get,
454 .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
455 .rx_queue_setup = eth_igb_rx_queue_setup,
456 .rx_queue_release = eth_igb_rx_queue_release,
457 .tx_queue_setup = eth_igb_tx_queue_setup,
458 .tx_queue_release = eth_igb_tx_queue_release,
459 .set_mc_addr_list = eth_igb_set_mc_addr_list,
460 .rxq_info_get = igb_rxq_info_get,
461 .txq_info_get = igb_txq_info_get,
462 .mac_addr_set = igbvf_default_mac_addr_set,
463 .get_reg = igbvf_get_regs,
466 /* store statistics names and its offset in stats structure */
467 struct rte_igb_xstats_name_off {
468 char name[RTE_ETH_XSTATS_NAME_SIZE];
472 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
473 {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
474 {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
475 {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
476 {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
477 {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
478 {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
479 {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
481 {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
482 {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
483 {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
484 {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
485 {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
486 {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
487 {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
488 {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
489 {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
490 {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
491 {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
493 {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
494 {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
495 {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
496 {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
497 {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
499 {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
501 {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
502 {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
503 {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
504 {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
505 {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
506 {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
507 {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
508 {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
509 {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
510 {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
511 {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
512 {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
513 {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
514 {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
515 {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
516 {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
517 {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
518 {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
520 {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
522 {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
523 {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
524 {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
525 {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
526 {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
527 {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
528 {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
530 {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
533 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
534 sizeof(rte_igb_stats_strings[0]))
536 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
537 {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
538 {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
539 {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
540 {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
541 {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
544 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
545 sizeof(rte_igbvf_stats_strings[0]))
548 * Atomically reads the link status information from global
549 * structure rte_eth_dev.
552 * - Pointer to the structure rte_eth_dev to read from.
553 * - Pointer to the buffer to be saved with the link status.
556 * - On success, zero.
557 * - On failure, negative value.
560 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
561 struct rte_eth_link *link)
563 struct rte_eth_link *dst = link;
564 struct rte_eth_link *src = &(dev->data->dev_link);
566 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
567 *(uint64_t *)src) == 0)
574 * Atomically writes the link status information into global
575 * structure rte_eth_dev.
578 * - Pointer to the structure rte_eth_dev to read from.
579 * - Pointer to the buffer to be saved with the link status.
582 * - On success, zero.
583 * - On failure, negative value.
586 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
587 struct rte_eth_link *link)
589 struct rte_eth_link *dst = &(dev->data->dev_link);
590 struct rte_eth_link *src = link;
592 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
593 *(uint64_t *)src) == 0)
600 igb_intr_enable(struct rte_eth_dev *dev)
602 struct e1000_interrupt *intr =
603 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
604 struct e1000_hw *hw =
605 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
607 E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
608 E1000_WRITE_FLUSH(hw);
612 igb_intr_disable(struct e1000_hw *hw)
614 E1000_WRITE_REG(hw, E1000_IMC, ~0);
615 E1000_WRITE_FLUSH(hw);
619 igbvf_intr_enable(struct rte_eth_dev *dev)
621 struct e1000_hw *hw =
622 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
624 /* only for mailbox */
625 E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
626 E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
627 E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
628 E1000_WRITE_FLUSH(hw);
631 /* only for mailbox now. If RX/TX needed, should extend this function. */
633 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
638 tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
639 tmp |= E1000_VTIVAR_VALID;
640 E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
644 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
646 struct e1000_hw *hw =
647 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
649 /* Configure VF other cause ivar */
650 igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
653 static inline int32_t
654 igb_pf_reset_hw(struct e1000_hw *hw)
659 status = e1000_reset_hw(hw);
661 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
662 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
663 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
664 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
665 E1000_WRITE_FLUSH(hw);
671 igb_identify_hardware(struct rte_eth_dev *dev)
673 struct e1000_hw *hw =
674 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
676 hw->vendor_id = dev->pci_dev->id.vendor_id;
677 hw->device_id = dev->pci_dev->id.device_id;
678 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
679 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
681 e1000_set_mac_type(hw);
683 /* need to check if it is a vf device below */
687 igb_reset_swfw_lock(struct e1000_hw *hw)
692 * Do mac ops initialization manually here, since we will need
693 * some function pointers set by this call.
695 ret_val = e1000_init_mac_params(hw);
700 * SMBI lock should not fail in this early stage. If this is the case,
701 * it is due to an improper exit of the application.
702 * So force the release of the faulty lock.
704 if (e1000_get_hw_semaphore_generic(hw) < 0) {
705 PMD_DRV_LOG(DEBUG, "SMBI lock released");
707 e1000_put_hw_semaphore_generic(hw);
709 if (hw->mac.ops.acquire_swfw_sync != NULL) {
713 * Phy lock should not fail in this early stage. If this is the case,
714 * it is due to an improper exit of the application.
715 * So force the release of the faulty lock.
717 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
718 if (hw->bus.func > E1000_FUNC_1)
720 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
721 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
724 hw->mac.ops.release_swfw_sync(hw, mask);
727 * This one is more tricky since it is common to all ports; but
728 * swfw_sync retries last long enough (1s) to be almost sure that if
729 * lock can not be taken it is due to an improper lock of the
732 mask = E1000_SWFW_EEP_SM;
733 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
734 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
736 hw->mac.ops.release_swfw_sync(hw, mask);
739 return E1000_SUCCESS;
743 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
746 struct rte_pci_device *pci_dev;
747 struct e1000_hw *hw =
748 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
749 struct e1000_vfta * shadow_vfta =
750 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
751 struct e1000_filter_info *filter_info =
752 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
753 struct e1000_adapter *adapter =
754 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
758 pci_dev = eth_dev->pci_dev;
760 eth_dev->dev_ops = ð_igb_ops;
761 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
762 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
764 /* for secondary processes, we don't initialise any further as primary
765 * has already done this work. Only check we don't need a different
767 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
768 if (eth_dev->data->scattered_rx)
769 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
773 rte_eth_copy_pci_info(eth_dev, pci_dev);
775 hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
777 igb_identify_hardware(eth_dev);
778 if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
783 e1000_get_bus_info(hw);
785 /* Reset any pending lock */
786 if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
791 /* Finish initialization */
792 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
798 hw->phy.autoneg_wait_to_complete = 0;
799 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
802 if (hw->phy.media_type == e1000_media_type_copper) {
803 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
804 hw->phy.disable_polarity_correction = 0;
805 hw->phy.ms_type = e1000_ms_hw_default;
809 * Start from a known state, this is important in reading the nvm
814 /* Make sure we have a good EEPROM before we read from it */
815 if (e1000_validate_nvm_checksum(hw) < 0) {
817 * Some PCI-E parts fail the first check due to
818 * the link being in sleep state, call it again,
819 * if it fails a second time its a real issue.
821 if (e1000_validate_nvm_checksum(hw) < 0) {
822 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
828 /* Read the permanent MAC address out of the EEPROM */
829 if (e1000_read_mac_addr(hw) != 0) {
830 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
835 /* Allocate memory for storing MAC addresses */
836 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
837 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
838 if (eth_dev->data->mac_addrs == NULL) {
839 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
840 "store MAC addresses",
841 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
846 /* Copy the permanent MAC address */
847 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
849 /* initialize the vfta */
850 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
852 /* Now initialize the hardware */
853 if (igb_hardware_init(hw) != 0) {
854 PMD_INIT_LOG(ERR, "Hardware initialization failed");
855 rte_free(eth_dev->data->mac_addrs);
856 eth_dev->data->mac_addrs = NULL;
860 hw->mac.get_link_status = 1;
861 adapter->stopped = 0;
863 /* Indicate SOL/IDER usage */
864 if (e1000_check_reset_block(hw) < 0) {
865 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
869 /* initialize PF if max_vfs not zero */
870 igb_pf_host_init(eth_dev);
872 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
873 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
874 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
875 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
876 E1000_WRITE_FLUSH(hw);
878 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
879 eth_dev->data->port_id, pci_dev->id.vendor_id,
880 pci_dev->id.device_id);
882 rte_intr_callback_register(&pci_dev->intr_handle,
883 eth_igb_interrupt_handler,
886 /* enable uio/vfio intr/eventfd mapping */
887 rte_intr_enable(&pci_dev->intr_handle);
889 /* enable support intr */
890 igb_intr_enable(eth_dev);
892 TAILQ_INIT(&filter_info->flex_list);
893 filter_info->flex_mask = 0;
894 TAILQ_INIT(&filter_info->twotuple_list);
895 filter_info->twotuple_mask = 0;
896 TAILQ_INIT(&filter_info->fivetuple_list);
897 filter_info->fivetuple_mask = 0;
902 igb_hw_control_release(hw);
908 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
910 struct rte_pci_device *pci_dev;
912 struct e1000_adapter *adapter =
913 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
915 PMD_INIT_FUNC_TRACE();
917 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
920 hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
921 pci_dev = eth_dev->pci_dev;
923 if (adapter->stopped == 0)
924 eth_igb_close(eth_dev);
926 eth_dev->dev_ops = NULL;
927 eth_dev->rx_pkt_burst = NULL;
928 eth_dev->tx_pkt_burst = NULL;
930 /* Reset any pending lock */
931 igb_reset_swfw_lock(hw);
933 rte_free(eth_dev->data->mac_addrs);
934 eth_dev->data->mac_addrs = NULL;
936 /* uninitialize PF if max_vfs not zero */
937 igb_pf_host_uninit(eth_dev);
939 /* disable uio intr before callback unregister */
940 rte_intr_disable(&(pci_dev->intr_handle));
941 rte_intr_callback_unregister(&(pci_dev->intr_handle),
942 eth_igb_interrupt_handler, (void *)eth_dev);
948 * Virtual Function device init
951 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
953 struct rte_pci_device *pci_dev;
954 struct e1000_adapter *adapter =
955 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
956 struct e1000_hw *hw =
957 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
959 struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
961 PMD_INIT_FUNC_TRACE();
963 eth_dev->dev_ops = &igbvf_eth_dev_ops;
964 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
965 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
967 /* for secondary processes, we don't initialise any further as primary
968 * has already done this work. Only check we don't need a different
970 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
971 if (eth_dev->data->scattered_rx)
972 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
976 pci_dev = eth_dev->pci_dev;
978 rte_eth_copy_pci_info(eth_dev, pci_dev);
980 hw->device_id = pci_dev->id.device_id;
981 hw->vendor_id = pci_dev->id.vendor_id;
982 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
983 adapter->stopped = 0;
985 /* Initialize the shared code (base driver) */
986 diag = e1000_setup_init_funcs(hw, TRUE);
988 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
993 /* init_mailbox_params */
994 hw->mbx.ops.init_params(hw);
996 /* Disable the interrupts for VF */
997 igbvf_intr_disable(hw);
999 diag = hw->mac.ops.reset_hw(hw);
1001 /* Allocate memory for storing MAC addresses */
1002 eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1003 hw->mac.rar_entry_count, 0);
1004 if (eth_dev->data->mac_addrs == NULL) {
1006 "Failed to allocate %d bytes needed to store MAC "
1008 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1012 /* Generate a random MAC address, if none was assigned by PF. */
1013 if (is_zero_ether_addr(perm_addr)) {
1014 eth_random_addr(perm_addr->addr_bytes);
1015 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1016 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1017 "%02x:%02x:%02x:%02x:%02x:%02x",
1018 perm_addr->addr_bytes[0],
1019 perm_addr->addr_bytes[1],
1020 perm_addr->addr_bytes[2],
1021 perm_addr->addr_bytes[3],
1022 perm_addr->addr_bytes[4],
1023 perm_addr->addr_bytes[5]);
1026 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1028 rte_free(eth_dev->data->mac_addrs);
1029 eth_dev->data->mac_addrs = NULL;
1032 /* Copy the permanent MAC address */
1033 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1034 ð_dev->data->mac_addrs[0]);
1036 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1038 eth_dev->data->port_id, pci_dev->id.vendor_id,
1039 pci_dev->id.device_id, "igb_mac_82576_vf");
1041 rte_intr_callback_register(&pci_dev->intr_handle,
1042 eth_igbvf_interrupt_handler,
1049 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1051 struct e1000_adapter *adapter =
1052 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1053 struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1055 PMD_INIT_FUNC_TRACE();
1057 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1060 if (adapter->stopped == 0)
1061 igbvf_dev_close(eth_dev);
1063 eth_dev->dev_ops = NULL;
1064 eth_dev->rx_pkt_burst = NULL;
1065 eth_dev->tx_pkt_burst = NULL;
1067 rte_free(eth_dev->data->mac_addrs);
1068 eth_dev->data->mac_addrs = NULL;
1070 /* disable uio intr before callback unregister */
1071 rte_intr_disable(&pci_dev->intr_handle);
1072 rte_intr_callback_unregister(&pci_dev->intr_handle,
1073 eth_igbvf_interrupt_handler,
1079 static struct eth_driver rte_igb_pmd = {
1081 .id_table = pci_id_igb_map,
1082 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1083 RTE_PCI_DRV_DETACHABLE,
1084 .probe = rte_eth_dev_pci_probe,
1085 .remove = rte_eth_dev_pci_remove,
1087 .eth_dev_init = eth_igb_dev_init,
1088 .eth_dev_uninit = eth_igb_dev_uninit,
1089 .dev_private_size = sizeof(struct e1000_adapter),
1093 * virtual function driver struct
1095 static struct eth_driver rte_igbvf_pmd = {
1097 .id_table = pci_id_igbvf_map,
1098 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1099 .probe = rte_eth_dev_pci_probe,
1100 .remove = rte_eth_dev_pci_remove,
1102 .eth_dev_init = eth_igbvf_dev_init,
1103 .eth_dev_uninit = eth_igbvf_dev_uninit,
1104 .dev_private_size = sizeof(struct e1000_adapter),
1108 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1110 struct e1000_hw *hw =
1111 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1112 /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1113 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1114 rctl |= E1000_RCTL_VFE;
1115 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1119 igb_check_mq_mode(struct rte_eth_dev *dev)
1121 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1122 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1123 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1124 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1126 if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1127 tx_mq_mode == ETH_MQ_TX_DCB ||
1128 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1129 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1132 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1133 /* Check multi-queue mode.
1134 * To no break software we accept ETH_MQ_RX_NONE as this might
1135 * be used to turn off VLAN filter.
1138 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1139 rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1140 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1141 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1143 /* Only support one queue on VFs.
1144 * RSS together with SRIOV is not supported.
1146 PMD_INIT_LOG(ERR, "SRIOV is active,"
1147 " wrong mq_mode rx %d.",
1151 /* TX mode is not used here, so mode might be ignored.*/
1152 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1153 /* SRIOV only works in VMDq enable mode */
1154 PMD_INIT_LOG(WARNING, "SRIOV is active,"
1155 " TX mode %d is not supported. "
1156 " Driver will behave as %d mode.",
1157 tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1160 /* check valid queue number */
1161 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1162 PMD_INIT_LOG(ERR, "SRIOV is active,"
1163 " only support one queue on VFs.");
1167 /* To no break software that set invalid mode, only display
1168 * warning if invalid mode is used.
1170 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1171 rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1172 rx_mq_mode != ETH_MQ_RX_RSS) {
1173 /* RSS together with VMDq not supported*/
1174 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1179 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1180 tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1181 PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1182 " Due to txmode is meaningless in this"
1183 " driver, just ignore.",
1191 eth_igb_configure(struct rte_eth_dev *dev)
1193 struct e1000_interrupt *intr =
1194 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1197 PMD_INIT_FUNC_TRACE();
1199 /* multipe queue mode checking */
1200 ret = igb_check_mq_mode(dev);
1202 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1207 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1208 PMD_INIT_FUNC_TRACE();
1214 eth_igb_start(struct rte_eth_dev *dev)
1216 struct e1000_hw *hw =
1217 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1218 struct e1000_adapter *adapter =
1219 E1000_DEV_PRIVATE(dev->data->dev_private);
1220 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1222 uint32_t intr_vector = 0;
1228 PMD_INIT_FUNC_TRACE();
1230 /* disable uio/vfio intr/eventfd mapping */
1231 rte_intr_disable(intr_handle);
1233 /* Power up the phy. Needed to make the link go Up */
1234 eth_igb_dev_set_link_up(dev);
1237 * Packet Buffer Allocation (PBA)
1238 * Writing PBA sets the receive portion of the buffer
1239 * the remainder is used for the transmit buffer.
1241 if (hw->mac.type == e1000_82575) {
1244 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1245 E1000_WRITE_REG(hw, E1000_PBA, pba);
1248 /* Put the address into the Receive Address Array */
1249 e1000_rar_set(hw, hw->mac.addr, 0);
1251 /* Initialize the hardware */
1252 if (igb_hardware_init(hw)) {
1253 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1256 adapter->stopped = 0;
1258 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1260 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1261 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1262 ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1263 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1264 E1000_WRITE_FLUSH(hw);
1266 /* configure PF module if SRIOV enabled */
1267 igb_pf_host_configure(dev);
1269 /* check and configure queue intr-vector mapping */
1270 if ((rte_intr_cap_multiple(intr_handle) ||
1271 !RTE_ETH_DEV_SRIOV(dev).active) &&
1272 dev->data->dev_conf.intr_conf.rxq != 0) {
1273 intr_vector = dev->data->nb_rx_queues;
1274 if (rte_intr_efd_enable(intr_handle, intr_vector))
1278 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1279 intr_handle->intr_vec =
1280 rte_zmalloc("intr_vec",
1281 dev->data->nb_rx_queues * sizeof(int), 0);
1282 if (intr_handle->intr_vec == NULL) {
1283 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1284 " intr_vec\n", dev->data->nb_rx_queues);
1289 /* confiugre msix for rx interrupt */
1290 eth_igb_configure_msix_intr(dev);
1292 /* Configure for OS presence */
1293 igb_init_manageability(hw);
1295 eth_igb_tx_init(dev);
1297 /* This can fail when allocating mbufs for descriptor rings */
1298 ret = eth_igb_rx_init(dev);
1300 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1301 igb_dev_clear_queues(dev);
1305 e1000_clear_hw_cntrs_base_generic(hw);
1308 * VLAN Offload Settings
1310 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1311 ETH_VLAN_EXTEND_MASK;
1312 eth_igb_vlan_offload_set(dev, mask);
1314 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1315 /* Enable VLAN filter since VMDq always use VLAN filter */
1316 igb_vmdq_vlan_hw_filter_enable(dev);
1319 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1320 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1321 (hw->mac.type == e1000_i211)) {
1322 /* Configure EITR with the maximum possible value (0xFFFF) */
1323 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1326 /* Setup link speed and duplex */
1327 speeds = &dev->data->dev_conf.link_speeds;
1328 if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1329 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1330 hw->mac.autoneg = 1;
1333 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1336 hw->phy.autoneg_advertised = 0;
1338 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1339 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1340 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1342 goto error_invalid_config;
1344 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1345 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1348 if (*speeds & ETH_LINK_SPEED_10M) {
1349 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1352 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1353 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1356 if (*speeds & ETH_LINK_SPEED_100M) {
1357 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1360 if (*speeds & ETH_LINK_SPEED_1G) {
1361 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1364 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1365 goto error_invalid_config;
1367 /* Set/reset the mac.autoneg based on the link speed,
1371 hw->mac.autoneg = 0;
1372 hw->mac.forced_speed_duplex =
1373 hw->phy.autoneg_advertised;
1375 hw->mac.autoneg = 1;
1379 e1000_setup_link(hw);
1381 if (rte_intr_allow_others(intr_handle)) {
1382 /* check if lsc interrupt is enabled */
1383 if (dev->data->dev_conf.intr_conf.lsc != 0)
1384 eth_igb_lsc_interrupt_setup(dev, TRUE);
1386 eth_igb_lsc_interrupt_setup(dev, FALSE);
1388 rte_intr_callback_unregister(intr_handle,
1389 eth_igb_interrupt_handler,
1391 if (dev->data->dev_conf.intr_conf.lsc != 0)
1392 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1393 " no intr multiplex\n");
1396 /* check if rxq interrupt is enabled */
1397 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1398 rte_intr_dp_is_en(intr_handle))
1399 eth_igb_rxq_interrupt_setup(dev);
1401 /* enable uio/vfio intr/eventfd mapping */
1402 rte_intr_enable(intr_handle);
1404 /* resume enabled intr since hw reset */
1405 igb_intr_enable(dev);
1407 PMD_INIT_LOG(DEBUG, "<<");
1411 error_invalid_config:
1412 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1413 dev->data->dev_conf.link_speeds, dev->data->port_id);
1414 igb_dev_clear_queues(dev);
1418 /*********************************************************************
1420 * This routine disables all traffic on the adapter by issuing a
1421 * global reset on the MAC.
1423 **********************************************************************/
1425 eth_igb_stop(struct rte_eth_dev *dev)
1427 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428 struct e1000_filter_info *filter_info =
1429 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1430 struct rte_eth_link link;
1431 struct e1000_flex_filter *p_flex;
1432 struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1433 struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1434 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1436 igb_intr_disable(hw);
1438 /* disable intr eventfd mapping */
1439 rte_intr_disable(intr_handle);
1441 igb_pf_reset_hw(hw);
1442 E1000_WRITE_REG(hw, E1000_WUC, 0);
1444 /* Set bit for Go Link disconnect */
1445 if (hw->mac.type >= e1000_82580) {
1448 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1449 phpm_reg |= E1000_82580_PM_GO_LINKD;
1450 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1453 /* Power down the phy. Needed to make the link go Down */
1454 eth_igb_dev_set_link_down(dev);
1456 igb_dev_clear_queues(dev);
1458 /* clear the recorded link status */
1459 memset(&link, 0, sizeof(link));
1460 rte_igb_dev_atomic_write_link_status(dev, &link);
1462 /* Remove all flex filters of the device */
1463 while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1464 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1467 filter_info->flex_mask = 0;
1469 /* Remove all ntuple filters of the device */
1470 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1471 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1472 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1473 TAILQ_REMOVE(&filter_info->fivetuple_list,
1477 filter_info->fivetuple_mask = 0;
1478 for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1479 p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1480 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1481 TAILQ_REMOVE(&filter_info->twotuple_list,
1485 filter_info->twotuple_mask = 0;
1487 if (!rte_intr_allow_others(intr_handle))
1488 /* resume to the default handler */
1489 rte_intr_callback_register(intr_handle,
1490 eth_igb_interrupt_handler,
1493 /* Clean datapath event and queue/vec mapping */
1494 rte_intr_efd_disable(intr_handle);
1495 if (intr_handle->intr_vec != NULL) {
1496 rte_free(intr_handle->intr_vec);
1497 intr_handle->intr_vec = NULL;
1502 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1504 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1506 if (hw->phy.media_type == e1000_media_type_copper)
1507 e1000_power_up_phy(hw);
1509 e1000_power_up_fiber_serdes_link(hw);
1515 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1517 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1519 if (hw->phy.media_type == e1000_media_type_copper)
1520 e1000_power_down_phy(hw);
1522 e1000_shutdown_fiber_serdes_link(hw);
1528 eth_igb_close(struct rte_eth_dev *dev)
1530 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1531 struct e1000_adapter *adapter =
1532 E1000_DEV_PRIVATE(dev->data->dev_private);
1533 struct rte_eth_link link;
1534 struct rte_pci_device *pci_dev;
1537 adapter->stopped = 1;
1539 e1000_phy_hw_reset(hw);
1540 igb_release_manageability(hw);
1541 igb_hw_control_release(hw);
1543 /* Clear bit for Go Link disconnect */
1544 if (hw->mac.type >= e1000_82580) {
1547 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1548 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1549 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1552 igb_dev_free_queues(dev);
1554 pci_dev = dev->pci_dev;
1555 if (pci_dev->intr_handle.intr_vec) {
1556 rte_free(pci_dev->intr_handle.intr_vec);
1557 pci_dev->intr_handle.intr_vec = NULL;
1560 memset(&link, 0, sizeof(link));
1561 rte_igb_dev_atomic_write_link_status(dev, &link);
1565 igb_get_rx_buffer_size(struct e1000_hw *hw)
1567 uint32_t rx_buf_size;
1568 if (hw->mac.type == e1000_82576) {
1569 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1570 } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1571 /* PBS needs to be translated according to a lookup table */
1572 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1573 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1574 rx_buf_size = (rx_buf_size << 10);
1575 } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1576 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1578 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1584 /*********************************************************************
1586 * Initialize the hardware
1588 **********************************************************************/
1590 igb_hardware_init(struct e1000_hw *hw)
1592 uint32_t rx_buf_size;
1595 /* Let the firmware know the OS is in control */
1596 igb_hw_control_acquire(hw);
1599 * These parameters control the automatic generation (Tx) and
1600 * response (Rx) to Ethernet PAUSE frames.
1601 * - High water mark should allow for at least two standard size (1518)
1602 * frames to be received after sending an XOFF.
1603 * - Low water mark works best when it is very near the high water mark.
1604 * This allows the receiver to restart by sending XON when it has
1605 * drained a bit. Here we use an arbitrary value of 1500 which will
1606 * restart after one full frame is pulled from the buffer. There
1607 * could be several smaller frames in the buffer and if so they will
1608 * not trigger the XON until their total number reduces the buffer
1610 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1612 rx_buf_size = igb_get_rx_buffer_size(hw);
1614 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1615 hw->fc.low_water = hw->fc.high_water - 1500;
1616 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1617 hw->fc.send_xon = 1;
1619 /* Set Flow control, use the tunable location if sane */
1620 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1621 hw->fc.requested_mode = igb_fc_setting;
1623 hw->fc.requested_mode = e1000_fc_none;
1625 /* Issue a global reset */
1626 igb_pf_reset_hw(hw);
1627 E1000_WRITE_REG(hw, E1000_WUC, 0);
1629 diag = e1000_init_hw(hw);
1633 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1634 e1000_get_phy_info(hw);
1635 e1000_check_for_link(hw);
1640 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1642 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1646 uint64_t old_gprc = stats->gprc;
1647 uint64_t old_gptc = stats->gptc;
1648 uint64_t old_tpr = stats->tpr;
1649 uint64_t old_tpt = stats->tpt;
1650 uint64_t old_rpthc = stats->rpthc;
1651 uint64_t old_hgptc = stats->hgptc;
1653 if(hw->phy.media_type == e1000_media_type_copper ||
1654 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1656 E1000_READ_REG(hw,E1000_SYMERRS);
1657 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1660 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1661 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1662 stats->scc += E1000_READ_REG(hw, E1000_SCC);
1663 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1665 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1666 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1667 stats->colc += E1000_READ_REG(hw, E1000_COLC);
1668 stats->dc += E1000_READ_REG(hw, E1000_DC);
1669 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1670 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1671 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1673 ** For watchdog management we need to know if we have been
1674 ** paused during the last interval, so capture that here.
1676 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1677 stats->xoffrxc += pause_frames;
1678 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1679 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1680 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1681 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1682 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1683 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1684 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1685 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1686 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1687 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1688 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1689 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1691 /* For the 64-bit byte counters the low dword must be read first. */
1692 /* Both registers clear on the read of the high dword */
1694 /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1695 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1696 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1697 stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1698 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1699 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1700 stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1702 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1703 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1704 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1705 stats->roc += E1000_READ_REG(hw, E1000_ROC);
1706 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1708 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1709 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1711 stats->tor += E1000_READ_REG(hw, E1000_TORL);
1712 stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1713 stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1714 stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1715 stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1716 stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1718 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1719 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1720 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1721 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1722 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1723 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1724 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1725 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1727 /* Interrupt Counts */
1729 stats->iac += E1000_READ_REG(hw, E1000_IAC);
1730 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1731 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1732 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1733 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1734 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1735 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1736 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1737 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1739 /* Host to Card Statistics */
1741 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1742 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1743 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1744 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1745 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1746 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1747 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1748 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1749 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1750 stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1751 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1752 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1753 stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1754 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1755 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1756 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1758 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1759 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1760 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1761 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1762 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1763 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1767 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1769 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770 struct e1000_hw_stats *stats =
1771 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1773 igb_read_stats_registers(hw, stats);
1775 if (rte_stats == NULL)
1779 rte_stats->imissed = stats->mpc;
1780 rte_stats->ierrors = stats->crcerrs +
1781 stats->rlec + stats->ruc + stats->roc +
1782 stats->rxerrc + stats->algnerrc + stats->cexterr;
1785 rte_stats->oerrors = stats->ecol + stats->latecol;
1787 rte_stats->ipackets = stats->gprc;
1788 rte_stats->opackets = stats->gptc;
1789 rte_stats->ibytes = stats->gorc;
1790 rte_stats->obytes = stats->gotc;
1794 eth_igb_stats_reset(struct rte_eth_dev *dev)
1796 struct e1000_hw_stats *hw_stats =
1797 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1799 /* HW registers are cleared on read */
1800 eth_igb_stats_get(dev, NULL);
1802 /* Reset software totals */
1803 memset(hw_stats, 0, sizeof(*hw_stats));
1807 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1809 struct e1000_hw_stats *stats =
1810 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1812 /* HW registers are cleared on read */
1813 eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1815 /* Reset software totals */
1816 memset(stats, 0, sizeof(*stats));
1819 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1820 struct rte_eth_xstat_name *xstats_names,
1821 __rte_unused unsigned limit)
1825 if (xstats_names == NULL)
1826 return IGB_NB_XSTATS;
1828 /* Note: limit checked in rte_eth_xstats_names() */
1830 for (i = 0; i < IGB_NB_XSTATS; i++) {
1831 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1832 "%s", rte_igb_stats_strings[i].name);
1835 return IGB_NB_XSTATS;
1839 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1842 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1843 struct e1000_hw_stats *hw_stats =
1844 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1847 if (n < IGB_NB_XSTATS)
1848 return IGB_NB_XSTATS;
1850 igb_read_stats_registers(hw, hw_stats);
1852 /* If this is a reset xstats is NULL, and we have cleared the
1853 * registers by reading them.
1858 /* Extended stats */
1859 for (i = 0; i < IGB_NB_XSTATS; i++) {
1861 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1862 rte_igb_stats_strings[i].offset);
1865 return IGB_NB_XSTATS;
1869 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1871 /* Good Rx packets, include VF loopback */
1872 UPDATE_VF_STAT(E1000_VFGPRC,
1873 hw_stats->last_gprc, hw_stats->gprc);
1875 /* Good Rx octets, include VF loopback */
1876 UPDATE_VF_STAT(E1000_VFGORC,
1877 hw_stats->last_gorc, hw_stats->gorc);
1879 /* Good Tx packets, include VF loopback */
1880 UPDATE_VF_STAT(E1000_VFGPTC,
1881 hw_stats->last_gptc, hw_stats->gptc);
1883 /* Good Tx octets, include VF loopback */
1884 UPDATE_VF_STAT(E1000_VFGOTC,
1885 hw_stats->last_gotc, hw_stats->gotc);
1887 /* Rx Multicst packets */
1888 UPDATE_VF_STAT(E1000_VFMPRC,
1889 hw_stats->last_mprc, hw_stats->mprc);
1891 /* Good Rx loopback packets */
1892 UPDATE_VF_STAT(E1000_VFGPRLBC,
1893 hw_stats->last_gprlbc, hw_stats->gprlbc);
1895 /* Good Rx loopback octets */
1896 UPDATE_VF_STAT(E1000_VFGORLBC,
1897 hw_stats->last_gorlbc, hw_stats->gorlbc);
1899 /* Good Tx loopback packets */
1900 UPDATE_VF_STAT(E1000_VFGPTLBC,
1901 hw_stats->last_gptlbc, hw_stats->gptlbc);
1903 /* Good Tx loopback octets */
1904 UPDATE_VF_STAT(E1000_VFGOTLBC,
1905 hw_stats->last_gotlbc, hw_stats->gotlbc);
1908 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1909 struct rte_eth_xstat_name *xstats_names,
1910 __rte_unused unsigned limit)
1914 if (xstats_names != NULL)
1915 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1916 snprintf(xstats_names[i].name,
1917 sizeof(xstats_names[i].name), "%s",
1918 rte_igbvf_stats_strings[i].name);
1920 return IGBVF_NB_XSTATS;
1924 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1927 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1929 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1932 if (n < IGBVF_NB_XSTATS)
1933 return IGBVF_NB_XSTATS;
1935 igbvf_read_stats_registers(hw, hw_stats);
1940 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1942 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1943 rte_igbvf_stats_strings[i].offset);
1946 return IGBVF_NB_XSTATS;
1950 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1952 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1954 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1956 igbvf_read_stats_registers(hw, hw_stats);
1958 if (rte_stats == NULL)
1961 rte_stats->ipackets = hw_stats->gprc;
1962 rte_stats->ibytes = hw_stats->gorc;
1963 rte_stats->opackets = hw_stats->gptc;
1964 rte_stats->obytes = hw_stats->gotc;
1968 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1970 struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1971 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1973 /* Sync HW register to the last stats */
1974 eth_igbvf_stats_get(dev, NULL);
1976 /* reset HW current stats*/
1977 memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1978 offsetof(struct e1000_vf_stats, gprc));
1982 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1984 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1986 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1987 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
1988 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1989 dev_info->rx_offload_capa =
1990 DEV_RX_OFFLOAD_VLAN_STRIP |
1991 DEV_RX_OFFLOAD_IPV4_CKSUM |
1992 DEV_RX_OFFLOAD_UDP_CKSUM |
1993 DEV_RX_OFFLOAD_TCP_CKSUM;
1994 dev_info->tx_offload_capa =
1995 DEV_TX_OFFLOAD_VLAN_INSERT |
1996 DEV_TX_OFFLOAD_IPV4_CKSUM |
1997 DEV_TX_OFFLOAD_UDP_CKSUM |
1998 DEV_TX_OFFLOAD_TCP_CKSUM |
1999 DEV_TX_OFFLOAD_SCTP_CKSUM |
2000 DEV_TX_OFFLOAD_TCP_TSO;
2002 switch (hw->mac.type) {
2004 dev_info->max_rx_queues = 4;
2005 dev_info->max_tx_queues = 4;
2006 dev_info->max_vmdq_pools = 0;
2010 dev_info->max_rx_queues = 16;
2011 dev_info->max_tx_queues = 16;
2012 dev_info->max_vmdq_pools = ETH_8_POOLS;
2013 dev_info->vmdq_queue_num = 16;
2017 dev_info->max_rx_queues = 8;
2018 dev_info->max_tx_queues = 8;
2019 dev_info->max_vmdq_pools = ETH_8_POOLS;
2020 dev_info->vmdq_queue_num = 8;
2024 dev_info->max_rx_queues = 8;
2025 dev_info->max_tx_queues = 8;
2026 dev_info->max_vmdq_pools = ETH_8_POOLS;
2027 dev_info->vmdq_queue_num = 8;
2031 dev_info->max_rx_queues = 8;
2032 dev_info->max_tx_queues = 8;
2036 dev_info->max_rx_queues = 4;
2037 dev_info->max_tx_queues = 4;
2038 dev_info->max_vmdq_pools = 0;
2042 dev_info->max_rx_queues = 2;
2043 dev_info->max_tx_queues = 2;
2044 dev_info->max_vmdq_pools = 0;
2048 /* Should not happen */
2051 dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2052 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2053 dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2055 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2057 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2058 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2059 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2061 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2065 dev_info->default_txconf = (struct rte_eth_txconf) {
2067 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2068 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2069 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2074 dev_info->rx_desc_lim = rx_desc_lim;
2075 dev_info->tx_desc_lim = tx_desc_lim;
2077 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2078 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2082 static const uint32_t *
2083 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2085 static const uint32_t ptypes[] = {
2086 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2089 RTE_PTYPE_L3_IPV4_EXT,
2091 RTE_PTYPE_L3_IPV6_EXT,
2095 RTE_PTYPE_TUNNEL_IP,
2096 RTE_PTYPE_INNER_L3_IPV6,
2097 RTE_PTYPE_INNER_L3_IPV6_EXT,
2098 RTE_PTYPE_INNER_L4_TCP,
2099 RTE_PTYPE_INNER_L4_UDP,
2103 if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2104 dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2110 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2112 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2114 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2115 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
2116 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2117 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2118 DEV_RX_OFFLOAD_IPV4_CKSUM |
2119 DEV_RX_OFFLOAD_UDP_CKSUM |
2120 DEV_RX_OFFLOAD_TCP_CKSUM;
2121 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2122 DEV_TX_OFFLOAD_IPV4_CKSUM |
2123 DEV_TX_OFFLOAD_UDP_CKSUM |
2124 DEV_TX_OFFLOAD_TCP_CKSUM |
2125 DEV_TX_OFFLOAD_SCTP_CKSUM |
2126 DEV_TX_OFFLOAD_TCP_TSO;
2127 switch (hw->mac.type) {
2129 dev_info->max_rx_queues = 2;
2130 dev_info->max_tx_queues = 2;
2132 case e1000_vfadapt_i350:
2133 dev_info->max_rx_queues = 1;
2134 dev_info->max_tx_queues = 1;
2137 /* Should not happen */
2141 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2143 .pthresh = IGB_DEFAULT_RX_PTHRESH,
2144 .hthresh = IGB_DEFAULT_RX_HTHRESH,
2145 .wthresh = IGB_DEFAULT_RX_WTHRESH,
2147 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2151 dev_info->default_txconf = (struct rte_eth_txconf) {
2153 .pthresh = IGB_DEFAULT_TX_PTHRESH,
2154 .hthresh = IGB_DEFAULT_TX_HTHRESH,
2155 .wthresh = IGB_DEFAULT_TX_WTHRESH,
2160 dev_info->rx_desc_lim = rx_desc_lim;
2161 dev_info->tx_desc_lim = tx_desc_lim;
2164 /* return 0 means link status changed, -1 means not changed */
2166 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2168 struct e1000_hw *hw =
2169 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2170 struct rte_eth_link link, old;
2171 int link_check, count;
2174 hw->mac.get_link_status = 1;
2176 /* possible wait-to-complete in up to 9 seconds */
2177 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2178 /* Read the real link status */
2179 switch (hw->phy.media_type) {
2180 case e1000_media_type_copper:
2181 /* Do the work to read phy */
2182 e1000_check_for_link(hw);
2183 link_check = !hw->mac.get_link_status;
2186 case e1000_media_type_fiber:
2187 e1000_check_for_link(hw);
2188 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2192 case e1000_media_type_internal_serdes:
2193 e1000_check_for_link(hw);
2194 link_check = hw->mac.serdes_has_link;
2197 /* VF device is type_unknown */
2198 case e1000_media_type_unknown:
2199 eth_igbvf_link_update(hw);
2200 link_check = !hw->mac.get_link_status;
2206 if (link_check || wait_to_complete == 0)
2208 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2210 memset(&link, 0, sizeof(link));
2211 rte_igb_dev_atomic_read_link_status(dev, &link);
2214 /* Now we check if a transition has happened */
2216 uint16_t duplex, speed;
2217 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2218 link.link_duplex = (duplex == FULL_DUPLEX) ?
2219 ETH_LINK_FULL_DUPLEX :
2220 ETH_LINK_HALF_DUPLEX;
2221 link.link_speed = speed;
2222 link.link_status = ETH_LINK_UP;
2223 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2224 ETH_LINK_SPEED_FIXED);
2225 } else if (!link_check) {
2226 link.link_speed = 0;
2227 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2228 link.link_status = ETH_LINK_DOWN;
2229 link.link_autoneg = ETH_LINK_FIXED;
2231 rte_igb_dev_atomic_write_link_status(dev, &link);
2234 if (old.link_status == link.link_status)
2242 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2243 * For ASF and Pass Through versions of f/w this means
2244 * that the driver is loaded.
2247 igb_hw_control_acquire(struct e1000_hw *hw)
2251 /* Let firmware know the driver has taken over */
2252 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2253 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2257 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2258 * For ASF and Pass Through versions of f/w this means that the
2259 * driver is no longer loaded.
2262 igb_hw_control_release(struct e1000_hw *hw)
2266 /* Let firmware taken over control of h/w */
2267 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2268 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2269 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2273 * Bit of a misnomer, what this really means is
2274 * to enable OS management of the system... aka
2275 * to disable special hardware management features.
2278 igb_init_manageability(struct e1000_hw *hw)
2280 if (e1000_enable_mng_pass_thru(hw)) {
2281 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2282 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2284 /* disable hardware interception of ARP */
2285 manc &= ~(E1000_MANC_ARP_EN);
2287 /* enable receiving management packets to the host */
2288 manc |= E1000_MANC_EN_MNG2HOST;
2289 manc2h |= 1 << 5; /* Mng Port 623 */
2290 manc2h |= 1 << 6; /* Mng Port 664 */
2291 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2292 E1000_WRITE_REG(hw, E1000_MANC, manc);
2297 igb_release_manageability(struct e1000_hw *hw)
2299 if (e1000_enable_mng_pass_thru(hw)) {
2300 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2302 manc |= E1000_MANC_ARP_EN;
2303 manc &= ~E1000_MANC_EN_MNG2HOST;
2305 E1000_WRITE_REG(hw, E1000_MANC, manc);
2310 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2312 struct e1000_hw *hw =
2313 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316 rctl = E1000_READ_REG(hw, E1000_RCTL);
2317 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2318 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2322 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2324 struct e1000_hw *hw =
2325 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2328 rctl = E1000_READ_REG(hw, E1000_RCTL);
2329 rctl &= (~E1000_RCTL_UPE);
2330 if (dev->data->all_multicast == 1)
2331 rctl |= E1000_RCTL_MPE;
2333 rctl &= (~E1000_RCTL_MPE);
2334 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2338 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2340 struct e1000_hw *hw =
2341 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2344 rctl = E1000_READ_REG(hw, E1000_RCTL);
2345 rctl |= E1000_RCTL_MPE;
2346 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2350 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2352 struct e1000_hw *hw =
2353 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2356 if (dev->data->promiscuous == 1)
2357 return; /* must remain in all_multicast mode */
2358 rctl = E1000_READ_REG(hw, E1000_RCTL);
2359 rctl &= (~E1000_RCTL_MPE);
2360 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2364 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2366 struct e1000_hw *hw =
2367 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2368 struct e1000_vfta * shadow_vfta =
2369 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2374 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2375 E1000_VFTA_ENTRY_MASK);
2376 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2377 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2382 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2384 /* update local VFTA copy */
2385 shadow_vfta->vfta[vid_idx] = vfta;
2391 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2392 enum rte_vlan_type vlan_type,
2395 struct e1000_hw *hw =
2396 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399 qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2400 qinq &= E1000_CTRL_EXT_EXT_VLAN;
2402 /* only outer TPID of double VLAN can be configured*/
2403 if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2404 reg = E1000_READ_REG(hw, E1000_VET);
2405 reg = (reg & (~E1000_VET_VET_EXT)) |
2406 ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2407 E1000_WRITE_REG(hw, E1000_VET, reg);
2412 /* all other TPID values are read-only*/
2413 PMD_DRV_LOG(ERR, "Not supported");
2419 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2421 struct e1000_hw *hw =
2422 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2425 /* Filter Table Disable */
2426 reg = E1000_READ_REG(hw, E1000_RCTL);
2427 reg &= ~E1000_RCTL_CFIEN;
2428 reg &= ~E1000_RCTL_VFE;
2429 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2433 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2435 struct e1000_hw *hw =
2436 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2437 struct e1000_vfta * shadow_vfta =
2438 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2442 /* Filter Table Enable, CFI not used for packet acceptance */
2443 reg = E1000_READ_REG(hw, E1000_RCTL);
2444 reg &= ~E1000_RCTL_CFIEN;
2445 reg |= E1000_RCTL_VFE;
2446 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2448 /* restore VFTA table */
2449 for (i = 0; i < IGB_VFTA_SIZE; i++)
2450 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2454 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2456 struct e1000_hw *hw =
2457 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2460 /* VLAN Mode Disable */
2461 reg = E1000_READ_REG(hw, E1000_CTRL);
2462 reg &= ~E1000_CTRL_VME;
2463 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2467 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2469 struct e1000_hw *hw =
2470 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2473 /* VLAN Mode Enable */
2474 reg = E1000_READ_REG(hw, E1000_CTRL);
2475 reg |= E1000_CTRL_VME;
2476 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2480 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2482 struct e1000_hw *hw =
2483 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486 /* CTRL_EXT: Extended VLAN */
2487 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2488 reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2489 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2491 /* Update maximum packet length */
2492 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2493 E1000_WRITE_REG(hw, E1000_RLPML,
2494 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2499 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2501 struct e1000_hw *hw =
2502 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2505 /* CTRL_EXT: Extended VLAN */
2506 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2507 reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2508 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2510 /* Update maximum packet length */
2511 if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2512 E1000_WRITE_REG(hw, E1000_RLPML,
2513 dev->data->dev_conf.rxmode.max_rx_pkt_len +
2518 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2520 if(mask & ETH_VLAN_STRIP_MASK){
2521 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2522 igb_vlan_hw_strip_enable(dev);
2524 igb_vlan_hw_strip_disable(dev);
2527 if(mask & ETH_VLAN_FILTER_MASK){
2528 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2529 igb_vlan_hw_filter_enable(dev);
2531 igb_vlan_hw_filter_disable(dev);
2534 if(mask & ETH_VLAN_EXTEND_MASK){
2535 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2536 igb_vlan_hw_extend_enable(dev);
2538 igb_vlan_hw_extend_disable(dev);
2544 * It enables the interrupt mask and then enable the interrupt.
2547 * Pointer to struct rte_eth_dev.
2552 * - On success, zero.
2553 * - On failure, a negative value.
2556 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2558 struct e1000_interrupt *intr =
2559 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2562 intr->mask |= E1000_ICR_LSC;
2564 intr->mask &= ~E1000_ICR_LSC;
2569 /* It clears the interrupt causes and enables the interrupt.
2570 * It will be called once only during nic initialized.
2573 * Pointer to struct rte_eth_dev.
2576 * - On success, zero.
2577 * - On failure, a negative value.
2579 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2581 uint32_t mask, regval;
2582 struct e1000_hw *hw =
2583 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584 struct rte_eth_dev_info dev_info;
2586 memset(&dev_info, 0, sizeof(dev_info));
2587 eth_igb_infos_get(dev, &dev_info);
2589 mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2590 regval = E1000_READ_REG(hw, E1000_EIMS);
2591 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2597 * It reads ICR and gets interrupt causes, check it and set a bit flag
2598 * to update link status.
2601 * Pointer to struct rte_eth_dev.
2604 * - On success, zero.
2605 * - On failure, a negative value.
2608 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2611 struct e1000_hw *hw =
2612 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2613 struct e1000_interrupt *intr =
2614 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2616 igb_intr_disable(hw);
2618 /* read-on-clear nic registers here */
2619 icr = E1000_READ_REG(hw, E1000_ICR);
2622 if (icr & E1000_ICR_LSC) {
2623 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2626 if (icr & E1000_ICR_VMMB)
2627 intr->flags |= E1000_FLAG_MAILBOX;
2633 * It executes link_update after knowing an interrupt is prsent.
2636 * Pointer to struct rte_eth_dev.
2639 * - On success, zero.
2640 * - On failure, a negative value.
2643 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2645 struct e1000_hw *hw =
2646 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647 struct e1000_interrupt *intr =
2648 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2649 uint32_t tctl, rctl;
2650 struct rte_eth_link link;
2653 if (intr->flags & E1000_FLAG_MAILBOX) {
2654 igb_pf_mbx_process(dev);
2655 intr->flags &= ~E1000_FLAG_MAILBOX;
2658 igb_intr_enable(dev);
2659 rte_intr_enable(&(dev->pci_dev->intr_handle));
2661 if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2662 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2664 /* set get_link_status to check register later */
2665 hw->mac.get_link_status = 1;
2666 ret = eth_igb_link_update(dev, 0);
2668 /* check if link has changed */
2672 memset(&link, 0, sizeof(link));
2673 rte_igb_dev_atomic_read_link_status(dev, &link);
2674 if (link.link_status) {
2676 " Port %d: Link Up - speed %u Mbps - %s",
2678 (unsigned)link.link_speed,
2679 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2680 "full-duplex" : "half-duplex");
2682 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2683 dev->data->port_id);
2686 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2687 dev->pci_dev->addr.domain,
2688 dev->pci_dev->addr.bus,
2689 dev->pci_dev->addr.devid,
2690 dev->pci_dev->addr.function);
2691 tctl = E1000_READ_REG(hw, E1000_TCTL);
2692 rctl = E1000_READ_REG(hw, E1000_RCTL);
2693 if (link.link_status) {
2695 tctl |= E1000_TCTL_EN;
2696 rctl |= E1000_RCTL_EN;
2699 tctl &= ~E1000_TCTL_EN;
2700 rctl &= ~E1000_RCTL_EN;
2702 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2703 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2704 E1000_WRITE_FLUSH(hw);
2705 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2712 * Interrupt handler which shall be registered at first.
2715 * Pointer to interrupt handle.
2717 * The address of parameter (struct rte_eth_dev *) regsitered before.
2723 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2726 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2728 eth_igb_interrupt_get_status(dev);
2729 eth_igb_interrupt_action(dev);
2733 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2736 struct e1000_hw *hw =
2737 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2738 struct e1000_interrupt *intr =
2739 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2741 igbvf_intr_disable(hw);
2743 /* read-on-clear nic registers here */
2744 eicr = E1000_READ_REG(hw, E1000_EICR);
2747 if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2748 intr->flags |= E1000_FLAG_MAILBOX;
2753 void igbvf_mbx_process(struct rte_eth_dev *dev)
2755 struct e1000_hw *hw =
2756 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2757 struct e1000_mbx_info *mbx = &hw->mbx;
2760 /* peek the message first */
2761 in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2763 /* PF reset VF event */
2764 if (in_msg == E1000_PF_CONTROL_MSG) {
2765 /* dummy mbx read to ack pf */
2766 if (mbx->ops.read(hw, &in_msg, 1, 0))
2768 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2774 eth_igbvf_interrupt_action(struct rte_eth_dev *dev)
2776 struct e1000_interrupt *intr =
2777 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2779 if (intr->flags & E1000_FLAG_MAILBOX) {
2780 igbvf_mbx_process(dev);
2781 intr->flags &= ~E1000_FLAG_MAILBOX;
2784 igbvf_intr_enable(dev);
2785 rte_intr_enable(&dev->pci_dev->intr_handle);
2791 eth_igbvf_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2794 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2796 eth_igbvf_interrupt_get_status(dev);
2797 eth_igbvf_interrupt_action(dev);
2801 eth_igb_led_on(struct rte_eth_dev *dev)
2803 struct e1000_hw *hw;
2805 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2806 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2810 eth_igb_led_off(struct rte_eth_dev *dev)
2812 struct e1000_hw *hw;
2814 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2815 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2819 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2821 struct e1000_hw *hw;
2826 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2827 fc_conf->pause_time = hw->fc.pause_time;
2828 fc_conf->high_water = hw->fc.high_water;
2829 fc_conf->low_water = hw->fc.low_water;
2830 fc_conf->send_xon = hw->fc.send_xon;
2831 fc_conf->autoneg = hw->mac.autoneg;
2834 * Return rx_pause and tx_pause status according to actual setting of
2835 * the TFCE and RFCE bits in the CTRL register.
2837 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2838 if (ctrl & E1000_CTRL_TFCE)
2843 if (ctrl & E1000_CTRL_RFCE)
2848 if (rx_pause && tx_pause)
2849 fc_conf->mode = RTE_FC_FULL;
2851 fc_conf->mode = RTE_FC_RX_PAUSE;
2853 fc_conf->mode = RTE_FC_TX_PAUSE;
2855 fc_conf->mode = RTE_FC_NONE;
2861 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2863 struct e1000_hw *hw;
2865 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2871 uint32_t rx_buf_size;
2872 uint32_t max_high_water;
2875 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876 if (fc_conf->autoneg != hw->mac.autoneg)
2878 rx_buf_size = igb_get_rx_buffer_size(hw);
2879 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2881 /* At least reserve one Ethernet frame for watermark */
2882 max_high_water = rx_buf_size - ETHER_MAX_LEN;
2883 if ((fc_conf->high_water > max_high_water) ||
2884 (fc_conf->high_water < fc_conf->low_water)) {
2885 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2886 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
2890 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2891 hw->fc.pause_time = fc_conf->pause_time;
2892 hw->fc.high_water = fc_conf->high_water;
2893 hw->fc.low_water = fc_conf->low_water;
2894 hw->fc.send_xon = fc_conf->send_xon;
2896 err = e1000_setup_link_generic(hw);
2897 if (err == E1000_SUCCESS) {
2899 /* check if we want to forward MAC frames - driver doesn't have native
2900 * capability to do that, so we'll write the registers ourselves */
2902 rctl = E1000_READ_REG(hw, E1000_RCTL);
2904 /* set or clear MFLCN.PMCF bit depending on configuration */
2905 if (fc_conf->mac_ctrl_frame_fwd != 0)
2906 rctl |= E1000_RCTL_PMCF;
2908 rctl &= ~E1000_RCTL_PMCF;
2910 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2911 E1000_WRITE_FLUSH(hw);
2916 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2920 #define E1000_RAH_POOLSEL_SHIFT (18)
2922 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2923 uint32_t index, __rte_unused uint32_t pool)
2925 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2928 e1000_rar_set(hw, mac_addr->addr_bytes, index);
2929 rah = E1000_READ_REG(hw, E1000_RAH(index));
2930 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2931 E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2935 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2937 uint8_t addr[ETHER_ADDR_LEN];
2938 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2940 memset(addr, 0, sizeof(addr));
2942 e1000_rar_set(hw, addr, index);
2946 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2947 struct ether_addr *addr)
2949 eth_igb_rar_clear(dev, 0);
2951 eth_igb_rar_set(dev, (void *)addr, 0, 0);
2954 * Virtual Function operations
2957 igbvf_intr_disable(struct e1000_hw *hw)
2959 PMD_INIT_FUNC_TRACE();
2961 /* Clear interrupt mask to stop from interrupts being generated */
2962 E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2964 E1000_WRITE_FLUSH(hw);
2968 igbvf_stop_adapter(struct rte_eth_dev *dev)
2972 struct rte_eth_dev_info dev_info;
2973 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2975 memset(&dev_info, 0, sizeof(dev_info));
2976 eth_igbvf_infos_get(dev, &dev_info);
2978 /* Clear interrupt mask to stop from interrupts being generated */
2979 igbvf_intr_disable(hw);
2981 /* Clear any pending interrupts, flush previous writes */
2982 E1000_READ_REG(hw, E1000_EICR);
2984 /* Disable the transmit unit. Each queue must be disabled. */
2985 for (i = 0; i < dev_info.max_tx_queues; i++)
2986 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2988 /* Disable the receive unit by stopping each queue */
2989 for (i = 0; i < dev_info.max_rx_queues; i++) {
2990 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2991 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2992 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2993 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2997 /* flush all queues disables */
2998 E1000_WRITE_FLUSH(hw);
3002 static int eth_igbvf_link_update(struct e1000_hw *hw)
3004 struct e1000_mbx_info *mbx = &hw->mbx;
3005 struct e1000_mac_info *mac = &hw->mac;
3006 int ret_val = E1000_SUCCESS;
3008 PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3011 * We only want to run this if there has been a rst asserted.
3012 * in this case that could mean a link change, device reset,
3013 * or a virtual function reset
3016 /* If we were hit with a reset or timeout drop the link */
3017 if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3018 mac->get_link_status = TRUE;
3020 if (!mac->get_link_status)
3023 /* if link status is down no point in checking to see if pf is up */
3024 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3027 /* if we passed all the tests above then the link is up and we no
3028 * longer need to check for link */
3029 mac->get_link_status = FALSE;
3037 igbvf_dev_configure(struct rte_eth_dev *dev)
3039 struct rte_eth_conf* conf = &dev->data->dev_conf;
3041 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3042 dev->data->port_id);
3045 * VF has no ability to enable/disable HW CRC
3046 * Keep the persistent behavior the same as Host PF
3048 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3049 if (!conf->rxmode.hw_strip_crc) {
3050 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3051 conf->rxmode.hw_strip_crc = 1;
3054 if (conf->rxmode.hw_strip_crc) {
3055 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3056 conf->rxmode.hw_strip_crc = 0;
3064 igbvf_dev_start(struct rte_eth_dev *dev)
3066 struct e1000_hw *hw =
3067 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068 struct e1000_adapter *adapter =
3069 E1000_DEV_PRIVATE(dev->data->dev_private);
3071 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3072 uint32_t intr_vector = 0;
3074 PMD_INIT_FUNC_TRACE();
3076 hw->mac.ops.reset_hw(hw);
3077 adapter->stopped = 0;
3080 igbvf_set_vfta_all(dev,1);
3082 eth_igbvf_tx_init(dev);
3084 /* This can fail when allocating mbufs for descriptor rings */
3085 ret = eth_igbvf_rx_init(dev);
3087 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3088 igb_dev_clear_queues(dev);
3092 /* check and configure queue intr-vector mapping */
3093 if (rte_intr_cap_multiple(intr_handle) &&
3094 dev->data->dev_conf.intr_conf.rxq) {
3095 intr_vector = dev->data->nb_rx_queues;
3096 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3101 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3102 intr_handle->intr_vec =
3103 rte_zmalloc("intr_vec",
3104 dev->data->nb_rx_queues * sizeof(int), 0);
3105 if (!intr_handle->intr_vec) {
3106 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3107 " intr_vec\n", dev->data->nb_rx_queues);
3112 eth_igbvf_configure_msix_intr(dev);
3114 /* enable uio/vfio intr/eventfd mapping */
3115 rte_intr_enable(intr_handle);
3117 /* resume enabled intr since hw reset */
3118 igbvf_intr_enable(dev);
3124 igbvf_dev_stop(struct rte_eth_dev *dev)
3126 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3128 PMD_INIT_FUNC_TRACE();
3130 igbvf_stop_adapter(dev);
3133 * Clear what we set, but we still keep shadow_vfta to
3134 * restore after device starts
3136 igbvf_set_vfta_all(dev,0);
3138 igb_dev_clear_queues(dev);
3140 /* disable intr eventfd mapping */
3141 rte_intr_disable(intr_handle);
3143 /* Clean datapath event and queue/vec mapping */
3144 rte_intr_efd_disable(intr_handle);
3145 if (intr_handle->intr_vec) {
3146 rte_free(intr_handle->intr_vec);
3147 intr_handle->intr_vec = NULL;
3152 igbvf_dev_close(struct rte_eth_dev *dev)
3154 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3155 struct e1000_adapter *adapter =
3156 E1000_DEV_PRIVATE(dev->data->dev_private);
3157 struct ether_addr addr;
3159 PMD_INIT_FUNC_TRACE();
3163 igbvf_dev_stop(dev);
3164 adapter->stopped = 1;
3165 igb_dev_free_queues(dev);
3168 * reprogram the RAR with a zero mac address,
3169 * to ensure that the VF traffic goes to the PF
3170 * after stop, close and detach of the VF.
3173 memset(&addr, 0, sizeof(addr));
3174 igbvf_default_mac_addr_set(dev, &addr);
3178 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3180 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3182 /* Set both unicast and multicast promisc */
3183 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3187 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3189 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3191 /* If in allmulticast mode leave multicast promisc */
3192 if (dev->data->all_multicast == 1)
3193 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3195 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3199 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3201 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3203 /* In promiscuous mode multicast promisc already set */
3204 if (dev->data->promiscuous == 0)
3205 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3209 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3211 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3213 /* In promiscuous mode leave multicast promisc enabled */
3214 if (dev->data->promiscuous == 0)
3215 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3218 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3220 struct e1000_mbx_info *mbx = &hw->mbx;
3224 /* After set vlan, vlan strip will also be enabled in igb driver*/
3225 msgbuf[0] = E1000_VF_SET_VLAN;
3227 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3229 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3231 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3235 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3239 msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3240 if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3247 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3249 struct e1000_hw *hw =
3250 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3251 struct e1000_vfta * shadow_vfta =
3252 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3253 int i = 0, j = 0, vfta = 0, mask = 1;
3255 for (i = 0; i < IGB_VFTA_SIZE; i++){
3256 vfta = shadow_vfta->vfta[i];
3259 for (j = 0; j < 32; j++){
3262 (uint16_t)((i<<5)+j), on);
3271 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3273 struct e1000_hw *hw =
3274 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3275 struct e1000_vfta * shadow_vfta =
3276 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3277 uint32_t vid_idx = 0;
3278 uint32_t vid_bit = 0;
3281 PMD_INIT_FUNC_TRACE();
3283 /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3284 ret = igbvf_set_vfta(hw, vlan_id, !!on);
3286 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3289 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3290 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3292 /*Save what we set and retore it after device reset*/
3294 shadow_vfta->vfta[vid_idx] |= vid_bit;
3296 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3302 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3304 struct e1000_hw *hw =
3305 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3307 /* index is not used by rar_set() */
3308 hw->mac.ops.rar_set(hw, (void *)addr, 0);
3313 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3314 struct rte_eth_rss_reta_entry64 *reta_conf,
3319 uint16_t idx, shift;
3320 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3322 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3323 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3324 "(%d) doesn't match the number hardware can supported "
3325 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3329 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3330 idx = i / RTE_RETA_GROUP_SIZE;
3331 shift = i % RTE_RETA_GROUP_SIZE;
3332 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3336 if (mask == IGB_4_BIT_MASK)
3339 r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3340 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3341 if (mask & (0x1 << j))
3342 reta |= reta_conf[idx].reta[shift + j] <<
3345 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3347 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3354 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3355 struct rte_eth_rss_reta_entry64 *reta_conf,
3360 uint16_t idx, shift;
3361 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3363 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3364 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3365 "(%d) doesn't match the number hardware can supported "
3366 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3370 for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3371 idx = i / RTE_RETA_GROUP_SIZE;
3372 shift = i % RTE_RETA_GROUP_SIZE;
3373 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3377 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3378 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3379 if (mask & (0x1 << j))
3380 reta_conf[idx].reta[shift + j] =
3381 ((reta >> (CHAR_BIT * j)) &
3389 #define MAC_TYPE_FILTER_SUP(type) do {\
3390 if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3391 (type) != e1000_82576)\
3396 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3397 struct rte_eth_syn_filter *filter,
3400 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3401 uint32_t synqf, rfctl;
3403 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3406 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3409 if (synqf & E1000_SYN_FILTER_ENABLE)
3412 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3413 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3415 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3416 if (filter->hig_pri)
3417 rfctl |= E1000_RFCTL_SYNQFP;
3419 rfctl &= ~E1000_RFCTL_SYNQFP;
3421 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3423 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3428 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3429 E1000_WRITE_FLUSH(hw);
3434 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3435 struct rte_eth_syn_filter *filter)
3437 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3438 uint32_t synqf, rfctl;
3440 synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3441 if (synqf & E1000_SYN_FILTER_ENABLE) {
3442 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3443 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3444 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3445 E1000_SYN_FILTER_QUEUE_SHIFT);
3453 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3454 enum rte_filter_op filter_op,
3457 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3460 MAC_TYPE_FILTER_SUP(hw->mac.type);
3462 if (filter_op == RTE_ETH_FILTER_NOP)
3466 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3471 switch (filter_op) {
3472 case RTE_ETH_FILTER_ADD:
3473 ret = eth_igb_syn_filter_set(dev,
3474 (struct rte_eth_syn_filter *)arg,
3477 case RTE_ETH_FILTER_DELETE:
3478 ret = eth_igb_syn_filter_set(dev,
3479 (struct rte_eth_syn_filter *)arg,
3482 case RTE_ETH_FILTER_GET:
3483 ret = eth_igb_syn_filter_get(dev,
3484 (struct rte_eth_syn_filter *)arg);
3487 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3495 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
3496 if ((type) != e1000_82580 && (type) != e1000_i350)\
3500 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3502 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3503 struct e1000_2tuple_filter_info *filter_info)
3505 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3507 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3508 return -EINVAL; /* filter index is out of range. */
3509 if (filter->tcp_flags > TCP_FLAG_ALL)
3510 return -EINVAL; /* flags is invalid. */
3512 switch (filter->dst_port_mask) {
3514 filter_info->dst_port_mask = 0;
3515 filter_info->dst_port = filter->dst_port;
3518 filter_info->dst_port_mask = 1;
3521 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3525 switch (filter->proto_mask) {
3527 filter_info->proto_mask = 0;
3528 filter_info->proto = filter->proto;
3531 filter_info->proto_mask = 1;
3534 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3538 filter_info->priority = (uint8_t)filter->priority;
3539 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3540 filter_info->tcp_flags = filter->tcp_flags;
3542 filter_info->tcp_flags = 0;
3547 static inline struct e1000_2tuple_filter *
3548 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3549 struct e1000_2tuple_filter_info *key)
3551 struct e1000_2tuple_filter *it;
3553 TAILQ_FOREACH(it, filter_list, entries) {
3554 if (memcmp(key, &it->filter_info,
3555 sizeof(struct e1000_2tuple_filter_info)) == 0) {
3563 * igb_add_2tuple_filter - add a 2tuple filter
3566 * dev: Pointer to struct rte_eth_dev.
3567 * ntuple_filter: ponter to the filter that will be added.
3570 * - On success, zero.
3571 * - On failure, a negative value.
3574 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3575 struct rte_eth_ntuple_filter *ntuple_filter)
3577 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3578 struct e1000_filter_info *filter_info =
3579 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3580 struct e1000_2tuple_filter *filter;
3581 uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3582 uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3585 filter = rte_zmalloc("e1000_2tuple_filter",
3586 sizeof(struct e1000_2tuple_filter), 0);
3590 ret = ntuple_filter_to_2tuple(ntuple_filter,
3591 &filter->filter_info);
3596 if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3597 &filter->filter_info) != NULL) {
3598 PMD_DRV_LOG(ERR, "filter exists.");
3602 filter->queue = ntuple_filter->queue;
3605 * look for an unused 2tuple filter index,
3606 * and insert the filter to list.
3608 for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3609 if (!(filter_info->twotuple_mask & (1 << i))) {
3610 filter_info->twotuple_mask |= 1 << i;
3612 TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3618 if (i >= E1000_MAX_TTQF_FILTERS) {
3619 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3624 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3625 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3626 imir |= E1000_IMIR_PORT_BP;
3628 imir &= ~E1000_IMIR_PORT_BP;
3630 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3632 ttqf |= E1000_TTQF_QUEUE_ENABLE;
3633 ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3634 ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3635 if (filter->filter_info.proto_mask == 0)
3636 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3638 /* tcp flags bits setting. */
3639 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3640 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3641 imir_ext |= E1000_IMIREXT_CTRL_URG;
3642 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3643 imir_ext |= E1000_IMIREXT_CTRL_ACK;
3644 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3645 imir_ext |= E1000_IMIREXT_CTRL_PSH;
3646 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3647 imir_ext |= E1000_IMIREXT_CTRL_RST;
3648 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3649 imir_ext |= E1000_IMIREXT_CTRL_SYN;
3650 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3651 imir_ext |= E1000_IMIREXT_CTRL_FIN;
3653 imir_ext |= E1000_IMIREXT_CTRL_BP;
3654 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3655 E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3656 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3661 * igb_remove_2tuple_filter - remove a 2tuple filter
3664 * dev: Pointer to struct rte_eth_dev.
3665 * ntuple_filter: ponter to the filter that will be removed.
3668 * - On success, zero.
3669 * - On failure, a negative value.
3672 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3673 struct rte_eth_ntuple_filter *ntuple_filter)
3675 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3676 struct e1000_filter_info *filter_info =
3677 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3678 struct e1000_2tuple_filter_info filter_2tuple;
3679 struct e1000_2tuple_filter *filter;
3682 memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3683 ret = ntuple_filter_to_2tuple(ntuple_filter,
3688 filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3690 if (filter == NULL) {
3691 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3695 filter_info->twotuple_mask &= ~(1 << filter->index);
3696 TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3699 E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3700 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3701 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3705 static inline struct e1000_flex_filter *
3706 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3707 struct e1000_flex_filter_info *key)
3709 struct e1000_flex_filter *it;
3711 TAILQ_FOREACH(it, filter_list, entries) {
3712 if (memcmp(key, &it->filter_info,
3713 sizeof(struct e1000_flex_filter_info)) == 0)
3721 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3722 struct rte_eth_flex_filter *filter,
3725 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3726 struct e1000_filter_info *filter_info =
3727 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3728 struct e1000_flex_filter *flex_filter, *it;
3729 uint32_t wufc, queueing, mask;
3731 uint8_t shift, i, j = 0;
3733 flex_filter = rte_zmalloc("e1000_flex_filter",
3734 sizeof(struct e1000_flex_filter), 0);
3735 if (flex_filter == NULL)
3738 flex_filter->filter_info.len = filter->len;
3739 flex_filter->filter_info.priority = filter->priority;
3740 memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3741 for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3743 /* reverse bits in flex filter's mask*/
3744 for (shift = 0; shift < CHAR_BIT; shift++) {
3745 if (filter->mask[i] & (0x01 << shift))
3746 mask |= (0x80 >> shift);
3748 flex_filter->filter_info.mask[i] = mask;
3751 wufc = E1000_READ_REG(hw, E1000_WUFC);
3754 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3755 &flex_filter->filter_info) != NULL) {
3756 PMD_DRV_LOG(ERR, "filter exists.");
3757 rte_free(flex_filter);
3760 flex_filter->queue = filter->queue;
3762 * look for an unused flex filter index
3763 * and insert the filter into the list.
3765 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3766 if (!(filter_info->flex_mask & (1 << i))) {
3767 filter_info->flex_mask |= 1 << i;
3768 flex_filter->index = i;
3769 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3775 if (i >= E1000_MAX_FLEX_FILTERS) {
3776 PMD_DRV_LOG(ERR, "flex filters are full.");
3777 rte_free(flex_filter);
3781 if (flex_filter->index < E1000_MAX_FHFT)
3782 reg_off = E1000_FHFT(flex_filter->index);
3784 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3786 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3787 (E1000_WUFC_FLX0 << flex_filter->index));
3788 queueing = filter->len |
3789 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3790 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3791 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3793 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3794 E1000_WRITE_REG(hw, reg_off,
3795 flex_filter->filter_info.dwords[j]);
3796 reg_off += sizeof(uint32_t);
3797 E1000_WRITE_REG(hw, reg_off,
3798 flex_filter->filter_info.dwords[++j]);
3799 reg_off += sizeof(uint32_t);
3800 E1000_WRITE_REG(hw, reg_off,
3801 (uint32_t)flex_filter->filter_info.mask[i]);
3802 reg_off += sizeof(uint32_t) * 2;
3806 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3807 &flex_filter->filter_info);
3809 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3810 rte_free(flex_filter);
3814 if (it->index < E1000_MAX_FHFT)
3815 reg_off = E1000_FHFT(it->index);
3817 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3819 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3820 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3821 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3822 (~(E1000_WUFC_FLX0 << it->index)));
3824 filter_info->flex_mask &= ~(1 << it->index);
3825 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3827 rte_free(flex_filter);
3834 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3835 struct rte_eth_flex_filter *filter)
3837 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3838 struct e1000_filter_info *filter_info =
3839 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3840 struct e1000_flex_filter flex_filter, *it;
3841 uint32_t wufc, queueing, wufc_en = 0;
3843 memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3844 flex_filter.filter_info.len = filter->len;
3845 flex_filter.filter_info.priority = filter->priority;
3846 memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3847 memcpy(flex_filter.filter_info.mask, filter->mask,
3848 RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
3850 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3851 &flex_filter.filter_info);
3853 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3857 wufc = E1000_READ_REG(hw, E1000_WUFC);
3858 wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3860 if ((wufc & wufc_en) == wufc_en) {
3861 uint32_t reg_off = 0;
3862 if (it->index < E1000_MAX_FHFT)
3863 reg_off = E1000_FHFT(it->index);
3865 reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3867 queueing = E1000_READ_REG(hw,
3868 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3869 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3870 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3871 E1000_FHFT_QUEUEING_PRIO_SHIFT;
3872 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3873 E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3880 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3881 enum rte_filter_op filter_op,
3884 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3885 struct rte_eth_flex_filter *filter;
3888 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3890 if (filter_op == RTE_ETH_FILTER_NOP)
3894 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3899 filter = (struct rte_eth_flex_filter *)arg;
3900 if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3901 || filter->len % sizeof(uint64_t) != 0) {
3902 PMD_DRV_LOG(ERR, "filter's length is out of range");
3905 if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3906 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3910 switch (filter_op) {
3911 case RTE_ETH_FILTER_ADD:
3912 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3914 case RTE_ETH_FILTER_DELETE:
3915 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3917 case RTE_ETH_FILTER_GET:
3918 ret = eth_igb_get_flex_filter(dev, filter);
3921 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3929 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3931 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3932 struct e1000_5tuple_filter_info *filter_info)
3934 if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3936 if (filter->priority > E1000_2TUPLE_MAX_PRI)
3937 return -EINVAL; /* filter index is out of range. */
3938 if (filter->tcp_flags > TCP_FLAG_ALL)
3939 return -EINVAL; /* flags is invalid. */
3941 switch (filter->dst_ip_mask) {
3943 filter_info->dst_ip_mask = 0;
3944 filter_info->dst_ip = filter->dst_ip;
3947 filter_info->dst_ip_mask = 1;
3950 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3954 switch (filter->src_ip_mask) {
3956 filter_info->src_ip_mask = 0;
3957 filter_info->src_ip = filter->src_ip;
3960 filter_info->src_ip_mask = 1;
3963 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3967 switch (filter->dst_port_mask) {
3969 filter_info->dst_port_mask = 0;
3970 filter_info->dst_port = filter->dst_port;
3973 filter_info->dst_port_mask = 1;
3976 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3980 switch (filter->src_port_mask) {
3982 filter_info->src_port_mask = 0;
3983 filter_info->src_port = filter->src_port;
3986 filter_info->src_port_mask = 1;
3989 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3993 switch (filter->proto_mask) {
3995 filter_info->proto_mask = 0;
3996 filter_info->proto = filter->proto;
3999 filter_info->proto_mask = 1;
4002 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4006 filter_info->priority = (uint8_t)filter->priority;
4007 if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4008 filter_info->tcp_flags = filter->tcp_flags;
4010 filter_info->tcp_flags = 0;
4015 static inline struct e1000_5tuple_filter *
4016 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4017 struct e1000_5tuple_filter_info *key)
4019 struct e1000_5tuple_filter *it;
4021 TAILQ_FOREACH(it, filter_list, entries) {
4022 if (memcmp(key, &it->filter_info,
4023 sizeof(struct e1000_5tuple_filter_info)) == 0) {
4031 * igb_add_5tuple_filter_82576 - add a 5tuple filter
4034 * dev: Pointer to struct rte_eth_dev.
4035 * ntuple_filter: ponter to the filter that will be added.
4038 * - On success, zero.
4039 * - On failure, a negative value.
4042 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4043 struct rte_eth_ntuple_filter *ntuple_filter)
4045 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4046 struct e1000_filter_info *filter_info =
4047 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4048 struct e1000_5tuple_filter *filter;
4049 uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4050 uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4054 filter = rte_zmalloc("e1000_5tuple_filter",
4055 sizeof(struct e1000_5tuple_filter), 0);
4059 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4060 &filter->filter_info);
4066 if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4067 &filter->filter_info) != NULL) {
4068 PMD_DRV_LOG(ERR, "filter exists.");
4072 filter->queue = ntuple_filter->queue;
4075 * look for an unused 5tuple filter index,
4076 * and insert the filter to list.
4078 for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4079 if (!(filter_info->fivetuple_mask & (1 << i))) {
4080 filter_info->fivetuple_mask |= 1 << i;
4082 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4088 if (i >= E1000_MAX_FTQF_FILTERS) {
4089 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4094 ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4095 if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4096 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4097 if (filter->filter_info.dst_ip_mask == 0)
4098 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4099 if (filter->filter_info.src_port_mask == 0)
4100 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4101 if (filter->filter_info.proto_mask == 0)
4102 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4103 ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4104 E1000_FTQF_QUEUE_MASK;
4105 ftqf |= E1000_FTQF_QUEUE_ENABLE;
4106 E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4107 E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4108 E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4110 spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4111 E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4113 imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4114 if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4115 imir |= E1000_IMIR_PORT_BP;
4117 imir &= ~E1000_IMIR_PORT_BP;
4118 imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4120 /* tcp flags bits setting. */
4121 if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4122 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4123 imir_ext |= E1000_IMIREXT_CTRL_URG;
4124 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4125 imir_ext |= E1000_IMIREXT_CTRL_ACK;
4126 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4127 imir_ext |= E1000_IMIREXT_CTRL_PSH;
4128 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4129 imir_ext |= E1000_IMIREXT_CTRL_RST;
4130 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4131 imir_ext |= E1000_IMIREXT_CTRL_SYN;
4132 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4133 imir_ext |= E1000_IMIREXT_CTRL_FIN;
4135 imir_ext |= E1000_IMIREXT_CTRL_BP;
4136 E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4137 E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4142 * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4145 * dev: Pointer to struct rte_eth_dev.
4146 * ntuple_filter: ponter to the filter that will be removed.
4149 * - On success, zero.
4150 * - On failure, a negative value.
4153 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4154 struct rte_eth_ntuple_filter *ntuple_filter)
4156 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4157 struct e1000_filter_info *filter_info =
4158 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4159 struct e1000_5tuple_filter_info filter_5tuple;
4160 struct e1000_5tuple_filter *filter;
4163 memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4164 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4169 filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4171 if (filter == NULL) {
4172 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4176 filter_info->fivetuple_mask &= ~(1 << filter->index);
4177 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4180 E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4181 E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4182 E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4183 E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4184 E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4185 E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4186 E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4191 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4194 struct e1000_hw *hw;
4195 struct rte_eth_dev_info dev_info;
4196 uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4199 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4201 #ifdef RTE_LIBRTE_82571_SUPPORT
4202 /* XXX: not bigger than max_rx_pktlen */
4203 if (hw->mac.type == e1000_82571)
4206 eth_igb_infos_get(dev, &dev_info);
4208 /* check that mtu is within the allowed range */
4209 if ((mtu < ETHER_MIN_MTU) ||
4210 (frame_size > dev_info.max_rx_pktlen))
4213 /* refuse mtu that requires the support of scattered packets when this
4214 * feature has not been enabled before. */
4215 if (!dev->data->scattered_rx &&
4216 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4219 rctl = E1000_READ_REG(hw, E1000_RCTL);
4221 /* switch to jumbo mode if needed */
4222 if (frame_size > ETHER_MAX_LEN) {
4223 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4224 rctl |= E1000_RCTL_LPE;
4226 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4227 rctl &= ~E1000_RCTL_LPE;
4229 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4231 /* update max frame size */
4232 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4234 E1000_WRITE_REG(hw, E1000_RLPML,
4235 dev->data->dev_conf.rxmode.max_rx_pkt_len);
4241 * igb_add_del_ntuple_filter - add or delete a ntuple filter
4244 * dev: Pointer to struct rte_eth_dev.
4245 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4246 * add: if true, add filter, if false, remove filter
4249 * - On success, zero.
4250 * - On failure, a negative value.
4253 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4254 struct rte_eth_ntuple_filter *ntuple_filter,
4257 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4260 switch (ntuple_filter->flags) {
4261 case RTE_5TUPLE_FLAGS:
4262 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4263 if (hw->mac.type != e1000_82576)
4266 ret = igb_add_5tuple_filter_82576(dev,
4269 ret = igb_remove_5tuple_filter_82576(dev,
4272 case RTE_2TUPLE_FLAGS:
4273 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4274 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4277 ret = igb_add_2tuple_filter(dev, ntuple_filter);
4279 ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4290 * igb_get_ntuple_filter - get a ntuple filter
4293 * dev: Pointer to struct rte_eth_dev.
4294 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4297 * - On success, zero.
4298 * - On failure, a negative value.
4301 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4302 struct rte_eth_ntuple_filter *ntuple_filter)
4304 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4305 struct e1000_filter_info *filter_info =
4306 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4307 struct e1000_5tuple_filter_info filter_5tuple;
4308 struct e1000_2tuple_filter_info filter_2tuple;
4309 struct e1000_5tuple_filter *p_5tuple_filter;
4310 struct e1000_2tuple_filter *p_2tuple_filter;
4313 switch (ntuple_filter->flags) {
4314 case RTE_5TUPLE_FLAGS:
4315 case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4316 if (hw->mac.type != e1000_82576)
4318 memset(&filter_5tuple,
4320 sizeof(struct e1000_5tuple_filter_info));
4321 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4325 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4326 &filter_info->fivetuple_list,
4328 if (p_5tuple_filter == NULL) {
4329 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4332 ntuple_filter->queue = p_5tuple_filter->queue;
4334 case RTE_2TUPLE_FLAGS:
4335 case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4336 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4338 memset(&filter_2tuple,
4340 sizeof(struct e1000_2tuple_filter_info));
4341 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4344 p_2tuple_filter = igb_2tuple_filter_lookup(
4345 &filter_info->twotuple_list,
4347 if (p_2tuple_filter == NULL) {
4348 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4351 ntuple_filter->queue = p_2tuple_filter->queue;
4362 * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4363 * @dev: pointer to rte_eth_dev structure
4364 * @filter_op:operation will be taken.
4365 * @arg: a pointer to specific structure corresponding to the filter_op
4368 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4369 enum rte_filter_op filter_op,
4372 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4375 MAC_TYPE_FILTER_SUP(hw->mac.type);
4377 if (filter_op == RTE_ETH_FILTER_NOP)
4381 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4386 switch (filter_op) {
4387 case RTE_ETH_FILTER_ADD:
4388 ret = igb_add_del_ntuple_filter(dev,
4389 (struct rte_eth_ntuple_filter *)arg,
4392 case RTE_ETH_FILTER_DELETE:
4393 ret = igb_add_del_ntuple_filter(dev,
4394 (struct rte_eth_ntuple_filter *)arg,
4397 case RTE_ETH_FILTER_GET:
4398 ret = igb_get_ntuple_filter(dev,
4399 (struct rte_eth_ntuple_filter *)arg);
4402 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4410 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4415 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4416 if (filter_info->ethertype_filters[i] == ethertype &&
4417 (filter_info->ethertype_mask & (1 << i)))
4424 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4429 for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4430 if (!(filter_info->ethertype_mask & (1 << i))) {
4431 filter_info->ethertype_mask |= 1 << i;
4432 filter_info->ethertype_filters[i] = ethertype;
4440 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4443 if (idx >= E1000_MAX_ETQF_FILTERS)
4445 filter_info->ethertype_mask &= ~(1 << idx);
4446 filter_info->ethertype_filters[idx] = 0;
4452 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4453 struct rte_eth_ethertype_filter *filter,
4456 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4457 struct e1000_filter_info *filter_info =
4458 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4462 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4463 filter->ether_type == ETHER_TYPE_IPv6) {
4464 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4465 " ethertype filter.", filter->ether_type);
4469 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4470 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4473 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4474 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4478 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4479 if (ret >= 0 && add) {
4480 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4481 filter->ether_type);
4484 if (ret < 0 && !add) {
4485 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4486 filter->ether_type);
4491 ret = igb_ethertype_filter_insert(filter_info,
4492 filter->ether_type);
4494 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4498 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4499 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4500 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4502 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4506 E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4507 E1000_WRITE_FLUSH(hw);
4513 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4514 struct rte_eth_ethertype_filter *filter)
4516 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4517 struct e1000_filter_info *filter_info =
4518 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4522 ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4524 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4525 filter->ether_type);
4529 etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4530 if (etqf & E1000_ETQF_FILTER_ENABLE) {
4531 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4533 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4534 E1000_ETQF_QUEUE_SHIFT;
4542 * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4543 * @dev: pointer to rte_eth_dev structure
4544 * @filter_op:operation will be taken.
4545 * @arg: a pointer to specific structure corresponding to the filter_op
4548 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4549 enum rte_filter_op filter_op,
4552 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4555 MAC_TYPE_FILTER_SUP(hw->mac.type);
4557 if (filter_op == RTE_ETH_FILTER_NOP)
4561 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4566 switch (filter_op) {
4567 case RTE_ETH_FILTER_ADD:
4568 ret = igb_add_del_ethertype_filter(dev,
4569 (struct rte_eth_ethertype_filter *)arg,
4572 case RTE_ETH_FILTER_DELETE:
4573 ret = igb_add_del_ethertype_filter(dev,
4574 (struct rte_eth_ethertype_filter *)arg,
4577 case RTE_ETH_FILTER_GET:
4578 ret = igb_get_ethertype_filter(dev,
4579 (struct rte_eth_ethertype_filter *)arg);
4582 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4590 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4591 enum rte_filter_type filter_type,
4592 enum rte_filter_op filter_op,
4597 switch (filter_type) {
4598 case RTE_ETH_FILTER_NTUPLE:
4599 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4601 case RTE_ETH_FILTER_ETHERTYPE:
4602 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4604 case RTE_ETH_FILTER_SYN:
4605 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4607 case RTE_ETH_FILTER_FLEXIBLE:
4608 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4611 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4620 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4621 struct ether_addr *mc_addr_set,
4622 uint32_t nb_mc_addr)
4624 struct e1000_hw *hw;
4626 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4627 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4632 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4634 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4635 uint64_t systime_cycles;
4637 switch (hw->mac.type) {
4641 * Need to read System Time Residue Register to be able
4642 * to read the other two registers.
4644 E1000_READ_REG(hw, E1000_SYSTIMR);
4645 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4646 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4647 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4654 * Need to read System Time Residue Register to be able
4655 * to read the other two registers.
4657 E1000_READ_REG(hw, E1000_SYSTIMR);
4658 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4659 /* Only the 8 LSB are valid. */
4660 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4664 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4665 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4670 return systime_cycles;
4674 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4676 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4677 uint64_t rx_tstamp_cycles;
4679 switch (hw->mac.type) {
4682 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4683 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4684 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4690 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4691 /* Only the 8 LSB are valid. */
4692 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4696 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4697 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4702 return rx_tstamp_cycles;
4706 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4708 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4709 uint64_t tx_tstamp_cycles;
4711 switch (hw->mac.type) {
4714 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4715 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4716 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4722 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4723 /* Only the 8 LSB are valid. */
4724 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4728 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4729 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4734 return tx_tstamp_cycles;
4738 igb_start_timecounters(struct rte_eth_dev *dev)
4740 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4741 struct e1000_adapter *adapter =
4742 (struct e1000_adapter *)dev->data->dev_private;
4743 uint32_t incval = 1;
4745 uint64_t mask = E1000_CYCLECOUNTER_MASK;
4747 switch (hw->mac.type) {
4751 /* 32 LSB bits + 8 MSB bits = 40 bits */
4752 mask = (1ULL << 40) - 1;
4757 * Start incrementing the register
4758 * used to timestamp PTP packets.
4760 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4763 incval = E1000_INCVALUE_82576;
4764 shift = IGB_82576_TSYNC_SHIFT;
4765 E1000_WRITE_REG(hw, E1000_TIMINCA,
4766 E1000_INCPERIOD_82576 | incval);
4773 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4774 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4775 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4777 adapter->systime_tc.cc_mask = mask;
4778 adapter->systime_tc.cc_shift = shift;
4779 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4781 adapter->rx_tstamp_tc.cc_mask = mask;
4782 adapter->rx_tstamp_tc.cc_shift = shift;
4783 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4785 adapter->tx_tstamp_tc.cc_mask = mask;
4786 adapter->tx_tstamp_tc.cc_shift = shift;
4787 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4791 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4793 struct e1000_adapter *adapter =
4794 (struct e1000_adapter *)dev->data->dev_private;
4796 adapter->systime_tc.nsec += delta;
4797 adapter->rx_tstamp_tc.nsec += delta;
4798 adapter->tx_tstamp_tc.nsec += delta;
4804 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4807 struct e1000_adapter *adapter =
4808 (struct e1000_adapter *)dev->data->dev_private;
4810 ns = rte_timespec_to_ns(ts);
4812 /* Set the timecounters to a new value. */
4813 adapter->systime_tc.nsec = ns;
4814 adapter->rx_tstamp_tc.nsec = ns;
4815 adapter->tx_tstamp_tc.nsec = ns;
4821 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4823 uint64_t ns, systime_cycles;
4824 struct e1000_adapter *adapter =
4825 (struct e1000_adapter *)dev->data->dev_private;
4827 systime_cycles = igb_read_systime_cyclecounter(dev);
4828 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4829 *ts = rte_ns_to_timespec(ns);
4835 igb_timesync_enable(struct rte_eth_dev *dev)
4837 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4841 /* Stop the timesync system time. */
4842 E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4843 /* Reset the timesync system time value. */
4844 switch (hw->mac.type) {
4850 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4853 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4854 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4857 /* Not supported. */
4861 /* Enable system time for it isn't on by default. */
4862 tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4863 tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4864 E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4866 igb_start_timecounters(dev);
4868 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4869 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4871 E1000_ETQF_FILTER_ENABLE |
4874 /* Enable timestamping of received PTP packets. */
4875 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4876 tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4877 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4879 /* Enable Timestamping of transmitted PTP packets. */
4880 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4881 tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4882 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4888 igb_timesync_disable(struct rte_eth_dev *dev)
4890 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4893 /* Disable timestamping of transmitted PTP packets. */
4894 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4895 tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4896 E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4898 /* Disable timestamping of received PTP packets. */
4899 tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4900 tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4901 E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4903 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4904 E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4906 /* Stop incrementating the System Time registers. */
4907 E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4913 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4914 struct timespec *timestamp,
4915 uint32_t flags __rte_unused)
4917 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4918 struct e1000_adapter *adapter =
4919 (struct e1000_adapter *)dev->data->dev_private;
4920 uint32_t tsync_rxctl;
4921 uint64_t rx_tstamp_cycles;
4924 tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4925 if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4928 rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4929 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4930 *timestamp = rte_ns_to_timespec(ns);
4936 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4937 struct timespec *timestamp)
4939 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4940 struct e1000_adapter *adapter =
4941 (struct e1000_adapter *)dev->data->dev_private;
4942 uint32_t tsync_txctl;
4943 uint64_t tx_tstamp_cycles;
4946 tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4947 if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4950 tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4951 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4952 *timestamp = rte_ns_to_timespec(ns);
4958 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4962 const struct reg_info *reg_group;
4964 while ((reg_group = igb_regs[g_ind++]))
4965 count += igb_reg_group_count(reg_group);
4971 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4975 const struct reg_info *reg_group;
4977 while ((reg_group = igbvf_regs[g_ind++]))
4978 count += igb_reg_group_count(reg_group);
4984 eth_igb_get_regs(struct rte_eth_dev *dev,
4985 struct rte_dev_reg_info *regs)
4987 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4988 uint32_t *data = regs->data;
4991 const struct reg_info *reg_group;
4994 regs->length = eth_igb_get_reg_length(dev);
4995 regs->width = sizeof(uint32_t);
4999 /* Support only full register dump */
5000 if ((regs->length == 0) ||
5001 (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5002 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5004 while ((reg_group = igb_regs[g_ind++]))
5005 count += igb_read_regs_group(dev, &data[count],
5014 igbvf_get_regs(struct rte_eth_dev *dev,
5015 struct rte_dev_reg_info *regs)
5017 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5018 uint32_t *data = regs->data;
5021 const struct reg_info *reg_group;
5024 regs->length = igbvf_get_reg_length(dev);
5025 regs->width = sizeof(uint32_t);
5029 /* Support only full register dump */
5030 if ((regs->length == 0) ||
5031 (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5032 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5034 while ((reg_group = igbvf_regs[g_ind++]))
5035 count += igb_read_regs_group(dev, &data[count],
5044 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5046 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5048 /* Return unit is byte count */
5049 return hw->nvm.word_size * 2;
5053 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5054 struct rte_dev_eeprom_info *in_eeprom)
5056 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5057 struct e1000_nvm_info *nvm = &hw->nvm;
5058 uint16_t *data = in_eeprom->data;
5061 first = in_eeprom->offset >> 1;
5062 length = in_eeprom->length >> 1;
5063 if ((first >= hw->nvm.word_size) ||
5064 ((first + length) >= hw->nvm.word_size))
5067 in_eeprom->magic = hw->vendor_id |
5068 ((uint32_t)hw->device_id << 16);
5070 if ((nvm->ops.read) == NULL)
5073 return nvm->ops.read(hw, first, length, data);
5077 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5078 struct rte_dev_eeprom_info *in_eeprom)
5080 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5081 struct e1000_nvm_info *nvm = &hw->nvm;
5082 uint16_t *data = in_eeprom->data;
5085 first = in_eeprom->offset >> 1;
5086 length = in_eeprom->length >> 1;
5087 if ((first >= hw->nvm.word_size) ||
5088 ((first + length) >= hw->nvm.word_size))
5091 in_eeprom->magic = (uint32_t)hw->vendor_id |
5092 ((uint32_t)hw->device_id << 16);
5094 if ((nvm->ops.write) == NULL)
5096 return nvm->ops.write(hw, first, length, data);
5100 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5102 struct e1000_hw *hw =
5103 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5104 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5105 uint32_t vec = E1000_MISC_VEC_ID;
5107 if (rte_intr_allow_others(intr_handle))
5108 vec = E1000_RX_VEC_START;
5110 uint32_t mask = 1 << (queue_id + vec);
5112 E1000_WRITE_REG(hw, E1000_EIMC, mask);
5113 E1000_WRITE_FLUSH(hw);
5119 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5121 struct e1000_hw *hw =
5122 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5123 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5124 uint32_t vec = E1000_MISC_VEC_ID;
5126 if (rte_intr_allow_others(intr_handle))
5127 vec = E1000_RX_VEC_START;
5129 uint32_t mask = 1 << (queue_id + vec);
5132 regval = E1000_READ_REG(hw, E1000_EIMS);
5133 E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5134 E1000_WRITE_FLUSH(hw);
5136 rte_intr_enable(&dev->pci_dev->intr_handle);
5142 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
5143 uint8_t index, uint8_t offset)
5145 uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5148 val &= ~((uint32_t)0xFF << offset);
5150 /* write vector and valid bit */
5151 val |= (msix_vector | E1000_IVAR_VALID) << offset;
5153 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5157 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5158 uint8_t queue, uint8_t msix_vector)
5162 if (hw->mac.type == e1000_82575) {
5164 tmp = E1000_EICR_RX_QUEUE0 << queue;
5165 else if (direction == 1)
5166 tmp = E1000_EICR_TX_QUEUE0 << queue;
5167 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5168 } else if (hw->mac.type == e1000_82576) {
5169 if ((direction == 0) || (direction == 1))
5170 eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5171 ((queue & 0x8) << 1) +
5173 } else if ((hw->mac.type == e1000_82580) ||
5174 (hw->mac.type == e1000_i350) ||
5175 (hw->mac.type == e1000_i354) ||
5176 (hw->mac.type == e1000_i210) ||
5177 (hw->mac.type == e1000_i211)) {
5178 if ((direction == 0) || (direction == 1))
5179 eth_igb_write_ivar(hw, msix_vector,
5181 ((queue & 0x1) << 4) +
5186 /* Sets up the hardware to generate MSI-X interrupts properly
5188 * board private structure
5191 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5194 uint32_t tmpval, regval, intr_mask;
5195 struct e1000_hw *hw =
5196 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5197 uint32_t vec = E1000_MISC_VEC_ID;
5198 uint32_t base = E1000_MISC_VEC_ID;
5199 uint32_t misc_shift = 0;
5201 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5203 /* won't configure msix register if no mapping is done
5204 * between intr vector and event fd
5206 if (!rte_intr_dp_is_en(intr_handle))
5209 if (rte_intr_allow_others(intr_handle)) {
5210 vec = base = E1000_RX_VEC_START;
5214 /* set interrupt vector for other causes */
5215 if (hw->mac.type == e1000_82575) {
5216 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5217 /* enable MSI-X PBA support */
5218 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5220 /* Auto-Mask interrupts upon ICR read */
5221 tmpval |= E1000_CTRL_EXT_EIAME;
5222 tmpval |= E1000_CTRL_EXT_IRCA;
5224 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5226 /* enable msix_other interrupt */
5227 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5228 regval = E1000_READ_REG(hw, E1000_EIAC);
5229 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5230 regval = E1000_READ_REG(hw, E1000_EIAM);
5231 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5232 } else if ((hw->mac.type == e1000_82576) ||
5233 (hw->mac.type == e1000_82580) ||
5234 (hw->mac.type == e1000_i350) ||
5235 (hw->mac.type == e1000_i354) ||
5236 (hw->mac.type == e1000_i210) ||
5237 (hw->mac.type == e1000_i211)) {
5238 /* turn on MSI-X capability first */
5239 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5240 E1000_GPIE_PBA | E1000_GPIE_EIAME |
5242 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5244 regval = E1000_READ_REG(hw, E1000_EIAC);
5245 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5247 /* enable msix_other interrupt */
5248 regval = E1000_READ_REG(hw, E1000_EIMS);
5249 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5250 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5251 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5254 /* use EIAM to auto-mask when MSI-X interrupt
5255 * is asserted, this saves a register write for every interrupt
5257 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5259 regval = E1000_READ_REG(hw, E1000_EIAM);
5260 E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5262 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5263 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5264 intr_handle->intr_vec[queue_id] = vec;
5265 if (vec < base + intr_handle->nb_efd - 1)
5269 E1000_WRITE_FLUSH(hw);
5272 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd.pci_drv);
5273 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5274 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd.pci_drv);
5275 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);