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34 #ifndef _ENA_ETH_IO_H_
35 #define _ENA_ETH_IO_H_
37 /* Layer 3 protocol index */
38 enum ena_eth_io_l3_proto_index {
39 ENA_ETH_IO_L3_PROTO_UNKNOWN = 0,
41 ENA_ETH_IO_L3_PROTO_IPV4 = 8,
43 ENA_ETH_IO_L3_PROTO_IPV6 = 11,
45 ENA_ETH_IO_L3_PROTO_FCOE = 21,
47 ENA_ETH_IO_L3_PROTO_ROCE = 22,
50 /* Layer 4 protocol index */
51 enum ena_eth_io_l4_proto_index {
52 ENA_ETH_IO_L4_PROTO_UNKNOWN = 0,
54 ENA_ETH_IO_L4_PROTO_TCP = 12,
56 ENA_ETH_IO_L4_PROTO_UDP = 13,
58 ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23,
61 /* ENA IO Queue Tx descriptor */
62 struct ena_eth_io_tx_desc {
64 /* length, request id and control flags
65 * 15:0 : length - Buffer length in bytes, must
66 * include any packet trailers that the ENA supposed
67 * to update like End-to-End CRC, Authentication GMAC
68 * etc. This length must not include the
69 * 'Push_Buffer' length. This length must not include
70 * the 4-byte added in the end for 802.3 Ethernet FCS
71 * 21:16 : req_id_hi - Request ID[15:10]
72 * 22 : reserved22 - MBZ
73 * 23 : meta_desc - MBZ
75 * 25 : reserved1 - MBZ
76 * 26 : first - Indicates first descriptor in
78 * 27 : last - Indicates last descriptor in
80 * 28 : comp_req - Indicates whether completion
81 * should be posted, after packet is transmitted.
82 * Valid only for first descriptor
83 * 30:29 : reserved29 - MBZ
84 * 31 : reserved31 - MBZ
90 * 3:0 : l3_proto_idx - L3 protocol, if
91 * tunnel_ctrl[0] is set, then this is the inner
92 * packet L3. This field required when
93 * l3_csum_en,l3_csum or tso_en are set.
94 * 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and
95 * DF flags of the IPv4 header is 0. Otherwise must
98 * 7 : tso_en - Enable TSO, For TCP only. For packets
99 * with tunnel (tunnel_ctrl[0]=1), then the inner
100 * packet will be segmented while the outer tunnel is
102 * 12:8 : l4_proto_idx - L4 protocol, if
103 * tunnel_ctrl[0] is set, then this is the inner
104 * packet L4. This field need to be set when
105 * l4_csum_en or tso_en are set.
106 * 13 : l3_csum_en - enable IPv4 header checksum. if
107 * tunnel_ctrl[0] is set, then this will enable
108 * checksum for the inner packet IPv4
109 * 14 : l4_csum_en - enable TCP/UDP checksum. if
110 * tunnel_ctrl[0] is set, then this will enable
111 * checksum on the inner packet TCP/UDP checksum
112 * 15 : ethernet_fcs_dis - when set, the controller
113 * will not append the 802.3 Ethernet Frame Check
114 * Sequence to the packet
116 * 17 : l4_csum_partial - L4 partial checksum. when
117 * set to 0, the ENA calculates the L4 checksum,
118 * where the Destination Address required for the
119 * TCP/UDP pseudo-header is taken from the actual
120 * packet L3 header. when set to 1, the ENA doesn't
121 * calculate the sum of the pseudo-header, instead,
122 * the checksum field of the L4 is used instead. When
123 * TSO enabled, the checksum of the pseudo-header
124 * must not include the tcp length field. L4 partial
125 * checksum should be used for IPv6 packet that
126 * contains Routing Headers.
127 * 20:18 : tunnel_ctrl - Bit 0: tunneling exists, Bit
128 * 1: tunnel packet actually uses UDP as L4, Bit 2:
129 * tunnel packet L3 protocol: 0: IPv4 1: IPv6
130 * 21 : ts_req - Indicates that the packet is IEEE
131 * 1588v2 packet requiring the timestamp
132 * 31:22 : req_id_lo - Request ID[9:0]
136 /* word 2 : Buffer address bits[31:0] */
137 uint32_t buff_addr_lo;
140 /* address high and header size
141 * 15:0 : addr_hi - Buffer Pointer[47:32]
142 * 23:16 : reserved16_w2
143 * 31:24 : header_length - Header length. For Low
144 * Latency Queues, this fields indicates the number
145 * of bytes written to the headers' memory. For
146 * normal queues, if packet is TCP or UDP, and longer
147 * than max_header_size, then this field should be
148 * set to the sum of L4 header offset and L4 header
149 * size(without options), otherwise, this field
150 * should be set to 0. For both modes, this field
151 * must not exceed the max_header_size.
152 * max_header_size value is reported by the Max
153 * Queues Feature descriptor
155 uint32_t buff_addr_hi_hdr_sz;
158 /* ENA IO Queue Tx Meta descriptor */
159 struct ena_eth_io_tx_meta_desc {
161 /* length, request id and control flags
162 * 9:0 : req_id_lo - Request ID[9:0]
163 * 11:10 : outr_l3_off_hi - valid if
164 * tunnel_ctrl[0]=1. bits[4:3] of outer packet L3
166 * 12 : reserved12 - MBZ
167 * 13 : reserved13 - MBZ
168 * 14 : ext_valid - if set, offset fields in Word2
169 * are valid Also MSS High in Word 0 and Outer L3
170 * Offset High in WORD 0 and bits [31:24] in Word 3
171 * 15 : word3_valid - If set Crypto Info[23:0] of
174 * 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1:
175 * Extended Metadata Descriptor
176 * 21 : meta_store - Store extended metadata in queue
178 * 22 : reserved22 - MBZ
179 * 23 : meta_desc - MBO
181 * 25 : reserved25 - MBZ
182 * 26 : first - Indicates first descriptor in
184 * 27 : last - Indicates last descriptor in
186 * 28 : comp_req - Indicates whether completion
187 * should be posted, after packet is transmitted.
188 * Valid only for first descriptor
189 * 30:29 : reserved29 - MBZ
190 * 31 : reserved31 - MBZ
197 * 31:6 : reserved6 - MBZ
203 * 7:0 : l3_hdr_len - the header length L3 IP header.
204 * if tunnel_ctrl[0]=1, this is the IP header length
205 * of the inner packet. FIXME - check if includes IP
207 * 15:8 : l3_hdr_off - the offset of the first byte
208 * in the L3 header from the beginning of the to-be
209 * transmitted packet. if tunnel_ctrl[0]=1, this is
210 * the offset the L3 header of the inner packet
211 * 21:16 : l4_hdr_len_in_words - counts the L4 header
212 * length in words. there is an explicit assumption
213 * that L4 header appears right after L3 header and
214 * L4 offset is based on l3_hdr_off+l3_hdr_len FIXME
223 * 28:24 : outr_l3_hdr_len_words - valid if
224 * tunnel_ctrl[0]=1. Counts in words
225 * 31:29 : outr_l3_off_lo - valid if
226 * tunnel_ctrl[0]=1. bits[2:0] of outer packet L3
227 * offset. Counts the offset of the tunnel IP header
228 * from beginning of the packet. NOTE: if the tunnel
229 * header requires CRC or checksum, it is expected to
230 * be done by the driver as it is not done by the HW
235 /* ENA IO Queue Tx completions descriptor */
236 struct ena_eth_io_tx_cdesc {
238 /* Request ID[15:0] */
252 /* indicates location of submission queue head */
253 uint16_t sq_head_idx;
256 /* ENA IO Queue Rx descriptor */
257 struct ena_eth_io_rx_desc {
259 /* In bytes. 0 means 64KB */
267 * 1 : reserved1 - MBZ
268 * 2 : first - Indicates first descriptor in
270 * 3 : last - Indicates last descriptor in transaction
272 * 5 : reserved5 - MBO
273 * 7:6 : reserved6 - MBZ
283 /* word 2 : Buffer address bits[31:0] */
284 uint32_t buff_addr_lo;
287 /* Buffer Address bits[47:16] */
288 uint16_t buff_addr_hi;
291 uint16_t reserved16_w3;
294 /* ENA IO Queue Rx Completion Base Descriptor (4-word format). Note: all
295 * ethernet parsing information are valid only when last=1
297 struct ena_eth_io_rx_cdesc_base {
299 /* 4:0 : l3_proto_idx - L3 protocol index
300 * 6:5 : src_vlan_cnt - Source VLAN count
301 * 7 : tunnel - Tunnel exists
302 * 12:8 : l4_proto_idx - L4 protocol index
303 * 13 : l3_csum_err - when set, either the L3
304 * checksum error detected, or, the controller didn't
305 * validate the checksum, If tunnel exists, this
306 * result is for the inner packet. This bit is valid
307 * only when l3_proto_idx indicates IPv4 packet
308 * 14 : l4_csum_err - when set, either the L4
309 * checksum error detected, or, the controller didn't
310 * validate the checksum. If tunnel exists, this
311 * result is for the inner packet. This bit is valid
312 * only when l4_proto_idx indicates TCP/UDP packet,
313 * and, ipv4_frag is not set
314 * 15 : ipv4_frag - Indicates IPv4 fragmented packet
317 * 20 : secured_pkt - Set if packet was handled by
318 * inline crypto engine
319 * 22:21 : crypto_status - bit 0 secured direction:
320 * 0: decryption, 1: encryption. bit 1 reserved
323 * 25 : l3_csum2 - second checksum engine result
324 * 26 : first - Indicates first descriptor in
326 * 27 : last - Indicates last descriptor in
328 * 28 : inr_l4_csum - TCP/UDP checksum results for
331 * 30 : buffer - 0: Metadata descriptor. 1: Buffer
332 * Descriptor was used
342 /* word 2 : 32-bit hash result */
346 /* submission queue number */
352 /* ENA IO Queue Rx Completion Descriptor (8-word format) */
353 struct ena_eth_io_rx_cdesc_ext {
354 /* words 0:3 : Rx Completion Extended */
355 struct ena_eth_io_rx_cdesc_base base;
357 /* word 4 : Completed Buffer address bits[31:0] */
358 uint32_t buff_addr_lo;
361 /* the buffer address used bits[47:32] */
362 uint16_t buff_addr_hi;
366 /* word 6 : Reserved */
367 uint32_t reserved_w6;
369 /* word 7 : Reserved */
370 uint32_t reserved_w7;
373 /* ENA Interrupt Unmask Register */
374 struct ena_eth_io_intr_reg {
376 /* 14:0 : rx_intr_delay - rx interrupt delay value
377 * 29:15 : tx_intr_delay - tx interrupt delay value
378 * 30 : intr_unmask - if set, unmasks interrupt
381 uint32_t intr_control;
385 #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
386 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
387 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
388 #define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23
389 #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
390 #define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24
391 #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
392 #define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26
393 #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
394 #define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27
395 #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
396 #define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28
397 #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
398 #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
399 #define ENA_ETH_IO_TX_DESC_DF_SHIFT 4
400 #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
401 #define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7
402 #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
403 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8
404 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
405 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13
406 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)
407 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14
408 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)
409 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15
410 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
411 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
412 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
413 #define ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_SHIFT 18
414 #define ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_MASK GENMASK(20, 18)
415 #define ENA_ETH_IO_TX_DESC_TS_REQ_SHIFT 21
416 #define ENA_ETH_IO_TX_DESC_TS_REQ_MASK BIT(21)
417 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
418 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
419 #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
420 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24
421 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
424 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
425 #define ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_SHIFT 10
426 #define ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_MASK GENMASK(11, 10)
427 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
428 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
429 #define ENA_ETH_IO_TX_META_DESC_WORD3_VALID_SHIFT 15
430 #define ENA_ETH_IO_TX_META_DESC_WORD3_VALID_MASK BIT(15)
431 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_SHIFT 16
432 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_MASK GENMASK(19, 16)
433 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20
434 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)
435 #define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21
436 #define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)
437 #define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23
438 #define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)
439 #define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24
440 #define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)
441 #define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26
442 #define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)
443 #define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27
444 #define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)
445 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28
446 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)
447 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
448 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
449 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8
450 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
451 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16
452 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
453 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
454 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
455 #define ENA_ETH_IO_TX_META_DESC_CRYPTO_INFO_MASK GENMASK(23, 0)
456 #define ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_SHIFT 24
457 #define ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_MASK GENMASK(28, 24)
458 #define ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_SHIFT 29
459 #define ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_MASK GENMASK(31, 29)
462 #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
465 #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
466 #define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2
467 #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
468 #define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3
469 #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
470 #define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4
471 #define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)
474 #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
475 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
476 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
477 #define ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_SHIFT 7
478 #define ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_MASK BIT(7)
479 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
480 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
481 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
482 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)
483 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14
484 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
485 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
486 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
487 #define ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_SHIFT 20
488 #define ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_MASK BIT(20)
489 #define ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_SHIFT 21
490 #define ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_MASK GENMASK(22, 21)
491 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
492 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
493 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
494 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)
495 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26
496 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
497 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
498 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
499 #define ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_SHIFT 28
500 #define ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_MASK BIT(28)
501 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
502 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
505 #define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)
506 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15
507 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)
508 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
509 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
511 #if !defined(ENA_DEFS_LINUX_MAINLINE)
512 static inline uint32_t get_ena_eth_io_tx_desc_length(
513 const struct ena_eth_io_tx_desc *p)
515 return p->len_ctrl & ENA_ETH_IO_TX_DESC_LENGTH_MASK;
518 static inline void set_ena_eth_io_tx_desc_length(
519 struct ena_eth_io_tx_desc *p,
522 p->len_ctrl |= val & ENA_ETH_IO_TX_DESC_LENGTH_MASK;
525 static inline uint32_t get_ena_eth_io_tx_desc_req_id_hi(
526 const struct ena_eth_io_tx_desc *p)
528 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK)
529 >> ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT;
532 static inline void set_ena_eth_io_tx_desc_req_id_hi(
533 struct ena_eth_io_tx_desc *p,
537 (val << ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT)
538 & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK;
541 static inline uint32_t get_ena_eth_io_tx_desc_meta_desc(
542 const struct ena_eth_io_tx_desc *p)
544 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_META_DESC_MASK)
545 >> ENA_ETH_IO_TX_DESC_META_DESC_SHIFT;
548 static inline void set_ena_eth_io_tx_desc_meta_desc(
549 struct ena_eth_io_tx_desc *p,
553 (val << ENA_ETH_IO_TX_DESC_META_DESC_SHIFT)
554 & ENA_ETH_IO_TX_DESC_META_DESC_MASK;
557 static inline uint32_t get_ena_eth_io_tx_desc_phase(
558 const struct ena_eth_io_tx_desc *p)
560 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_PHASE_MASK)
561 >> ENA_ETH_IO_TX_DESC_PHASE_SHIFT;
564 static inline void set_ena_eth_io_tx_desc_phase(
565 struct ena_eth_io_tx_desc *p,
569 (val << ENA_ETH_IO_TX_DESC_PHASE_SHIFT)
570 & ENA_ETH_IO_TX_DESC_PHASE_MASK;
573 static inline uint32_t get_ena_eth_io_tx_desc_first(
574 const struct ena_eth_io_tx_desc *p)
576 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_FIRST_MASK)
577 >> ENA_ETH_IO_TX_DESC_FIRST_SHIFT;
580 static inline void set_ena_eth_io_tx_desc_first(
581 struct ena_eth_io_tx_desc *p,
585 (val << ENA_ETH_IO_TX_DESC_FIRST_SHIFT)
586 & ENA_ETH_IO_TX_DESC_FIRST_MASK;
589 static inline uint32_t get_ena_eth_io_tx_desc_last(
590 const struct ena_eth_io_tx_desc *p)
592 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_LAST_MASK)
593 >> ENA_ETH_IO_TX_DESC_LAST_SHIFT;
596 static inline void set_ena_eth_io_tx_desc_last(
597 struct ena_eth_io_tx_desc *p,
601 (val << ENA_ETH_IO_TX_DESC_LAST_SHIFT)
602 & ENA_ETH_IO_TX_DESC_LAST_MASK;
605 static inline uint32_t get_ena_eth_io_tx_desc_comp_req(
606 const struct ena_eth_io_tx_desc *p)
608 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK)
609 >> ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT;
612 static inline void set_ena_eth_io_tx_desc_comp_req(
613 struct ena_eth_io_tx_desc *p,
617 (val << ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT)
618 & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK;
621 static inline uint32_t get_ena_eth_io_tx_desc_l3_proto_idx(
622 const struct ena_eth_io_tx_desc *p)
624 return p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK;
627 static inline void set_ena_eth_io_tx_desc_l3_proto_idx(
628 struct ena_eth_io_tx_desc *p,
631 p->meta_ctrl |= val & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK;
634 static inline uint32_t get_ena_eth_io_tx_desc_DF(
635 const struct ena_eth_io_tx_desc *p)
637 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_DF_MASK)
638 >> ENA_ETH_IO_TX_DESC_DF_SHIFT;
641 static inline void set_ena_eth_io_tx_desc_DF(
642 struct ena_eth_io_tx_desc *p,
646 (val << ENA_ETH_IO_TX_DESC_DF_SHIFT)
647 & ENA_ETH_IO_TX_DESC_DF_MASK;
650 static inline uint32_t get_ena_eth_io_tx_desc_tso_en(
651 const struct ena_eth_io_tx_desc *p)
653 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TSO_EN_MASK)
654 >> ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT;
657 static inline void set_ena_eth_io_tx_desc_tso_en(
658 struct ena_eth_io_tx_desc *p,
662 (val << ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT)
663 & ENA_ETH_IO_TX_DESC_TSO_EN_MASK;
666 static inline uint32_t get_ena_eth_io_tx_desc_l4_proto_idx(
667 const struct ena_eth_io_tx_desc *p)
669 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK)
670 >> ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT;
673 static inline void set_ena_eth_io_tx_desc_l4_proto_idx(
674 struct ena_eth_io_tx_desc *p,
678 (val << ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT)
679 & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK;
682 static inline uint32_t get_ena_eth_io_tx_desc_l3_csum_en(
683 const struct ena_eth_io_tx_desc *p)
685 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK)
686 >> ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT;
689 static inline void set_ena_eth_io_tx_desc_l3_csum_en(
690 struct ena_eth_io_tx_desc *p,
694 (val << ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT)
695 & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK;
698 static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_en(
699 const struct ena_eth_io_tx_desc *p)
701 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK)
702 >> ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT;
705 static inline void set_ena_eth_io_tx_desc_l4_csum_en(
706 struct ena_eth_io_tx_desc *p,
710 (val << ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT)
711 & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK;
714 static inline uint32_t get_ena_eth_io_tx_desc_ethernet_fcs_dis(
715 const struct ena_eth_io_tx_desc *p)
717 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK)
718 >> ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT;
721 static inline void set_ena_eth_io_tx_desc_ethernet_fcs_dis(
722 struct ena_eth_io_tx_desc *p,
726 (val << ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT)
727 & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK;
730 static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_partial(
731 const struct ena_eth_io_tx_desc *p)
733 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK)
734 >> ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT;
737 static inline void set_ena_eth_io_tx_desc_l4_csum_partial(
738 struct ena_eth_io_tx_desc *p,
742 (val << ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT)
743 & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK;
746 static inline uint32_t get_ena_eth_io_tx_desc_tunnel_ctrl(
747 const struct ena_eth_io_tx_desc *p)
749 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_MASK)
750 >> ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_SHIFT;
753 static inline void set_ena_eth_io_tx_desc_tunnel_ctrl(
754 struct ena_eth_io_tx_desc *p,
758 (val << ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_SHIFT)
759 & ENA_ETH_IO_TX_DESC_TUNNEL_CTRL_MASK;
762 static inline uint32_t get_ena_eth_io_tx_desc_ts_req(
763 const struct ena_eth_io_tx_desc *p)
765 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TS_REQ_MASK)
766 >> ENA_ETH_IO_TX_DESC_TS_REQ_SHIFT;
769 static inline void set_ena_eth_io_tx_desc_ts_req(
770 struct ena_eth_io_tx_desc *p,
774 (val << ENA_ETH_IO_TX_DESC_TS_REQ_SHIFT)
775 & ENA_ETH_IO_TX_DESC_TS_REQ_MASK;
778 static inline uint32_t get_ena_eth_io_tx_desc_req_id_lo(
779 const struct ena_eth_io_tx_desc *p)
781 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK)
782 >> ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT;
785 static inline void set_ena_eth_io_tx_desc_req_id_lo(
786 struct ena_eth_io_tx_desc *p,
790 (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT)
791 & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK;
794 static inline uint32_t get_ena_eth_io_tx_desc_addr_hi(
795 const struct ena_eth_io_tx_desc *p)
797 return p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK;
800 static inline void set_ena_eth_io_tx_desc_addr_hi(
801 struct ena_eth_io_tx_desc *p,
804 p->buff_addr_hi_hdr_sz |= val & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK;
807 static inline uint32_t get_ena_eth_io_tx_desc_header_length(
808 const struct ena_eth_io_tx_desc *p)
810 return (p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK)
811 >> ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT;
814 static inline void set_ena_eth_io_tx_desc_header_length(
815 struct ena_eth_io_tx_desc *p,
818 p->buff_addr_hi_hdr_sz |=
819 (val << ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT)
820 & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK;
823 static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_lo(
824 const struct ena_eth_io_tx_meta_desc *p)
826 return p->len_ctrl & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK;
829 static inline void set_ena_eth_io_tx_meta_desc_req_id_lo(
830 struct ena_eth_io_tx_meta_desc *p,
833 p->len_ctrl |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK;
836 static inline uint32_t get_ena_eth_io_tx_meta_desc_outr_l3_off_hi(
837 const struct ena_eth_io_tx_meta_desc *p)
839 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_MASK)
840 >> ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_SHIFT;
843 static inline void set_ena_eth_io_tx_meta_desc_outr_l3_off_hi(
844 struct ena_eth_io_tx_meta_desc *p,
848 (val << ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_SHIFT)
849 & ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_HI_MASK;
852 static inline uint32_t get_ena_eth_io_tx_meta_desc_ext_valid(
853 const struct ena_eth_io_tx_meta_desc *p)
855 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK)
856 >> ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT;
859 static inline void set_ena_eth_io_tx_meta_desc_ext_valid(
860 struct ena_eth_io_tx_meta_desc *p,
864 (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT)
865 & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK;
868 static inline uint32_t get_ena_eth_io_tx_meta_desc_word3_valid(
869 const struct ena_eth_io_tx_meta_desc *p)
871 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_WORD3_VALID_MASK)
872 >> ENA_ETH_IO_TX_META_DESC_WORD3_VALID_SHIFT;
875 static inline void set_ena_eth_io_tx_meta_desc_word3_valid(
876 struct ena_eth_io_tx_meta_desc *p,
880 (val << ENA_ETH_IO_TX_META_DESC_WORD3_VALID_SHIFT)
881 & ENA_ETH_IO_TX_META_DESC_WORD3_VALID_MASK;
884 static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_hi_ptp(
885 const struct ena_eth_io_tx_meta_desc *p)
887 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_MASK)
888 >> ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_SHIFT;
891 static inline void set_ena_eth_io_tx_meta_desc_mss_hi_ptp(
892 struct ena_eth_io_tx_meta_desc *p,
896 (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_SHIFT)
897 & ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_MASK;
900 static inline uint32_t get_ena_eth_io_tx_meta_desc_eth_meta_type(
901 const struct ena_eth_io_tx_meta_desc *p)
903 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK)
904 >> ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT;
907 static inline void set_ena_eth_io_tx_meta_desc_eth_meta_type(
908 struct ena_eth_io_tx_meta_desc *p,
912 (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT)
913 & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;
916 static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_store(
917 const struct ena_eth_io_tx_meta_desc *p)
919 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK)
920 >> ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT;
923 static inline void set_ena_eth_io_tx_meta_desc_meta_store(
924 struct ena_eth_io_tx_meta_desc *p,
928 (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT)
929 & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK;
932 static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_desc(
933 const struct ena_eth_io_tx_meta_desc *p)
935 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK)
936 >> ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT;
939 static inline void set_ena_eth_io_tx_meta_desc_meta_desc(
940 struct ena_eth_io_tx_meta_desc *p,
944 (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT)
945 & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK;
948 static inline uint32_t get_ena_eth_io_tx_meta_desc_phase(
949 const struct ena_eth_io_tx_meta_desc *p)
951 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_PHASE_MASK)
952 >> ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT;
955 static inline void set_ena_eth_io_tx_meta_desc_phase(
956 struct ena_eth_io_tx_meta_desc *p,
960 (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT)
961 & ENA_ETH_IO_TX_META_DESC_PHASE_MASK;
964 static inline uint32_t get_ena_eth_io_tx_meta_desc_first(
965 const struct ena_eth_io_tx_meta_desc *p)
967 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_FIRST_MASK)
968 >> ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT;
971 static inline void set_ena_eth_io_tx_meta_desc_first(
972 struct ena_eth_io_tx_meta_desc *p,
976 (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT)
977 & ENA_ETH_IO_TX_META_DESC_FIRST_MASK;
980 static inline uint32_t get_ena_eth_io_tx_meta_desc_last(
981 const struct ena_eth_io_tx_meta_desc *p)
983 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_LAST_MASK)
984 >> ENA_ETH_IO_TX_META_DESC_LAST_SHIFT;
987 static inline void set_ena_eth_io_tx_meta_desc_last(
988 struct ena_eth_io_tx_meta_desc *p,
992 (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT)
993 & ENA_ETH_IO_TX_META_DESC_LAST_MASK;
996 static inline uint32_t get_ena_eth_io_tx_meta_desc_comp_req(
997 const struct ena_eth_io_tx_meta_desc *p)
999 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK)
1000 >> ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT;
1003 static inline void set_ena_eth_io_tx_meta_desc_comp_req(
1004 struct ena_eth_io_tx_meta_desc *p,
1008 (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT)
1009 & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK;
1012 static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_hi(
1013 const struct ena_eth_io_tx_meta_desc *p)
1015 return p->word1 & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK;
1018 static inline void set_ena_eth_io_tx_meta_desc_req_id_hi(
1019 struct ena_eth_io_tx_meta_desc *p,
1022 p->word1 |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK;
1025 static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_len(
1026 const struct ena_eth_io_tx_meta_desc *p)
1028 return p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK;
1031 static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_len(
1032 struct ena_eth_io_tx_meta_desc *p,
1035 p->word2 |= val & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK;
1038 static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_off(
1039 const struct ena_eth_io_tx_meta_desc *p)
1041 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK)
1042 >> ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT;
1045 static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_off(
1046 struct ena_eth_io_tx_meta_desc *p,
1050 (val << ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT)
1051 & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK;
1054 static inline uint32_t get_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(
1055 const struct ena_eth_io_tx_meta_desc *p)
1057 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK)
1058 >> ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT;
1061 static inline void set_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(
1062 struct ena_eth_io_tx_meta_desc *p,
1066 (val << ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT)
1067 & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK;
1070 static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_lo(
1071 const struct ena_eth_io_tx_meta_desc *p)
1073 return (p->word2 & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK)
1074 >> ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT;
1077 static inline void set_ena_eth_io_tx_meta_desc_mss_lo(
1078 struct ena_eth_io_tx_meta_desc *p,
1082 (val << ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT)
1083 & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;
1086 static inline uint32_t get_ena_eth_io_tx_meta_desc_crypto_info(
1087 const struct ena_eth_io_tx_meta_desc *p)
1089 return p->word3 & ENA_ETH_IO_TX_META_DESC_CRYPTO_INFO_MASK;
1092 static inline void set_ena_eth_io_tx_meta_desc_crypto_info(
1093 struct ena_eth_io_tx_meta_desc *p,
1096 p->word3 |= val & ENA_ETH_IO_TX_META_DESC_CRYPTO_INFO_MASK;
1099 static inline uint32_t get_ena_eth_io_tx_meta_desc_outr_l3_hdr_len_words(
1100 const struct ena_eth_io_tx_meta_desc *p)
1102 return (p->word3 & ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_MASK)
1103 >> ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_SHIFT;
1106 static inline void set_ena_eth_io_tx_meta_desc_outr_l3_hdr_len_words(
1107 struct ena_eth_io_tx_meta_desc *p,
1111 (val << ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_SHIFT)
1112 & ENA_ETH_IO_TX_META_DESC_OUTR_L3_HDR_LEN_WORDS_MASK;
1115 static inline uint32_t get_ena_eth_io_tx_meta_desc_outr_l3_off_lo(
1116 const struct ena_eth_io_tx_meta_desc *p)
1118 return (p->word3 & ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_MASK)
1119 >> ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_SHIFT;
1122 static inline void set_ena_eth_io_tx_meta_desc_outr_l3_off_lo(
1123 struct ena_eth_io_tx_meta_desc *p,
1127 (val << ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_SHIFT)
1128 & ENA_ETH_IO_TX_META_DESC_OUTR_L3_OFF_LO_MASK;
1131 static inline uint8_t get_ena_eth_io_tx_cdesc_phase(
1132 const struct ena_eth_io_tx_cdesc *p)
1134 return p->flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
1137 static inline void set_ena_eth_io_tx_cdesc_phase(
1138 struct ena_eth_io_tx_cdesc *p,
1141 p->flags |= val & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
1144 static inline uint8_t get_ena_eth_io_rx_desc_phase(
1145 const struct ena_eth_io_rx_desc *p)
1147 return p->ctrl & ENA_ETH_IO_RX_DESC_PHASE_MASK;
1150 static inline void set_ena_eth_io_rx_desc_phase(
1151 struct ena_eth_io_rx_desc *p,
1154 p->ctrl |= val & ENA_ETH_IO_RX_DESC_PHASE_MASK;
1157 static inline uint8_t get_ena_eth_io_rx_desc_first(
1158 const struct ena_eth_io_rx_desc *p)
1160 return (p->ctrl & ENA_ETH_IO_RX_DESC_FIRST_MASK)
1161 >> ENA_ETH_IO_RX_DESC_FIRST_SHIFT;
1164 static inline void set_ena_eth_io_rx_desc_first(
1165 struct ena_eth_io_rx_desc *p,
1169 (val << ENA_ETH_IO_RX_DESC_FIRST_SHIFT)
1170 & ENA_ETH_IO_RX_DESC_FIRST_MASK;
1173 static inline uint8_t get_ena_eth_io_rx_desc_last(
1174 const struct ena_eth_io_rx_desc *p)
1176 return (p->ctrl & ENA_ETH_IO_RX_DESC_LAST_MASK)
1177 >> ENA_ETH_IO_RX_DESC_LAST_SHIFT;
1180 static inline void set_ena_eth_io_rx_desc_last(
1181 struct ena_eth_io_rx_desc *p,
1185 (val << ENA_ETH_IO_RX_DESC_LAST_SHIFT)
1186 & ENA_ETH_IO_RX_DESC_LAST_MASK;
1189 static inline uint8_t get_ena_eth_io_rx_desc_comp_req(
1190 const struct ena_eth_io_rx_desc *p)
1192 return (p->ctrl & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK)
1193 >> ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT;
1196 static inline void set_ena_eth_io_rx_desc_comp_req(
1197 struct ena_eth_io_rx_desc *p,
1201 (val << ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT)
1202 & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;
1205 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_proto_idx(
1206 const struct ena_eth_io_rx_cdesc_base *p)
1208 return p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;
1211 static inline void set_ena_eth_io_rx_cdesc_base_l3_proto_idx(
1212 struct ena_eth_io_rx_cdesc_base *p,
1215 p->status |= val & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;
1218 static inline uint32_t get_ena_eth_io_rx_cdesc_base_src_vlan_cnt(
1219 const struct ena_eth_io_rx_cdesc_base *p)
1221 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK)
1222 >> ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT;
1225 static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(
1226 struct ena_eth_io_rx_cdesc_base *p,
1230 (val << ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT)
1231 & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK;
1234 static inline uint32_t get_ena_eth_io_rx_cdesc_base_tunnel(
1235 const struct ena_eth_io_rx_cdesc_base *p)
1237 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_MASK)
1238 >> ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_SHIFT;
1241 static inline void set_ena_eth_io_rx_cdesc_base_tunnel(
1242 struct ena_eth_io_rx_cdesc_base *p,
1246 (val << ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_SHIFT)
1247 & ENA_ETH_IO_RX_CDESC_BASE_TUNNEL_MASK;
1250 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(
1251 const struct ena_eth_io_rx_cdesc_base *p)
1253 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK)
1254 >> ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT;
1257 static inline void set_ena_eth_io_rx_cdesc_base_l4_proto_idx(
1258 struct ena_eth_io_rx_cdesc_base *p,
1262 (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT)
1263 & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK;
1266 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum_err(
1267 const struct ena_eth_io_rx_cdesc_base *p)
1269 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK)
1270 >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT;
1273 static inline void set_ena_eth_io_rx_cdesc_base_l3_csum_err(
1274 struct ena_eth_io_rx_cdesc_base *p,
1278 (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT)
1279 & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK;
1282 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_err(
1283 const struct ena_eth_io_rx_cdesc_base *p)
1285 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK)
1286 >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT;
1289 static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_err(
1290 struct ena_eth_io_rx_cdesc_base *p,
1294 (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT)
1295 & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK;
1298 static inline uint32_t get_ena_eth_io_rx_cdesc_base_ipv4_frag(
1299 const struct ena_eth_io_rx_cdesc_base *p)
1301 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK)
1302 >> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT;
1305 static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(
1306 struct ena_eth_io_rx_cdesc_base *p,
1310 (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT)
1311 & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK;
1314 static inline uint32_t get_ena_eth_io_rx_cdesc_base_secured_pkt(
1315 const struct ena_eth_io_rx_cdesc_base *p)
1317 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_MASK)
1318 >> ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_SHIFT;
1321 static inline void set_ena_eth_io_rx_cdesc_base_secured_pkt(
1322 struct ena_eth_io_rx_cdesc_base *p,
1326 (val << ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_SHIFT)
1327 & ENA_ETH_IO_RX_CDESC_BASE_SECURED_PKT_MASK;
1330 static inline uint32_t get_ena_eth_io_rx_cdesc_base_crypto_status(
1331 const struct ena_eth_io_rx_cdesc_base *p)
1333 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_MASK)
1334 >> ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_SHIFT;
1337 static inline void set_ena_eth_io_rx_cdesc_base_crypto_status(
1338 struct ena_eth_io_rx_cdesc_base *p,
1342 (val << ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_SHIFT)
1343 & ENA_ETH_IO_RX_CDESC_BASE_CRYPTO_STATUS_MASK;
1346 static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(
1347 const struct ena_eth_io_rx_cdesc_base *p)
1349 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK)
1350 >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;
1353 static inline void set_ena_eth_io_rx_cdesc_base_phase(
1354 struct ena_eth_io_rx_cdesc_base *p,
1358 (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT)
1359 & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK;
1362 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum2(
1363 const struct ena_eth_io_rx_cdesc_base *p)
1365 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK)
1366 >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT;
1369 static inline void set_ena_eth_io_rx_cdesc_base_l3_csum2(
1370 struct ena_eth_io_rx_cdesc_base *p,
1374 (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT)
1375 & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK;
1378 static inline uint32_t get_ena_eth_io_rx_cdesc_base_first(
1379 const struct ena_eth_io_rx_cdesc_base *p)
1381 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK)
1382 >> ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT;
1385 static inline void set_ena_eth_io_rx_cdesc_base_first(
1386 struct ena_eth_io_rx_cdesc_base *p,
1390 (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT)
1391 & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK;
1394 static inline uint32_t get_ena_eth_io_rx_cdesc_base_last(
1395 const struct ena_eth_io_rx_cdesc_base *p)
1397 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK)
1398 >> ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT;
1401 static inline void set_ena_eth_io_rx_cdesc_base_last(
1402 struct ena_eth_io_rx_cdesc_base *p,
1406 (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT)
1407 & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK;
1410 static inline uint32_t get_ena_eth_io_rx_cdesc_base_inr_l4_csum(
1411 const struct ena_eth_io_rx_cdesc_base *p)
1413 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_MASK)
1414 >> ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_SHIFT;
1417 static inline void set_ena_eth_io_rx_cdesc_base_inr_l4_csum(
1418 struct ena_eth_io_rx_cdesc_base *p,
1422 (val << ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_SHIFT)
1423 & ENA_ETH_IO_RX_CDESC_BASE_INR_L4_CSUM_MASK;
1426 static inline uint32_t get_ena_eth_io_rx_cdesc_base_buffer(
1427 const struct ena_eth_io_rx_cdesc_base *p)
1429 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK)
1430 >> ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT;
1433 static inline void set_ena_eth_io_rx_cdesc_base_buffer(
1434 struct ena_eth_io_rx_cdesc_base *p,
1438 (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT)
1439 & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK;
1442 static inline uint32_t get_ena_eth_io_intr_reg_rx_intr_delay(
1443 const struct ena_eth_io_intr_reg *p)
1445 return p->intr_control & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
1448 static inline void set_ena_eth_io_intr_reg_rx_intr_delay(
1449 struct ena_eth_io_intr_reg *p,
1452 p->intr_control |= val & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
1455 static inline uint32_t get_ena_eth_io_intr_reg_tx_intr_delay(
1456 const struct ena_eth_io_intr_reg *p)
1458 return (p->intr_control & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK)
1459 >> ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT;
1462 static inline void set_ena_eth_io_intr_reg_tx_intr_delay(
1463 struct ena_eth_io_intr_reg *p,
1467 (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)
1468 & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
1471 static inline uint32_t get_ena_eth_io_intr_reg_intr_unmask(
1472 const struct ena_eth_io_intr_reg *p)
1474 return (p->intr_control & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK)
1475 >> ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT;
1478 static inline void set_ena_eth_io_intr_reg_intr_unmask(
1479 struct ena_eth_io_intr_reg *p,
1483 (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT)
1484 & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
1487 #endif /* !defined(ENA_DEFS_LINUX_MAINLINE) */
1488 #endif /*_ENA_ETH_IO_H_ */