4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_ether.h>
35 #include <rte_ethdev.h>
37 #include <rte_atomic.h>
39 #include <rte_errno.h>
40 #include <rte_version.h>
41 #include <rte_eal_memconfig.h>
43 #include "ena_ethdev.h"
45 #include "ena_platform.h"
47 #include "ena_eth_com.h"
49 #include <ena_common_defs.h>
50 #include <ena_regs_defs.h>
51 #include <ena_admin_defs.h>
52 #include <ena_eth_io_defs.h>
54 #define DRV_MODULE_VER_MAJOR 1
55 #define DRV_MODULE_VER_MINOR 0
56 #define DRV_MODULE_VER_SUBMINOR 0
58 #define ENA_IO_TXQ_IDX(q) (2 * (q))
59 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
60 /*reverse version of ENA_IO_RXQ_IDX*/
61 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
63 /* While processing submitted and completed descriptors (rx and tx path
64 * respectively) in a loop it is desired to:
65 * - perform batch submissions while populating sumbissmion queue
66 * - avoid blocking transmission of other packets during cleanup phase
67 * Hence the utilization ratio of 1/8 of a queue size.
69 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
71 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
72 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
74 #define GET_L4_HDR_LEN(mbuf) \
75 ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, \
76 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
78 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
79 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
80 #define ENA_HASH_KEY_SIZE 40
81 #define ENA_ETH_SS_STATS 0xFF
82 #define ETH_GSTRING_LEN 32
84 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
86 enum ethtool_stringset {
92 char name[ETH_GSTRING_LEN];
96 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
98 .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
101 #define ENA_STAT_ENTRY(stat, stat_type) { \
103 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
106 #define ENA_STAT_RX_ENTRY(stat) \
107 ENA_STAT_ENTRY(stat, rx)
109 #define ENA_STAT_TX_ENTRY(stat) \
110 ENA_STAT_ENTRY(stat, tx)
112 #define ENA_STAT_GLOBAL_ENTRY(stat) \
113 ENA_STAT_ENTRY(stat, dev)
115 static const struct ena_stats ena_stats_global_strings[] = {
116 ENA_STAT_GLOBAL_ENTRY(tx_timeout),
117 ENA_STAT_GLOBAL_ENTRY(io_suspend),
118 ENA_STAT_GLOBAL_ENTRY(io_resume),
119 ENA_STAT_GLOBAL_ENTRY(wd_expired),
120 ENA_STAT_GLOBAL_ENTRY(interface_up),
121 ENA_STAT_GLOBAL_ENTRY(interface_down),
122 ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
125 static const struct ena_stats ena_stats_tx_strings[] = {
126 ENA_STAT_TX_ENTRY(cnt),
127 ENA_STAT_TX_ENTRY(bytes),
128 ENA_STAT_TX_ENTRY(queue_stop),
129 ENA_STAT_TX_ENTRY(queue_wakeup),
130 ENA_STAT_TX_ENTRY(dma_mapping_err),
131 ENA_STAT_TX_ENTRY(linearize),
132 ENA_STAT_TX_ENTRY(linearize_failed),
133 ENA_STAT_TX_ENTRY(tx_poll),
134 ENA_STAT_TX_ENTRY(doorbells),
135 ENA_STAT_TX_ENTRY(prepare_ctx_err),
136 ENA_STAT_TX_ENTRY(missing_tx_comp),
137 ENA_STAT_TX_ENTRY(bad_req_id),
140 static const struct ena_stats ena_stats_rx_strings[] = {
141 ENA_STAT_RX_ENTRY(cnt),
142 ENA_STAT_RX_ENTRY(bytes),
143 ENA_STAT_RX_ENTRY(refil_partial),
144 ENA_STAT_RX_ENTRY(bad_csum),
145 ENA_STAT_RX_ENTRY(page_alloc_fail),
146 ENA_STAT_RX_ENTRY(skb_alloc_fail),
147 ENA_STAT_RX_ENTRY(dma_mapping_err),
148 ENA_STAT_RX_ENTRY(bad_desc_num),
149 ENA_STAT_RX_ENTRY(small_copy_len_pkt),
152 static const struct ena_stats ena_stats_ena_com_strings[] = {
153 ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
154 ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
155 ENA_STAT_ENA_COM_ENTRY(completed_cmd),
156 ENA_STAT_ENA_COM_ENTRY(out_of_space),
157 ENA_STAT_ENA_COM_ENTRY(no_completion),
160 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
161 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
162 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
163 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
165 /** Vendor ID used by Amazon devices */
166 #define PCI_VENDOR_ID_AMAZON 0x1D0F
167 /** Amazon devices */
168 #define PCI_DEVICE_ID_ENA_VF 0xEC20
169 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
171 static struct rte_pci_id pci_id_ena_map[] = {
172 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
173 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
177 static int ena_device_init(struct ena_com_dev *ena_dev,
178 struct ena_com_dev_get_features_ctx *get_feat_ctx);
179 static int ena_dev_configure(struct rte_eth_dev *dev);
180 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
182 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
183 uint16_t nb_desc, unsigned int socket_id,
184 const struct rte_eth_txconf *tx_conf);
185 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
186 uint16_t nb_desc, unsigned int socket_id,
187 const struct rte_eth_rxconf *rx_conf,
188 struct rte_mempool *mp);
189 static uint16_t eth_ena_recv_pkts(void *rx_queue,
190 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
191 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
192 static void ena_init_rings(struct ena_adapter *adapter);
193 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
194 static int ena_start(struct rte_eth_dev *dev);
195 static void ena_close(struct rte_eth_dev *dev);
196 static void ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
197 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
198 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
199 static void ena_rx_queue_release(void *queue);
200 static void ena_tx_queue_release(void *queue);
201 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
202 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
203 static int ena_link_update(struct rte_eth_dev *dev,
204 __rte_unused int wait_to_complete);
205 static int ena_queue_restart(struct ena_ring *ring);
206 static int ena_queue_restart_all(struct rte_eth_dev *dev,
207 enum ena_ring_type ring_type);
208 static void ena_stats_restart(struct rte_eth_dev *dev);
209 static void ena_infos_get(__rte_unused struct rte_eth_dev *dev,
210 struct rte_eth_dev_info *dev_info);
211 static int ena_rss_reta_update(struct rte_eth_dev *dev,
212 struct rte_eth_rss_reta_entry64 *reta_conf,
214 static int ena_rss_reta_query(struct rte_eth_dev *dev,
215 struct rte_eth_rss_reta_entry64 *reta_conf,
217 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
219 static struct eth_dev_ops ena_dev_ops = {
220 .dev_configure = ena_dev_configure,
221 .dev_infos_get = ena_infos_get,
222 .rx_queue_setup = ena_rx_queue_setup,
223 .tx_queue_setup = ena_tx_queue_setup,
224 .dev_start = ena_start,
225 .link_update = ena_link_update,
226 .stats_get = ena_stats_get,
227 .mtu_set = ena_mtu_set,
228 .rx_queue_release = ena_rx_queue_release,
229 .tx_queue_release = ena_tx_queue_release,
230 .dev_close = ena_close,
231 .reta_update = ena_rss_reta_update,
232 .reta_query = ena_rss_reta_query,
235 #define NUMA_NO_NODE SOCKET_ID_ANY
237 static inline int ena_cpu_to_node(int cpu)
239 struct rte_config *config = rte_eal_get_configuration();
241 if (likely(cpu < RTE_MAX_MEMZONE))
242 return config->mem_config->memzone[cpu].socket_id;
247 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
248 struct ena_com_rx_ctx *ena_rx_ctx)
250 uint64_t ol_flags = 0;
251 uint32_t packet_type = 0;
253 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
254 packet_type |= RTE_PTYPE_L4_TCP;
255 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
256 packet_type |= RTE_PTYPE_L4_UDP;
258 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
259 packet_type |= RTE_PTYPE_L3_IPV4;
260 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
261 packet_type |= RTE_PTYPE_L3_IPV6;
263 if (unlikely(ena_rx_ctx->l4_csum_err))
264 ol_flags |= PKT_RX_L4_CKSUM_BAD;
265 if (unlikely(ena_rx_ctx->l3_csum_err))
266 ol_flags |= PKT_RX_IP_CKSUM_BAD;
268 mbuf->ol_flags = ol_flags;
269 mbuf->packet_type = packet_type;
272 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
273 struct ena_com_tx_ctx *ena_tx_ctx)
275 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
278 (PKT_TX_L4_MASK | PKT_TX_IP_CKSUM | PKT_TX_TCP_SEG)) {
279 /* check if TSO is required */
280 if (mbuf->ol_flags & PKT_TX_TCP_SEG) {
281 ena_tx_ctx->tso_enable = true;
283 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
286 /* check if L3 checksum is needed */
287 if (mbuf->ol_flags & PKT_TX_IP_CKSUM)
288 ena_tx_ctx->l3_csum_enable = true;
290 if (mbuf->ol_flags & PKT_TX_IPV6) {
291 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
293 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
295 /* set don't fragment (DF) flag */
296 if (mbuf->packet_type &
297 (RTE_PTYPE_L4_NONFRAG
298 | RTE_PTYPE_INNER_L4_NONFRAG))
299 ena_tx_ctx->df = true;
302 /* check if L4 checksum is needed */
303 switch (mbuf->ol_flags & PKT_TX_L4_MASK) {
304 case PKT_TX_TCP_CKSUM:
305 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
306 ena_tx_ctx->l4_csum_enable = true;
308 case PKT_TX_UDP_CKSUM:
309 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
310 ena_tx_ctx->l4_csum_enable = true;
313 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
314 ena_tx_ctx->l4_csum_enable = false;
318 ena_meta->mss = mbuf->tso_segsz;
319 ena_meta->l3_hdr_len = mbuf->l3_len;
320 ena_meta->l3_hdr_offset = mbuf->l2_len;
321 /* this param needed only for TSO */
322 ena_meta->l3_outer_hdr_len = 0;
323 ena_meta->l3_outer_hdr_offset = 0;
325 ena_tx_ctx->meta_valid = true;
327 ena_tx_ctx->meta_valid = false;
331 static void ena_config_host_info(struct ena_com_dev *ena_dev)
333 struct ena_admin_host_info *host_info;
336 /* Allocate only the host info */
337 rc = ena_com_allocate_host_info(ena_dev);
339 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
343 host_info = ena_dev->host_attr.host_info;
345 host_info->os_type = ENA_ADMIN_OS_DPDK;
346 host_info->kernel_ver = RTE_VERSION;
347 snprintf((char *)host_info->kernel_ver_str,
348 sizeof(host_info->kernel_ver_str),
349 "%s", rte_version());
350 host_info->os_dist = RTE_VERSION;
351 snprintf((char *)host_info->os_dist_str,
352 sizeof(host_info->os_dist_str),
353 "%s", rte_version());
354 host_info->driver_version =
355 (DRV_MODULE_VER_MAJOR) |
356 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
357 (DRV_MODULE_VER_SUBMINOR <<
358 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
360 rc = ena_com_set_host_attributes(ena_dev);
362 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
370 ena_com_delete_host_info(ena_dev);
374 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
376 if (sset != ETH_SS_STATS)
379 /* Workaround for clang:
380 * touch internal structures to prevent
383 ENA_TOUCH(ena_stats_global_strings);
384 ENA_TOUCH(ena_stats_tx_strings);
385 ENA_TOUCH(ena_stats_rx_strings);
386 ENA_TOUCH(ena_stats_ena_com_strings);
388 return dev->data->nb_tx_queues *
389 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
390 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
393 static void ena_config_debug_area(struct ena_adapter *adapter)
398 ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
400 RTE_LOG(ERR, PMD, "SS count is negative\n");
404 /* allocate 32 bytes for each string and 64bit for the value */
405 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
407 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
409 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
413 rc = ena_com_set_host_attributes(&adapter->ena_dev);
415 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
422 ena_com_delete_debug_area(&adapter->ena_dev);
425 static void ena_close(struct rte_eth_dev *dev)
427 struct ena_adapter *adapter =
428 (struct ena_adapter *)(dev->data->dev_private);
430 adapter->state = ENA_ADAPTER_STATE_STOPPED;
432 ena_rx_queue_release_all(dev);
433 ena_tx_queue_release_all(dev);
436 static int ena_rss_reta_update(struct rte_eth_dev *dev,
437 struct rte_eth_rss_reta_entry64 *reta_conf,
440 struct ena_adapter *adapter =
441 (struct ena_adapter *)(dev->data->dev_private);
442 struct ena_com_dev *ena_dev = &adapter->ena_dev;
448 if ((reta_size == 0) || (reta_conf == NULL))
451 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
452 RTE_LOG(WARNING, PMD,
453 "indirection table %d is bigger than supported (%d)\n",
454 reta_size, ENA_RX_RSS_TABLE_SIZE);
459 for (i = 0 ; i < reta_size ; i++) {
460 /* each reta_conf is for 64 entries.
461 * to support 128 we use 2 conf of 64
463 conf_idx = i / RTE_RETA_GROUP_SIZE;
464 idx = i % RTE_RETA_GROUP_SIZE;
465 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
467 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
468 ret = ena_com_indirect_table_fill_entry(ena_dev,
471 if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
473 "Cannot fill indirect table\n");
480 ret = ena_com_indirect_table_set(ena_dev);
481 if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
482 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
487 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n",
488 __func__, reta_size, adapter->rte_dev->data->port_id);
493 /* Query redirection table. */
494 static int ena_rss_reta_query(struct rte_eth_dev *dev,
495 struct rte_eth_rss_reta_entry64 *reta_conf,
498 struct ena_adapter *adapter =
499 (struct ena_adapter *)(dev->data->dev_private);
500 struct ena_com_dev *ena_dev = &adapter->ena_dev;
503 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
507 if (reta_size == 0 || reta_conf == NULL ||
508 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
511 ret = ena_com_indirect_table_get(ena_dev, indirect_table);
512 if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
513 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
518 for (i = 0 ; i < reta_size ; i++) {
519 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
520 reta_idx = i % RTE_RETA_GROUP_SIZE;
521 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
522 reta_conf[reta_conf_idx].reta[reta_idx] =
523 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
529 static int ena_rss_init_default(struct ena_adapter *adapter)
531 struct ena_com_dev *ena_dev = &adapter->ena_dev;
532 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
536 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
538 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
542 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
543 val = i % nb_rx_queues;
544 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
545 ENA_IO_RXQ_IDX(val));
546 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
547 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
552 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
553 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
554 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
555 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
559 rc = ena_com_set_default_hash_ctrl(ena_dev);
560 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
561 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
565 rc = ena_com_indirect_table_set(ena_dev);
566 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
567 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
570 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
571 adapter->rte_dev->data->port_id);
576 ena_com_rss_destroy(ena_dev);
582 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
584 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
585 int nb_queues = dev->data->nb_rx_queues;
588 for (i = 0; i < nb_queues; i++)
589 ena_rx_queue_release(queues[i]);
592 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
594 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
595 int nb_queues = dev->data->nb_tx_queues;
598 for (i = 0; i < nb_queues; i++)
599 ena_tx_queue_release(queues[i]);
602 static void ena_rx_queue_release(void *queue)
604 struct ena_ring *ring = (struct ena_ring *)queue;
605 struct ena_adapter *adapter = ring->adapter;
608 ena_assert_msg(ring->configured,
609 "API violation - releasing not configured queue");
610 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
613 /* Destroy HW queue */
614 ena_qid = ENA_IO_RXQ_IDX(ring->id);
615 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
618 ena_rx_queue_release_bufs(ring);
620 /* Free ring resources */
621 if (ring->rx_buffer_info)
622 rte_free(ring->rx_buffer_info);
623 ring->rx_buffer_info = NULL;
625 ring->configured = 0;
627 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
628 ring->port_id, ring->id);
631 static void ena_tx_queue_release(void *queue)
633 struct ena_ring *ring = (struct ena_ring *)queue;
634 struct ena_adapter *adapter = ring->adapter;
637 ena_assert_msg(ring->configured,
638 "API violation. Releasing not configured queue");
639 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
642 /* Destroy HW queue */
643 ena_qid = ENA_IO_TXQ_IDX(ring->id);
644 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
647 ena_tx_queue_release_bufs(ring);
649 /* Free ring resources */
650 if (ring->tx_buffer_info)
651 rte_free(ring->tx_buffer_info);
653 if (ring->empty_tx_reqs)
654 rte_free(ring->empty_tx_reqs);
656 ring->empty_tx_reqs = NULL;
657 ring->tx_buffer_info = NULL;
659 ring->configured = 0;
661 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
662 ring->port_id, ring->id);
665 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
667 unsigned int ring_mask = ring->ring_size - 1;
669 while (ring->next_to_clean != ring->next_to_use) {
671 ring->rx_buffer_info[ring->next_to_clean & ring_mask];
674 __rte_mbuf_raw_free(m);
676 ring->next_to_clean++;
680 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
684 for (i = 0; i < ring->ring_size; ++i) {
685 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
688 rte_pktmbuf_free(tx_buf->mbuf);
690 ring->next_to_clean++;
694 static int ena_link_update(struct rte_eth_dev *dev,
695 __rte_unused int wait_to_complete)
697 struct rte_eth_link *link = &dev->data->dev_link;
699 link->link_status = 1;
700 link->link_speed = ETH_SPEED_NUM_10G;
701 link->link_duplex = ETH_LINK_FULL_DUPLEX;
706 static int ena_queue_restart_all(struct rte_eth_dev *dev,
707 enum ena_ring_type ring_type)
709 struct ena_adapter *adapter =
710 (struct ena_adapter *)(dev->data->dev_private);
711 struct ena_ring *queues = NULL;
715 queues = (ring_type == ENA_RING_TYPE_RX) ?
716 adapter->rx_ring : adapter->tx_ring;
718 for (i = 0; i < adapter->num_queues; i++) {
719 if (queues[i].configured) {
720 if (ring_type == ENA_RING_TYPE_RX) {
722 dev->data->rx_queues[i] == &queues[i],
723 "Inconsistent state of rx queues\n");
726 dev->data->tx_queues[i] == &queues[i],
727 "Inconsistent state of tx queues\n");
730 rc = ena_queue_restart(&queues[i]);
734 "failed to restart queue %d type(%d)\n",
744 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
746 uint32_t max_frame_len = adapter->max_mtu;
748 if (adapter->rte_eth_dev_data->dev_conf.rxmode.jumbo_frame == 1)
750 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
752 return max_frame_len;
755 static int ena_check_valid_conf(struct ena_adapter *adapter)
757 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
759 if (max_frame_len > adapter->max_mtu) {
760 PMD_INIT_LOG(ERR, "Unsupported MTU of %d\n", max_frame_len);
768 ena_calc_queue_size(struct ena_com_dev *ena_dev,
769 struct ena_com_dev_get_features_ctx *get_feat_ctx)
771 uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
773 queue_size = RTE_MIN(queue_size,
774 get_feat_ctx->max_queues.max_cq_depth);
775 queue_size = RTE_MIN(queue_size,
776 get_feat_ctx->max_queues.max_sq_depth);
778 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
779 queue_size = RTE_MIN(queue_size,
780 get_feat_ctx->max_queues.max_llq_depth);
782 /* Round down to power of 2 */
783 if (!rte_is_power_of_2(queue_size))
784 queue_size = rte_align32pow2(queue_size >> 1);
786 if (queue_size == 0) {
787 PMD_INIT_LOG(ERR, "Invalid queue size\n");
794 static void ena_stats_restart(struct rte_eth_dev *dev)
796 struct ena_adapter *adapter =
797 (struct ena_adapter *)(dev->data->dev_private);
799 rte_atomic64_init(&adapter->drv_stats->ierrors);
800 rte_atomic64_init(&adapter->drv_stats->oerrors);
801 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
804 static void ena_stats_get(struct rte_eth_dev *dev,
805 struct rte_eth_stats *stats)
807 struct ena_admin_basic_stats ena_stats;
808 struct ena_adapter *adapter =
809 (struct ena_adapter *)(dev->data->dev_private);
810 struct ena_com_dev *ena_dev = &adapter->ena_dev;
813 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
816 memset(&ena_stats, 0, sizeof(ena_stats));
817 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
819 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
823 /* Set of basic statistics from ENA */
824 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
825 ena_stats.rx_pkts_low);
826 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
827 ena_stats.tx_pkts_low);
828 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
829 ena_stats.rx_bytes_low);
830 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
831 ena_stats.tx_bytes_low);
832 stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
833 ena_stats.rx_drops_low);
835 /* Driver related stats */
836 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
837 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
838 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
841 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
843 struct ena_adapter *adapter;
844 struct ena_com_dev *ena_dev;
847 ena_assert_msg(dev->data != NULL, "Uninitialized device");
848 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
849 adapter = (struct ena_adapter *)(dev->data->dev_private);
851 ena_dev = &adapter->ena_dev;
852 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
854 if (mtu > ena_get_mtu_conf(adapter)) {
856 "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
857 mtu, ena_get_mtu_conf(adapter));
862 rc = ena_com_set_dev_mtu(ena_dev, mtu);
864 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
866 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
872 static int ena_start(struct rte_eth_dev *dev)
874 struct ena_adapter *adapter =
875 (struct ena_adapter *)(dev->data->dev_private);
878 if (!(adapter->state == ENA_ADAPTER_STATE_CONFIG ||
879 adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
880 PMD_INIT_LOG(ERR, "API violation");
884 rc = ena_check_valid_conf(adapter);
888 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
892 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
896 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
897 ETH_MQ_RX_RSS_FLAG) {
898 rc = ena_rss_init_default(adapter);
903 ena_stats_restart(dev);
905 adapter->state = ENA_ADAPTER_STATE_RUNNING;
910 static int ena_queue_restart(struct ena_ring *ring)
914 ena_assert_msg(ring->configured == 1,
915 "Trying to restart unconfigured queue\n");
917 ring->next_to_clean = 0;
918 ring->next_to_use = 0;
920 if (ring->type == ENA_RING_TYPE_TX)
923 bufs_num = ring->ring_size - 1;
924 rc = ena_populate_rx_queue(ring, bufs_num);
925 if (rc != bufs_num) {
926 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
933 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
936 __rte_unused unsigned int socket_id,
937 __rte_unused const struct rte_eth_txconf *tx_conf)
939 struct ena_com_create_io_ctx ctx =
940 /* policy set to _HOST just to satisfy icc compiler */
941 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
942 ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
943 struct ena_ring *txq = NULL;
944 struct ena_adapter *adapter =
945 (struct ena_adapter *)(dev->data->dev_private);
949 struct ena_com_dev *ena_dev = &adapter->ena_dev;
951 txq = &adapter->tx_ring[queue_idx];
953 if (txq->configured) {
955 "API violation. Queue %d is already configured\n",
960 if (!rte_is_power_of_2(nb_desc)) {
962 "Unsupported size of RX queue: %d is not a power of 2.",
967 if (nb_desc > adapter->tx_ring_size) {
969 "Unsupported size of TX queue (max size: %d)\n",
970 adapter->tx_ring_size);
974 ena_qid = ENA_IO_TXQ_IDX(queue_idx);
976 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
978 ctx.msix_vector = -1; /* admin interrupts not used */
979 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
980 ctx.queue_size = adapter->tx_ring_size;
981 ctx.numa_node = ena_cpu_to_node(queue_idx);
983 rc = ena_com_create_io_queue(ena_dev, &ctx);
986 "failed to create io TX queue #%d (qid:%d) rc: %d\n",
987 queue_idx, ena_qid, rc);
989 txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
990 txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
992 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
994 &txq->ena_com_io_cq);
997 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
999 ena_com_destroy_io_queue(ena_dev, ena_qid);
1003 txq->port_id = dev->data->port_id;
1004 txq->next_to_clean = 0;
1005 txq->next_to_use = 0;
1006 txq->ring_size = nb_desc;
1008 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1009 sizeof(struct ena_tx_buffer) *
1011 RTE_CACHE_LINE_SIZE);
1012 if (!txq->tx_buffer_info) {
1013 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1017 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1018 sizeof(u16) * txq->ring_size,
1019 RTE_CACHE_LINE_SIZE);
1020 if (!txq->empty_tx_reqs) {
1021 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1022 rte_free(txq->tx_buffer_info);
1025 for (i = 0; i < txq->ring_size; i++)
1026 txq->empty_tx_reqs[i] = i;
1028 /* Store pointer to this queue in upper layer */
1029 txq->configured = 1;
1030 dev->data->tx_queues[queue_idx] = txq;
1035 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1038 __rte_unused unsigned int socket_id,
1039 __rte_unused const struct rte_eth_rxconf *rx_conf,
1040 struct rte_mempool *mp)
1042 struct ena_com_create_io_ctx ctx =
1043 /* policy set to _HOST just to satisfy icc compiler */
1044 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1045 ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1046 struct ena_adapter *adapter =
1047 (struct ena_adapter *)(dev->data->dev_private);
1048 struct ena_ring *rxq = NULL;
1049 uint16_t ena_qid = 0;
1051 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1053 rxq = &adapter->rx_ring[queue_idx];
1054 if (rxq->configured) {
1056 "API violation. Queue %d is already configured\n",
1061 if (!rte_is_power_of_2(nb_desc)) {
1063 "Unsupported size of TX queue: %d is not a power of 2.",
1068 if (nb_desc > adapter->rx_ring_size) {
1070 "Unsupported size of RX queue (max size: %d)\n",
1071 adapter->rx_ring_size);
1075 ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1078 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1079 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1080 ctx.msix_vector = -1; /* admin interrupts not used */
1081 ctx.queue_size = adapter->rx_ring_size;
1082 ctx.numa_node = ena_cpu_to_node(queue_idx);
1084 rc = ena_com_create_io_queue(ena_dev, &ctx);
1086 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1089 rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1090 rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1092 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1093 &rxq->ena_com_io_sq,
1094 &rxq->ena_com_io_cq);
1097 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1099 ena_com_destroy_io_queue(ena_dev, ena_qid);
1102 rxq->port_id = dev->data->port_id;
1103 rxq->next_to_clean = 0;
1104 rxq->next_to_use = 0;
1105 rxq->ring_size = nb_desc;
1108 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1109 sizeof(struct rte_mbuf *) * nb_desc,
1110 RTE_CACHE_LINE_SIZE);
1111 if (!rxq->rx_buffer_info) {
1112 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1116 /* Store pointer to this queue in upper layer */
1117 rxq->configured = 1;
1118 dev->data->rx_queues[queue_idx] = rxq;
1123 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1127 uint16_t ring_size = rxq->ring_size;
1128 uint16_t ring_mask = ring_size - 1;
1129 uint16_t next_to_use = rxq->next_to_use;
1131 struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1133 if (unlikely(!count))
1136 in_use = rxq->next_to_use - rxq->next_to_clean;
1137 ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1139 count = RTE_MIN(count,
1140 (uint16_t)(ring_size - (next_to_use & ring_mask)));
1142 /* get resources for incoming packets */
1143 rc = rte_mempool_get_bulk(rxq->mb_pool,
1144 (void **)(&mbufs[next_to_use & ring_mask]),
1146 if (unlikely(rc < 0)) {
1147 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1148 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1152 for (i = 0; i < count; i++) {
1153 uint16_t next_to_use_masked = next_to_use & ring_mask;
1154 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1155 struct ena_com_buf ebuf;
1157 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1158 /* prepare physical address for DMA transaction */
1159 ebuf.paddr = mbuf->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1160 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1161 /* pass resource to device */
1162 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1163 &ebuf, next_to_use_masked);
1165 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1167 RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1173 /* When we submitted free recources to device... */
1175 /* ...let HW know that it can fill buffers with data */
1177 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1179 rxq->next_to_use = next_to_use;
1185 static int ena_device_init(struct ena_com_dev *ena_dev,
1186 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1189 bool readless_supported;
1191 /* Initialize mmio registers */
1192 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1194 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1198 /* The PCIe configuration space revision id indicate if mmio reg
1201 readless_supported =
1202 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1203 & ENA_MMIO_DISABLE_REG_READ);
1204 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1207 rc = ena_com_dev_reset(ena_dev);
1209 RTE_LOG(ERR, PMD, "cannot reset device\n");
1210 goto err_mmio_read_less;
1213 /* check FW version */
1214 rc = ena_com_validate_version(ena_dev);
1216 RTE_LOG(ERR, PMD, "device version is too low\n");
1217 goto err_mmio_read_less;
1220 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1222 /* ENA device administration layer init */
1223 rc = ena_com_admin_init(ena_dev, NULL, true);
1226 "cannot initialize ena admin queue with device\n");
1227 goto err_mmio_read_less;
1230 /* To enable the msix interrupts the driver needs to know the number
1231 * of queues. So the driver uses polling mode to retrieve this
1234 ena_com_set_admin_polling_mode(ena_dev, true);
1236 ena_config_host_info(ena_dev);
1238 /* Get Device Attributes and features */
1239 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1242 "cannot get attribute for ena device rc= %d\n", rc);
1243 goto err_admin_init;
1249 ena_com_admin_destroy(ena_dev);
1252 ena_com_mmio_reg_read_request_destroy(ena_dev);
1257 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1259 struct rte_pci_device *pci_dev;
1260 struct ena_adapter *adapter =
1261 (struct ena_adapter *)(eth_dev->data->dev_private);
1262 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1263 struct ena_com_dev_get_features_ctx get_feat_ctx;
1266 static int adapters_found;
1268 memset(adapter, 0, sizeof(struct ena_adapter));
1269 ena_dev = &adapter->ena_dev;
1271 eth_dev->dev_ops = &ena_dev_ops;
1272 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1273 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1274 adapter->rte_eth_dev_data = eth_dev->data;
1275 adapter->rte_dev = eth_dev;
1277 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1280 pci_dev = eth_dev->pci_dev;
1281 adapter->pdev = pci_dev;
1283 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
1284 pci_dev->addr.domain,
1286 pci_dev->addr.devid,
1287 pci_dev->addr.function);
1289 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1290 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1292 /* Present ENA_MEM_BAR indicates available LLQ mode.
1293 * Use corresponding policy
1295 if (adapter->dev_mem_base)
1296 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
1297 else if (adapter->regs)
1298 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1300 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
1303 ena_dev->reg_bar = adapter->regs;
1304 ena_dev->dmadev = adapter->pdev;
1306 adapter->id_number = adapters_found;
1308 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1309 adapter->id_number);
1311 /* device specific initialization routine */
1312 rc = ena_device_init(ena_dev, &get_feat_ctx);
1314 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
1318 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1319 if (get_feat_ctx.max_queues.max_llq_num == 0) {
1321 "Trying to use LLQ but llq_num is 0.\n"
1322 "Fall back into regular queues.\n");
1323 ena_dev->tx_mem_queue_type =
1324 ENA_ADMIN_PLACEMENT_POLICY_HOST;
1325 adapter->num_queues =
1326 get_feat_ctx.max_queues.max_sq_num;
1328 adapter->num_queues =
1329 get_feat_ctx.max_queues.max_llq_num;
1332 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1335 queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1336 if ((queue_size <= 0) || (adapter->num_queues <= 0))
1339 adapter->tx_ring_size = queue_size;
1340 adapter->rx_ring_size = queue_size;
1342 /* prepare ring structures */
1343 ena_init_rings(adapter);
1345 ena_config_debug_area(adapter);
1347 /* Set max MTU for this device */
1348 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1350 /* Copy MAC address and point DPDK to it */
1351 eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1352 ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1353 (struct ether_addr *)adapter->mac_addr);
1355 adapter->drv_stats = rte_zmalloc("adapter stats",
1356 sizeof(*adapter->drv_stats),
1357 RTE_CACHE_LINE_SIZE);
1358 if (!adapter->drv_stats) {
1359 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1364 adapter->state = ENA_ADAPTER_STATE_INIT;
1369 static int ena_dev_configure(struct rte_eth_dev *dev)
1371 struct ena_adapter *adapter =
1372 (struct ena_adapter *)(dev->data->dev_private);
1374 if (!(adapter->state == ENA_ADAPTER_STATE_INIT ||
1375 adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
1376 PMD_INIT_LOG(ERR, "Illegal adapter state: %d\n",
1381 switch (adapter->state) {
1382 case ENA_ADAPTER_STATE_INIT:
1383 case ENA_ADAPTER_STATE_STOPPED:
1384 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1386 case ENA_ADAPTER_STATE_CONFIG:
1387 RTE_LOG(WARNING, PMD,
1388 "Ivalid driver state while trying to configure device\n");
1397 static void ena_init_rings(struct ena_adapter *adapter)
1401 for (i = 0; i < adapter->num_queues; i++) {
1402 struct ena_ring *ring = &adapter->tx_ring[i];
1404 ring->configured = 0;
1405 ring->type = ENA_RING_TYPE_TX;
1406 ring->adapter = adapter;
1408 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1409 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1412 for (i = 0; i < adapter->num_queues; i++) {
1413 struct ena_ring *ring = &adapter->rx_ring[i];
1415 ring->configured = 0;
1416 ring->type = ENA_RING_TYPE_RX;
1417 ring->adapter = adapter;
1422 static void ena_infos_get(struct rte_eth_dev *dev,
1423 struct rte_eth_dev_info *dev_info)
1425 struct ena_adapter *adapter;
1426 struct ena_com_dev *ena_dev;
1427 struct ena_com_dev_get_features_ctx feat;
1428 uint32_t rx_feat = 0, tx_feat = 0;
1431 ena_assert_msg(dev->data != NULL, "Uninitialized device");
1432 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1433 adapter = (struct ena_adapter *)(dev->data->dev_private);
1435 ena_dev = &adapter->ena_dev;
1436 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1438 dev_info->speed_capa =
1440 ETH_LINK_SPEED_2_5G |
1442 ETH_LINK_SPEED_10G |
1443 ETH_LINK_SPEED_25G |
1444 ETH_LINK_SPEED_40G |
1445 ETH_LINK_SPEED_50G |
1446 ETH_LINK_SPEED_100G;
1448 /* Get supported features from HW */
1449 rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1452 "Cannot get attribute for ena device rc= %d\n", rc);
1456 /* Set Tx & Rx features available for device */
1457 if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1458 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1460 if (feat.offload.tx &
1461 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1462 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1463 DEV_TX_OFFLOAD_UDP_CKSUM |
1464 DEV_TX_OFFLOAD_TCP_CKSUM;
1466 if (feat.offload.tx &
1467 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1468 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1469 DEV_RX_OFFLOAD_UDP_CKSUM |
1470 DEV_RX_OFFLOAD_TCP_CKSUM;
1472 /* Inform framework about available features */
1473 dev_info->rx_offload_capa = rx_feat;
1474 dev_info->tx_offload_capa = tx_feat;
1476 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1477 dev_info->max_rx_pktlen = adapter->max_mtu;
1478 dev_info->max_mac_addrs = 1;
1480 dev_info->max_rx_queues = adapter->num_queues;
1481 dev_info->max_tx_queues = adapter->num_queues;
1482 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1485 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1488 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1489 unsigned int ring_size = rx_ring->ring_size;
1490 unsigned int ring_mask = ring_size - 1;
1491 uint16_t next_to_clean = rx_ring->next_to_clean;
1492 uint16_t desc_in_use = 0;
1493 unsigned int recv_idx = 0;
1494 struct rte_mbuf *mbuf = NULL;
1495 struct rte_mbuf *mbuf_head = NULL;
1496 struct rte_mbuf *mbuf_prev = NULL;
1497 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1498 unsigned int completed;
1500 struct ena_com_rx_ctx ena_rx_ctx;
1503 /* Check adapter state */
1504 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1506 "Trying to receive pkts while device is NOT running\n");
1510 desc_in_use = rx_ring->next_to_use - next_to_clean;
1511 if (unlikely(nb_pkts > desc_in_use))
1512 nb_pkts = desc_in_use;
1514 for (completed = 0; completed < nb_pkts; completed++) {
1517 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1518 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1519 ena_rx_ctx.descs = 0;
1520 /* receive packet context */
1521 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1522 rx_ring->ena_com_io_sq,
1525 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1529 if (unlikely(ena_rx_ctx.descs == 0))
1532 while (segments < ena_rx_ctx.descs) {
1533 mbuf = rx_buff_info[next_to_clean & ring_mask];
1534 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1535 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1538 if (segments == 0) {
1539 mbuf->nb_segs = ena_rx_ctx.descs;
1540 mbuf->port = rx_ring->port_id;
1544 /* for multi-segment pkts create mbuf chain */
1545 mbuf_prev->next = mbuf;
1547 mbuf_head->pkt_len += mbuf->data_len;
1554 /* fill mbuf attributes if any */
1555 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1556 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1558 /* pass to DPDK application head mbuf */
1559 rx_pkts[recv_idx] = mbuf_head;
1563 rx_ring->next_to_clean = next_to_clean;
1565 desc_in_use = desc_in_use - completed + 1;
1566 /* Burst refill to save doorbells, memory barriers, const interval */
1567 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1568 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1573 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1576 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1577 uint16_t next_to_use = tx_ring->next_to_use;
1578 uint16_t next_to_clean = tx_ring->next_to_clean;
1579 struct rte_mbuf *mbuf;
1580 unsigned int ring_size = tx_ring->ring_size;
1581 unsigned int ring_mask = ring_size - 1;
1582 struct ena_com_tx_ctx ena_tx_ctx;
1583 struct ena_tx_buffer *tx_info;
1584 struct ena_com_buf *ebuf;
1585 uint16_t rc, req_id, total_tx_descs = 0;
1586 uint16_t sent_idx = 0, empty_tx_reqs;
1589 /* Check adapter state */
1590 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1592 "Trying to xmit pkts while device is NOT running\n");
1596 empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1597 if (nb_pkts > empty_tx_reqs)
1598 nb_pkts = empty_tx_reqs;
1600 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1601 mbuf = tx_pkts[sent_idx];
1603 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1604 tx_info = &tx_ring->tx_buffer_info[req_id];
1605 tx_info->mbuf = mbuf;
1606 tx_info->num_of_bufs = 0;
1607 ebuf = tx_info->bufs;
1609 /* Prepare TX context */
1610 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1611 memset(&ena_tx_ctx.ena_meta, 0x0,
1612 sizeof(struct ena_com_tx_meta));
1613 ena_tx_ctx.ena_bufs = ebuf;
1614 ena_tx_ctx.req_id = req_id;
1615 if (tx_ring->tx_mem_queue_type ==
1616 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1617 /* prepare the push buffer with
1618 * virtual address of the data
1620 ena_tx_ctx.header_len =
1621 RTE_MIN(mbuf->data_len,
1622 tx_ring->tx_max_header_size);
1623 ena_tx_ctx.push_header =
1624 (void *)((char *)mbuf->buf_addr +
1626 } /* there's no else as we take advantage of memset zeroing */
1628 /* Set TX offloads flags, if applicable */
1629 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx);
1631 if (unlikely(mbuf->ol_flags &
1632 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1633 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1635 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1637 /* Process first segment taking into
1638 * consideration pushed header
1640 if (mbuf->data_len > ena_tx_ctx.header_len) {
1641 ebuf->paddr = mbuf->buf_physaddr +
1643 ena_tx_ctx.header_len;
1644 ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1646 tx_info->num_of_bufs++;
1649 while ((mbuf = mbuf->next) != NULL) {
1650 ebuf->paddr = mbuf->buf_physaddr + mbuf->data_off;
1651 ebuf->len = mbuf->data_len;
1653 tx_info->num_of_bufs++;
1656 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1658 /* Write data to device */
1659 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1660 &ena_tx_ctx, &nb_hw_desc);
1664 tx_info->tx_descs = nb_hw_desc;
1669 /* If there are ready packets to be xmitted... */
1671 /* ...let HW do its best :-) */
1673 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1675 tx_ring->next_to_use = next_to_use;
1678 /* Clear complete packets */
1679 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1680 /* Get Tx info & store how many descs were processed */
1681 tx_info = &tx_ring->tx_buffer_info[req_id];
1682 total_tx_descs += tx_info->tx_descs;
1684 /* Free whole mbuf chain */
1685 mbuf = tx_info->mbuf;
1686 rte_pktmbuf_free(mbuf);
1687 tx_info->mbuf = NULL;
1689 /* Put back descriptor to the ring for reuse */
1690 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1693 /* If too many descs to clean, leave it for another run */
1694 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1698 if (total_tx_descs > 0) {
1699 /* acknowledge completion of sent packets */
1700 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1701 tx_ring->next_to_clean = next_to_clean;
1707 static struct eth_driver rte_ena_pmd = {
1709 .id_table = pci_id_ena_map,
1710 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1711 .probe = rte_eth_dev_pci_probe,
1712 .remove = rte_eth_dev_pci_remove,
1714 .eth_dev_init = eth_ena_dev_init,
1715 .dev_private_size = sizeof(struct ena_adapter),
1718 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd.pci_drv);
1719 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);