4 * Copyright(c) 2013-2016 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_ethdev.h>
35 #include <rte_malloc.h>
36 #include <rte_memzone.h>
37 #include <rte_string_fns.h>
39 #include <rte_spinlock.h>
40 #include <rte_kvargs.h>
43 #include "base/fm10k_api.h"
45 /* Default delay to acquire mailbox lock */
46 #define FM10K_MBXLOCK_DELAY_US 20
47 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
49 #define MAIN_VSI_POOL_NUMBER 0
51 /* Max try times to acquire switch status */
52 #define MAX_QUERY_SWITCH_STATE_TIMES 10
53 /* Wait interval to get switch status */
54 #define WAIT_SWITCH_MSG_US 100000
55 /* A period of quiescence for switch */
56 #define FM10K_SWITCH_QUIESCE_US 10000
57 /* Number of chars per uint32 type */
58 #define CHARS_PER_UINT32 (sizeof(uint32_t))
59 #define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
61 /* default 1:1 map from queue ID to interrupt vector ID */
62 #define Q2V(dev, queue_id) (dev->pci_dev->intr_handle.intr_vec[queue_id])
64 /* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
65 #define MAX_LPORT_NUM 128
66 #define GLORT_FD_Q_BASE 0x40
67 #define GLORT_PF_MASK 0xFFC0
68 #define GLORT_FD_MASK GLORT_PF_MASK
69 #define GLORT_FD_INDEX GLORT_FD_Q_BASE
71 static void fm10k_close_mbx_service(struct fm10k_hw *hw);
72 static void fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);
73 static void fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);
74 static void fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);
75 static void fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);
76 static inline int fm10k_glort_valid(struct fm10k_hw *hw);
78 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
79 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
80 const u8 *mac, bool add, uint32_t pool);
81 static void fm10k_tx_queue_release(void *queue);
82 static void fm10k_rx_queue_release(void *queue);
83 static void fm10k_set_rx_function(struct rte_eth_dev *dev);
84 static void fm10k_set_tx_function(struct rte_eth_dev *dev);
85 static int fm10k_check_ftag(struct rte_devargs *devargs);
86 static int fm10k_link_update(struct rte_eth_dev *dev, int wait_to_complete);
88 struct fm10k_xstats_name_off {
89 char name[RTE_ETH_XSTATS_NAME_SIZE];
93 struct fm10k_xstats_name_off fm10k_hw_stats_strings[] = {
94 {"completion_timeout_count", offsetof(struct fm10k_hw_stats, timeout)},
95 {"unsupported_requests_count", offsetof(struct fm10k_hw_stats, ur)},
96 {"completer_abort_count", offsetof(struct fm10k_hw_stats, ca)},
97 {"unsupported_message_count", offsetof(struct fm10k_hw_stats, um)},
98 {"checksum_error_count", offsetof(struct fm10k_hw_stats, xec)},
99 {"vlan_dropped", offsetof(struct fm10k_hw_stats, vlan_drop)},
100 {"loopback_dropped", offsetof(struct fm10k_hw_stats, loopback_drop)},
101 {"rx_mbuf_allocation_errors", offsetof(struct fm10k_hw_stats,
105 #define FM10K_NB_HW_XSTATS (sizeof(fm10k_hw_stats_strings) / \
106 sizeof(fm10k_hw_stats_strings[0]))
108 struct fm10k_xstats_name_off fm10k_hw_stats_rx_q_strings[] = {
109 {"packets", offsetof(struct fm10k_hw_stats_q, rx_packets)},
110 {"bytes", offsetof(struct fm10k_hw_stats_q, rx_bytes)},
111 {"dropped", offsetof(struct fm10k_hw_stats_q, rx_drops)},
114 #define FM10K_NB_RX_Q_XSTATS (sizeof(fm10k_hw_stats_rx_q_strings) / \
115 sizeof(fm10k_hw_stats_rx_q_strings[0]))
117 struct fm10k_xstats_name_off fm10k_hw_stats_tx_q_strings[] = {
118 {"packets", offsetof(struct fm10k_hw_stats_q, tx_packets)},
119 {"bytes", offsetof(struct fm10k_hw_stats_q, tx_bytes)},
122 #define FM10K_NB_TX_Q_XSTATS (sizeof(fm10k_hw_stats_tx_q_strings) / \
123 sizeof(fm10k_hw_stats_tx_q_strings[0]))
125 #define FM10K_NB_XSTATS (FM10K_NB_HW_XSTATS + FM10K_MAX_QUEUES_PF * \
126 (FM10K_NB_RX_Q_XSTATS + FM10K_NB_TX_Q_XSTATS))
128 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
131 fm10k_mbx_initlock(struct fm10k_hw *hw)
133 rte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
137 fm10k_mbx_lock(struct fm10k_hw *hw)
139 while (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))
140 rte_delay_us(FM10K_MBXLOCK_DELAY_US);
144 fm10k_mbx_unlock(struct fm10k_hw *hw)
146 rte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
149 /* Stubs needed for linkage when vPMD is disabled */
150 int __attribute__((weak))
151 fm10k_rx_vec_condition_check(__rte_unused struct rte_eth_dev *dev)
156 uint16_t __attribute__((weak))
158 __rte_unused void *rx_queue,
159 __rte_unused struct rte_mbuf **rx_pkts,
160 __rte_unused uint16_t nb_pkts)
165 uint16_t __attribute__((weak))
166 fm10k_recv_scattered_pkts_vec(
167 __rte_unused void *rx_queue,
168 __rte_unused struct rte_mbuf **rx_pkts,
169 __rte_unused uint16_t nb_pkts)
174 int __attribute__((weak))
175 fm10k_rxq_vec_setup(__rte_unused struct fm10k_rx_queue *rxq)
181 void __attribute__((weak))
182 fm10k_rx_queue_release_mbufs_vec(
183 __rte_unused struct fm10k_rx_queue *rxq)
188 void __attribute__((weak))
189 fm10k_txq_vec_setup(__rte_unused struct fm10k_tx_queue *txq)
194 int __attribute__((weak))
195 fm10k_tx_vec_condition_check(__rte_unused struct fm10k_tx_queue *txq)
200 uint16_t __attribute__((weak))
201 fm10k_xmit_pkts_vec(__rte_unused void *tx_queue,
202 __rte_unused struct rte_mbuf **tx_pkts,
203 __rte_unused uint16_t nb_pkts)
209 * reset queue to initial state, allocate software buffers used when starting
211 * return 0 on success
212 * return -ENOMEM if buffers cannot be allocated
213 * return -EINVAL if buffers do not satisfy alignment condition
216 rx_queue_reset(struct fm10k_rx_queue *q)
218 static const union fm10k_rx_desc zero = {{0} };
221 PMD_INIT_FUNC_TRACE();
223 diag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);
227 for (i = 0; i < q->nb_desc; ++i) {
228 fm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);
229 if (!fm10k_addr_alignment_valid(q->sw_ring[i])) {
230 rte_mempool_put_bulk(q->mp, (void **)q->sw_ring,
234 dma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);
235 q->hw_ring[i].q.pkt_addr = dma_addr;
236 q->hw_ring[i].q.hdr_addr = dma_addr;
239 /* initialize extra software ring entries. Space for these extra
240 * entries is always allocated.
242 memset(&q->fake_mbuf, 0x0, sizeof(q->fake_mbuf));
243 for (i = 0; i < q->nb_fake_desc; ++i) {
244 q->sw_ring[q->nb_desc + i] = &q->fake_mbuf;
245 q->hw_ring[q->nb_desc + i] = zero;
250 q->next_trigger = q->alloc_thresh - 1;
251 FM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);
252 q->rxrearm_start = 0;
259 * clean queue, descriptor rings, free software buffers used when stopping
263 rx_queue_clean(struct fm10k_rx_queue *q)
265 union fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };
267 PMD_INIT_FUNC_TRACE();
269 /* zero descriptor rings */
270 for (i = 0; i < q->nb_desc; ++i)
271 q->hw_ring[i] = zero;
273 /* zero faked descriptors */
274 for (i = 0; i < q->nb_fake_desc; ++i)
275 q->hw_ring[q->nb_desc + i] = zero;
277 /* vPMD driver has a different way of releasing mbufs. */
278 if (q->rx_using_sse) {
279 fm10k_rx_queue_release_mbufs_vec(q);
283 /* free software buffers */
284 for (i = 0; i < q->nb_desc; ++i) {
286 rte_pktmbuf_free_seg(q->sw_ring[i]);
287 q->sw_ring[i] = NULL;
293 * free all queue memory used when releasing the queue (i.e. configure)
296 rx_queue_free(struct fm10k_rx_queue *q)
298 PMD_INIT_FUNC_TRACE();
300 PMD_INIT_LOG(DEBUG, "Freeing rx queue %p", q);
303 rte_free(q->sw_ring);
312 * disable RX queue, wait unitl HW finished necessary flush operation
315 rx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
319 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
320 FM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),
321 reg & ~FM10K_RXQCTL_ENABLE);
323 /* Wait 100us at most */
324 for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
326 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
327 if (!(reg & FM10K_RXQCTL_ENABLE))
331 if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
338 * reset queue to initial state, allocate software buffers used when starting
342 tx_queue_reset(struct fm10k_tx_queue *q)
344 PMD_INIT_FUNC_TRACE();
348 q->nb_free = q->nb_desc - 1;
349 fifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);
350 FM10K_PCI_REG_WRITE(q->tail_ptr, 0);
354 * clean queue, descriptor rings, free software buffers used when stopping
358 tx_queue_clean(struct fm10k_tx_queue *q)
360 struct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};
362 PMD_INIT_FUNC_TRACE();
364 /* zero descriptor rings */
365 for (i = 0; i < q->nb_desc; ++i)
366 q->hw_ring[i] = zero;
368 /* free software buffers */
369 for (i = 0; i < q->nb_desc; ++i) {
371 rte_pktmbuf_free_seg(q->sw_ring[i]);
372 q->sw_ring[i] = NULL;
378 * free all queue memory used when releasing the queue (i.e. configure)
381 tx_queue_free(struct fm10k_tx_queue *q)
383 PMD_INIT_FUNC_TRACE();
385 PMD_INIT_LOG(DEBUG, "Freeing tx queue %p", q);
387 if (q->rs_tracker.list) {
388 rte_free(q->rs_tracker.list);
389 q->rs_tracker.list = NULL;
392 rte_free(q->sw_ring);
401 * disable TX queue, wait unitl HW finished necessary flush operation
404 tx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
408 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
409 FM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),
410 reg & ~FM10K_TXDCTL_ENABLE);
412 /* Wait 100us at most */
413 for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
415 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
416 if (!(reg & FM10K_TXDCTL_ENABLE))
420 if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
427 fm10k_check_mq_mode(struct rte_eth_dev *dev)
429 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
430 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
431 struct rte_eth_vmdq_rx_conf *vmdq_conf;
432 uint16_t nb_rx_q = dev->data->nb_rx_queues;
434 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
436 if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
437 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
441 if (!(rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG))
444 if (hw->mac.type == fm10k_mac_vf) {
445 PMD_INIT_LOG(ERR, "VMDQ mode is not supported in VF.");
449 /* Check VMDQ queue pool number */
450 if (vmdq_conf->nb_queue_pools >
451 sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT ||
452 vmdq_conf->nb_queue_pools > nb_rx_q) {
453 PMD_INIT_LOG(ERR, "Too many of queue pools: %d",
454 vmdq_conf->nb_queue_pools);
461 static const struct fm10k_txq_ops def_txq_ops = {
462 .reset = tx_queue_reset,
466 fm10k_dev_configure(struct rte_eth_dev *dev)
470 PMD_INIT_FUNC_TRACE();
472 if (dev->data->dev_conf.rxmode.hw_strip_crc == 0)
473 PMD_INIT_LOG(WARNING, "fm10k always strip CRC");
474 /* multipe queue mode checking */
475 ret = fm10k_check_mq_mode(dev);
477 PMD_DRV_LOG(ERR, "fm10k_check_mq_mode fails with %d.",
485 /* fls = find last set bit = 32 minus the number of leading zeros */
487 #define fls(x) (((x) == 0) ? 0 : (32 - __builtin_clz((x))))
491 fm10k_dev_vmdq_rx_configure(struct rte_eth_dev *dev)
493 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
494 struct rte_eth_vmdq_rx_conf *vmdq_conf;
497 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
499 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
500 if (!vmdq_conf->pool_map[i].pools)
503 fm10k_update_vlan(hw, vmdq_conf->pool_map[i].vlan_id, 0, true);
504 fm10k_mbx_unlock(hw);
509 fm10k_dev_pf_main_vsi_reset(struct rte_eth_dev *dev)
511 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
513 /* Add default mac address */
514 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
515 MAIN_VSI_POOL_NUMBER);
519 fm10k_dev_rss_configure(struct rte_eth_dev *dev)
521 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
522 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
523 uint32_t mrqc, *key, i, reta, j;
526 #define RSS_KEY_SIZE 40
527 static uint8_t rss_intel_key[RSS_KEY_SIZE] = {
528 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
529 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
530 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
531 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
532 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
535 if (dev->data->nb_rx_queues == 1 ||
536 dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||
537 dev_conf->rx_adv_conf.rss_conf.rss_hf == 0) {
538 FM10K_WRITE_REG(hw, FM10K_MRQC(0), 0);
542 /* random key is rss_intel_key (default) or user provided (rss_key) */
543 if (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)
544 key = (uint32_t *)rss_intel_key;
546 key = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;
548 /* Now fill our hash function seeds, 4 bytes at a time */
549 for (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)
550 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
553 * Fill in redirection table
554 * The byte-swap is needed because NIC registers are in
555 * little-endian order.
558 for (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {
559 if (j == dev->data->nb_rx_queues)
561 reta = (reta << CHAR_BIT) | j;
563 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),
568 * Generate RSS hash based on packet types, TCP/UDP
569 * port numbers and/or IPv4/v6 src and dst addresses
571 hf = dev_conf->rx_adv_conf.rss_conf.rss_hf;
573 mrqc |= (hf & ETH_RSS_IPV4) ? FM10K_MRQC_IPV4 : 0;
574 mrqc |= (hf & ETH_RSS_IPV6) ? FM10K_MRQC_IPV6 : 0;
575 mrqc |= (hf & ETH_RSS_IPV6_EX) ? FM10K_MRQC_IPV6 : 0;
576 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? FM10K_MRQC_TCP_IPV4 : 0;
577 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? FM10K_MRQC_TCP_IPV6 : 0;
578 mrqc |= (hf & ETH_RSS_IPV6_TCP_EX) ? FM10K_MRQC_TCP_IPV6 : 0;
579 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? FM10K_MRQC_UDP_IPV4 : 0;
580 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? FM10K_MRQC_UDP_IPV6 : 0;
581 mrqc |= (hf & ETH_RSS_IPV6_UDP_EX) ? FM10K_MRQC_UDP_IPV6 : 0;
584 PMD_INIT_LOG(ERR, "Specified RSS mode 0x%"PRIx64"is not"
589 FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
593 fm10k_dev_logic_port_update(struct rte_eth_dev *dev, uint16_t nb_lport_new)
595 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
598 for (i = 0; i < nb_lport_new; i++) {
599 /* Set unicast mode by default. App can change
600 * to other mode in other API func.
603 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map + i,
604 FM10K_XCAST_MODE_NONE);
605 fm10k_mbx_unlock(hw);
610 fm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)
612 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
613 struct rte_eth_vmdq_rx_conf *vmdq_conf;
614 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
615 struct fm10k_macvlan_filter_info *macvlan;
616 uint16_t nb_queue_pools = 0; /* pool number in configuration */
617 uint16_t nb_lport_new;
619 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
620 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
622 fm10k_dev_rss_configure(dev);
624 /* only PF supports VMDQ */
625 if (hw->mac.type != fm10k_mac_pf)
628 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
629 nb_queue_pools = vmdq_conf->nb_queue_pools;
631 /* no pool number change, no need to update logic port and VLAN/MAC */
632 if (macvlan->nb_queue_pools == nb_queue_pools)
635 nb_lport_new = nb_queue_pools ? nb_queue_pools : 1;
636 fm10k_dev_logic_port_update(dev, nb_lport_new);
638 /* reset MAC/VLAN as it's based on VMDQ or PF main VSI */
639 memset(dev->data->mac_addrs, 0,
640 ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM);
641 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
642 &dev->data->mac_addrs[0]);
643 memset(macvlan, 0, sizeof(*macvlan));
644 macvlan->nb_queue_pools = nb_queue_pools;
647 fm10k_dev_vmdq_rx_configure(dev);
649 fm10k_dev_pf_main_vsi_reset(dev);
653 fm10k_dev_tx_init(struct rte_eth_dev *dev)
655 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
657 struct fm10k_tx_queue *txq;
661 /* Disable TXINT to avoid possible interrupt */
662 for (i = 0; i < hw->mac.max_queues; i++)
663 FM10K_WRITE_REG(hw, FM10K_TXINT(i),
664 3 << FM10K_TXINT_TIMER_SHIFT);
667 for (i = 0; i < dev->data->nb_tx_queues; ++i) {
668 txq = dev->data->tx_queues[i];
669 base_addr = txq->hw_ring_phys_addr;
670 size = txq->nb_desc * sizeof(struct fm10k_tx_desc);
672 /* disable queue to avoid issues while updating state */
673 ret = tx_queue_disable(hw, i);
675 PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
678 /* Enable use of FTAG bit in TX descriptor, PFVTCTL
679 * register is read-only for VF.
681 if (fm10k_check_ftag(dev->pci_dev->device.devargs)) {
682 if (hw->mac.type == fm10k_mac_pf) {
683 FM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),
684 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
685 PMD_INIT_LOG(DEBUG, "FTAG mode is enabled");
687 PMD_INIT_LOG(ERR, "VF FTAG is not supported.");
692 /* set location and size for descriptor ring */
693 FM10K_WRITE_REG(hw, FM10K_TDBAL(i),
694 base_addr & UINT64_LOWER_32BITS_MASK);
695 FM10K_WRITE_REG(hw, FM10K_TDBAH(i),
696 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
697 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);
699 /* assign default SGLORT for each TX queue by PF */
700 if (hw->mac.type == fm10k_mac_pf)
701 FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);
704 /* set up vector or scalar TX function as appropriate */
705 fm10k_set_tx_function(dev);
711 fm10k_dev_rx_init(struct rte_eth_dev *dev)
713 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
714 struct fm10k_macvlan_filter_info *macvlan;
715 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
717 struct fm10k_rx_queue *rxq;
720 uint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
721 uint32_t logic_port = hw->mac.dglort_map;
723 uint16_t queue_stride = 0;
725 /* enable RXINT for interrupt mode */
727 if (rte_intr_dp_is_en(intr_handle)) {
728 for (; i < dev->data->nb_rx_queues; i++) {
729 FM10K_WRITE_REG(hw, FM10K_RXINT(i), Q2V(dev, i));
730 if (hw->mac.type == fm10k_mac_pf)
731 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, i)),
733 FM10K_ITR_MASK_CLEAR);
735 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, i)),
737 FM10K_ITR_MASK_CLEAR);
740 /* Disable other RXINT to avoid possible interrupt */
741 for (; i < hw->mac.max_queues; i++)
742 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
743 3 << FM10K_RXINT_TIMER_SHIFT);
745 /* Setup RX queues */
746 for (i = 0; i < dev->data->nb_rx_queues; ++i) {
747 rxq = dev->data->rx_queues[i];
748 base_addr = rxq->hw_ring_phys_addr;
749 size = rxq->nb_desc * sizeof(union fm10k_rx_desc);
751 /* disable queue to avoid issues while updating state */
752 ret = rx_queue_disable(hw, i);
754 PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
758 /* Setup the Base and Length of the Rx Descriptor Ring */
759 FM10K_WRITE_REG(hw, FM10K_RDBAL(i),
760 base_addr & UINT64_LOWER_32BITS_MASK);
761 FM10K_WRITE_REG(hw, FM10K_RDBAH(i),
762 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
763 FM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);
765 /* Configure the Rx buffer size for one buff without split */
766 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
767 RTE_PKTMBUF_HEADROOM);
768 /* As RX buffer is aligned to 512B within mbuf, some bytes are
769 * reserved for this purpose, and the worst case could be 511B.
770 * But SRR reg assumes all buffers have the same size. In order
771 * to fill the gap, we'll have to consider the worst case and
772 * assume 512B is reserved. If we don't do so, it's possible
773 * for HW to overwrite data to next mbuf.
775 buf_size -= FM10K_RX_DATABUF_ALIGN;
777 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
778 (buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |
779 FM10K_SRRCTL_LOOPBACK_SUPPRESS);
781 /* It adds dual VLAN length for supporting dual VLAN */
782 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
783 2 * FM10K_VLAN_TAG_SIZE) > buf_size ||
784 dev->data->dev_conf.rxmode.enable_scatter) {
786 dev->data->scattered_rx = 1;
787 reg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));
788 reg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;
789 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);
792 /* Enable drop on empty, it's RO for VF */
793 if (hw->mac.type == fm10k_mac_pf && rxq->drop_en)
794 rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
796 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);
797 FM10K_WRITE_FLUSH(hw);
800 /* Configure VMDQ/RSS if applicable */
801 fm10k_dev_mq_rx_configure(dev);
803 /* Decide the best RX function */
804 fm10k_set_rx_function(dev);
806 /* update RX_SGLORT for loopback suppress*/
807 if (hw->mac.type != fm10k_mac_pf)
809 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
810 if (macvlan->nb_queue_pools)
811 queue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;
812 for (i = 0; i < dev->data->nb_rx_queues; ++i) {
813 if (i && queue_stride && !(i % queue_stride))
815 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);
822 fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
824 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
827 struct fm10k_rx_queue *rxq;
829 PMD_INIT_FUNC_TRACE();
831 if (rx_queue_id < dev->data->nb_rx_queues) {
832 rxq = dev->data->rx_queues[rx_queue_id];
833 err = rx_queue_reset(rxq);
834 if (err == -ENOMEM) {
835 PMD_INIT_LOG(ERR, "Failed to alloc memory : %d", err);
837 } else if (err == -EINVAL) {
838 PMD_INIT_LOG(ERR, "Invalid buffer address alignment :"
843 /* Setup the HW Rx Head and Tail Descriptor Pointers
844 * Note: this must be done AFTER the queue is enabled on real
845 * hardware, but BEFORE the queue is enabled when using the
846 * emulation platform. Do it in both places for now and remove
847 * this comment and the following two register writes when the
848 * emulation platform is no longer being used.
850 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
851 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
853 /* Set PF ownership flag for PF devices */
854 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));
855 if (hw->mac.type == fm10k_mac_pf)
856 reg |= FM10K_RXQCTL_PF;
857 reg |= FM10K_RXQCTL_ENABLE;
858 /* enable RX queue */
859 FM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);
860 FM10K_WRITE_FLUSH(hw);
862 /* Setup the HW Rx Head and Tail Descriptor Pointers
863 * Note: this must be done AFTER the queue is enabled
865 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
866 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
867 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
874 fm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
876 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
878 PMD_INIT_FUNC_TRACE();
880 if (rx_queue_id < dev->data->nb_rx_queues) {
881 /* Disable RX queue */
882 rx_queue_disable(hw, rx_queue_id);
884 /* Free mbuf and clean HW ring */
885 rx_queue_clean(dev->data->rx_queues[rx_queue_id]);
886 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
893 fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
895 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
896 /** @todo - this should be defined in the shared code */
897 #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY 0x00010000
898 uint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;
901 PMD_INIT_FUNC_TRACE();
903 if (tx_queue_id < dev->data->nb_tx_queues) {
904 struct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];
908 /* reset head and tail pointers */
909 FM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);
910 FM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);
912 /* enable TX queue */
913 FM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),
914 FM10K_TXDCTL_ENABLE | txdctl);
915 FM10K_WRITE_FLUSH(hw);
916 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
924 fm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
926 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
928 PMD_INIT_FUNC_TRACE();
930 if (tx_queue_id < dev->data->nb_tx_queues) {
931 tx_queue_disable(hw, tx_queue_id);
932 tx_queue_clean(dev->data->tx_queues[tx_queue_id]);
933 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
939 static inline int fm10k_glort_valid(struct fm10k_hw *hw)
941 return ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)
942 != FM10K_DGLORTMAP_NONE);
946 fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)
948 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
951 PMD_INIT_FUNC_TRACE();
953 /* Return if it didn't acquire valid glort range */
954 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
958 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
959 FM10K_XCAST_MODE_PROMISC);
960 fm10k_mbx_unlock(hw);
962 if (status != FM10K_SUCCESS)
963 PMD_INIT_LOG(ERR, "Failed to enable promiscuous mode");
967 fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)
969 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
973 PMD_INIT_FUNC_TRACE();
975 /* Return if it didn't acquire valid glort range */
976 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
979 if (dev->data->all_multicast == 1)
980 mode = FM10K_XCAST_MODE_ALLMULTI;
982 mode = FM10K_XCAST_MODE_NONE;
985 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
987 fm10k_mbx_unlock(hw);
989 if (status != FM10K_SUCCESS)
990 PMD_INIT_LOG(ERR, "Failed to disable promiscuous mode");
994 fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)
996 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
999 PMD_INIT_FUNC_TRACE();
1001 /* Return if it didn't acquire valid glort range */
1002 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1005 /* If promiscuous mode is enabled, it doesn't make sense to enable
1006 * allmulticast and disable promiscuous since fm10k only can select
1009 if (dev->data->promiscuous) {
1010 PMD_INIT_LOG(INFO, "Promiscuous mode is enabled, "\
1011 "needn't enable allmulticast");
1016 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1017 FM10K_XCAST_MODE_ALLMULTI);
1018 fm10k_mbx_unlock(hw);
1020 if (status != FM10K_SUCCESS)
1021 PMD_INIT_LOG(ERR, "Failed to enable allmulticast mode");
1025 fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)
1027 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1030 PMD_INIT_FUNC_TRACE();
1032 /* Return if it didn't acquire valid glort range */
1033 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1036 if (dev->data->promiscuous) {
1037 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode "\
1038 "since promisc mode is enabled");
1043 /* Change mode to unicast mode */
1044 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1045 FM10K_XCAST_MODE_NONE);
1046 fm10k_mbx_unlock(hw);
1048 if (status != FM10K_SUCCESS)
1049 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode");
1053 fm10k_dev_dglort_map_configure(struct rte_eth_dev *dev)
1055 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1056 uint32_t dglortdec, pool_len, rss_len, i, dglortmask;
1057 uint16_t nb_queue_pools;
1058 struct fm10k_macvlan_filter_info *macvlan;
1060 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1061 nb_queue_pools = macvlan->nb_queue_pools;
1062 pool_len = nb_queue_pools ? fls(nb_queue_pools - 1) : 0;
1063 rss_len = fls(dev->data->nb_rx_queues - 1) - pool_len;
1065 /* GLORT 0x0-0x3F are used by PF and VMDQ, 0x40-0x7F used by FD */
1066 dglortdec = (rss_len << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | pool_len;
1067 dglortmask = (GLORT_PF_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1069 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), dglortmask);
1070 /* Configure VMDQ/RSS DGlort Decoder */
1071 FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0), dglortdec);
1073 /* Flow Director configurations, only queue number is valid. */
1074 dglortdec = fls(dev->data->nb_rx_queues - 1);
1075 dglortmask = (GLORT_FD_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1076 (hw->mac.dglort_map + GLORT_FD_Q_BASE);
1077 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(1), dglortmask);
1078 FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(1), dglortdec);
1080 /* Invalidate all other GLORT entries */
1081 for (i = 2; i < FM10K_DGLORT_COUNT; i++)
1082 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),
1083 FM10K_DGLORTMAP_NONE);
1086 #define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)
1088 fm10k_dev_start(struct rte_eth_dev *dev)
1090 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1093 PMD_INIT_FUNC_TRACE();
1095 /* stop, init, then start the hw */
1096 diag = fm10k_stop_hw(hw);
1097 if (diag != FM10K_SUCCESS) {
1098 PMD_INIT_LOG(ERR, "Hardware stop failed: %d", diag);
1102 diag = fm10k_init_hw(hw);
1103 if (diag != FM10K_SUCCESS) {
1104 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
1108 diag = fm10k_start_hw(hw);
1109 if (diag != FM10K_SUCCESS) {
1110 PMD_INIT_LOG(ERR, "Hardware start failed: %d", diag);
1114 diag = fm10k_dev_tx_init(dev);
1116 PMD_INIT_LOG(ERR, "TX init failed: %d", diag);
1120 if (fm10k_dev_rxq_interrupt_setup(dev))
1123 diag = fm10k_dev_rx_init(dev);
1125 PMD_INIT_LOG(ERR, "RX init failed: %d", diag);
1129 if (hw->mac.type == fm10k_mac_pf)
1130 fm10k_dev_dglort_map_configure(dev);
1132 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1133 struct fm10k_rx_queue *rxq;
1134 rxq = dev->data->rx_queues[i];
1136 if (rxq->rx_deferred_start)
1138 diag = fm10k_dev_rx_queue_start(dev, i);
1141 for (j = 0; j < i; ++j)
1142 rx_queue_clean(dev->data->rx_queues[j]);
1147 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1148 struct fm10k_tx_queue *txq;
1149 txq = dev->data->tx_queues[i];
1151 if (txq->tx_deferred_start)
1153 diag = fm10k_dev_tx_queue_start(dev, i);
1156 for (j = 0; j < i; ++j)
1157 tx_queue_clean(dev->data->tx_queues[j]);
1158 for (j = 0; j < dev->data->nb_rx_queues; ++j)
1159 rx_queue_clean(dev->data->rx_queues[j]);
1164 /* Update default vlan when not in VMDQ mode */
1165 if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
1166 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
1168 fm10k_link_update(dev, 0);
1174 fm10k_dev_stop(struct rte_eth_dev *dev)
1176 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1177 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1180 PMD_INIT_FUNC_TRACE();
1182 if (dev->data->tx_queues)
1183 for (i = 0; i < dev->data->nb_tx_queues; i++)
1184 fm10k_dev_tx_queue_stop(dev, i);
1186 if (dev->data->rx_queues)
1187 for (i = 0; i < dev->data->nb_rx_queues; i++)
1188 fm10k_dev_rx_queue_stop(dev, i);
1190 /* Disable datapath event */
1191 if (rte_intr_dp_is_en(intr_handle)) {
1192 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1193 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
1194 3 << FM10K_RXINT_TIMER_SHIFT);
1195 if (hw->mac.type == fm10k_mac_pf)
1196 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, i)),
1197 FM10K_ITR_MASK_SET);
1199 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, i)),
1200 FM10K_ITR_MASK_SET);
1203 /* Clean datapath event and queue/vec mapping */
1204 rte_intr_efd_disable(intr_handle);
1205 rte_free(intr_handle->intr_vec);
1206 intr_handle->intr_vec = NULL;
1210 fm10k_dev_queue_release(struct rte_eth_dev *dev)
1214 PMD_INIT_FUNC_TRACE();
1216 if (dev->data->tx_queues) {
1217 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1218 struct fm10k_tx_queue *txq = dev->data->tx_queues[i];
1224 if (dev->data->rx_queues) {
1225 for (i = 0; i < dev->data->nb_rx_queues; i++)
1226 fm10k_rx_queue_release(dev->data->rx_queues[i]);
1231 fm10k_dev_close(struct rte_eth_dev *dev)
1233 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1235 PMD_INIT_FUNC_TRACE();
1238 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
1239 MAX_LPORT_NUM, false);
1240 fm10k_mbx_unlock(hw);
1242 /* allow 10ms for device to quiesce */
1243 rte_delay_us(FM10K_SWITCH_QUIESCE_US);
1245 /* Stop mailbox service first */
1246 fm10k_close_mbx_service(hw);
1247 fm10k_dev_stop(dev);
1248 fm10k_dev_queue_release(dev);
1253 fm10k_link_update(struct rte_eth_dev *dev,
1254 __rte_unused int wait_to_complete)
1256 PMD_INIT_FUNC_TRACE();
1258 /* The host-interface link is always up. The speed is ~50Gbps per Gen3
1259 * x8 PCIe interface. For now, we leave the speed undefined since there
1260 * is no 50Gbps Ethernet. */
1261 dev->data->dev_link.link_speed = 0;
1262 dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
1263 dev->data->dev_link.link_status = ETH_LINK_UP;
1268 static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1269 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
1274 if (xstats_names != NULL) {
1275 /* Note: limit checked in rte_eth_xstats_names() */
1278 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1279 snprintf(xstats_names[count].name,
1280 sizeof(xstats_names[count].name),
1281 "%s", fm10k_hw_stats_strings[count].name);
1285 /* PF queue stats */
1286 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1287 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1288 snprintf(xstats_names[count].name,
1289 sizeof(xstats_names[count].name),
1291 fm10k_hw_stats_rx_q_strings[i].name);
1294 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1295 snprintf(xstats_names[count].name,
1296 sizeof(xstats_names[count].name),
1298 fm10k_hw_stats_tx_q_strings[i].name);
1303 return FM10K_NB_XSTATS;
1307 fm10k_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1310 struct fm10k_hw_stats *hw_stats =
1311 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1312 unsigned i, q, count = 0;
1314 if (n < FM10K_NB_XSTATS)
1315 return FM10K_NB_XSTATS;
1318 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1319 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1320 fm10k_hw_stats_strings[count].offset);
1321 xstats[count].id = count;
1325 /* PF queue stats */
1326 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1327 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1328 xstats[count].value =
1329 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1330 fm10k_hw_stats_rx_q_strings[i].offset);
1331 xstats[count].id = count;
1334 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1335 xstats[count].value =
1336 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1337 fm10k_hw_stats_tx_q_strings[i].offset);
1338 xstats[count].id = count;
1343 return FM10K_NB_XSTATS;
1347 fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1349 uint64_t ipackets, opackets, ibytes, obytes;
1350 struct fm10k_hw *hw =
1351 FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352 struct fm10k_hw_stats *hw_stats =
1353 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1356 PMD_INIT_FUNC_TRACE();
1358 fm10k_update_hw_stats(hw, hw_stats);
1360 ipackets = opackets = ibytes = obytes = 0;
1361 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1362 (i < hw->mac.max_queues); ++i) {
1363 stats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;
1364 stats->q_opackets[i] = hw_stats->q[i].tx_packets.count;
1365 stats->q_ibytes[i] = hw_stats->q[i].rx_bytes.count;
1366 stats->q_obytes[i] = hw_stats->q[i].tx_bytes.count;
1367 ipackets += stats->q_ipackets[i];
1368 opackets += stats->q_opackets[i];
1369 ibytes += stats->q_ibytes[i];
1370 obytes += stats->q_obytes[i];
1372 stats->ipackets = ipackets;
1373 stats->opackets = opackets;
1374 stats->ibytes = ibytes;
1375 stats->obytes = obytes;
1379 fm10k_stats_reset(struct rte_eth_dev *dev)
1381 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1382 struct fm10k_hw_stats *hw_stats =
1383 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1385 PMD_INIT_FUNC_TRACE();
1387 memset(hw_stats, 0, sizeof(*hw_stats));
1388 fm10k_rebind_hw_stats(hw, hw_stats);
1392 fm10k_dev_infos_get(struct rte_eth_dev *dev,
1393 struct rte_eth_dev_info *dev_info)
1395 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397 PMD_INIT_FUNC_TRACE();
1399 dev_info->min_rx_bufsize = FM10K_MIN_RX_BUF_SIZE;
1400 dev_info->max_rx_pktlen = FM10K_MAX_PKT_SIZE;
1401 dev_info->max_rx_queues = hw->mac.max_queues;
1402 dev_info->max_tx_queues = hw->mac.max_queues;
1403 dev_info->max_mac_addrs = FM10K_MAX_MACADDR_NUM;
1404 dev_info->max_hash_mac_addrs = 0;
1405 dev_info->max_vfs = dev->pci_dev->max_vfs;
1406 dev_info->vmdq_pool_base = 0;
1407 dev_info->vmdq_queue_base = 0;
1408 dev_info->max_vmdq_pools = ETH_32_POOLS;
1409 dev_info->vmdq_queue_num = FM10K_MAX_QUEUES_PF;
1410 dev_info->rx_offload_capa =
1411 DEV_RX_OFFLOAD_VLAN_STRIP |
1412 DEV_RX_OFFLOAD_IPV4_CKSUM |
1413 DEV_RX_OFFLOAD_UDP_CKSUM |
1414 DEV_RX_OFFLOAD_TCP_CKSUM;
1415 dev_info->tx_offload_capa =
1416 DEV_TX_OFFLOAD_VLAN_INSERT |
1417 DEV_TX_OFFLOAD_IPV4_CKSUM |
1418 DEV_TX_OFFLOAD_UDP_CKSUM |
1419 DEV_TX_OFFLOAD_TCP_CKSUM |
1420 DEV_TX_OFFLOAD_TCP_TSO;
1422 dev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);
1423 dev_info->reta_size = FM10K_MAX_RSS_INDICES;
1425 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1427 .pthresh = FM10K_DEFAULT_RX_PTHRESH,
1428 .hthresh = FM10K_DEFAULT_RX_HTHRESH,
1429 .wthresh = FM10K_DEFAULT_RX_WTHRESH,
1431 .rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),
1435 dev_info->default_txconf = (struct rte_eth_txconf) {
1437 .pthresh = FM10K_DEFAULT_TX_PTHRESH,
1438 .hthresh = FM10K_DEFAULT_TX_HTHRESH,
1439 .wthresh = FM10K_DEFAULT_TX_WTHRESH,
1441 .tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),
1442 .tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),
1443 .txq_flags = FM10K_SIMPLE_TX_FLAG,
1446 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1447 .nb_max = FM10K_MAX_RX_DESC,
1448 .nb_min = FM10K_MIN_RX_DESC,
1449 .nb_align = FM10K_MULT_RX_DESC,
1452 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1453 .nb_max = FM10K_MAX_TX_DESC,
1454 .nb_min = FM10K_MIN_TX_DESC,
1455 .nb_align = FM10K_MULT_TX_DESC,
1458 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
1459 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
1460 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1463 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
1464 static const uint32_t *
1465 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1467 if (dev->rx_pkt_burst == fm10k_recv_pkts ||
1468 dev->rx_pkt_burst == fm10k_recv_scattered_pkts) {
1469 static uint32_t ptypes[] = {
1470 /* refers to rx_desc_to_ol_flags() */
1473 RTE_PTYPE_L3_IPV4_EXT,
1475 RTE_PTYPE_L3_IPV6_EXT,
1482 } else if (dev->rx_pkt_burst == fm10k_recv_pkts_vec ||
1483 dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec) {
1484 static uint32_t ptypes_vec[] = {
1485 /* refers to fm10k_desc_to_pktype_v() */
1487 RTE_PTYPE_L3_IPV4_EXT,
1489 RTE_PTYPE_L3_IPV6_EXT,
1492 RTE_PTYPE_TUNNEL_GENEVE,
1493 RTE_PTYPE_TUNNEL_NVGRE,
1494 RTE_PTYPE_TUNNEL_VXLAN,
1495 RTE_PTYPE_TUNNEL_GRE,
1505 static const uint32_t *
1506 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1513 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1516 uint16_t mac_num = 0;
1517 uint32_t vid_idx, vid_bit, mac_index;
1518 struct fm10k_hw *hw;
1519 struct fm10k_macvlan_filter_info *macvlan;
1520 struct rte_eth_dev_data *data = dev->data;
1522 hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1523 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1525 if (macvlan->nb_queue_pools > 0) { /* VMDQ mode */
1526 PMD_INIT_LOG(ERR, "Cannot change VLAN filter in VMDQ mode");
1530 if (vlan_id > ETH_VLAN_ID_MAX) {
1531 PMD_INIT_LOG(ERR, "Invalid vlan_id: must be < 4096");
1535 vid_idx = FM10K_VFTA_IDX(vlan_id);
1536 vid_bit = FM10K_VFTA_BIT(vlan_id);
1537 /* this VLAN ID is already in the VLAN filter table, return SUCCESS */
1538 if (on && (macvlan->vfta[vid_idx] & vid_bit))
1540 /* this VLAN ID is NOT in the VLAN filter table, cannot remove */
1541 if (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {
1542 PMD_INIT_LOG(ERR, "Invalid vlan_id: not existing "
1543 "in the VLAN filter table");
1548 result = fm10k_update_vlan(hw, vlan_id, 0, on);
1549 fm10k_mbx_unlock(hw);
1550 if (result != FM10K_SUCCESS) {
1551 PMD_INIT_LOG(ERR, "VLAN update failed: %d", result);
1555 for (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&
1556 (result == FM10K_SUCCESS); mac_index++) {
1557 if (is_zero_ether_addr(&data->mac_addrs[mac_index]))
1559 if (mac_num > macvlan->mac_num - 1) {
1560 PMD_INIT_LOG(ERR, "MAC address number "
1565 result = fm10k_update_uc_addr(hw, hw->mac.dglort_map,
1566 data->mac_addrs[mac_index].addr_bytes,
1568 fm10k_mbx_unlock(hw);
1571 if (result != FM10K_SUCCESS) {
1572 PMD_INIT_LOG(ERR, "MAC address update failed: %d", result);
1577 macvlan->vlan_num++;
1578 macvlan->vfta[vid_idx] |= vid_bit;
1580 macvlan->vlan_num--;
1581 macvlan->vfta[vid_idx] &= ~vid_bit;
1587 fm10k_vlan_offload_set(__rte_unused struct rte_eth_dev *dev, int mask)
1589 if (mask & ETH_VLAN_STRIP_MASK) {
1590 if (!dev->data->dev_conf.rxmode.hw_vlan_strip)
1591 PMD_INIT_LOG(ERR, "VLAN stripping is "
1592 "always on in fm10k");
1595 if (mask & ETH_VLAN_EXTEND_MASK) {
1596 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1597 PMD_INIT_LOG(ERR, "VLAN QinQ is not "
1598 "supported in fm10k");
1601 if (mask & ETH_VLAN_FILTER_MASK) {
1602 if (!dev->data->dev_conf.rxmode.hw_vlan_filter)
1603 PMD_INIT_LOG(ERR, "VLAN filter is always on in fm10k");
1607 /* Add/Remove a MAC address, and update filters to main VSI */
1608 static void fm10k_MAC_filter_set_main_vsi(struct rte_eth_dev *dev,
1609 const u8 *mac, bool add, uint32_t pool)
1611 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1612 struct fm10k_macvlan_filter_info *macvlan;
1615 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1617 if (pool != MAIN_VSI_POOL_NUMBER) {
1618 PMD_DRV_LOG(ERR, "VMDQ not enabled, can't set "
1619 "mac to pool %u", pool);
1622 for (i = 0, j = 0; j < FM10K_VFTA_SIZE; j++) {
1623 if (!macvlan->vfta[j])
1625 for (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {
1626 if (!(macvlan->vfta[j] & (1 << k)))
1628 if (i + 1 > macvlan->vlan_num) {
1629 PMD_INIT_LOG(ERR, "vlan number not match");
1633 fm10k_update_uc_addr(hw, hw->mac.dglort_map, mac,
1634 j * FM10K_UINT32_BIT_SIZE + k, add, 0);
1635 fm10k_mbx_unlock(hw);
1641 /* Add/Remove a MAC address, and update filters to VMDQ */
1642 static void fm10k_MAC_filter_set_vmdq(struct rte_eth_dev *dev,
1643 const u8 *mac, bool add, uint32_t pool)
1645 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646 struct fm10k_macvlan_filter_info *macvlan;
1647 struct rte_eth_vmdq_rx_conf *vmdq_conf;
1650 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1651 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1653 if (pool > macvlan->nb_queue_pools) {
1654 PMD_DRV_LOG(ERR, "Pool number %u invalid."
1656 pool, macvlan->nb_queue_pools);
1659 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
1660 if (!(vmdq_conf->pool_map[i].pools & (1UL << pool)))
1663 fm10k_update_uc_addr(hw, hw->mac.dglort_map + pool, mac,
1664 vmdq_conf->pool_map[i].vlan_id, add, 0);
1665 fm10k_mbx_unlock(hw);
1669 /* Add/Remove a MAC address, and update filters */
1670 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
1671 const u8 *mac, bool add, uint32_t pool)
1673 struct fm10k_macvlan_filter_info *macvlan;
1675 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1677 if (macvlan->nb_queue_pools > 0) /* VMDQ mode */
1678 fm10k_MAC_filter_set_vmdq(dev, mac, add, pool);
1680 fm10k_MAC_filter_set_main_vsi(dev, mac, add, pool);
1688 /* Add a MAC address, and update filters */
1690 fm10k_macaddr_add(struct rte_eth_dev *dev,
1691 struct ether_addr *mac_addr,
1695 struct fm10k_macvlan_filter_info *macvlan;
1697 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1698 fm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE, pool);
1699 macvlan->mac_vmdq_id[index] = pool;
1702 /* Remove a MAC address, and update filters */
1704 fm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1706 struct rte_eth_dev_data *data = dev->data;
1707 struct fm10k_macvlan_filter_info *macvlan;
1709 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1710 fm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,
1711 FALSE, macvlan->mac_vmdq_id[index]);
1712 macvlan->mac_vmdq_id[index] = 0;
1716 check_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)
1718 if ((request < min) || (request > max) || ((request % mult) != 0))
1726 check_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)
1728 if ((request < min) || (request > max) || ((div % request) != 0))
1735 handle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)
1737 uint16_t rx_free_thresh;
1739 if (conf->rx_free_thresh == 0)
1740 rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);
1742 rx_free_thresh = conf->rx_free_thresh;
1744 /* make sure the requested threshold satisfies the constraints */
1745 if (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),
1746 FM10K_RX_FREE_THRESH_MAX(q),
1747 FM10K_RX_FREE_THRESH_DIV(q),
1749 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be "
1750 "less than or equal to %u, "
1751 "greater than or equal to %u, "
1752 "and a divisor of %u",
1753 rx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),
1754 FM10K_RX_FREE_THRESH_MIN(q),
1755 FM10K_RX_FREE_THRESH_DIV(q));
1759 q->alloc_thresh = rx_free_thresh;
1760 q->drop_en = conf->rx_drop_en;
1761 q->rx_deferred_start = conf->rx_deferred_start;
1767 * Hardware requires specific alignment for Rx packet buffers. At
1768 * least one of the following two conditions must be satisfied.
1769 * 1. Address is 512B aligned
1770 * 2. Address is 8B aligned and buffer does not cross 4K boundary.
1772 * As such, the driver may need to adjust the DMA address within the
1773 * buffer by up to 512B.
1775 * return 1 if the element size is valid, otherwise return 0.
1778 mempool_element_size_valid(struct rte_mempool *mp)
1782 /* elt_size includes mbuf header and headroom */
1783 min_size = mp->elt_size - sizeof(struct rte_mbuf) -
1784 RTE_PKTMBUF_HEADROOM;
1786 /* account for up to 512B of alignment */
1787 min_size -= FM10K_RX_DATABUF_ALIGN;
1789 /* sanity check for overflow */
1790 if (min_size > mp->elt_size)
1798 fm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1799 uint16_t nb_desc, unsigned int socket_id,
1800 const struct rte_eth_rxconf *conf, struct rte_mempool *mp)
1802 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1803 struct fm10k_dev_info *dev_info =
1804 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
1805 struct fm10k_rx_queue *q;
1806 const struct rte_memzone *mz;
1808 PMD_INIT_FUNC_TRACE();
1810 /* make sure the mempool element size can account for alignment. */
1811 if (!mempool_element_size_valid(mp)) {
1812 PMD_INIT_LOG(ERR, "Error : Mempool element size is too small");
1816 /* make sure a valid number of descriptors have been requested */
1817 if (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,
1818 FM10K_MULT_RX_DESC, nb_desc)) {
1819 PMD_INIT_LOG(ERR, "Number of Rx descriptors (%u) must be "
1820 "less than or equal to %"PRIu32", "
1821 "greater than or equal to %u, "
1822 "and a multiple of %u",
1823 nb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,
1824 FM10K_MULT_RX_DESC);
1829 * if this queue existed already, free the associated memory. The
1830 * queue cannot be reused in case we need to allocate memory on
1831 * different socket than was previously used.
1833 if (dev->data->rx_queues[queue_id] != NULL) {
1834 rx_queue_free(dev->data->rx_queues[queue_id]);
1835 dev->data->rx_queues[queue_id] = NULL;
1838 /* allocate memory for the queue structure */
1839 q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1842 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1848 q->nb_desc = nb_desc;
1849 q->nb_fake_desc = FM10K_MULT_RX_DESC;
1850 q->port_id = dev->data->port_id;
1851 q->queue_id = queue_id;
1852 q->tail_ptr = (volatile uint32_t *)
1853 &((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];
1854 if (handle_rxconf(q, conf))
1857 /* allocate memory for the software ring */
1858 q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1859 (nb_desc + q->nb_fake_desc) * sizeof(struct rte_mbuf *),
1860 RTE_CACHE_LINE_SIZE, socket_id);
1861 if (q->sw_ring == NULL) {
1862 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1868 * allocate memory for the hardware descriptor ring. A memzone large
1869 * enough to hold the maximum ring size is requested to allow for
1870 * resizing in later calls to the queue setup function.
1872 mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_id,
1873 FM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC,
1876 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1877 rte_free(q->sw_ring);
1881 q->hw_ring = mz->addr;
1882 q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1884 /* Check if number of descs satisfied Vector requirement */
1885 if (!rte_is_power_of_2(nb_desc)) {
1886 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
1887 "preconditions - canceling the feature for "
1888 "the whole port[%d]",
1889 q->queue_id, q->port_id);
1890 dev_info->rx_vec_allowed = false;
1892 fm10k_rxq_vec_setup(q);
1894 dev->data->rx_queues[queue_id] = q;
1899 fm10k_rx_queue_release(void *queue)
1901 PMD_INIT_FUNC_TRACE();
1903 rx_queue_free(queue);
1907 handle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)
1909 uint16_t tx_free_thresh;
1910 uint16_t tx_rs_thresh;
1912 /* constraint MACROs require that tx_free_thresh is configured
1913 * before tx_rs_thresh */
1914 if (conf->tx_free_thresh == 0)
1915 tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);
1917 tx_free_thresh = conf->tx_free_thresh;
1919 /* make sure the requested threshold satisfies the constraints */
1920 if (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),
1921 FM10K_TX_FREE_THRESH_MAX(q),
1922 FM10K_TX_FREE_THRESH_DIV(q),
1924 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be "
1925 "less than or equal to %u, "
1926 "greater than or equal to %u, "
1927 "and a divisor of %u",
1928 tx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),
1929 FM10K_TX_FREE_THRESH_MIN(q),
1930 FM10K_TX_FREE_THRESH_DIV(q));
1934 q->free_thresh = tx_free_thresh;
1936 if (conf->tx_rs_thresh == 0)
1937 tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);
1939 tx_rs_thresh = conf->tx_rs_thresh;
1941 q->tx_deferred_start = conf->tx_deferred_start;
1943 /* make sure the requested threshold satisfies the constraints */
1944 if (check_thresh(FM10K_TX_RS_THRESH_MIN(q),
1945 FM10K_TX_RS_THRESH_MAX(q),
1946 FM10K_TX_RS_THRESH_DIV(q),
1948 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be "
1949 "less than or equal to %u, "
1950 "greater than or equal to %u, "
1951 "and a divisor of %u",
1952 tx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),
1953 FM10K_TX_RS_THRESH_MIN(q),
1954 FM10K_TX_RS_THRESH_DIV(q));
1958 q->rs_thresh = tx_rs_thresh;
1964 fm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1965 uint16_t nb_desc, unsigned int socket_id,
1966 const struct rte_eth_txconf *conf)
1968 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1969 struct fm10k_tx_queue *q;
1970 const struct rte_memzone *mz;
1972 PMD_INIT_FUNC_TRACE();
1974 /* make sure a valid number of descriptors have been requested */
1975 if (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,
1976 FM10K_MULT_TX_DESC, nb_desc)) {
1977 PMD_INIT_LOG(ERR, "Number of Tx descriptors (%u) must be "
1978 "less than or equal to %"PRIu32", "
1979 "greater than or equal to %u, "
1980 "and a multiple of %u",
1981 nb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,
1982 FM10K_MULT_TX_DESC);
1987 * if this queue existed already, free the associated memory. The
1988 * queue cannot be reused in case we need to allocate memory on
1989 * different socket than was previously used.
1991 if (dev->data->tx_queues[queue_id] != NULL) {
1992 struct fm10k_tx_queue *txq = dev->data->tx_queues[queue_id];
1995 dev->data->tx_queues[queue_id] = NULL;
1998 /* allocate memory for the queue structure */
1999 q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
2002 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
2007 q->nb_desc = nb_desc;
2008 q->port_id = dev->data->port_id;
2009 q->queue_id = queue_id;
2010 q->txq_flags = conf->txq_flags;
2011 q->ops = &def_txq_ops;
2012 q->tail_ptr = (volatile uint32_t *)
2013 &((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];
2014 if (handle_txconf(q, conf))
2017 /* allocate memory for the software ring */
2018 q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
2019 nb_desc * sizeof(struct rte_mbuf *),
2020 RTE_CACHE_LINE_SIZE, socket_id);
2021 if (q->sw_ring == NULL) {
2022 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
2028 * allocate memory for the hardware descriptor ring. A memzone large
2029 * enough to hold the maximum ring size is requested to allow for
2030 * resizing in later calls to the queue setup function.
2032 mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_id,
2033 FM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC,
2036 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
2037 rte_free(q->sw_ring);
2041 q->hw_ring = mz->addr;
2042 q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2045 * allocate memory for the RS bit tracker. Enough slots to hold the
2046 * descriptor index for each RS bit needing to be set are required.
2048 q->rs_tracker.list = rte_zmalloc_socket("fm10k rs tracker",
2049 ((nb_desc + 1) / q->rs_thresh) *
2051 RTE_CACHE_LINE_SIZE, socket_id);
2052 if (q->rs_tracker.list == NULL) {
2053 PMD_INIT_LOG(ERR, "Cannot allocate RS bit tracker");
2054 rte_free(q->sw_ring);
2059 dev->data->tx_queues[queue_id] = q;
2064 fm10k_tx_queue_release(void *queue)
2066 struct fm10k_tx_queue *q = queue;
2067 PMD_INIT_FUNC_TRACE();
2073 fm10k_reta_update(struct rte_eth_dev *dev,
2074 struct rte_eth_rss_reta_entry64 *reta_conf,
2077 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078 uint16_t i, j, idx, shift;
2082 PMD_INIT_FUNC_TRACE();
2084 if (reta_size > FM10K_MAX_RSS_INDICES) {
2085 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2086 "(%d) doesn't match the number hardware can supported "
2087 "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2092 * Update Redirection Table RETA[n], n=0..31. The redirection table has
2093 * 128-entries in 32 registers
2095 for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2096 idx = i / RTE_RETA_GROUP_SIZE;
2097 shift = i % RTE_RETA_GROUP_SIZE;
2098 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2099 BIT_MASK_PER_UINT32);
2104 if (mask != BIT_MASK_PER_UINT32)
2105 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2107 for (j = 0; j < CHARS_PER_UINT32; j++) {
2108 if (mask & (0x1 << j)) {
2110 reta &= ~(UINT8_MAX << CHAR_BIT * j);
2111 reta |= reta_conf[idx].reta[shift + j] <<
2115 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);
2122 fm10k_reta_query(struct rte_eth_dev *dev,
2123 struct rte_eth_rss_reta_entry64 *reta_conf,
2126 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2127 uint16_t i, j, idx, shift;
2131 PMD_INIT_FUNC_TRACE();
2133 if (reta_size < FM10K_MAX_RSS_INDICES) {
2134 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2135 "(%d) doesn't match the number hardware can supported "
2136 "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2141 * Read Redirection Table RETA[n], n=0..31. The redirection table has
2142 * 128-entries in 32 registers
2144 for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2145 idx = i / RTE_RETA_GROUP_SIZE;
2146 shift = i % RTE_RETA_GROUP_SIZE;
2147 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2148 BIT_MASK_PER_UINT32);
2152 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2153 for (j = 0; j < CHARS_PER_UINT32; j++) {
2154 if (mask & (0x1 << j))
2155 reta_conf[idx].reta[shift + j] = ((reta >>
2156 CHAR_BIT * j) & UINT8_MAX);
2164 fm10k_rss_hash_update(struct rte_eth_dev *dev,
2165 struct rte_eth_rss_conf *rss_conf)
2167 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2168 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2170 uint64_t hf = rss_conf->rss_hf;
2173 PMD_INIT_FUNC_TRACE();
2175 if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2176 FM10K_RSSRK_ENTRIES_PER_REG))
2183 mrqc |= (hf & ETH_RSS_IPV4) ? FM10K_MRQC_IPV4 : 0;
2184 mrqc |= (hf & ETH_RSS_IPV6) ? FM10K_MRQC_IPV6 : 0;
2185 mrqc |= (hf & ETH_RSS_IPV6_EX) ? FM10K_MRQC_IPV6 : 0;
2186 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? FM10K_MRQC_TCP_IPV4 : 0;
2187 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? FM10K_MRQC_TCP_IPV6 : 0;
2188 mrqc |= (hf & ETH_RSS_IPV6_TCP_EX) ? FM10K_MRQC_TCP_IPV6 : 0;
2189 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? FM10K_MRQC_UDP_IPV4 : 0;
2190 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? FM10K_MRQC_UDP_IPV6 : 0;
2191 mrqc |= (hf & ETH_RSS_IPV6_UDP_EX) ? FM10K_MRQC_UDP_IPV6 : 0;
2193 /* If the mapping doesn't fit any supported, return */
2198 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2199 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
2201 FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
2207 fm10k_rss_hash_conf_get(struct rte_eth_dev *dev,
2208 struct rte_eth_rss_conf *rss_conf)
2210 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2211 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2216 PMD_INIT_FUNC_TRACE();
2218 if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2219 FM10K_RSSRK_ENTRIES_PER_REG))
2223 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2224 key[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));
2226 mrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));
2228 hf |= (mrqc & FM10K_MRQC_IPV4) ? ETH_RSS_IPV4 : 0;
2229 hf |= (mrqc & FM10K_MRQC_IPV6) ? ETH_RSS_IPV6 : 0;
2230 hf |= (mrqc & FM10K_MRQC_IPV6) ? ETH_RSS_IPV6_EX : 0;
2231 hf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP : 0;
2232 hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP : 0;
2233 hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX : 0;
2234 hf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP : 0;
2235 hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP : 0;
2236 hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX : 0;
2238 rss_conf->rss_hf = hf;
2244 fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)
2246 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2247 uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2249 /* Bind all local non-queue interrupt to vector 0 */
2250 int_map |= FM10K_MISC_VEC_ID;
2252 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2253 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2254 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2255 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2256 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2257 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2259 /* Enable misc causes */
2260 FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
2261 FM10K_EIMR_ENABLE(THI_FAULT) |
2262 FM10K_EIMR_ENABLE(FUM_FAULT) |
2263 FM10K_EIMR_ENABLE(MAILBOX) |
2264 FM10K_EIMR_ENABLE(SWITCHREADY) |
2265 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
2266 FM10K_EIMR_ENABLE(SRAMERROR) |
2267 FM10K_EIMR_ENABLE(VFLR));
2270 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2271 FM10K_ITR_MASK_CLEAR);
2272 FM10K_WRITE_FLUSH(hw);
2276 fm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)
2278 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2279 uint32_t int_map = FM10K_INT_MAP_DISABLE;
2281 int_map |= FM10K_MISC_VEC_ID;
2283 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2284 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2285 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2286 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2287 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2288 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2290 /* Disable misc causes */
2291 FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |
2292 FM10K_EIMR_DISABLE(THI_FAULT) |
2293 FM10K_EIMR_DISABLE(FUM_FAULT) |
2294 FM10K_EIMR_DISABLE(MAILBOX) |
2295 FM10K_EIMR_DISABLE(SWITCHREADY) |
2296 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
2297 FM10K_EIMR_DISABLE(SRAMERROR) |
2298 FM10K_EIMR_DISABLE(VFLR));
2301 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);
2302 FM10K_WRITE_FLUSH(hw);
2306 fm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)
2308 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2309 uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2311 /* Bind all local non-queue interrupt to vector 0 */
2312 int_map |= FM10K_MISC_VEC_ID;
2314 /* Only INT 0 available, other 15 are reserved. */
2315 FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2318 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2319 FM10K_ITR_MASK_CLEAR);
2320 FM10K_WRITE_FLUSH(hw);
2324 fm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)
2326 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2327 uint32_t int_map = FM10K_INT_MAP_DISABLE;
2329 int_map |= FM10K_MISC_VEC_ID;
2331 /* Only INT 0 available, other 15 are reserved. */
2332 FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2335 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);
2336 FM10K_WRITE_FLUSH(hw);
2340 fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2342 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2345 if (hw->mac.type == fm10k_mac_pf)
2346 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)),
2347 FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2349 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)),
2350 FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2351 rte_intr_enable(&dev->pci_dev->intr_handle);
2356 fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2358 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2361 if (hw->mac.type == fm10k_mac_pf)
2362 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)),
2363 FM10K_ITR_MASK_SET);
2365 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)),
2366 FM10K_ITR_MASK_SET);
2371 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2373 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2374 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2375 uint32_t intr_vector, vec;
2379 /* fm10k needs one separate interrupt for mailbox,
2380 * so only drivers which support multiple interrupt vectors
2381 * e.g. vfio-pci can work for fm10k interrupt mode
2383 if (!rte_intr_cap_multiple(intr_handle) ||
2384 dev->data->dev_conf.intr_conf.rxq == 0)
2387 intr_vector = dev->data->nb_rx_queues;
2389 /* disable interrupt first */
2390 rte_intr_disable(&dev->pci_dev->intr_handle);
2391 if (hw->mac.type == fm10k_mac_pf)
2392 fm10k_dev_disable_intr_pf(dev);
2394 fm10k_dev_disable_intr_vf(dev);
2396 if (rte_intr_efd_enable(intr_handle, intr_vector)) {
2397 PMD_INIT_LOG(ERR, "Failed to init event fd");
2401 if (rte_intr_dp_is_en(intr_handle) && !result) {
2402 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2403 dev->data->nb_rx_queues * sizeof(int), 0);
2404 if (intr_handle->intr_vec) {
2405 for (queue_id = 0, vec = FM10K_RX_VEC_START;
2406 queue_id < dev->data->nb_rx_queues;
2408 intr_handle->intr_vec[queue_id] = vec;
2409 if (vec < intr_handle->nb_efd - 1
2410 + FM10K_RX_VEC_START)
2414 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2415 " intr_vec", dev->data->nb_rx_queues);
2416 rte_intr_efd_disable(intr_handle);
2421 if (hw->mac.type == fm10k_mac_pf)
2422 fm10k_dev_enable_intr_pf(dev);
2424 fm10k_dev_enable_intr_vf(dev);
2425 rte_intr_enable(&dev->pci_dev->intr_handle);
2426 hw->mac.ops.update_int_moderator(hw);
2431 fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)
2433 struct fm10k_fault fault;
2435 const char *estr = "Unknown error";
2437 /* Process PCA fault */
2438 if (eicr & FM10K_EICR_PCA_FAULT) {
2439 err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);
2442 switch (fault.type) {
2444 estr = "PCA_NO_FAULT"; break;
2445 case PCA_UNMAPPED_ADDR:
2446 estr = "PCA_UNMAPPED_ADDR"; break;
2447 case PCA_BAD_QACCESS_PF:
2448 estr = "PCA_BAD_QACCESS_PF"; break;
2449 case PCA_BAD_QACCESS_VF:
2450 estr = "PCA_BAD_QACCESS_VF"; break;
2451 case PCA_MALICIOUS_REQ:
2452 estr = "PCA_MALICIOUS_REQ"; break;
2453 case PCA_POISONED_TLP:
2454 estr = "PCA_POISONED_TLP"; break;
2456 estr = "PCA_TLP_ABORT"; break;
2460 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2461 estr, fault.func ? "VF" : "PF", fault.func,
2462 fault.address, fault.specinfo);
2465 /* Process THI fault */
2466 if (eicr & FM10K_EICR_THI_FAULT) {
2467 err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);
2470 switch (fault.type) {
2472 estr = "THI_NO_FAULT"; break;
2473 case THI_MAL_DIS_Q_FAULT:
2474 estr = "THI_MAL_DIS_Q_FAULT"; break;
2478 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2479 estr, fault.func ? "VF" : "PF", fault.func,
2480 fault.address, fault.specinfo);
2483 /* Process FUM fault */
2484 if (eicr & FM10K_EICR_FUM_FAULT) {
2485 err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);
2488 switch (fault.type) {
2490 estr = "FUM_NO_FAULT"; break;
2491 case FUM_UNMAPPED_ADDR:
2492 estr = "FUM_UNMAPPED_ADDR"; break;
2493 case FUM_POISONED_TLP:
2494 estr = "FUM_POISONED_TLP"; break;
2495 case FUM_BAD_VF_QACCESS:
2496 estr = "FUM_BAD_VF_QACCESS"; break;
2497 case FUM_ADD_DECODE_ERR:
2498 estr = "FUM_ADD_DECODE_ERR"; break;
2500 estr = "FUM_RO_ERROR"; break;
2501 case FUM_QPRC_CRC_ERROR:
2502 estr = "FUM_QPRC_CRC_ERROR"; break;
2503 case FUM_CSR_TIMEOUT:
2504 estr = "FUM_CSR_TIMEOUT"; break;
2505 case FUM_INVALID_TYPE:
2506 estr = "FUM_INVALID_TYPE"; break;
2507 case FUM_INVALID_LENGTH:
2508 estr = "FUM_INVALID_LENGTH"; break;
2509 case FUM_INVALID_BE:
2510 estr = "FUM_INVALID_BE"; break;
2511 case FUM_INVALID_ALIGN:
2512 estr = "FUM_INVALID_ALIGN"; break;
2516 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2517 estr, fault.func ? "VF" : "PF", fault.func,
2518 fault.address, fault.specinfo);
2523 PMD_INIT_LOG(ERR, "Failed to handle fault event.");
2528 * PF interrupt handler triggered by NIC for handling specific interrupt.
2531 * Pointer to interrupt handle.
2533 * The address of parameter (struct rte_eth_dev *) regsitered before.
2539 fm10k_dev_interrupt_handler_pf(
2540 __rte_unused struct rte_intr_handle *handle,
2543 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2544 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2545 uint32_t cause, status;
2547 if (hw->mac.type != fm10k_mac_pf)
2550 cause = FM10K_READ_REG(hw, FM10K_EICR);
2552 /* Handle PCI fault cases */
2553 if (cause & FM10K_EICR_FAULT_MASK) {
2554 PMD_INIT_LOG(ERR, "INT: find fault!");
2555 fm10k_dev_handle_fault(hw, cause);
2558 /* Handle switch up/down */
2559 if (cause & FM10K_EICR_SWITCHNOTREADY)
2560 PMD_INIT_LOG(ERR, "INT: Switch is not ready");
2562 if (cause & FM10K_EICR_SWITCHREADY)
2563 PMD_INIT_LOG(INFO, "INT: Switch is ready");
2565 /* Handle mailbox message */
2567 hw->mbx.ops.process(hw, &hw->mbx);
2568 fm10k_mbx_unlock(hw);
2570 /* Handle SRAM error */
2571 if (cause & FM10K_EICR_SRAMERROR) {
2572 PMD_INIT_LOG(ERR, "INT: SRAM error on PEP");
2574 status = FM10K_READ_REG(hw, FM10K_SRAM_IP);
2575 /* Write to clear pending bits */
2576 FM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);
2578 /* Todo: print out error message after shared code updates */
2581 /* Clear these 3 events if having any */
2582 cause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |
2583 FM10K_EICR_SWITCHREADY;
2585 FM10K_WRITE_REG(hw, FM10K_EICR, cause);
2587 /* Re-enable interrupt from device side */
2588 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2589 FM10K_ITR_MASK_CLEAR);
2590 /* Re-enable interrupt from host side */
2591 rte_intr_enable(&(dev->pci_dev->intr_handle));
2595 * VF interrupt handler triggered by NIC for handling specific interrupt.
2598 * Pointer to interrupt handle.
2600 * The address of parameter (struct rte_eth_dev *) regsitered before.
2606 fm10k_dev_interrupt_handler_vf(
2607 __rte_unused struct rte_intr_handle *handle,
2610 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2611 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2613 if (hw->mac.type != fm10k_mac_vf)
2616 /* Handle mailbox message if lock is acquired */
2618 hw->mbx.ops.process(hw, &hw->mbx);
2619 fm10k_mbx_unlock(hw);
2621 /* Re-enable interrupt from device side */
2622 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2623 FM10K_ITR_MASK_CLEAR);
2624 /* Re-enable interrupt from host side */
2625 rte_intr_enable(&(dev->pci_dev->intr_handle));
2628 /* Mailbox message handler in VF */
2629 static const struct fm10k_msg_data fm10k_msgdata_vf[] = {
2630 FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
2631 FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
2632 FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
2633 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2637 fm10k_setup_mbx_service(struct fm10k_hw *hw)
2641 /* Initialize mailbox lock */
2642 fm10k_mbx_initlock(hw);
2644 /* Replace default message handler with new ones */
2645 if (hw->mac.type == fm10k_mac_vf)
2646 err = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);
2649 PMD_INIT_LOG(ERR, "Failed to register mailbox handler.err:%d",
2653 /* Connect to SM for PF device or PF for VF device */
2654 return hw->mbx.ops.connect(hw, &hw->mbx);
2658 fm10k_close_mbx_service(struct fm10k_hw *hw)
2660 /* Disconnect from SM for PF device or PF for VF device */
2661 hw->mbx.ops.disconnect(hw, &hw->mbx);
2664 static const struct eth_dev_ops fm10k_eth_dev_ops = {
2665 .dev_configure = fm10k_dev_configure,
2666 .dev_start = fm10k_dev_start,
2667 .dev_stop = fm10k_dev_stop,
2668 .dev_close = fm10k_dev_close,
2669 .promiscuous_enable = fm10k_dev_promiscuous_enable,
2670 .promiscuous_disable = fm10k_dev_promiscuous_disable,
2671 .allmulticast_enable = fm10k_dev_allmulticast_enable,
2672 .allmulticast_disable = fm10k_dev_allmulticast_disable,
2673 .stats_get = fm10k_stats_get,
2674 .xstats_get = fm10k_xstats_get,
2675 .xstats_get_names = fm10k_xstats_get_names,
2676 .stats_reset = fm10k_stats_reset,
2677 .xstats_reset = fm10k_stats_reset,
2678 .link_update = fm10k_link_update,
2679 .dev_infos_get = fm10k_dev_infos_get,
2680 .dev_supported_ptypes_get = fm10k_dev_supported_ptypes_get,
2681 .vlan_filter_set = fm10k_vlan_filter_set,
2682 .vlan_offload_set = fm10k_vlan_offload_set,
2683 .mac_addr_add = fm10k_macaddr_add,
2684 .mac_addr_remove = fm10k_macaddr_remove,
2685 .rx_queue_start = fm10k_dev_rx_queue_start,
2686 .rx_queue_stop = fm10k_dev_rx_queue_stop,
2687 .tx_queue_start = fm10k_dev_tx_queue_start,
2688 .tx_queue_stop = fm10k_dev_tx_queue_stop,
2689 .rx_queue_setup = fm10k_rx_queue_setup,
2690 .rx_queue_release = fm10k_rx_queue_release,
2691 .tx_queue_setup = fm10k_tx_queue_setup,
2692 .tx_queue_release = fm10k_tx_queue_release,
2693 .rx_descriptor_done = fm10k_dev_rx_descriptor_done,
2694 .rx_queue_intr_enable = fm10k_dev_rx_queue_intr_enable,
2695 .rx_queue_intr_disable = fm10k_dev_rx_queue_intr_disable,
2696 .reta_update = fm10k_reta_update,
2697 .reta_query = fm10k_reta_query,
2698 .rss_hash_update = fm10k_rss_hash_update,
2699 .rss_hash_conf_get = fm10k_rss_hash_conf_get,
2702 static int ftag_check_handler(__rte_unused const char *key,
2703 const char *value, __rte_unused void *opaque)
2705 if (strcmp(value, "1"))
2712 fm10k_check_ftag(struct rte_devargs *devargs)
2714 struct rte_kvargs *kvlist;
2715 const char *ftag_key = "enable_ftag";
2717 if (devargs == NULL)
2720 kvlist = rte_kvargs_parse(devargs->args, NULL);
2724 if (!rte_kvargs_count(kvlist, ftag_key)) {
2725 rte_kvargs_free(kvlist);
2728 /* FTAG is enabled when there's key-value pair: enable_ftag=1 */
2729 if (rte_kvargs_process(kvlist, ftag_key,
2730 ftag_check_handler, NULL) < 0) {
2731 rte_kvargs_free(kvlist);
2734 rte_kvargs_free(kvlist);
2739 static void __attribute__((cold))
2740 fm10k_set_tx_function(struct rte_eth_dev *dev)
2742 struct fm10k_tx_queue *txq;
2745 uint16_t tx_ftag_en = 0;
2747 if (fm10k_check_ftag(dev->pci_dev->device.devargs))
2750 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2751 txq = dev->data->tx_queues[i];
2752 txq->tx_ftag_en = tx_ftag_en;
2753 /* Check if Vector Tx is satisfied */
2754 if (fm10k_tx_vec_condition_check(txq))
2759 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2760 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2761 txq = dev->data->tx_queues[i];
2762 fm10k_txq_vec_setup(txq);
2764 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2766 dev->tx_pkt_burst = fm10k_xmit_pkts;
2767 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2771 static void __attribute__((cold))
2772 fm10k_set_rx_function(struct rte_eth_dev *dev)
2774 struct fm10k_dev_info *dev_info =
2775 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2776 uint16_t i, rx_using_sse;
2777 uint16_t rx_ftag_en = 0;
2779 if (fm10k_check_ftag(dev->pci_dev->device.devargs))
2782 /* In order to allow Vector Rx there are a few configuration
2783 * conditions to be met.
2785 if (!fm10k_rx_vec_condition_check(dev) &&
2786 dev_info->rx_vec_allowed && !rx_ftag_en) {
2787 if (dev->data->scattered_rx)
2788 dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec;
2790 dev->rx_pkt_burst = fm10k_recv_pkts_vec;
2791 } else if (dev->data->scattered_rx)
2792 dev->rx_pkt_burst = fm10k_recv_scattered_pkts;
2794 dev->rx_pkt_burst = fm10k_recv_pkts;
2797 (dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec ||
2798 dev->rx_pkt_burst == fm10k_recv_pkts_vec);
2801 PMD_INIT_LOG(DEBUG, "Use vector Rx func");
2803 PMD_INIT_LOG(DEBUG, "Use regular Rx func");
2805 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2806 struct fm10k_rx_queue *rxq = dev->data->rx_queues[i];
2808 rxq->rx_using_sse = rx_using_sse;
2809 rxq->rx_ftag_en = rx_ftag_en;
2814 fm10k_params_init(struct rte_eth_dev *dev)
2816 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2817 struct fm10k_dev_info *info =
2818 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2820 /* Inialize bus info. Normally we would call fm10k_get_bus_info(), but
2821 * there is no way to get link status without reading BAR4. Until this
2822 * works, assume we have maximum bandwidth.
2823 * @todo - fix bus info
2825 hw->bus_caps.speed = fm10k_bus_speed_8000;
2826 hw->bus_caps.width = fm10k_bus_width_pcie_x8;
2827 hw->bus_caps.payload = fm10k_bus_payload_512;
2828 hw->bus.speed = fm10k_bus_speed_8000;
2829 hw->bus.width = fm10k_bus_width_pcie_x8;
2830 hw->bus.payload = fm10k_bus_payload_256;
2832 info->rx_vec_allowed = true;
2836 eth_fm10k_dev_init(struct rte_eth_dev *dev)
2838 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2840 struct fm10k_macvlan_filter_info *macvlan;
2842 PMD_INIT_FUNC_TRACE();
2844 dev->dev_ops = &fm10k_eth_dev_ops;
2845 dev->rx_pkt_burst = &fm10k_recv_pkts;
2846 dev->tx_pkt_burst = &fm10k_xmit_pkts;
2848 /* only initialize in the primary process */
2849 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2852 rte_eth_copy_pci_info(dev, dev->pci_dev);
2854 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
2855 memset(macvlan, 0, sizeof(*macvlan));
2856 /* Vendor and Device ID need to be set before init of shared code */
2857 memset(hw, 0, sizeof(*hw));
2858 hw->device_id = dev->pci_dev->id.device_id;
2859 hw->vendor_id = dev->pci_dev->id.vendor_id;
2860 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
2861 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
2862 hw->revision_id = 0;
2863 hw->hw_addr = (void *)dev->pci_dev->mem_resource[0].addr;
2864 if (hw->hw_addr == NULL) {
2865 PMD_INIT_LOG(ERR, "Bad mem resource."
2866 " Try to blacklist unused devices.");
2870 /* Store fm10k_adapter pointer */
2871 hw->back = dev->data->dev_private;
2873 /* Initialize the shared code */
2874 diag = fm10k_init_shared_code(hw);
2875 if (diag != FM10K_SUCCESS) {
2876 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
2880 /* Initialize parameters */
2881 fm10k_params_init(dev);
2883 /* Initialize the hw */
2884 diag = fm10k_init_hw(hw);
2885 if (diag != FM10K_SUCCESS) {
2886 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
2890 /* Initialize MAC address(es) */
2891 dev->data->mac_addrs = rte_zmalloc("fm10k",
2892 ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);
2893 if (dev->data->mac_addrs == NULL) {
2894 PMD_INIT_LOG(ERR, "Cannot allocate memory for MAC addresses");
2898 diag = fm10k_read_mac_addr(hw);
2900 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2901 &dev->data->mac_addrs[0]);
2903 if (diag != FM10K_SUCCESS ||
2904 !is_valid_assigned_ether_addr(dev->data->mac_addrs)) {
2906 /* Generate a random addr */
2907 eth_random_addr(hw->mac.addr);
2908 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
2909 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2910 &dev->data->mac_addrs[0]);
2913 /* Reset the hw statistics */
2914 fm10k_stats_reset(dev);
2917 diag = fm10k_reset_hw(hw);
2918 if (diag != FM10K_SUCCESS) {
2919 PMD_INIT_LOG(ERR, "Hardware reset failed: %d", diag);
2923 /* Setup mailbox service */
2924 diag = fm10k_setup_mbx_service(hw);
2925 if (diag != FM10K_SUCCESS) {
2926 PMD_INIT_LOG(ERR, "Failed to setup mailbox: %d", diag);
2930 /*PF/VF has different interrupt handling mechanism */
2931 if (hw->mac.type == fm10k_mac_pf) {
2932 /* register callback func to eal lib */
2933 rte_intr_callback_register(&(dev->pci_dev->intr_handle),
2934 fm10k_dev_interrupt_handler_pf, (void *)dev);
2936 /* enable MISC interrupt */
2937 fm10k_dev_enable_intr_pf(dev);
2939 rte_intr_callback_register(&(dev->pci_dev->intr_handle),
2940 fm10k_dev_interrupt_handler_vf, (void *)dev);
2942 fm10k_dev_enable_intr_vf(dev);
2945 /* Enable intr after callback registered */
2946 rte_intr_enable(&(dev->pci_dev->intr_handle));
2948 hw->mac.ops.update_int_moderator(hw);
2950 /* Make sure Switch Manager is ready before going forward. */
2951 if (hw->mac.type == fm10k_mac_pf) {
2952 int switch_ready = 0;
2954 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2956 hw->mac.ops.get_host_state(hw, &switch_ready);
2957 fm10k_mbx_unlock(hw);
2960 /* Delay some time to acquire async LPORT_MAP info. */
2961 rte_delay_us(WAIT_SWITCH_MSG_US);
2964 if (switch_ready == 0) {
2965 PMD_INIT_LOG(ERR, "switch is not ready");
2971 * Below function will trigger operations on mailbox, acquire lock to
2972 * avoid race condition from interrupt handler. Operations on mailbox
2973 * FIFO will trigger interrupt to PF/SM, in which interrupt handler
2974 * will handle and generate an interrupt to our side. Then, FIFO in
2975 * mailbox will be touched.
2978 /* Enable port first */
2979 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2982 /* Set unicast mode by default. App can change to other mode in other
2985 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
2986 FM10K_XCAST_MODE_NONE);
2988 fm10k_mbx_unlock(hw);
2990 /* Make sure default VID is ready before going forward. */
2991 if (hw->mac.type == fm10k_mac_pf) {
2992 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2993 if (hw->mac.default_vid)
2995 /* Delay some time to acquire async port VLAN info. */
2996 rte_delay_us(WAIT_SWITCH_MSG_US);
2999 if (!hw->mac.default_vid) {
3000 PMD_INIT_LOG(ERR, "default VID is not ready");
3005 /* Add default mac address */
3006 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
3007 MAIN_VSI_POOL_NUMBER);
3013 eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
3015 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3017 PMD_INIT_FUNC_TRACE();
3019 /* only uninitialize in the primary process */
3020 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3023 /* safe to close dev here */
3024 fm10k_dev_close(dev);
3026 dev->dev_ops = NULL;
3027 dev->rx_pkt_burst = NULL;
3028 dev->tx_pkt_burst = NULL;
3030 /* disable uio/vfio intr */
3031 rte_intr_disable(&(dev->pci_dev->intr_handle));
3033 /*PF/VF has different interrupt handling mechanism */
3034 if (hw->mac.type == fm10k_mac_pf) {
3035 /* disable interrupt */
3036 fm10k_dev_disable_intr_pf(dev);
3038 /* unregister callback func to eal lib */
3039 rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
3040 fm10k_dev_interrupt_handler_pf, (void *)dev);
3042 /* disable interrupt */
3043 fm10k_dev_disable_intr_vf(dev);
3045 rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
3046 fm10k_dev_interrupt_handler_vf, (void *)dev);
3049 /* free mac memory */
3050 if (dev->data->mac_addrs) {
3051 rte_free(dev->data->mac_addrs);
3052 dev->data->mac_addrs = NULL;
3055 memset(hw, 0, sizeof(*hw));
3061 * The set of PCI devices this driver supports. This driver will enable both PF
3062 * and SRIOV-VF devices.
3064 static const struct rte_pci_id pci_id_fm10k_map[] = {
3065 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_PF) },
3066 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_SDI_FM10420_QDA2) },
3067 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_VF) },
3068 { .vendor_id = 0, /* sentinel */ },
3071 static struct eth_driver rte_pmd_fm10k = {
3073 .id_table = pci_id_fm10k_map,
3074 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3075 RTE_PCI_DRV_DETACHABLE,
3076 .probe = rte_eth_dev_pci_probe,
3077 .remove = rte_eth_dev_pci_remove,
3079 .eth_dev_init = eth_fm10k_dev_init,
3080 .eth_dev_uninit = eth_fm10k_dev_uninit,
3081 .dev_private_size = sizeof(struct fm10k_adapter),
3084 RTE_PMD_REGISTER_PCI(net_fm10k, rte_pmd_fm10k.pci_drv);
3085 RTE_PMD_REGISTER_PCI_TABLE(net_fm10k, pci_id_fm10k_map);