drivers/net/i40e/base/i40e_type.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #ifndef _I40E_TYPE_H_
   6 #define _I40E_TYPE_H_
   7
   8 #include "i40e_status.h"
   9 #include "i40e_osdep.h"
  10 #include "i40e_register.h"
  11 #include "i40e_adminq.h"
  12 #include "i40e_hmc.h"
  13 #include "i40e_lan_hmc.h"
  14 #include "i40e_devids.h"
  15
  16 #define UNREFERENCED_XPARAMETER
  17 #define UNREFERENCED_1PARAMETER(_p) (_p);
  18 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  19 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  20 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  21 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  22
  23 #ifndef LINUX_MACROS
  24 #ifndef BIT
  25 #define BIT(a) (1UL << (a))
  26 #endif /* BIT */
  27 #ifndef BIT_ULL
  28 #define BIT_ULL(a) (1ULL << (a))
  29 #endif /* BIT_ULL */
  30 #endif /* LINUX_MACROS */
  31
  32 #ifndef I40E_MASK
  33 /* I40E_MASK is a macro used on 32 bit registers */
  34 #define I40E_MASK(mask, shift) (mask << shift)
  35 #endif
  36
  37 #define I40E_MAX_PF                     16
  38 #define I40E_MAX_PF_VSI                 64
  39 #define I40E_MAX_PF_QP                  128
  40 #define I40E_MAX_VSI_QP                 16
  41 #define I40E_MAX_VF_VSI                 3
  42 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  43 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  44
  45 /* something less than 1 minute */
  46 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  47
  48 /* Max default timeout in ms, */
  49 #define I40E_MAX_NVM_TIMEOUT            18000
  50
  51 /* Max timeout in ms for the phy to respond */
  52 #define I40E_MAX_PHY_TIMEOUT            500
  53
  54 /* Check whether address is multicast. */
  55 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  56
  57 /* Check whether an address is broadcast. */
  58 #define I40E_IS_BROADCAST(address)      \
  59         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  60         (((u8 *)(address))[1] == ((u8)0xff)))
  61
  62 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  63 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  64
  65 /* forward declaration */
  66 struct i40e_hw;
  67 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  68
  69 #ifndef ETH_ALEN
  70 #define ETH_ALEN        6
  71 #endif
  72 /* Data type manipulation macros. */
  73 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  74 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  75
  76 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
  77 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
  78
  79 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
  80 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
  81
  82 /* Number of Transmit Descriptors must be a multiple of 8. */
  83 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
  84 /* Number of Receive Descriptors must be a multiple of 32 if
  85  * the number of descriptors is greater than 32.
  86  */
  87 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
  88
  89 #define I40E_DESC_UNUSED(R)     \
  90         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  91         (R)->next_to_clean - (R)->next_to_use - 1)
  92
  93 /* bitfields for Tx queue mapping in QTX_CTL */
  94 #define I40E_QTX_CTL_VF_QUEUE   0x0
  95 #define I40E_QTX_CTL_VM_QUEUE   0x1
  96 #define I40E_QTX_CTL_PF_QUEUE   0x2
  97
  98 /* debug masks - set these bits in hw->debug_mask to control output */
  99 enum i40e_debug_mask {
 100         I40E_DEBUG_INIT                 = 0x00000001,
 101         I40E_DEBUG_RELEASE              = 0x00000002,
 102
 103         I40E_DEBUG_LINK                 = 0x00000010,
 104         I40E_DEBUG_PHY                  = 0x00000020,
 105         I40E_DEBUG_HMC                  = 0x00000040,
 106         I40E_DEBUG_NVM                  = 0x00000080,
 107         I40E_DEBUG_LAN                  = 0x00000100,
 108         I40E_DEBUG_FLOW                 = 0x00000200,
 109         I40E_DEBUG_DCB                  = 0x00000400,
 110         I40E_DEBUG_DIAG                 = 0x00000800,
 111         I40E_DEBUG_FD                   = 0x00001000,
 112         I40E_DEBUG_PACKAGE              = 0x00002000,
 113
 114         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 115         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 116         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 117         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 118         I40E_DEBUG_AQ                   = 0x0F000000,
 119
 120         I40E_DEBUG_USER                 = 0xF0000000,
 121
 122         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 123 };
 124
 125 /* PCI Bus Info */
 126 #define I40E_PCI_LINK_STATUS            0xB2
 127 #define I40E_PCI_LINK_WIDTH             0x3F0
 128 #define I40E_PCI_LINK_WIDTH_1           0x10
 129 #define I40E_PCI_LINK_WIDTH_2           0x20
 130 #define I40E_PCI_LINK_WIDTH_4           0x40
 131 #define I40E_PCI_LINK_WIDTH_8           0x80
 132 #define I40E_PCI_LINK_SPEED             0xF
 133 #define I40E_PCI_LINK_SPEED_2500        0x1
 134 #define I40E_PCI_LINK_SPEED_5000        0x2
 135 #define I40E_PCI_LINK_SPEED_8000        0x3
 136
 137 #define I40E_MDIO_CLAUSE22_STCODE_MASK  I40E_MASK(1, \
 138                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 139 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_MASK(1, \
 140                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 141 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_MASK(2, \
 142                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 143
 144 #define I40E_MDIO_CLAUSE45_STCODE_MASK  I40E_MASK(0, \
 145                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 146 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_MASK(0, \
 147                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 148 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_MASK(1, \
 149                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 150 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    I40E_MASK(2, \
 151                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 152 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_MASK(3, \
 153                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 154
 155 #define I40E_PHY_COM_REG_PAGE                   0x1E
 156 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 157 #define I40E_PHY_LED_MANUAL_ON                  0x100
 158 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 159 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 160 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 161
 162 /* Memory types */
 163 enum i40e_memset_type {
 164         I40E_NONDMA_MEM = 0,
 165         I40E_DMA_MEM
 166 };
 167
 168 /* Memcpy types */
 169 enum i40e_memcpy_type {
 170         I40E_NONDMA_TO_NONDMA = 0,
 171         I40E_NONDMA_TO_DMA,
 172         I40E_DMA_TO_DMA,
 173         I40E_DMA_TO_NONDMA
 174 };
 175
 176 /* These are structs for managing the hardware information and the operations.
 177  * The structures of function pointers are filled out at init time when we
 178  * know for sure exactly which hardware we're working with.  This gives us the
 179  * flexibility of using the same main driver code but adapting to slightly
 180  * different hardware needs as new parts are developed.  For this architecture,
 181  * the Firmware and AdminQ are intended to insulate the driver from most of the
 182  * future changes, but these structures will also do part of the job.
 183  */
 184 enum i40e_mac_type {
 185         I40E_MAC_UNKNOWN = 0,
 186         I40E_MAC_XL710,
 187         I40E_MAC_VF,
 188         I40E_MAC_X722,
 189         I40E_MAC_X722_VF,
 190         I40E_MAC_GENERIC,
 191 };
 192
 193 enum i40e_media_type {
 194         I40E_MEDIA_TYPE_UNKNOWN = 0,
 195         I40E_MEDIA_TYPE_FIBER,
 196         I40E_MEDIA_TYPE_BASET,
 197         I40E_MEDIA_TYPE_BACKPLANE,
 198         I40E_MEDIA_TYPE_CX4,
 199         I40E_MEDIA_TYPE_DA,
 200         I40E_MEDIA_TYPE_VIRTUAL
 201 };
 202
 203 enum i40e_fc_mode {
 204         I40E_FC_NONE = 0,
 205         I40E_FC_RX_PAUSE,
 206         I40E_FC_TX_PAUSE,
 207         I40E_FC_FULL,
 208         I40E_FC_PFC,
 209         I40E_FC_DEFAULT
 210 };
 211
 212 enum i40e_set_fc_aq_failures {
 213         I40E_SET_FC_AQ_FAIL_NONE = 0,
 214         I40E_SET_FC_AQ_FAIL_GET = 1,
 215         I40E_SET_FC_AQ_FAIL_SET = 2,
 216         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 217         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 218 };
 219
 220 enum i40e_vsi_type {
 221         I40E_VSI_MAIN   = 0,
 222         I40E_VSI_VMDQ1  = 1,
 223         I40E_VSI_VMDQ2  = 2,
 224         I40E_VSI_CTRL   = 3,
 225         I40E_VSI_FCOE   = 4,
 226         I40E_VSI_MIRROR = 5,
 227         I40E_VSI_SRIOV  = 6,
 228         I40E_VSI_FDIR   = 7,
 229         I40E_VSI_TYPE_UNKNOWN
 230 };
 231
 232 enum i40e_queue_type {
 233         I40E_QUEUE_TYPE_RX = 0,
 234         I40E_QUEUE_TYPE_TX,
 235         I40E_QUEUE_TYPE_PE_CEQ,
 236         I40E_QUEUE_TYPE_UNKNOWN
 237 };
 238
 239 struct i40e_link_status {
 240         enum i40e_aq_phy_type phy_type;
 241         enum i40e_aq_link_speed link_speed;
 242         u8 link_info;
 243         u8 an_info;
 244         u8 req_fec_info;
 245         u8 fec_info;
 246         u8 ext_info;
 247         u8 loopback;
 248         /* is Link Status Event notification to SW enabled */
 249         bool lse_enable;
 250         u16 max_frame_size;
 251         bool crc_enable;
 252         u8 pacing;
 253         u8 requested_speeds;
 254         u8 module_type[3];
 255         /* 1st byte: module identifier */
 256 #define I40E_MODULE_TYPE_SFP            0x03
 257 #define I40E_MODULE_TYPE_QSFP           0x0D
 258         /* 2nd byte: ethernet compliance codes for 10/40G */
 259 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 260 #define I40E_MODULE_TYPE_40G_LR4        0x02
 261 #define I40E_MODULE_TYPE_40G_SR4        0x04
 262 #define I40E_MODULE_TYPE_40G_CR4        0x08
 263 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 264 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 265 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 266 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 267         /* 3rd byte: ethernet compliance codes for 1G */
 268 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 269 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 270 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 271 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 272 };
 273
 274 struct i40e_phy_info {
 275         struct i40e_link_status link_info;
 276         struct i40e_link_status link_info_old;
 277         bool get_link_info;
 278         enum i40e_media_type media_type;
 279         /* all the phy types the NVM is capable of */
 280         u64 phy_types;
 281 };
 282
 283 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 284 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 285 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 286 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 287 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 288 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 289 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 290 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 291 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 292 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 293 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 294 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 295 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 296 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 297 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 298 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 299 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 300 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 301 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 302 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 303 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 304 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 305 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 306 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 307 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 308 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 309 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 310                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 311 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 312 /*
 313  * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
 314  * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
 315  * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
 316  * a shift is needed to adjust for this with values larger than 31. The
 317  * only affected values are I40E_PHY_TYPE_25GBASE_*.
 318  */
 319 #define I40E_PHY_TYPE_OFFSET 1
 320 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
 321                                              I40E_PHY_TYPE_OFFSET)
 322 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
 323                                              I40E_PHY_TYPE_OFFSET)
 324 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
 325                                              I40E_PHY_TYPE_OFFSET)
 326 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
 327                                              I40E_PHY_TYPE_OFFSET)
 328 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
 329                                              I40E_PHY_TYPE_OFFSET)
 330 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
 331                                              I40E_PHY_TYPE_OFFSET)
 332 #ifdef CARLSVILLE_HW
 333 /* Offset for 2.5G/5G PHY Types value to bit number conversion */
 334 #define I40E_PHY_TYPE_OFFSET2 (-10)
 335 #define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \
 336                                              I40E_PHY_TYPE_OFFSET2)
 337 #define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \
 338                                              I40E_PHY_TYPE_OFFSET2)
 339 #endif
 340 #define I40E_HW_CAP_MAX_GPIO                    30
 341 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 342 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 343
 344 enum i40e_acpi_programming_method {
 345         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 346         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 347 };
 348
 349 #define I40E_WOL_SUPPORT_MASK                   0x1
 350 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       0x2
 351 #define I40E_PROXY_SUPPORT_MASK                 0x4
 352
 353 /* Capabilities of a PF or a VF or the whole device */
 354 struct i40e_hw_capabilities {
 355         u32  switch_mode;
 356 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 357 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 358 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 359
 360         /* Cloud filter modes:
 361          * Mode1: Filter on L4 port only
 362          * Mode2: Filter for non-tunneled traffic
 363          * Mode3: Filter for tunnel traffic
 364          */
 365 #define I40E_CLOUD_FILTER_MODE1 0x6
 366 #define I40E_CLOUD_FILTER_MODE2 0x7
 367 #define I40E_CLOUD_FILTER_MODE3 0x8
 368 #define I40E_SWITCH_MODE_MASK   0xF
 369
 370         u32  management_mode;
 371         u32  mng_protocols_over_mctp;
 372 #define I40E_MNG_PROTOCOL_PLDM          0x2
 373 #define I40E_MNG_PROTOCOL_OEM_COMMANDS  0x4
 374 #define I40E_MNG_PROTOCOL_NCSI          0x8
 375         u32  npar_enable;
 376         u32  os2bmc;
 377         u32  valid_functions;
 378         bool sr_iov_1_1;
 379         bool vmdq;
 380         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 381         bool evb_802_1_qbh; /* Bridge Port Extension */
 382         bool dcb;
 383         bool fcoe;
 384         bool iscsi; /* Indicates iSCSI enabled */
 385         bool flex10_enable;
 386         bool flex10_capable;
 387         u32  flex10_mode;
 388 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 389 #define I40E_FLEX10_MODE_DCC            0x1
 390 #define I40E_FLEX10_MODE_DCI            0x2
 391
 392         u32 flex10_status;
 393 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 394 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 395
 396         bool sec_rev_disabled;
 397         bool update_disabled;
 398 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 399 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 400
 401         bool mgmt_cem;
 402         bool ieee_1588;
 403         bool iwarp;
 404         bool fd;
 405         u32 fd_filters_guaranteed;
 406         u32 fd_filters_best_effort;
 407         bool rss;
 408         u32 rss_table_size;
 409         u32 rss_table_entry_width;
 410         bool led[I40E_HW_CAP_MAX_GPIO];
 411         bool sdp[I40E_HW_CAP_MAX_GPIO];
 412         u32 nvm_image_type;
 413         u32 num_flow_director_filters;
 414         u32 num_vfs;
 415         u32 vf_base_id;
 416         u32 num_vsis;
 417         u32 num_rx_qp;
 418         u32 num_tx_qp;
 419         u32 base_queue;
 420         u32 num_msix_vectors;
 421         u32 num_msix_vectors_vf;
 422         u32 led_pin_num;
 423         u32 sdp_pin_num;
 424         u32 mdio_port_num;
 425         u32 mdio_port_mode;
 426         u8 rx_buf_chain_len;
 427         u32 enabled_tcmap;
 428         u32 maxtc;
 429         u64 wr_csr_prot;
 430         bool apm_wol_support;
 431         enum i40e_acpi_programming_method acpi_prog_method;
 432         bool proxy_support;
 433 };
 434
 435 struct i40e_mac_info {
 436         enum i40e_mac_type type;
 437         u8 addr[ETH_ALEN];
 438         u8 perm_addr[ETH_ALEN];
 439         u8 san_addr[ETH_ALEN];
 440         u8 port_addr[ETH_ALEN];
 441         u16 max_fcoeq;
 442 };
 443
 444 enum i40e_aq_resources_ids {
 445         I40E_NVM_RESOURCE_ID = 1
 446 };
 447
 448 enum i40e_aq_resource_access_type {
 449         I40E_RESOURCE_READ = 1,
 450         I40E_RESOURCE_WRITE
 451 };
 452
 453 struct i40e_nvm_info {
 454         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 455         u32 timeout;              /* [ms] */
 456         u16 sr_size;              /* Shadow RAM size in words */
 457         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 458         u16 version;              /* NVM package version */
 459         u32 eetrack;              /* NVM data version */
 460         u32 oem_ver;              /* OEM version info */
 461 };
 462
 463 /* definitions used in NVM update support */
 464
 465 enum i40e_nvmupd_cmd {
 466         I40E_NVMUPD_INVALID,
 467         I40E_NVMUPD_READ_CON,
 468         I40E_NVMUPD_READ_SNT,
 469         I40E_NVMUPD_READ_LCB,
 470         I40E_NVMUPD_READ_SA,
 471         I40E_NVMUPD_WRITE_ERA,
 472         I40E_NVMUPD_WRITE_CON,
 473         I40E_NVMUPD_WRITE_SNT,
 474         I40E_NVMUPD_WRITE_LCB,
 475         I40E_NVMUPD_WRITE_SA,
 476         I40E_NVMUPD_CSUM_CON,
 477         I40E_NVMUPD_CSUM_SA,
 478         I40E_NVMUPD_CSUM_LCB,
 479         I40E_NVMUPD_STATUS,
 480         I40E_NVMUPD_EXEC_AQ,
 481         I40E_NVMUPD_GET_AQ_RESULT,
 482         I40E_NVMUPD_GET_AQ_EVENT,
 483 };
 484
 485 enum i40e_nvmupd_state {
 486         I40E_NVMUPD_STATE_INIT,
 487         I40E_NVMUPD_STATE_READING,
 488         I40E_NVMUPD_STATE_WRITING,
 489         I40E_NVMUPD_STATE_INIT_WAIT,
 490         I40E_NVMUPD_STATE_WRITE_WAIT,
 491         I40E_NVMUPD_STATE_ERROR
 492 };
 493
 494 /* nvm_access definition and its masks/shifts need to be accessible to
 495  * application, core driver, and shared code.  Where is the right file?
 496  */
 497 #define I40E_NVM_READ   0xB
 498 #define I40E_NVM_WRITE  0xC
 499
 500 #define I40E_NVM_MOD_PNT_MASK 0xFF
 501
 502 #define I40E_NVM_TRANS_SHIFT                    8
 503 #define I40E_NVM_TRANS_MASK                     (0xf << I40E_NVM_TRANS_SHIFT)
 504 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT       12
 505 #define I40E_NVM_PRESERVATION_FLAGS_MASK \
 506                                 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
 507 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED    0x01
 508 #define I40E_NVM_PRESERVATION_FLAGS_ALL         0x02
 509 #define I40E_NVM_CON                            0x0
 510 #define I40E_NVM_SNT                            0x1
 511 #define I40E_NVM_LCB                            0x2
 512 #define I40E_NVM_SA                             (I40E_NVM_SNT | I40E_NVM_LCB)
 513 #define I40E_NVM_ERA                            0x4
 514 #define I40E_NVM_CSUM                           0x8
 515 #define I40E_NVM_AQE                            0xe
 516 #define I40E_NVM_EXEC                           0xf
 517
 518 #define I40E_NVM_ADAPT_SHIFT    16
 519 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 520
 521 #define I40E_NVMUPD_MAX_DATA    4096
 522 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 523
 524 struct i40e_nvm_access {
 525         u32 command;
 526         u32 config;
 527         u32 offset;     /* in bytes */
 528         u32 data_size;  /* in bytes */
 529         u8 data[1];
 530 };
 531
 532 /* (Q)SFP module access definitions */
 533 #define I40E_I2C_EEPROM_DEV_ADDR        0xA0
 534 #define I40E_I2C_EEPROM_DEV_ADDR2       0xA2
 535 #define I40E_MODULE_TYPE_ADDR           0x00
 536 #define I40E_MODULE_REVISION_ADDR       0x01
 537 #define I40E_MODULE_SFF_8472_COMP       0x5E
 538 #define I40E_MODULE_SFF_8472_SWAP       0x5C
 539 #define I40E_MODULE_SFF_ADDR_MODE       0x04
 540 #define I40E_MODULE_SFF_DIAG_CAPAB      0x40
 541 #define I40E_MODULE_TYPE_QSFP_PLUS      0x0D
 542 #define I40E_MODULE_TYPE_QSFP28         0x11
 543 #define I40E_MODULE_QSFP_MAX_LEN        640
 544
 545 /* PCI bus types */
 546 enum i40e_bus_type {
 547         i40e_bus_type_unknown = 0,
 548         i40e_bus_type_pci,
 549         i40e_bus_type_pcix,
 550         i40e_bus_type_pci_express,
 551         i40e_bus_type_reserved
 552 };
 553
 554 /* PCI bus speeds */
 555 enum i40e_bus_speed {
 556         i40e_bus_speed_unknown  = 0,
 557         i40e_bus_speed_33       = 33,
 558         i40e_bus_speed_66       = 66,
 559         i40e_bus_speed_100      = 100,
 560         i40e_bus_speed_120      = 120,
 561         i40e_bus_speed_133      = 133,
 562         i40e_bus_speed_2500     = 2500,
 563         i40e_bus_speed_5000     = 5000,
 564         i40e_bus_speed_8000     = 8000,
 565         i40e_bus_speed_reserved
 566 };
 567
 568 /* PCI bus widths */
 569 enum i40e_bus_width {
 570         i40e_bus_width_unknown  = 0,
 571         i40e_bus_width_pcie_x1  = 1,
 572         i40e_bus_width_pcie_x2  = 2,
 573         i40e_bus_width_pcie_x4  = 4,
 574         i40e_bus_width_pcie_x8  = 8,
 575         i40e_bus_width_32       = 32,
 576         i40e_bus_width_64       = 64,
 577         i40e_bus_width_reserved
 578 };
 579
 580 /* Bus parameters */
 581 struct i40e_bus_info {
 582         enum i40e_bus_speed speed;
 583         enum i40e_bus_width width;
 584         enum i40e_bus_type type;
 585
 586         u16 func;
 587         u16 device;
 588         u16 lan_id;
 589         u16 bus_id;
 590 };
 591
 592 /* Flow control (FC) parameters */
 593 struct i40e_fc_info {
 594         enum i40e_fc_mode current_mode; /* FC mode in effect */
 595         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 596 };
 597
 598 #define I40E_MAX_TRAFFIC_CLASS          8
 599 #define I40E_MAX_USER_PRIORITY          8
 600 #define I40E_DCBX_MAX_APPS              32
 601 #define I40E_LLDPDU_SIZE                1500
 602 #define I40E_TLV_STATUS_OPER            0x1
 603 #define I40E_TLV_STATUS_SYNC            0x2
 604 #define I40E_TLV_STATUS_ERR             0x4
 605 #define I40E_CEE_OPER_MAX_APPS          3
 606 #define I40E_APP_PROTOID_FCOE           0x8906
 607 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 608 #define I40E_APP_PROTOID_FIP            0x8914
 609 #define I40E_APP_SEL_ETHTYPE            0x1
 610 #define I40E_APP_SEL_TCPIP              0x2
 611 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 612 #define I40E_CEE_APP_SEL_TCPIP          0x1
 613
 614 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 615 struct i40e_dcb_ets_config {
 616         u8 willing;
 617         u8 cbs;
 618         u8 maxtcs;
 619         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 620         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 621         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 622 };
 623
 624 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 625 struct i40e_dcb_pfc_config {
 626         u8 willing;
 627         u8 mbc;
 628         u8 pfccap;
 629         u8 pfcenable;
 630 };
 631
 632 /* CEE or IEEE 802.1Qaz Application Priority data */
 633 struct i40e_dcb_app_priority_table {
 634         u8  priority;
 635         u8  selector;
 636         u16 protocolid;
 637 };
 638
 639 struct i40e_dcbx_config {
 640         u8  dcbx_mode;
 641 #define I40E_DCBX_MODE_CEE      0x1
 642 #define I40E_DCBX_MODE_IEEE     0x2
 643         u8  app_mode;
 644 #define I40E_DCBX_APPS_NON_WILLING      0x1
 645         u32 numapps;
 646         u32 tlv_status; /* CEE mode TLV status */
 647         struct i40e_dcb_ets_config etscfg;
 648         struct i40e_dcb_ets_config etsrec;
 649         struct i40e_dcb_pfc_config pfc;
 650         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 651 };
 652
 653 /* Port hardware description */
 654 struct i40e_hw {
 655         u8 *hw_addr;
 656         void *back;
 657
 658         /* subsystem structs */
 659         struct i40e_phy_info phy;
 660         struct i40e_mac_info mac;
 661         struct i40e_bus_info bus;
 662         struct i40e_nvm_info nvm;
 663         struct i40e_fc_info fc;
 664
 665         /* pci info */
 666         u16 device_id;
 667         u16 vendor_id;
 668         u16 subsystem_device_id;
 669         u16 subsystem_vendor_id;
 670         u8 revision_id;
 671         u8 port;
 672         bool adapter_stopped;
 673         bool adapter_closed;
 674
 675         /* capabilities for entire device and PCI func */
 676         struct i40e_hw_capabilities dev_caps;
 677         struct i40e_hw_capabilities func_caps;
 678
 679         /* Flow Director shared filter space */
 680         u16 fdir_shared_filter_count;
 681
 682         /* device profile info */
 683         u8  pf_id;
 684         u16 main_vsi_seid;
 685
 686         /* for multi-function MACs */
 687         u16 partition_id;
 688         u16 num_partitions;
 689         u16 num_ports;
 690
 691         /* Closest numa node to the device */
 692         u16 numa_node;
 693
 694         /* Admin Queue info */
 695         struct i40e_adminq_info aq;
 696
 697         /* state of nvm update process */
 698         enum i40e_nvmupd_state nvmupd_state;
 699         struct i40e_aq_desc nvm_wb_desc;
 700         struct i40e_aq_desc nvm_aq_event_desc;
 701         struct i40e_virt_mem nvm_buff;
 702         bool nvm_release_on_done;
 703         u16 nvm_wait_opcode;
 704
 705         /* HMC info */
 706         struct i40e_hmc_info hmc; /* HMC info struct */
 707
 708         /* LLDP/DCBX Status */
 709         u16 dcbx_status;
 710
 711         /* DCBX info */
 712         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 713         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 714         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 715
 716         /* WoL and proxy support */
 717         u16 num_wol_proxy_filters;
 718         u16 wol_proxy_vsi_seid;
 719
 720 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 721 #define I40E_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)
 722 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
 723 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
 724 #define I40E_HW_FLAG_FW_LLDP_STOPPABLE      BIT_ULL(4)
 725         u64 flags;
 726
 727         /* Used in set switch config AQ command */
 728         u16 switch_tag;
 729         u16 first_tag;
 730         u16 second_tag;
 731
 732         /* debug mask */
 733         u32 debug_mask;
 734         char err_str[16];
 735 };
 736
 737 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
 738 {
 739         return (hw->mac.type == I40E_MAC_VF ||
 740                 hw->mac.type == I40E_MAC_X722_VF);
 741 }
 742
 743 struct i40e_driver_version {
 744         u8 major_version;
 745         u8 minor_version;
 746         u8 build_version;
 747         u8 subbuild_version;
 748         u8 driver_string[32];
 749 };
 750
 751 /* RX Descriptors */
 752 union i40e_16byte_rx_desc {
 753         struct {
 754                 __le64 pkt_addr; /* Packet buffer address */
 755                 __le64 hdr_addr; /* Header buffer address */
 756         } read;
 757         struct {
 758                 struct {
 759                         struct {
 760                                 union {
 761                                         __le16 mirroring_status;
 762                                         __le16 fcoe_ctx_id;
 763                                 } mirr_fcoe;
 764                                 __le16 l2tag1;
 765                         } lo_dword;
 766                         union {
 767                                 __le32 rss; /* RSS Hash */
 768                                 __le32 fd_id; /* Flow director filter id */
 769                                 __le32 fcoe_param; /* FCoE DDP Context id */
 770                         } hi_dword;
 771                 } qword0;
 772                 struct {
 773                         /* ext status/error/pktype/length */
 774                         __le64 status_error_len;
 775                 } qword1;
 776         } wb;  /* writeback */
 777 };
 778
 779 union i40e_32byte_rx_desc {
 780         struct {
 781                 __le64  pkt_addr; /* Packet buffer address */
 782                 __le64  hdr_addr; /* Header buffer address */
 783                         /* bit 0 of hdr_buffer_addr is DD bit */
 784                 __le64  rsvd1;
 785                 __le64  rsvd2;
 786         } read;
 787         struct {
 788                 struct {
 789                         struct {
 790                                 union {
 791                                         __le16 mirroring_status;
 792                                         __le16 fcoe_ctx_id;
 793                                 } mirr_fcoe;
 794                                 __le16 l2tag1;
 795                         } lo_dword;
 796                         union {
 797                                 __le32 rss; /* RSS Hash */
 798                                 __le32 fcoe_param; /* FCoE DDP Context id */
 799                                 /* Flow director filter id in case of
 800                                  * Programming status desc WB
 801                                  */
 802                                 __le32 fd_id;
 803                         } hi_dword;
 804                 } qword0;
 805                 struct {
 806                         /* status/error/pktype/length */
 807                         __le64 status_error_len;
 808                 } qword1;
 809                 struct {
 810                         __le16 ext_status; /* extended status */
 811                         __le16 rsvd;
 812                         __le16 l2tag2_1;
 813                         __le16 l2tag2_2;
 814                 } qword2;
 815                 struct {
 816                         union {
 817                                 __le32 flex_bytes_lo;
 818                                 __le32 pe_status;
 819                         } lo_dword;
 820                         union {
 821                                 __le32 flex_bytes_hi;
 822                                 __le32 fd_id;
 823                         } hi_dword;
 824                 } qword3;
 825         } wb;  /* writeback */
 826 };
 827
 828 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 829 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 830                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 831 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 832 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 833                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 834
 835 enum i40e_rx_desc_status_bits {
 836         /* Note: These are predefined bit offsets */
 837         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 838         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 839         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 840         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 841         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 842         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 843         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 844         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 845
 846         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 847         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 848         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 849         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 850         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 851         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 852         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 853         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 854 };
 855
 856 #define I40E_RXD_QW1_STATUS_SHIFT       0
 857 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 858                                          I40E_RXD_QW1_STATUS_SHIFT)
 859
 860 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 861 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 862                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 863
 864 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 865 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 866
 867 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 868 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 869                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 870
 871 enum i40e_rx_desc_fltstat_values {
 872         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 873         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 874         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 875         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 876 };
 877
 878 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 879 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 880 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 881 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 882
 883 #define I40E_RXD_QW1_ERROR_SHIFT        19
 884 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 885
 886 enum i40e_rx_desc_error_bits {
 887         /* Note: These are predefined bit offsets */
 888         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 889         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 890         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 891         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 892         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 893         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 894         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 895         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 896         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 897 };
 898
 899 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 900         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 901         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 902         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 903         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 904         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 905 };
 906
 907 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 908 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 909
 910 /* Packet type non-ip values */
 911 enum i40e_rx_l2_ptype {
 912         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 913         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 914         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 915         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 916         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 917         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 918         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 919         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 920         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 921         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 922         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 923         I40E_RX_PTYPE_L2_ARP                            = 11,
 924         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 925         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 926         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 927         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 928         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 929         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 930         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 931         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 932         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 933         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 934         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 935         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 936         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 937         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 938 };
 939
 940 struct i40e_rx_ptype_decoded {
 941         u32 ptype:8;
 942         u32 known:1;
 943         u32 outer_ip:1;
 944         u32 outer_ip_ver:1;
 945         u32 outer_frag:1;
 946         u32 tunnel_type:3;
 947         u32 tunnel_end_prot:2;
 948         u32 tunnel_end_frag:1;
 949         u32 inner_prot:4;
 950         u32 payload_layer:3;
 951 };
 952
 953 enum i40e_rx_ptype_outer_ip {
 954         I40E_RX_PTYPE_OUTER_L2  = 0,
 955         I40E_RX_PTYPE_OUTER_IP  = 1
 956 };
 957
 958 enum i40e_rx_ptype_outer_ip_ver {
 959         I40E_RX_PTYPE_OUTER_NONE        = 0,
 960         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 961         I40E_RX_PTYPE_OUTER_IPV6        = 1
 962 };
 963
 964 enum i40e_rx_ptype_outer_fragmented {
 965         I40E_RX_PTYPE_NOT_FRAG  = 0,
 966         I40E_RX_PTYPE_FRAG      = 1
 967 };
 968
 969 enum i40e_rx_ptype_tunnel_type {
 970         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 971         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 972         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 973         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 974         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 975 };
 976
 977 enum i40e_rx_ptype_tunnel_end_prot {
 978         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 979         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 980         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 981 };
 982
 983 enum i40e_rx_ptype_inner_prot {
 984         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 985         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 986         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 987         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 988         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 989         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 990 };
 991
 992 enum i40e_rx_ptype_payload_layer {
 993         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 994         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 995         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 996         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 997 };
 998
 999 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
1000 #define I40E_RX_PTYPE_SHIFT             56
1001
1002 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
1003 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
1004                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
1005
1006 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
1007 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
1008                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
1009
1010 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
1011 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
1012
1013 #define I40E_RXD_QW1_NEXTP_SHIFT        38
1014 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
1015
1016 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
1017 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
1018                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
1019
1020 enum i40e_rx_desc_ext_status_bits {
1021         /* Note: These are predefined bit offsets */
1022         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
1023         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
1024         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
1025         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
1026         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
1027         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1028         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
1029 };
1030
1031 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
1032 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1033
1034 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
1035 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1036
1037 enum i40e_rx_desc_pe_status_bits {
1038         /* Note: These are predefined bit offsets */
1039         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1040         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1041         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1042         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1043         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1044         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1045         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1046         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1047         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1048 };
1049
1050 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1051 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1052
1053 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1054 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1055                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1056
1057 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1058 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1059                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1060
1061 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1062 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1063                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1064
1065 enum i40e_rx_prog_status_desc_status_bits {
1066         /* Note: These are predefined bit offsets */
1067         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1068         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1069 };
1070
1071 enum i40e_rx_prog_status_desc_prog_id_masks {
1072         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1073         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1074         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1075 };
1076
1077 enum i40e_rx_prog_status_desc_error_bits {
1078         /* Note: These are predefined bit offsets */
1079         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1080         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1081         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1082         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1083 };
1084
1085 #define I40E_TWO_BIT_MASK       0x3
1086 #define I40E_THREE_BIT_MASK     0x7
1087 #define I40E_FOUR_BIT_MASK      0xF
1088 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1089
1090 /* TX Descriptor */
1091 struct i40e_tx_desc {
1092         __le64 buffer_addr; /* Address of descriptor's data buf */
1093         __le64 cmd_type_offset_bsz;
1094 };
1095
1096 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1097 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1098
1099 enum i40e_tx_desc_dtype_value {
1100         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1101         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1102         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1103         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1104         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1105         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1106         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1107         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1108         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1109         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1110 };
1111
1112 #define I40E_TXD_QW1_CMD_SHIFT  4
1113 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1114
1115 enum i40e_tx_desc_cmd_bits {
1116         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1117         I40E_TX_DESC_CMD_RS                     = 0x0002,
1118         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1119         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1120         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1121         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1122         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1123         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1124         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1125         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1126         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1127         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1128         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1129         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1130         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1131         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1132         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1133         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1134 };
1135
1136 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1137 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1138                                          I40E_TXD_QW1_OFFSET_SHIFT)
1139
1140 enum i40e_tx_desc_length_fields {
1141         /* Note: These are predefined bit offsets */
1142         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1143         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1144         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1145 };
1146
1147 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1148 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1149 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1150 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1151
1152 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1153 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1154                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1155
1156 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1157 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1158
1159 /* Context descriptors */
1160 struct i40e_tx_context_desc {
1161         __le32 tunneling_params;
1162         __le16 l2tag2;
1163         __le16 rsvd;
1164         __le64 type_cmd_tso_mss;
1165 };
1166
1167 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1168 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1169
1170 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1171 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1172
1173 enum i40e_tx_ctx_desc_cmd_bits {
1174         I40E_TX_CTX_DESC_TSO            = 0x01,
1175         I40E_TX_CTX_DESC_TSYN           = 0x02,
1176         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1177         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1178         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1179         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1180         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1181         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1182         I40E_TX_CTX_DESC_SWPE           = 0x40
1183 };
1184
1185 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1186 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1187                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1188
1189 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1190 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1191                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1192
1193 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1194 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1195
1196 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1197 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1198                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1199
1200 enum i40e_tx_ctx_desc_eipt_offload {
1201         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1202         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1203         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1204         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1205 };
1206
1207 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1208 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1209                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1210
1211 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1212 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1213
1214 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1215 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1216
1217 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1218 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1219
1220 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1221
1222 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1223 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1224                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1225
1226 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1227 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1228                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1229
1230 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1231 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1232 struct i40e_nop_desc {
1233         __le64 rsvd;
1234         __le64 dtype_cmd;
1235 };
1236
1237 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1238 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1239
1240 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1241 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1242
1243 enum i40e_tx_nop_desc_cmd_bits {
1244         /* Note: These are predefined bit offsets */
1245         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1246         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1247         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1248 };
1249
1250 struct i40e_filter_program_desc {
1251         __le32 qindex_flex_ptype_vsi;
1252         __le32 rsvd;
1253         __le32 dtype_cmd_cntindex;
1254         __le32 fd_id;
1255 };
1256 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1257 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1258                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1259 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1260 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1261                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1262 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1263 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1264                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1265
1266 /* Packet Classifier Types for filters */
1267 enum i40e_filter_pctype {
1268         /* Note: Values 0-28 are reserved for future use.
1269          * Value 29, 30, 32 are not supported on XL710 and X710.
1270          */
1271         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1272         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1273         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1274         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1275         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1276         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1277         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1278         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1279         /* Note: Values 37-38 are reserved for future use.
1280          * Value 39, 40, 42 are not supported on XL710 and X710.
1281          */
1282         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1283         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1284         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1285         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1286         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1287         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1288         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1289         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1290         /* Note: Value 47 is reserved for future use */
1291         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1292         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1293         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1294         /* Note: Values 51-62 are reserved for future use */
1295         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1296 };
1297
1298 enum i40e_filter_program_desc_dest {
1299         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1300         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1301         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1302 };
1303
1304 enum i40e_filter_program_desc_fd_status {
1305         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1306         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1307         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1308         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1309 };
1310
1311 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1312 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1313                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1314
1315 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1316 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1317
1318 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1319 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1320                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1321
1322 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1323 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1324
1325 enum i40e_filter_program_desc_pcmd {
1326         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1327         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1328 };
1329
1330 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1331 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1332
1333 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1334 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1335
1336 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1337                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1338 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1339                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1340
1341 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1342                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1343 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1344
1345 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1346 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1347                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1348
1349 enum i40e_filter_type {
1350         I40E_FLOW_DIRECTOR_FLTR = 0,
1351         I40E_PE_QUAD_HASH_FLTR = 1,
1352         I40E_ETHERTYPE_FLTR,
1353         I40E_FCOE_CTX_FLTR,
1354         I40E_MAC_VLAN_FLTR,
1355         I40E_HASH_FLTR
1356 };
1357
1358 struct i40e_vsi_context {
1359         u16 seid;
1360         u16 uplink_seid;
1361         u16 vsi_number;
1362         u16 vsis_allocated;
1363         u16 vsis_unallocated;
1364         u16 flags;
1365         u8 pf_num;
1366         u8 vf_num;
1367         u8 connection_type;
1368         struct i40e_aqc_vsi_properties_data info;
1369 };
1370
1371 struct i40e_veb_context {
1372         u16 seid;
1373         u16 uplink_seid;
1374         u16 veb_number;
1375         u16 vebs_allocated;
1376         u16 vebs_unallocated;
1377         u16 flags;
1378         struct i40e_aqc_get_veb_parameters_completion info;
1379 };
1380
1381 /* Statistics collected by each port, VSI, VEB, and S-channel */
1382 struct i40e_eth_stats {
1383         u64 rx_bytes;                   /* gorc */
1384         u64 rx_unicast;                 /* uprc */
1385         u64 rx_multicast;               /* mprc */
1386         u64 rx_broadcast;               /* bprc */
1387         u64 rx_discards;                /* rdpc */
1388         u64 rx_unknown_protocol;        /* rupp */
1389         u64 tx_bytes;                   /* gotc */
1390         u64 tx_unicast;                 /* uptc */
1391         u64 tx_multicast;               /* mptc */
1392         u64 tx_broadcast;               /* bptc */
1393         u64 tx_discards;                /* tdpc */
1394         u64 tx_errors;                  /* tepc */
1395 };
1396
1397 /* Statistics collected per VEB per TC */
1398 struct i40e_veb_tc_stats {
1399         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1400         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1401         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1402         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1403 };
1404
1405 /* Statistics collected per function for FCoE */
1406 struct i40e_fcoe_stats {
1407         u64 rx_fcoe_packets;            /* fcoeprc */
1408         u64 rx_fcoe_dwords;             /* focedwrc */
1409         u64 rx_fcoe_dropped;            /* fcoerpdc */
1410         u64 tx_fcoe_packets;            /* fcoeptc */
1411         u64 tx_fcoe_dwords;             /* focedwtc */
1412         u64 fcoe_bad_fccrc;             /* fcoecrc */
1413         u64 fcoe_last_error;            /* fcoelast */
1414         u64 fcoe_ddp_count;             /* fcoeddpc */
1415 };
1416
1417 /* offset to per function FCoE statistics block */
1418 #define I40E_FCOE_VF_STAT_OFFSET        0
1419 #define I40E_FCOE_PF_STAT_OFFSET        128
1420 #define I40E_FCOE_STAT_MAX              (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1421
1422 /* Statistics collected by the MAC */
1423 struct i40e_hw_port_stats {
1424         /* eth stats collected by the port */
1425         struct i40e_eth_stats eth;
1426
1427         /* additional port specific stats */
1428         u64 tx_dropped_link_down;       /* tdold */
1429         u64 crc_errors;                 /* crcerrs */
1430         u64 illegal_bytes;              /* illerrc */
1431         u64 error_bytes;                /* errbc */
1432         u64 mac_local_faults;           /* mlfc */
1433         u64 mac_remote_faults;          /* mrfc */
1434         u64 rx_length_errors;           /* rlec */
1435         u64 link_xon_rx;                /* lxonrxc */
1436         u64 link_xoff_rx;               /* lxoffrxc */
1437         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1438         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1439         u64 link_xon_tx;                /* lxontxc */
1440         u64 link_xoff_tx;               /* lxofftxc */
1441         u64 priority_xon_tx[8];         /* pxontxc[8] */
1442         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1443         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1444         u64 rx_size_64;                 /* prc64 */
1445         u64 rx_size_127;                /* prc127 */
1446         u64 rx_size_255;                /* prc255 */
1447         u64 rx_size_511;                /* prc511 */
1448         u64 rx_size_1023;               /* prc1023 */
1449         u64 rx_size_1522;               /* prc1522 */
1450         u64 rx_size_big;                /* prc9522 */
1451         u64 rx_undersize;               /* ruc */
1452         u64 rx_fragments;               /* rfc */
1453         u64 rx_oversize;                /* roc */
1454         u64 rx_jabber;                  /* rjc */
1455         u64 tx_size_64;                 /* ptc64 */
1456         u64 tx_size_127;                /* ptc127 */
1457         u64 tx_size_255;                /* ptc255 */
1458         u64 tx_size_511;                /* ptc511 */
1459         u64 tx_size_1023;               /* ptc1023 */
1460         u64 tx_size_1522;               /* ptc1522 */
1461         u64 tx_size_big;                /* ptc9522 */
1462         u64 mac_short_packet_dropped;   /* mspdc */
1463         u64 checksum_error;             /* xec */
1464         /* flow director stats */
1465         u64 fd_atr_match;
1466         u64 fd_sb_match;
1467         u64 fd_atr_tunnel_match;
1468         u32 fd_atr_status;
1469         u32 fd_sb_status;
1470         /* EEE LPI */
1471         u32 tx_lpi_status;
1472         u32 rx_lpi_status;
1473         u64 tx_lpi_count;               /* etlpic */
1474         u64 rx_lpi_count;               /* erlpic */
1475 };
1476
1477 /* Checksum and Shadow RAM pointers */
1478 #define I40E_SR_NVM_CONTROL_WORD                0x00
1479 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1480 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1481 #define I40E_SR_OPTION_ROM_PTR                  0x05
1482 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1483 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1484 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1485 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1486 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1487 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1488 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1489 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1490 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1491 #define I40E_EMP_MODULE_PTR                     0x0F
1492 #define I40E_SR_EMP_MODULE_PTR                  0x48
1493 #define I40E_SR_PBA_FLAGS                       0x15
1494 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1495 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1496 #define I40E_NVM_OEM_VER_OFF                    0x83
1497 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1498 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1499 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1500 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1501 #define I40E_SR_NVM_MAP_VERSION                 0x29
1502 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1503 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1504 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1505 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1506 #define I40E_SR_VPD_PTR                         0x2F
1507 #define I40E_SR_PXE_SETUP_PTR                   0x30
1508 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1509 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1510 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1511 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1512 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1513 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1514 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1515 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1516 #define I40E_SR_PHY_ACTIVITY_LIST_PTR           0x3D
1517 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1518 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1519 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1520 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1521 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1522 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1523 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1524 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1525 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1526 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1527
1528 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1529 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1530 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1531 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1532 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1533 #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID   BIT(5)
1534 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE          BIT(12)
1535 #define I40E_PTR_TYPE                           BIT(15)
1536 #define I40E_SR_OCP_CFG_WORD0                   0x2B
1537 #define I40E_SR_OCP_ENABLED                     BIT(15)
1538
1539 /* Shadow RAM related */
1540 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1541 #define I40E_SR_BUF_ALIGNMENT           4096
1542 #define I40E_SR_WORDS_IN_1KB            512
1543 /* Checksum should be calculated such that after adding all the words,
1544  * including the checksum word itself, the sum should be 0xBABA.
1545  */
1546 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1547
1548 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1549
1550 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1551
1552 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1553         I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1554         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1555         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1556         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1557         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1558         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1559         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1560         I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1561         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1562         I40E_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1563         I40E_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1564         I40E_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1565         I40E_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1566 };
1567
1568 /* FCoE DIF/DIX Context descriptor */
1569 struct i40e_fcoe_difdix_context_desc {
1570         __le64 flags_buff0_buff1_ref;
1571         __le64 difapp_msk_bias;
1572 };
1573
1574 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT    0
1575 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK     (0xFFFULL << \
1576                                         I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1577
1578 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1579         /* 2 BITS */
1580         I40E_FCOE_DIFDIX_CTX_DESC_RSVD                          = 0x0000,
1581         /* 1 BIT  */
1582         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK                = 0x0000,
1583         /* 1 BIT  */
1584         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK             = 0x0004,
1585         /* 2 BITS */
1586         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE                  = 0x0000,
1587         /* 2 BITS */
1588         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY            = 0x0008,
1589         /* 2 BITS */
1590         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG     = 0x0010,
1591         /* 2 BITS */
1592         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG  = 0x0018,
1593         /* 2 BITS */
1594         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST                  = 0x0000,
1595         /* 2 BITS */
1596         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK               = 0x0020,
1597         /* 2 BITS */
1598         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG                = 0x0040,
1599         /* 2 BITS */
1600         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD                  = 0x0060,
1601         /* 1 BIT  */
1602         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM                  = 0x0000,
1603         /* 1 BIT  */
1604         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC                   = 0x0080,
1605         /* 2 BITS */
1606         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG                 = 0x0000,
1607         /* 2 BITS */
1608         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF                   = 0x0100,
1609         /* 2 BITS */
1610         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD                  = 0x0200,
1611         /* 2 BITS */
1612         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS              = 0x0300,
1613         /* 1 BIT  */
1614         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG                  = 0x0000,
1615         /* 1 BIT  */
1616         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG                    = 0x0400,
1617         /* 1 BIT */
1618         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B                   = 0x0000,
1619         /* 1 BIT */
1620         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K                     = 0x0800
1621 };
1622
1623 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT    12
1624 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK     (0x3FFULL << \
1625                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1626
1627 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT    22
1628 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK     (0x3FFULL << \
1629                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1630
1631 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT      32
1632 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK       (0xFFFFFFFFULL << \
1633                                         I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1634
1635 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT      0
1636 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK       (0xFFFFULL << \
1637                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1638
1639 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT  16
1640 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK   (0xFFFFULL << \
1641                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1642
1643 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1644 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK  (0xFFFFFFFFULL << \
1645                                         I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1646
1647 /* FCoE DIF/DIX Buffers descriptor */
1648 struct i40e_fcoe_difdix_buffers_desc {
1649         __le64 buff_addr0;
1650         __le64 buff_addr1;
1651 };
1652
1653 /* FCoE DDP Context descriptor */
1654 struct i40e_fcoe_ddp_context_desc {
1655         __le64 rsvd;
1656         __le64 type_cmd_foff_lsize;
1657 };
1658
1659 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1660 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1661                                         I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1662
1663 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1664 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1665                                          I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1666
1667 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1668         I40E_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1669         I40E_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1670         I40E_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1671         I40E_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1672         I40E_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1673         I40E_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1674 };
1675
1676 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1677 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1678                                          I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1679
1680 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1681 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1682                                         I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1683
1684 /* FCoE DDP/DWO Queue Context descriptor */
1685 struct i40e_fcoe_queue_context_desc {
1686         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1687         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1688 };
1689
1690 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1691 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1692                                         I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1693
1694 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1695 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1696                                         I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1697
1698 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1699 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1700                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1701
1702 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1703 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1704                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1705
1706 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1707         I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1708         I40E_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1709 };
1710
1711 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1712 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1713                                         I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1714
1715 /* FCoE DDP/DWO Filter Context descriptor */
1716 struct i40e_fcoe_filter_context_desc {
1717         __le32 param;
1718         __le16 seqn;
1719
1720         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1721         __le16 rsvd_dmaindx;
1722
1723         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1724         __le64 flags_rsvd_lanq;
1725 };
1726
1727 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1728 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1729                                         I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1730
1731 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1732         I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1733         I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1734         I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1735         I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1736         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1737         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1738 };
1739
1740 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1741 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1742                                         I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1743
1744 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1745 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1746                         I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1747
1748 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1749 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1750                         I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1751
1752 enum i40e_switch_element_types {
1753         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1754         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1755         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1756         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1757         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1758         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1759         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1760         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1761         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1762 };
1763
1764 /* Supported EtherType filters */
1765 enum i40e_ether_type_index {
1766         I40E_ETHER_TYPE_1588            = 0,
1767         I40E_ETHER_TYPE_FIP             = 1,
1768         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1769         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1770         I40E_ETHER_TYPE_LLDP            = 4,
1771         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1772         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1773         I40E_ETHER_TYPE_QCN_CNM         = 7,
1774         I40E_ETHER_TYPE_8021X           = 8,
1775         I40E_ETHER_TYPE_ARP             = 9,
1776         I40E_ETHER_TYPE_RSV1            = 10,
1777         I40E_ETHER_TYPE_RSV2            = 11,
1778 };
1779
1780 /* Filter context base size is 1K */
1781 #define I40E_HASH_FILTER_BASE_SIZE      1024
1782 /* Supported Hash filter values */
1783 enum i40e_hash_filter_size {
1784         I40E_HASH_FILTER_SIZE_1K        = 0,
1785         I40E_HASH_FILTER_SIZE_2K        = 1,
1786         I40E_HASH_FILTER_SIZE_4K        = 2,
1787         I40E_HASH_FILTER_SIZE_8K        = 3,
1788         I40E_HASH_FILTER_SIZE_16K       = 4,
1789         I40E_HASH_FILTER_SIZE_32K       = 5,
1790         I40E_HASH_FILTER_SIZE_64K       = 6,
1791         I40E_HASH_FILTER_SIZE_128K      = 7,
1792         I40E_HASH_FILTER_SIZE_256K      = 8,
1793         I40E_HASH_FILTER_SIZE_512K      = 9,
1794         I40E_HASH_FILTER_SIZE_1M        = 10,
1795 };
1796
1797 /* DMA context base size is 0.5K */
1798 #define I40E_DMA_CNTX_BASE_SIZE         512
1799 /* Supported DMA context values */
1800 enum i40e_dma_cntx_size {
1801         I40E_DMA_CNTX_SIZE_512          = 0,
1802         I40E_DMA_CNTX_SIZE_1K           = 1,
1803         I40E_DMA_CNTX_SIZE_2K           = 2,
1804         I40E_DMA_CNTX_SIZE_4K           = 3,
1805         I40E_DMA_CNTX_SIZE_8K           = 4,
1806         I40E_DMA_CNTX_SIZE_16K          = 5,
1807         I40E_DMA_CNTX_SIZE_32K          = 6,
1808         I40E_DMA_CNTX_SIZE_64K          = 7,
1809         I40E_DMA_CNTX_SIZE_128K         = 8,
1810         I40E_DMA_CNTX_SIZE_256K         = 9,
1811 };
1812
1813 /* Supported Hash look up table (LUT) sizes */
1814 enum i40e_hash_lut_size {
1815         I40E_HASH_LUT_SIZE_128          = 0,
1816         I40E_HASH_LUT_SIZE_512          = 1,
1817 };
1818
1819 /* Structure to hold a per PF filter control settings */
1820 struct i40e_filter_control_settings {
1821         /* number of PE Quad Hash filter buckets */
1822         enum i40e_hash_filter_size pe_filt_num;
1823         /* number of PE Quad Hash contexts */
1824         enum i40e_dma_cntx_size pe_cntx_num;
1825         /* number of FCoE filter buckets */
1826         enum i40e_hash_filter_size fcoe_filt_num;
1827         /* number of FCoE DDP contexts */
1828         enum i40e_dma_cntx_size fcoe_cntx_num;
1829         /* size of the Hash LUT */
1830         enum i40e_hash_lut_size hash_lut_size;
1831         /* enable FDIR filters for PF and its VFs */
1832         bool enable_fdir;
1833         /* enable Ethertype filters for PF and its VFs */
1834         bool enable_ethtype;
1835         /* enable MAC/VLAN filters for PF and its VFs */
1836         bool enable_macvlan;
1837 };
1838
1839 /* Structure to hold device level control filter counts */
1840 struct i40e_control_filter_stats {
1841         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1842         u16 etype_used;       /* Used perfect EtherType filters */
1843         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1844         u16 etype_free;       /* Un-used perfect EtherType filters */
1845 };
1846
1847 enum i40e_reset_type {
1848         I40E_RESET_POR          = 0,
1849         I40E_RESET_CORER        = 1,
1850         I40E_RESET_GLOBR        = 2,
1851         I40E_RESET_EMPR         = 3,
1852 };
1853
1854 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1855 #define I40E_NVM_LLDP_CFG_PTR   0x06
1856 #define I40E_SR_LLDP_CFG_PTR    0x31
1857 struct i40e_lldp_variables {
1858         u16 length;
1859         u16 adminstatus;
1860         u16 msgfasttx;
1861         u16 msgtxinterval;
1862         u16 txparams;
1863         u16 timers;
1864         u16 crc8;
1865 };
1866
1867 /* Offsets into Alternate Ram */
1868 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1869 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1870 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1871 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1872 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1873 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1874
1875 /* Alternate Ram Bandwidth Masks */
1876 #define I40E_ALT_BW_VALUE_MASK          0xFF
1877 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1878 #define I40E_ALT_BW_VALID_MASK          0x80000000
1879
1880 /* RSS Hash Table Size */
1881 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1882
1883 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1884 #define I40E_L3_SRC_SHIFT               47
1885 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1886 #define I40E_L3_V6_SRC_SHIFT            43
1887 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1888 #define I40E_L3_DST_SHIFT               35
1889 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1890 #define I40E_L3_V6_DST_SHIFT            35
1891 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1892 #define I40E_L4_SRC_SHIFT               34
1893 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1894 #define I40E_L4_DST_SHIFT               33
1895 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1896 #define I40E_VERIFY_TAG_SHIFT           31
1897 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1898
1899 #define I40E_FLEX_50_SHIFT              13
1900 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1901 #define I40E_FLEX_51_SHIFT              12
1902 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1903 #define I40E_FLEX_52_SHIFT              11
1904 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1905 #define I40E_FLEX_53_SHIFT              10
1906 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1907 #define I40E_FLEX_54_SHIFT              9
1908 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1909 #define I40E_FLEX_55_SHIFT              8
1910 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1911 #define I40E_FLEX_56_SHIFT              7
1912 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1913 #define I40E_FLEX_57_SHIFT              6
1914 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1915
1916 /* Version format for Dynamic Device Personalization(DDP) */
1917 struct i40e_ddp_version {
1918         u8 major;
1919         u8 minor;
1920         u8 update;
1921         u8 draft;
1922 };
1923
1924 #define I40E_DDP_NAME_SIZE      32
1925
1926 /* Package header */
1927 struct i40e_package_header {
1928         struct i40e_ddp_version version;
1929         u32 segment_count;
1930         u32 segment_offset[1];
1931 };
1932
1933 /* Generic segment header */
1934 struct i40e_generic_seg_header {
1935 #define SEGMENT_TYPE_METADATA   0x00000001
1936 #define SEGMENT_TYPE_NOTES      0x00000002
1937 #define SEGMENT_TYPE_I40E       0x00000011
1938 #define SEGMENT_TYPE_X722       0x00000012
1939         u32 type;
1940         struct i40e_ddp_version version;
1941         u32 size;
1942         char name[I40E_DDP_NAME_SIZE];
1943 };
1944
1945 struct i40e_metadata_segment {
1946         struct i40e_generic_seg_header header;
1947         struct i40e_ddp_version version;
1948 #define I40E_DDP_TRACKID_RDONLY         0
1949 #define I40E_DDP_TRACKID_INVALID        0xFFFFFFFF
1950         u32 track_id;
1951         char name[I40E_DDP_NAME_SIZE];
1952 };
1953
1954 struct i40e_device_id_entry {
1955         u32 vendor_dev_id;
1956         u32 sub_vendor_dev_id;
1957 };
1958
1959 struct i40e_profile_segment {
1960         struct i40e_generic_seg_header header;
1961         struct i40e_ddp_version version;
1962         char name[I40E_DDP_NAME_SIZE];
1963         u32 device_table_count;
1964         struct i40e_device_id_entry device_table[1];
1965 };
1966
1967 struct i40e_section_table {
1968         u32 section_count;
1969         u32 section_offset[1];
1970 };
1971
1972 struct i40e_profile_section_header {
1973         u16 tbl_size;
1974         u16 data_end;
1975         struct {
1976 #define SECTION_TYPE_INFO       0x00000010
1977 #define SECTION_TYPE_MMIO       0x00000800
1978 #define SECTION_TYPE_RB_MMIO    0x00001800
1979 #define SECTION_TYPE_AQ         0x00000801
1980 #define SECTION_TYPE_RB_AQ      0x00001801
1981 #define SECTION_TYPE_NOTE       0x80000000
1982 #define SECTION_TYPE_NAME       0x80000001
1983 #define SECTION_TYPE_PROTO      0x80000002
1984 #define SECTION_TYPE_PCTYPE     0x80000003
1985 #define SECTION_TYPE_PTYPE      0x80000004
1986                 u32 type;
1987                 u32 offset;
1988                 u32 size;
1989         } section;
1990 };
1991
1992 struct i40e_profile_tlv_section_record {
1993         u8 rtype;
1994         u8 type;
1995         u16 len;
1996         u8 data[12];
1997 };
1998
1999 /* Generic AQ section in proflie */
2000 struct i40e_profile_aq_section {
2001         u16 opcode;
2002         u16 flags;
2003         u8  param[16];
2004         u16 datalen;
2005         u8  data[1];
2006 };
2007
2008 struct i40e_profile_info {
2009         u32 track_id;
2010         struct i40e_ddp_version version;
2011         u8 op;
2012 #define I40E_DDP_ADD_TRACKID            0x01
2013 #define I40E_DDP_REMOVE_TRACKID 0x02
2014         u8 reserved[7];
2015         u8 name[I40E_DDP_NAME_SIZE];
2016 };
2017 #endif /* _I40E_TYPE_H_ */