4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
53 #include <rte_tailq.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
64 #include "i40e_regs.h"
66 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
67 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
69 #define I40E_CLEAR_PXE_WAIT_MS 200
71 /* Maximun number of capability elements */
72 #define I40E_MAX_CAP_ELE_NUM 128
74 /* Wait count and inteval */
75 #define I40E_CHK_Q_ENA_COUNT 1000
76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
78 /* Maximun number of VSI */
79 #define I40E_MAX_NUM_VSIS (384UL)
81 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
83 /* Flow control default timer */
84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
86 /* Flow control default high water */
87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
89 /* Flow control default low water */
90 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
92 /* Flow control enable fwd bit */
93 #define I40E_PRTMAC_FWD_CTRL 0x00000001
95 /* Receive Packet Buffer size */
96 #define I40E_RXPBSIZE (968 * 1024)
99 #define I40E_KILOSHIFT 10
101 /* Receive Average Packet Size in Byte*/
102 #define I40E_PACKET_AVERAGE_SIZE 128
104 /* Mask of PF interrupt causes */
105 #define I40E_PFINT_ICR0_ENA_MASK ( \
106 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
107 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
108 I40E_PFINT_ICR0_ENA_GRST_MASK | \
109 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
110 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
112 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
113 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
114 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
116 #define I40E_FLOW_TYPES ( \
117 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
118 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
122 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
127 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
129 /* Additional timesync values. */
130 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
131 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
132 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
133 #define I40E_PRTTSYN_TSYNENA 0x80000000
134 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
135 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
137 #define I40E_MAX_PERCENT 100
138 #define I40E_DEFAULT_DCB_APP_NUM 1
139 #define I40E_DEFAULT_DCB_APP_PRIO 3
141 #define I40E_INSET_NONE 0x00000000000000000ULL
144 #define I40E_INSET_DMAC 0x0000000000000001ULL
145 #define I40E_INSET_SMAC 0x0000000000000002ULL
146 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
147 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
148 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
151 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
152 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
153 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
154 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
155 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
156 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
157 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
159 /* bit 16 ~ bit 31 */
160 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
161 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
162 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
163 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
164 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
165 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
166 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
167 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
169 /* bit 32 ~ bit 47, tunnel fields */
170 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
171 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
172 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
173 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
174 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
175 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
177 /* bit 48 ~ bit 55 */
178 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
180 /* bit 56 ~ bit 63, Flex Payload */
181 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
182 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
188 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
189 #define I40E_INSET_FLEX_PAYLOAD \
190 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
191 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
192 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
193 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
196 * Below are values for writing un-exposed registers suggested
199 /* Destination MAC address */
200 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
201 /* Source MAC address */
202 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
203 /* Outer (S-Tag) VLAN tag in the outer L2 header */
204 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
205 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
206 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
207 /* Single VLAN tag in the inner L2 header */
208 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
209 /* Source IPv4 address */
210 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
211 /* Destination IPv4 address */
212 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
213 /* Source IPv4 address for X722 */
214 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
215 /* Destination IPv4 address for X722 */
216 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
217 /* IPv4 Protocol for X722 */
218 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
219 /* IPv4 Time to Live for X722 */
220 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
221 /* IPv4 Type of Service (TOS) */
222 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
224 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
225 /* IPv4 Time to Live */
226 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
227 /* Source IPv6 address */
228 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
229 /* Destination IPv6 address */
230 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
231 /* IPv6 Traffic Class (TC) */
232 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
233 /* IPv6 Next Header */
234 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
236 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
238 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
239 /* Destination L4 port */
240 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
241 /* SCTP verification tag */
242 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
243 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
244 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
245 /* Source port of tunneling UDP */
246 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
247 /* Destination port of tunneling UDP */
248 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
249 /* UDP Tunneling ID, NVGRE/GRE key */
250 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
251 /* Last ether type */
252 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
253 /* Tunneling outer destination IPv4 address */
254 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
255 /* Tunneling outer destination IPv6 address */
256 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
257 /* 1st word of flex payload */
258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
259 /* 2nd word of flex payload */
260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
261 /* 3rd word of flex payload */
262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
263 /* 4th word of flex payload */
264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
265 /* 5th word of flex payload */
266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
267 /* 6th word of flex payload */
268 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
269 /* 7th word of flex payload */
270 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
271 /* 8th word of flex payload */
272 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
273 /* all 8 words flex payload */
274 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
275 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
277 #define I40E_TRANSLATE_INSET 0
278 #define I40E_TRANSLATE_REG 1
280 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
281 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
282 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
283 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
284 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
285 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
287 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
288 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
290 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
292 /* PCI offset for querying capability */
293 #define PCI_DEV_CAP_REG 0xA4
294 /* PCI offset for enabling/disabling Extended Tag */
295 #define PCI_DEV_CTRL_REG 0xA8
296 /* Bit mask of Extended Tag capability */
297 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
298 /* Bit shift of Extended Tag enable/disable */
299 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
300 /* Bit mask of Extended Tag enable/disable */
301 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
303 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
304 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
305 static int i40e_dev_configure(struct rte_eth_dev *dev);
306 static int i40e_dev_start(struct rte_eth_dev *dev);
307 static void i40e_dev_stop(struct rte_eth_dev *dev);
308 static void i40e_dev_close(struct rte_eth_dev *dev);
309 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
310 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
311 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
312 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
313 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
314 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
315 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
316 struct rte_eth_stats *stats);
317 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
318 struct rte_eth_xstat *xstats, unsigned n);
319 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
320 struct rte_eth_xstat_name *xstats_names,
322 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
323 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
327 static void i40e_dev_info_get(struct rte_eth_dev *dev,
328 struct rte_eth_dev_info *dev_info);
329 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
332 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
333 enum rte_vlan_type vlan_type,
335 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
336 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
339 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
340 static int i40e_dev_led_on(struct rte_eth_dev *dev);
341 static int i40e_dev_led_off(struct rte_eth_dev *dev);
342 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
343 struct rte_eth_fc_conf *fc_conf);
344 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
345 struct rte_eth_fc_conf *fc_conf);
346 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
347 struct rte_eth_pfc_conf *pfc_conf);
348 static void i40e_macaddr_add(struct rte_eth_dev *dev,
349 struct ether_addr *mac_addr,
352 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
353 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
354 struct rte_eth_rss_reta_entry64 *reta_conf,
356 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
357 struct rte_eth_rss_reta_entry64 *reta_conf,
360 static int i40e_get_cap(struct i40e_hw *hw);
361 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
362 static int i40e_pf_setup(struct i40e_pf *pf);
363 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
364 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
365 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
366 static int i40e_dcb_setup(struct rte_eth_dev *dev);
367 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
368 bool offset_loaded, uint64_t *offset, uint64_t *stat);
369 static void i40e_stat_update_48(struct i40e_hw *hw,
375 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
376 static void i40e_dev_interrupt_handler(
377 __rte_unused struct rte_intr_handle *handle, void *param);
378 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
379 uint32_t base, uint32_t num);
380 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
381 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
383 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
385 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
386 static int i40e_veb_release(struct i40e_veb *veb);
387 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
388 struct i40e_vsi *vsi);
389 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
390 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
391 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
392 struct i40e_macvlan_filter *mv_f,
394 struct ether_addr *addr);
395 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
396 struct i40e_macvlan_filter *mv_f,
399 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
400 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
401 struct rte_eth_rss_conf *rss_conf);
402 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
403 struct rte_eth_rss_conf *rss_conf);
404 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
405 struct rte_eth_udp_tunnel *udp_tunnel);
406 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
407 struct rte_eth_udp_tunnel *udp_tunnel);
408 static void i40e_filter_input_set_init(struct i40e_pf *pf);
409 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
410 struct rte_eth_ethertype_filter *filter,
412 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
413 enum rte_filter_op filter_op,
415 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
416 enum rte_filter_type filter_type,
417 enum rte_filter_op filter_op,
419 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
420 struct rte_eth_dcb_info *dcb_info);
421 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
422 static void i40e_configure_registers(struct i40e_hw *hw);
423 static void i40e_hw_init(struct rte_eth_dev *dev);
424 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
425 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
426 struct rte_eth_mirror_conf *mirror_conf,
427 uint8_t sw_id, uint8_t on);
428 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
430 static int i40e_timesync_enable(struct rte_eth_dev *dev);
431 static int i40e_timesync_disable(struct rte_eth_dev *dev);
432 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
433 struct timespec *timestamp,
435 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
436 struct timespec *timestamp);
437 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
439 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
441 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
442 struct timespec *timestamp);
443 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
444 const struct timespec *timestamp);
446 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
448 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
451 static int i40e_get_regs(struct rte_eth_dev *dev,
452 struct rte_dev_reg_info *regs);
454 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
456 static int i40e_get_eeprom(struct rte_eth_dev *dev,
457 struct rte_dev_eeprom_info *eeprom);
459 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
460 struct ether_addr *mac_addr);
462 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
463 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
465 static const struct rte_pci_id pci_id_i40e_map[] = {
466 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
467 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
468 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
469 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
470 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
471 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
472 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
473 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
474 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
475 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
476 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
477 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
478 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
479 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
480 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
481 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
482 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
483 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
484 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
485 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
486 { .vendor_id = 0, /* sentinel */ },
489 static const struct eth_dev_ops i40e_eth_dev_ops = {
490 .dev_configure = i40e_dev_configure,
491 .dev_start = i40e_dev_start,
492 .dev_stop = i40e_dev_stop,
493 .dev_close = i40e_dev_close,
494 .promiscuous_enable = i40e_dev_promiscuous_enable,
495 .promiscuous_disable = i40e_dev_promiscuous_disable,
496 .allmulticast_enable = i40e_dev_allmulticast_enable,
497 .allmulticast_disable = i40e_dev_allmulticast_disable,
498 .dev_set_link_up = i40e_dev_set_link_up,
499 .dev_set_link_down = i40e_dev_set_link_down,
500 .link_update = i40e_dev_link_update,
501 .stats_get = i40e_dev_stats_get,
502 .xstats_get = i40e_dev_xstats_get,
503 .xstats_get_names = i40e_dev_xstats_get_names,
504 .stats_reset = i40e_dev_stats_reset,
505 .xstats_reset = i40e_dev_stats_reset,
506 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
507 .dev_infos_get = i40e_dev_info_get,
508 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
509 .vlan_filter_set = i40e_vlan_filter_set,
510 .vlan_tpid_set = i40e_vlan_tpid_set,
511 .vlan_offload_set = i40e_vlan_offload_set,
512 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
513 .vlan_pvid_set = i40e_vlan_pvid_set,
514 .rx_queue_start = i40e_dev_rx_queue_start,
515 .rx_queue_stop = i40e_dev_rx_queue_stop,
516 .tx_queue_start = i40e_dev_tx_queue_start,
517 .tx_queue_stop = i40e_dev_tx_queue_stop,
518 .rx_queue_setup = i40e_dev_rx_queue_setup,
519 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
520 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
521 .rx_queue_release = i40e_dev_rx_queue_release,
522 .rx_queue_count = i40e_dev_rx_queue_count,
523 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
524 .tx_queue_setup = i40e_dev_tx_queue_setup,
525 .tx_queue_release = i40e_dev_tx_queue_release,
526 .dev_led_on = i40e_dev_led_on,
527 .dev_led_off = i40e_dev_led_off,
528 .flow_ctrl_get = i40e_flow_ctrl_get,
529 .flow_ctrl_set = i40e_flow_ctrl_set,
530 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
531 .mac_addr_add = i40e_macaddr_add,
532 .mac_addr_remove = i40e_macaddr_remove,
533 .reta_update = i40e_dev_rss_reta_update,
534 .reta_query = i40e_dev_rss_reta_query,
535 .rss_hash_update = i40e_dev_rss_hash_update,
536 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
537 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
538 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
539 .filter_ctrl = i40e_dev_filter_ctrl,
540 .rxq_info_get = i40e_rxq_info_get,
541 .txq_info_get = i40e_txq_info_get,
542 .mirror_rule_set = i40e_mirror_rule_set,
543 .mirror_rule_reset = i40e_mirror_rule_reset,
544 .timesync_enable = i40e_timesync_enable,
545 .timesync_disable = i40e_timesync_disable,
546 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
547 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
548 .get_dcb_info = i40e_dev_get_dcb_info,
549 .timesync_adjust_time = i40e_timesync_adjust_time,
550 .timesync_read_time = i40e_timesync_read_time,
551 .timesync_write_time = i40e_timesync_write_time,
552 .get_reg = i40e_get_regs,
553 .get_eeprom_length = i40e_get_eeprom_length,
554 .get_eeprom = i40e_get_eeprom,
555 .mac_addr_set = i40e_set_default_mac_addr,
556 .mtu_set = i40e_dev_mtu_set,
559 /* store statistics names and its offset in stats structure */
560 struct rte_i40e_xstats_name_off {
561 char name[RTE_ETH_XSTATS_NAME_SIZE];
565 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
566 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
567 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
568 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
569 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
570 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
571 rx_unknown_protocol)},
572 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
573 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
574 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
575 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
578 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
579 sizeof(rte_i40e_stats_strings[0]))
581 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
582 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
583 tx_dropped_link_down)},
584 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
585 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
587 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
588 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
590 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
592 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
594 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
595 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
596 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
597 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
598 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
599 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
601 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
603 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
605 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
607 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
609 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
611 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
613 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
615 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
616 mac_short_packet_dropped)},
617 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
619 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
620 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
621 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
623 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
625 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
627 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
629 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
631 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
633 {"rx_flow_director_atr_match_packets",
634 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
635 {"rx_flow_director_sb_match_packets",
636 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
637 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
639 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
641 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
643 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
647 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
648 sizeof(rte_i40e_hw_port_strings[0]))
650 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
651 {"xon_packets", offsetof(struct i40e_hw_port_stats,
653 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
657 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
658 sizeof(rte_i40e_rxq_prio_strings[0]))
660 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
661 {"xon_packets", offsetof(struct i40e_hw_port_stats,
663 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
665 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
666 priority_xon_2_xoff)},
669 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
670 sizeof(rte_i40e_txq_prio_strings[0]))
672 static struct eth_driver rte_i40e_pmd = {
674 .id_table = pci_id_i40e_map,
675 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
676 RTE_PCI_DRV_DETACHABLE,
677 .probe = rte_eth_dev_pci_probe,
678 .remove = rte_eth_dev_pci_remove,
680 .eth_dev_init = eth_i40e_dev_init,
681 .eth_dev_uninit = eth_i40e_dev_uninit,
682 .dev_private_size = sizeof(struct i40e_adapter),
686 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
687 struct rte_eth_link *link)
689 struct rte_eth_link *dst = link;
690 struct rte_eth_link *src = &(dev->data->dev_link);
692 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
693 *(uint64_t *)src) == 0)
700 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
701 struct rte_eth_link *link)
703 struct rte_eth_link *dst = &(dev->data->dev_link);
704 struct rte_eth_link *src = link;
706 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
707 *(uint64_t *)src) == 0)
713 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
714 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
716 #ifndef I40E_GLQF_ORT
717 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
719 #ifndef I40E_GLQF_PIT
720 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
723 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
726 * Initialize registers for flexible payload, which should be set by NVM.
727 * This should be removed from code once it is fixed in NVM.
729 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
730 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
731 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
732 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
733 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
734 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
735 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
736 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
737 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
738 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
739 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
740 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
742 /* Initialize registers for parsing packet type of QinQ */
743 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
744 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
747 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
750 * Add a ethertype filter to drop all flow control frames transmitted
754 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
756 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
757 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
758 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
759 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
762 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
763 I40E_FLOW_CONTROL_ETHERTYPE, flags,
764 pf->main_vsi_seid, 0,
767 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
768 " frames from VSIs.");
772 floating_veb_list_handler(__rte_unused const char *key,
773 const char *floating_veb_value,
777 unsigned int count = 0;
780 bool *vf_floating_veb = opaque;
782 while (isblank(*floating_veb_value))
783 floating_veb_value++;
785 /* Reset floating VEB configuration for VFs */
786 for (idx = 0; idx < I40E_MAX_VF; idx++)
787 vf_floating_veb[idx] = false;
791 while (isblank(*floating_veb_value))
792 floating_veb_value++;
793 if (*floating_veb_value == '\0')
796 idx = strtoul(floating_veb_value, &end, 10);
797 if (errno || end == NULL)
799 while (isblank(*end))
803 } else if ((*end == ';') || (*end == '\0')) {
805 if (min == I40E_MAX_VF)
807 if (max >= I40E_MAX_VF)
808 max = I40E_MAX_VF - 1;
809 for (idx = min; idx <= max; idx++) {
810 vf_floating_veb[idx] = true;
817 floating_veb_value = end + 1;
818 } while (*end != '\0');
827 config_vf_floating_veb(struct rte_devargs *devargs,
828 uint16_t floating_veb,
829 bool *vf_floating_veb)
831 struct rte_kvargs *kvlist;
833 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
837 /* All the VFs attach to the floating VEB by default
838 * when the floating VEB is enabled.
840 for (i = 0; i < I40E_MAX_VF; i++)
841 vf_floating_veb[i] = true;
846 kvlist = rte_kvargs_parse(devargs->args, NULL);
850 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
851 rte_kvargs_free(kvlist);
854 /* When the floating_veb_list parameter exists, all the VFs
855 * will attach to the legacy VEB firstly, then configure VFs
856 * to the floating VEB according to the floating_veb_list.
858 if (rte_kvargs_process(kvlist, floating_veb_list,
859 floating_veb_list_handler,
860 vf_floating_veb) < 0) {
861 rte_kvargs_free(kvlist);
864 rte_kvargs_free(kvlist);
868 i40e_check_floating_handler(__rte_unused const char *key,
870 __rte_unused void *opaque)
872 if (strcmp(value, "1"))
879 is_floating_veb_supported(struct rte_devargs *devargs)
881 struct rte_kvargs *kvlist;
882 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
887 kvlist = rte_kvargs_parse(devargs->args, NULL);
891 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
892 rte_kvargs_free(kvlist);
895 /* Floating VEB is enabled when there's key-value:
896 * enable_floating_veb=1
898 if (rte_kvargs_process(kvlist, floating_veb_key,
899 i40e_check_floating_handler, NULL) < 0) {
900 rte_kvargs_free(kvlist);
903 rte_kvargs_free(kvlist);
909 config_floating_veb(struct rte_eth_dev *dev)
911 struct rte_pci_device *pci_dev = dev->pci_dev;
912 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
913 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
915 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
917 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
919 is_floating_veb_supported(pci_dev->device.devargs);
920 config_vf_floating_veb(pci_dev->device.devargs,
922 pf->floating_veb_list);
924 pf->floating_veb = false;
928 #define I40E_L2_TAGS_S_TAG_SHIFT 1
929 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
932 eth_i40e_dev_init(struct rte_eth_dev *dev)
934 struct rte_pci_device *pci_dev;
935 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
936 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
937 struct i40e_vsi *vsi;
942 PMD_INIT_FUNC_TRACE();
944 dev->dev_ops = &i40e_eth_dev_ops;
945 dev->rx_pkt_burst = i40e_recv_pkts;
946 dev->tx_pkt_burst = i40e_xmit_pkts;
948 /* for secondary processes, we don't initialise any further as primary
949 * has already done this work. Only check we don't need a different
951 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
952 i40e_set_rx_function(dev);
953 i40e_set_tx_function(dev);
956 pci_dev = dev->pci_dev;
958 rte_eth_copy_pci_info(dev, pci_dev);
960 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
961 pf->adapter->eth_dev = dev;
962 pf->dev_data = dev->data;
964 hw->back = I40E_PF_TO_ADAPTER(pf);
965 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
967 PMD_INIT_LOG(ERR, "Hardware is not available, "
968 "as address is NULL");
972 hw->vendor_id = pci_dev->id.vendor_id;
973 hw->device_id = pci_dev->id.device_id;
974 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
975 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
976 hw->bus.device = pci_dev->addr.devid;
977 hw->bus.func = pci_dev->addr.function;
978 hw->adapter_stopped = 0;
980 /* Make sure all is clean before doing PF reset */
983 /* Initialize the hardware */
986 /* Reset here to make sure all is clean for each PF */
987 ret = i40e_pf_reset(hw);
989 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
993 /* Initialize the shared code (base driver) */
994 ret = i40e_init_shared_code(hw);
996 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1001 * To work around the NVM issue, initialize registers
1002 * for flexible payload and packet type of QinQ by
1003 * software. It should be removed once issues are fixed
1006 i40e_GLQF_reg_init(hw);
1008 /* Initialize the input set for filters (hash and fd) to default value */
1009 i40e_filter_input_set_init(pf);
1011 /* Initialize the parameters for adminq */
1012 i40e_init_adminq_parameter(hw);
1013 ret = i40e_init_adminq(hw);
1014 if (ret != I40E_SUCCESS) {
1015 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1018 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1019 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1020 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1021 ((hw->nvm.version >> 12) & 0xf),
1022 ((hw->nvm.version >> 4) & 0xff),
1023 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1025 /* Need the special FW version to support floating VEB */
1026 config_floating_veb(dev);
1027 /* Clear PXE mode */
1028 i40e_clear_pxe_mode(hw);
1029 ret = i40e_dev_sync_phy_type(hw);
1031 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1032 goto err_sync_phy_type;
1035 * On X710, performance number is far from the expectation on recent
1036 * firmware versions. The fix for this issue may not be integrated in
1037 * the following firmware version. So the workaround in software driver
1038 * is needed. It needs to modify the initial values of 3 internal only
1039 * registers. Note that the workaround can be removed when it is fixed
1040 * in firmware in the future.
1042 i40e_configure_registers(hw);
1044 /* Get hw capabilities */
1045 ret = i40e_get_cap(hw);
1046 if (ret != I40E_SUCCESS) {
1047 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1048 goto err_get_capabilities;
1051 /* Initialize parameters for PF */
1052 ret = i40e_pf_parameter_init(dev);
1054 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1055 goto err_parameter_init;
1058 /* Initialize the queue management */
1059 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1061 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1062 goto err_qp_pool_init;
1064 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1065 hw->func_caps.num_msix_vectors - 1);
1067 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1068 goto err_msix_pool_init;
1071 /* Initialize lan hmc */
1072 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1073 hw->func_caps.num_rx_qp, 0, 0);
1074 if (ret != I40E_SUCCESS) {
1075 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1076 goto err_init_lan_hmc;
1079 /* Configure lan hmc */
1080 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1081 if (ret != I40E_SUCCESS) {
1082 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1083 goto err_configure_lan_hmc;
1086 /* Get and check the mac address */
1087 i40e_get_mac_addr(hw, hw->mac.addr);
1088 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1089 PMD_INIT_LOG(ERR, "mac address is not valid");
1091 goto err_get_mac_addr;
1093 /* Copy the permanent MAC address */
1094 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1095 (struct ether_addr *) hw->mac.perm_addr);
1097 /* Disable flow control */
1098 hw->fc.requested_mode = I40E_FC_NONE;
1099 i40e_set_fc(hw, &aq_fail, TRUE);
1101 /* Set the global registers with default ether type value */
1102 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1103 if (ret != I40E_SUCCESS) {
1104 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1106 goto err_setup_pf_switch;
1109 /* PF setup, which includes VSI setup */
1110 ret = i40e_pf_setup(pf);
1112 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1113 goto err_setup_pf_switch;
1116 /* reset all stats of the device, including pf and main vsi */
1117 i40e_dev_stats_reset(dev);
1121 /* Disable double vlan by default */
1122 i40e_vsi_config_double_vlan(vsi, FALSE);
1124 /* Disable S-TAG identification when floating_veb is disabled */
1125 if (!pf->floating_veb) {
1126 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1127 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1128 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1129 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1133 if (!vsi->max_macaddrs)
1134 len = ETHER_ADDR_LEN;
1136 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1138 /* Should be after VSI initialized */
1139 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1140 if (!dev->data->mac_addrs) {
1141 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1142 "for storing mac address");
1145 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1146 &dev->data->mac_addrs[0]);
1148 /* initialize pf host driver to setup SRIOV resource if applicable */
1149 i40e_pf_host_init(dev);
1151 /* register callback func to eal lib */
1152 rte_intr_callback_register(&(pci_dev->intr_handle),
1153 i40e_dev_interrupt_handler, (void *)dev);
1155 /* configure and enable device interrupt */
1156 i40e_pf_config_irq0(hw, TRUE);
1157 i40e_pf_enable_irq0(hw);
1159 /* enable uio intr after callback register */
1160 rte_intr_enable(&(pci_dev->intr_handle));
1162 * Add an ethertype filter to drop all flow control frames transmitted
1163 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1166 i40e_add_tx_flow_control_drop_filter(pf);
1168 /* Set the max frame size to 0x2600 by default,
1169 * in case other drivers changed the default value.
1171 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1173 /* initialize mirror rule list */
1174 TAILQ_INIT(&pf->mirror_list);
1176 /* Init dcb to sw mode by default */
1177 ret = i40e_dcb_init_configure(dev, TRUE);
1178 if (ret != I40E_SUCCESS) {
1179 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1180 pf->flags &= ~I40E_FLAG_DCB;
1186 i40e_vsi_release(pf->main_vsi);
1187 err_setup_pf_switch:
1189 err_configure_lan_hmc:
1190 (void)i40e_shutdown_lan_hmc(hw);
1192 i40e_res_pool_destroy(&pf->msix_pool);
1194 i40e_res_pool_destroy(&pf->qp_pool);
1197 err_get_capabilities:
1199 (void)i40e_shutdown_adminq(hw);
1205 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1207 struct rte_pci_device *pci_dev;
1209 struct i40e_filter_control_settings settings;
1211 uint8_t aq_fail = 0;
1213 PMD_INIT_FUNC_TRACE();
1215 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1218 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1219 pci_dev = dev->pci_dev;
1221 if (hw->adapter_stopped == 0)
1222 i40e_dev_close(dev);
1224 dev->dev_ops = NULL;
1225 dev->rx_pkt_burst = NULL;
1226 dev->tx_pkt_burst = NULL;
1228 /* Clear PXE mode */
1229 i40e_clear_pxe_mode(hw);
1231 /* Unconfigure filter control */
1232 memset(&settings, 0, sizeof(settings));
1233 ret = i40e_set_filter_control(hw, &settings);
1235 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1238 /* Disable flow control */
1239 hw->fc.requested_mode = I40E_FC_NONE;
1240 i40e_set_fc(hw, &aq_fail, TRUE);
1242 /* uninitialize pf host driver */
1243 i40e_pf_host_uninit(dev);
1245 rte_free(dev->data->mac_addrs);
1246 dev->data->mac_addrs = NULL;
1248 /* disable uio intr before callback unregister */
1249 rte_intr_disable(&(pci_dev->intr_handle));
1251 /* register callback func to eal lib */
1252 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1253 i40e_dev_interrupt_handler, (void *)dev);
1259 i40e_dev_configure(struct rte_eth_dev *dev)
1261 struct i40e_adapter *ad =
1262 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1263 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1264 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1267 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1268 * bulk allocation or vector Rx preconditions we will reset it.
1270 ad->rx_bulk_alloc_allowed = true;
1271 ad->rx_vec_allowed = true;
1272 ad->tx_simple_allowed = true;
1273 ad->tx_vec_allowed = true;
1275 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1276 ret = i40e_fdir_setup(pf);
1277 if (ret != I40E_SUCCESS) {
1278 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1281 ret = i40e_fdir_configure(dev);
1283 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1287 i40e_fdir_teardown(pf);
1289 ret = i40e_dev_init_vlan(dev);
1294 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1295 * RSS setting have different requirements.
1296 * General PMD driver call sequence are NIC init, configure,
1297 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1298 * will try to lookup the VSI that specific queue belongs to if VMDQ
1299 * applicable. So, VMDQ setting has to be done before
1300 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1301 * For RSS setting, it will try to calculate actual configured RX queue
1302 * number, which will be available after rx_queue_setup(). dev_start()
1303 * function is good to place RSS setup.
1305 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1306 ret = i40e_vmdq_setup(dev);
1311 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1312 ret = i40e_dcb_setup(dev);
1314 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1322 /* need to release vmdq resource if exists */
1323 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1324 i40e_vsi_release(pf->vmdq[i].vsi);
1325 pf->vmdq[i].vsi = NULL;
1330 /* need to release fdir resource if exists */
1331 i40e_fdir_teardown(pf);
1336 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1338 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1339 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1340 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1341 uint16_t msix_vect = vsi->msix_intr;
1344 for (i = 0; i < vsi->nb_qps; i++) {
1345 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1346 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1350 if (vsi->type != I40E_VSI_SRIOV) {
1351 if (!rte_intr_allow_others(intr_handle)) {
1352 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1353 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1355 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1358 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1359 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1361 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1366 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1367 vsi->user_param + (msix_vect - 1);
1369 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1370 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1372 I40E_WRITE_FLUSH(hw);
1376 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1377 int base_queue, int nb_queue)
1381 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1383 /* Bind all RX queues to allocated MSIX interrupt */
1384 for (i = 0; i < nb_queue; i++) {
1385 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1386 I40E_QINT_RQCTL_ITR_INDX_MASK |
1387 ((base_queue + i + 1) <<
1388 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1389 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1390 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1392 if (i == nb_queue - 1)
1393 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1394 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1397 /* Write first RX queue to Link list register as the head element */
1398 if (vsi->type != I40E_VSI_SRIOV) {
1400 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1402 if (msix_vect == I40E_MISC_VEC_ID) {
1403 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1405 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1407 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1409 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1412 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1414 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1416 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1418 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1425 if (msix_vect == I40E_MISC_VEC_ID) {
1427 I40E_VPINT_LNKLST0(vsi->user_param),
1429 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1431 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1433 /* num_msix_vectors_vf needs to minus irq0 */
1434 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1435 vsi->user_param + (msix_vect - 1);
1437 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1439 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1441 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1445 I40E_WRITE_FLUSH(hw);
1449 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1451 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1452 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1453 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1454 uint16_t msix_vect = vsi->msix_intr;
1455 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1456 uint16_t queue_idx = 0;
1461 for (i = 0; i < vsi->nb_qps; i++) {
1462 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1463 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1466 /* INTENA flag is not auto-cleared for interrupt */
1467 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1468 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1469 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1470 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1471 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1473 /* VF bind interrupt */
1474 if (vsi->type == I40E_VSI_SRIOV) {
1475 __vsi_queues_bind_intr(vsi, msix_vect,
1476 vsi->base_queue, vsi->nb_qps);
1480 /* PF & VMDq bind interrupt */
1481 if (rte_intr_dp_is_en(intr_handle)) {
1482 if (vsi->type == I40E_VSI_MAIN) {
1485 } else if (vsi->type == I40E_VSI_VMDQ2) {
1486 struct i40e_vsi *main_vsi =
1487 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1488 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1493 for (i = 0; i < vsi->nb_used_qps; i++) {
1495 if (!rte_intr_allow_others(intr_handle))
1496 /* allow to share MISC_VEC_ID */
1497 msix_vect = I40E_MISC_VEC_ID;
1499 /* no enough msix_vect, map all to one */
1500 __vsi_queues_bind_intr(vsi, msix_vect,
1501 vsi->base_queue + i,
1502 vsi->nb_used_qps - i);
1503 for (; !!record && i < vsi->nb_used_qps; i++)
1504 intr_handle->intr_vec[queue_idx + i] =
1508 /* 1:1 queue/msix_vect mapping */
1509 __vsi_queues_bind_intr(vsi, msix_vect,
1510 vsi->base_queue + i, 1);
1512 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1520 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1522 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1523 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1524 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1525 uint16_t interval = i40e_calc_itr_interval(\
1526 RTE_LIBRTE_I40E_ITR_INTERVAL);
1527 uint16_t msix_intr, i;
1529 if (rte_intr_allow_others(intr_handle))
1530 for (i = 0; i < vsi->nb_msix; i++) {
1531 msix_intr = vsi->msix_intr + i;
1532 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1533 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1534 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1535 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1537 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1540 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1541 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1542 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1543 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1545 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1547 I40E_WRITE_FLUSH(hw);
1551 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1553 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1554 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1555 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1556 uint16_t msix_intr, i;
1558 if (rte_intr_allow_others(intr_handle))
1559 for (i = 0; i < vsi->nb_msix; i++) {
1560 msix_intr = vsi->msix_intr + i;
1561 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1565 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1567 I40E_WRITE_FLUSH(hw);
1570 static inline uint8_t
1571 i40e_parse_link_speeds(uint16_t link_speeds)
1573 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1575 if (link_speeds & ETH_LINK_SPEED_40G)
1576 link_speed |= I40E_LINK_SPEED_40GB;
1577 if (link_speeds & ETH_LINK_SPEED_25G)
1578 link_speed |= I40E_LINK_SPEED_25GB;
1579 if (link_speeds & ETH_LINK_SPEED_20G)
1580 link_speed |= I40E_LINK_SPEED_20GB;
1581 if (link_speeds & ETH_LINK_SPEED_10G)
1582 link_speed |= I40E_LINK_SPEED_10GB;
1583 if (link_speeds & ETH_LINK_SPEED_1G)
1584 link_speed |= I40E_LINK_SPEED_1GB;
1585 if (link_speeds & ETH_LINK_SPEED_100M)
1586 link_speed |= I40E_LINK_SPEED_100MB;
1592 i40e_phy_conf_link(struct i40e_hw *hw,
1594 uint8_t force_speed,
1597 enum i40e_status_code status;
1598 struct i40e_aq_get_phy_abilities_resp phy_ab;
1599 struct i40e_aq_set_phy_config phy_conf;
1600 enum i40e_aq_phy_type cnt;
1601 uint32_t phy_type_mask = 0;
1603 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1604 I40E_AQ_PHY_FLAG_PAUSE_RX |
1605 I40E_AQ_PHY_FLAG_PAUSE_RX |
1606 I40E_AQ_PHY_FLAG_LOW_POWER;
1607 const uint8_t advt = I40E_LINK_SPEED_40GB |
1608 I40E_LINK_SPEED_25GB |
1609 I40E_LINK_SPEED_10GB |
1610 I40E_LINK_SPEED_1GB |
1611 I40E_LINK_SPEED_100MB;
1615 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1620 /* If link already up, no need to set up again */
1621 if (is_up && phy_ab.phy_type != 0)
1622 return I40E_SUCCESS;
1624 memset(&phy_conf, 0, sizeof(phy_conf));
1626 /* bits 0-2 use the values from get_phy_abilities_resp */
1628 abilities |= phy_ab.abilities & mask;
1630 /* update ablities and speed */
1631 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1632 phy_conf.link_speed = advt;
1634 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1636 phy_conf.abilities = abilities;
1640 /* To enable link, phy_type mask needs to include each type */
1641 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1642 phy_type_mask |= 1 << cnt;
1644 /* use get_phy_abilities_resp value for the rest */
1645 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1646 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1647 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1648 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1649 phy_conf.fec_config = phy_ab.mod_type_ext;
1650 phy_conf.eee_capability = phy_ab.eee_capability;
1651 phy_conf.eeer = phy_ab.eeer_val;
1652 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1654 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1655 phy_ab.abilities, phy_ab.link_speed);
1656 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1657 phy_conf.abilities, phy_conf.link_speed);
1659 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1663 return I40E_SUCCESS;
1667 i40e_apply_link_speed(struct rte_eth_dev *dev)
1670 uint8_t abilities = 0;
1671 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1672 struct rte_eth_conf *conf = &dev->data->dev_conf;
1674 speed = i40e_parse_link_speeds(conf->link_speeds);
1675 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1676 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1677 abilities |= I40E_AQ_PHY_AN_ENABLED;
1678 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1680 return i40e_phy_conf_link(hw, abilities, speed, true);
1684 i40e_dev_start(struct rte_eth_dev *dev)
1686 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1687 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1688 struct i40e_vsi *main_vsi = pf->main_vsi;
1690 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1691 uint32_t intr_vector = 0;
1693 hw->adapter_stopped = 0;
1695 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1696 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1697 dev->data->port_id);
1701 rte_intr_disable(intr_handle);
1703 if ((rte_intr_cap_multiple(intr_handle) ||
1704 !RTE_ETH_DEV_SRIOV(dev).active) &&
1705 dev->data->dev_conf.intr_conf.rxq != 0) {
1706 intr_vector = dev->data->nb_rx_queues;
1707 if (rte_intr_efd_enable(intr_handle, intr_vector))
1711 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1712 intr_handle->intr_vec =
1713 rte_zmalloc("intr_vec",
1714 dev->data->nb_rx_queues * sizeof(int),
1716 if (!intr_handle->intr_vec) {
1717 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1718 " intr_vec\n", dev->data->nb_rx_queues);
1723 /* Initialize VSI */
1724 ret = i40e_dev_rxtx_init(pf);
1725 if (ret != I40E_SUCCESS) {
1726 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1730 /* Map queues with MSIX interrupt */
1731 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1732 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1733 i40e_vsi_queues_bind_intr(main_vsi);
1734 i40e_vsi_enable_queues_intr(main_vsi);
1736 /* Map VMDQ VSI queues with MSIX interrupt */
1737 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1738 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1739 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1740 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1743 /* enable FDIR MSIX interrupt */
1744 if (pf->fdir.fdir_vsi) {
1745 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1746 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1749 /* Enable all queues which have been configured */
1750 ret = i40e_dev_switch_queues(pf, TRUE);
1751 if (ret != I40E_SUCCESS) {
1752 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1756 /* Enable receiving broadcast packets */
1757 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1758 if (ret != I40E_SUCCESS)
1759 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1761 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1762 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1764 if (ret != I40E_SUCCESS)
1765 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1768 /* Apply link configure */
1769 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1770 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1771 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1772 ETH_LINK_SPEED_40G)) {
1773 PMD_DRV_LOG(ERR, "Invalid link setting");
1776 ret = i40e_apply_link_speed(dev);
1777 if (I40E_SUCCESS != ret) {
1778 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1782 if (!rte_intr_allow_others(intr_handle)) {
1783 rte_intr_callback_unregister(intr_handle,
1784 i40e_dev_interrupt_handler,
1786 /* configure and enable device interrupt */
1787 i40e_pf_config_irq0(hw, FALSE);
1788 i40e_pf_enable_irq0(hw);
1790 if (dev->data->dev_conf.intr_conf.lsc != 0)
1791 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1792 " no intr multiplex\n");
1793 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1794 ret = i40e_aq_set_phy_int_mask(hw,
1795 ~(I40E_AQ_EVENT_LINK_UPDOWN |
1796 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1797 I40E_AQ_EVENT_MEDIA_NA), NULL);
1798 if (ret != I40E_SUCCESS)
1799 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1801 /* Call get_link_info aq commond to enable LSE */
1802 i40e_dev_link_update(dev, 0);
1805 /* enable uio intr after callback register */
1806 rte_intr_enable(intr_handle);
1808 return I40E_SUCCESS;
1811 i40e_dev_switch_queues(pf, FALSE);
1812 i40e_dev_clear_queues(dev);
1818 i40e_dev_stop(struct rte_eth_dev *dev)
1820 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1821 struct i40e_vsi *main_vsi = pf->main_vsi;
1822 struct i40e_mirror_rule *p_mirror;
1823 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1826 /* Disable all queues */
1827 i40e_dev_switch_queues(pf, FALSE);
1829 /* un-map queues with interrupt registers */
1830 i40e_vsi_disable_queues_intr(main_vsi);
1831 i40e_vsi_queues_unbind_intr(main_vsi);
1833 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1834 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1835 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1838 if (pf->fdir.fdir_vsi) {
1839 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1840 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1842 /* Clear all queues and release memory */
1843 i40e_dev_clear_queues(dev);
1846 i40e_dev_set_link_down(dev);
1848 /* Remove all mirror rules */
1849 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1850 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1853 pf->nb_mirror_rule = 0;
1855 if (!rte_intr_allow_others(intr_handle))
1856 /* resume to the default handler */
1857 rte_intr_callback_register(intr_handle,
1858 i40e_dev_interrupt_handler,
1861 /* Clean datapath event and queue/vec mapping */
1862 rte_intr_efd_disable(intr_handle);
1863 if (intr_handle->intr_vec) {
1864 rte_free(intr_handle->intr_vec);
1865 intr_handle->intr_vec = NULL;
1870 i40e_dev_close(struct rte_eth_dev *dev)
1872 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1873 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1877 PMD_INIT_FUNC_TRACE();
1880 hw->adapter_stopped = 1;
1881 i40e_dev_free_queues(dev);
1883 /* Disable interrupt */
1884 i40e_pf_disable_irq0(hw);
1885 rte_intr_disable(&(dev->pci_dev->intr_handle));
1887 /* shutdown and destroy the HMC */
1888 i40e_shutdown_lan_hmc(hw);
1890 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1891 i40e_vsi_release(pf->vmdq[i].vsi);
1892 pf->vmdq[i].vsi = NULL;
1897 /* release all the existing VSIs and VEBs */
1898 i40e_fdir_teardown(pf);
1899 i40e_vsi_release(pf->main_vsi);
1901 /* shutdown the adminq */
1902 i40e_aq_queue_shutdown(hw, true);
1903 i40e_shutdown_adminq(hw);
1905 i40e_res_pool_destroy(&pf->qp_pool);
1906 i40e_res_pool_destroy(&pf->msix_pool);
1908 /* force a PF reset to clean anything leftover */
1909 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1910 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1911 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1912 I40E_WRITE_FLUSH(hw);
1916 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1918 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1919 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1920 struct i40e_vsi *vsi = pf->main_vsi;
1923 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1925 if (status != I40E_SUCCESS)
1926 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1928 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1930 if (status != I40E_SUCCESS)
1931 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1936 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1938 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1939 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1940 struct i40e_vsi *vsi = pf->main_vsi;
1943 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1945 if (status != I40E_SUCCESS)
1946 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1948 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1950 if (status != I40E_SUCCESS)
1951 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1955 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1957 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1958 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959 struct i40e_vsi *vsi = pf->main_vsi;
1962 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1963 if (ret != I40E_SUCCESS)
1964 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1968 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1970 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1971 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972 struct i40e_vsi *vsi = pf->main_vsi;
1975 if (dev->data->promiscuous == 1)
1976 return; /* must remain in all_multicast mode */
1978 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1979 vsi->seid, FALSE, NULL);
1980 if (ret != I40E_SUCCESS)
1981 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1985 * Set device link up.
1988 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1990 /* re-apply link speed setting */
1991 return i40e_apply_link_speed(dev);
1995 * Set device link down.
1998 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2000 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2001 uint8_t abilities = 0;
2002 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2005 return i40e_phy_conf_link(hw, abilities, speed, false);
2009 i40e_dev_link_update(struct rte_eth_dev *dev,
2010 int wait_to_complete)
2012 #define CHECK_INTERVAL 100 /* 100ms */
2013 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2014 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2015 struct i40e_link_status link_status;
2016 struct rte_eth_link link, old;
2018 unsigned rep_cnt = MAX_REPEAT_TIME;
2019 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2021 memset(&link, 0, sizeof(link));
2022 memset(&old, 0, sizeof(old));
2023 memset(&link_status, 0, sizeof(link_status));
2024 rte_i40e_dev_atomic_read_link_status(dev, &old);
2027 /* Get link status information from hardware */
2028 status = i40e_aq_get_link_info(hw, enable_lse,
2029 &link_status, NULL);
2030 if (status != I40E_SUCCESS) {
2031 link.link_speed = ETH_SPEED_NUM_100M;
2032 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2033 PMD_DRV_LOG(ERR, "Failed to get link info");
2037 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2038 if (!wait_to_complete || link.link_status)
2041 rte_delay_ms(CHECK_INTERVAL);
2042 } while (--rep_cnt);
2044 if (!link.link_status)
2047 /* i40e uses full duplex only */
2048 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2050 /* Parse the link status */
2051 switch (link_status.link_speed) {
2052 case I40E_LINK_SPEED_100MB:
2053 link.link_speed = ETH_SPEED_NUM_100M;
2055 case I40E_LINK_SPEED_1GB:
2056 link.link_speed = ETH_SPEED_NUM_1G;
2058 case I40E_LINK_SPEED_10GB:
2059 link.link_speed = ETH_SPEED_NUM_10G;
2061 case I40E_LINK_SPEED_20GB:
2062 link.link_speed = ETH_SPEED_NUM_20G;
2064 case I40E_LINK_SPEED_25GB:
2065 link.link_speed = ETH_SPEED_NUM_25G;
2067 case I40E_LINK_SPEED_40GB:
2068 link.link_speed = ETH_SPEED_NUM_40G;
2071 link.link_speed = ETH_SPEED_NUM_100M;
2075 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2076 ETH_LINK_SPEED_FIXED);
2079 rte_i40e_dev_atomic_write_link_status(dev, &link);
2080 if (link.link_status == old.link_status)
2083 i40e_notify_all_vfs_link_status(dev);
2088 /* Get all the statistics of a VSI */
2090 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2092 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2093 struct i40e_eth_stats *nes = &vsi->eth_stats;
2094 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2095 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2097 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2098 vsi->offset_loaded, &oes->rx_bytes,
2100 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2101 vsi->offset_loaded, &oes->rx_unicast,
2103 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2104 vsi->offset_loaded, &oes->rx_multicast,
2105 &nes->rx_multicast);
2106 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2107 vsi->offset_loaded, &oes->rx_broadcast,
2108 &nes->rx_broadcast);
2109 /* exclude CRC bytes */
2110 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2111 nes->rx_broadcast) * ETHER_CRC_LEN;
2113 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2114 &oes->rx_discards, &nes->rx_discards);
2115 /* GLV_REPC not supported */
2116 /* GLV_RMPC not supported */
2117 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2118 &oes->rx_unknown_protocol,
2119 &nes->rx_unknown_protocol);
2120 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2121 vsi->offset_loaded, &oes->tx_bytes,
2123 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2124 vsi->offset_loaded, &oes->tx_unicast,
2126 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2127 vsi->offset_loaded, &oes->tx_multicast,
2128 &nes->tx_multicast);
2129 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2130 vsi->offset_loaded, &oes->tx_broadcast,
2131 &nes->tx_broadcast);
2132 /* exclude CRC bytes */
2133 nes->tx_bytes -= (nes->tx_unicast + nes->tx_multicast +
2134 nes->tx_broadcast) * ETHER_CRC_LEN;
2135 /* GLV_TDPC not supported */
2136 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2137 &oes->tx_errors, &nes->tx_errors);
2138 vsi->offset_loaded = true;
2140 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2142 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2143 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2144 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2145 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2146 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2147 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2148 nes->rx_unknown_protocol);
2149 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2150 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2151 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2152 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2153 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2154 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2155 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2160 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2163 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2164 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2166 /* Get rx/tx bytes of internal transfer packets */
2167 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2168 I40E_GLV_GORCL(hw->port),
2170 &pf->internal_rx_bytes_offset,
2171 &pf->internal_rx_bytes);
2173 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2174 I40E_GLV_GOTCL(hw->port),
2176 &pf->internal_tx_bytes_offset,
2177 &pf->internal_tx_bytes);
2179 /* Get statistics of struct i40e_eth_stats */
2180 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2181 I40E_GLPRT_GORCL(hw->port),
2182 pf->offset_loaded, &os->eth.rx_bytes,
2184 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2185 I40E_GLPRT_UPRCL(hw->port),
2186 pf->offset_loaded, &os->eth.rx_unicast,
2187 &ns->eth.rx_unicast);
2188 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2189 I40E_GLPRT_MPRCL(hw->port),
2190 pf->offset_loaded, &os->eth.rx_multicast,
2191 &ns->eth.rx_multicast);
2192 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2193 I40E_GLPRT_BPRCL(hw->port),
2194 pf->offset_loaded, &os->eth.rx_broadcast,
2195 &ns->eth.rx_broadcast);
2196 /* Workaround: CRC size should not be included in byte statistics,
2197 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2199 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2200 ns->eth.rx_broadcast) * ETHER_CRC_LEN + pf->internal_rx_bytes;
2202 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2203 pf->offset_loaded, &os->eth.rx_discards,
2204 &ns->eth.rx_discards);
2205 /* GLPRT_REPC not supported */
2206 /* GLPRT_RMPC not supported */
2207 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2209 &os->eth.rx_unknown_protocol,
2210 &ns->eth.rx_unknown_protocol);
2211 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2212 I40E_GLPRT_GOTCL(hw->port),
2213 pf->offset_loaded, &os->eth.tx_bytes,
2215 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2216 I40E_GLPRT_UPTCL(hw->port),
2217 pf->offset_loaded, &os->eth.tx_unicast,
2218 &ns->eth.tx_unicast);
2219 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2220 I40E_GLPRT_MPTCL(hw->port),
2221 pf->offset_loaded, &os->eth.tx_multicast,
2222 &ns->eth.tx_multicast);
2223 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2224 I40E_GLPRT_BPTCL(hw->port),
2225 pf->offset_loaded, &os->eth.tx_broadcast,
2226 &ns->eth.tx_broadcast);
2227 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2228 ns->eth.tx_broadcast) * ETHER_CRC_LEN + pf->internal_tx_bytes;
2229 /* GLPRT_TEPC not supported */
2231 /* additional port specific stats */
2232 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2233 pf->offset_loaded, &os->tx_dropped_link_down,
2234 &ns->tx_dropped_link_down);
2235 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2236 pf->offset_loaded, &os->crc_errors,
2238 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2239 pf->offset_loaded, &os->illegal_bytes,
2240 &ns->illegal_bytes);
2241 /* GLPRT_ERRBC not supported */
2242 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2243 pf->offset_loaded, &os->mac_local_faults,
2244 &ns->mac_local_faults);
2245 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2246 pf->offset_loaded, &os->mac_remote_faults,
2247 &ns->mac_remote_faults);
2248 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2249 pf->offset_loaded, &os->rx_length_errors,
2250 &ns->rx_length_errors);
2251 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2252 pf->offset_loaded, &os->link_xon_rx,
2254 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2255 pf->offset_loaded, &os->link_xoff_rx,
2257 for (i = 0; i < 8; i++) {
2258 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2260 &os->priority_xon_rx[i],
2261 &ns->priority_xon_rx[i]);
2262 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2264 &os->priority_xoff_rx[i],
2265 &ns->priority_xoff_rx[i]);
2267 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2268 pf->offset_loaded, &os->link_xon_tx,
2270 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2271 pf->offset_loaded, &os->link_xoff_tx,
2273 for (i = 0; i < 8; i++) {
2274 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2276 &os->priority_xon_tx[i],
2277 &ns->priority_xon_tx[i]);
2278 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2280 &os->priority_xoff_tx[i],
2281 &ns->priority_xoff_tx[i]);
2282 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2284 &os->priority_xon_2_xoff[i],
2285 &ns->priority_xon_2_xoff[i]);
2287 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2288 I40E_GLPRT_PRC64L(hw->port),
2289 pf->offset_loaded, &os->rx_size_64,
2291 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2292 I40E_GLPRT_PRC127L(hw->port),
2293 pf->offset_loaded, &os->rx_size_127,
2295 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2296 I40E_GLPRT_PRC255L(hw->port),
2297 pf->offset_loaded, &os->rx_size_255,
2299 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2300 I40E_GLPRT_PRC511L(hw->port),
2301 pf->offset_loaded, &os->rx_size_511,
2303 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2304 I40E_GLPRT_PRC1023L(hw->port),
2305 pf->offset_loaded, &os->rx_size_1023,
2307 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2308 I40E_GLPRT_PRC1522L(hw->port),
2309 pf->offset_loaded, &os->rx_size_1522,
2311 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2312 I40E_GLPRT_PRC9522L(hw->port),
2313 pf->offset_loaded, &os->rx_size_big,
2315 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2316 pf->offset_loaded, &os->rx_undersize,
2318 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2319 pf->offset_loaded, &os->rx_fragments,
2321 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2322 pf->offset_loaded, &os->rx_oversize,
2324 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2325 pf->offset_loaded, &os->rx_jabber,
2327 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2328 I40E_GLPRT_PTC64L(hw->port),
2329 pf->offset_loaded, &os->tx_size_64,
2331 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2332 I40E_GLPRT_PTC127L(hw->port),
2333 pf->offset_loaded, &os->tx_size_127,
2335 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2336 I40E_GLPRT_PTC255L(hw->port),
2337 pf->offset_loaded, &os->tx_size_255,
2339 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2340 I40E_GLPRT_PTC511L(hw->port),
2341 pf->offset_loaded, &os->tx_size_511,
2343 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2344 I40E_GLPRT_PTC1023L(hw->port),
2345 pf->offset_loaded, &os->tx_size_1023,
2347 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2348 I40E_GLPRT_PTC1522L(hw->port),
2349 pf->offset_loaded, &os->tx_size_1522,
2351 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2352 I40E_GLPRT_PTC9522L(hw->port),
2353 pf->offset_loaded, &os->tx_size_big,
2355 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2357 &os->fd_sb_match, &ns->fd_sb_match);
2358 /* GLPRT_MSPDC not supported */
2359 /* GLPRT_XEC not supported */
2361 pf->offset_loaded = true;
2364 i40e_update_vsi_stats(pf->main_vsi);
2367 /* Get all statistics of a port */
2369 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2371 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2372 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2373 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2376 /* call read registers - updates values, now write them to struct */
2377 i40e_read_stats_registers(pf, hw);
2379 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2380 pf->main_vsi->eth_stats.rx_multicast +
2381 pf->main_vsi->eth_stats.rx_broadcast -
2382 pf->main_vsi->eth_stats.rx_discards;
2383 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2384 pf->main_vsi->eth_stats.tx_multicast +
2385 pf->main_vsi->eth_stats.tx_broadcast;
2386 stats->ibytes = ns->eth.rx_bytes;
2387 stats->obytes = ns->eth.tx_bytes;
2388 stats->oerrors = ns->eth.tx_errors +
2389 pf->main_vsi->eth_stats.tx_errors;
2392 stats->imissed = ns->eth.rx_discards +
2393 pf->main_vsi->eth_stats.rx_discards;
2394 stats->ierrors = ns->crc_errors +
2395 ns->rx_length_errors + ns->rx_undersize +
2396 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2398 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2399 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2400 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2401 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2402 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2403 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2404 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2405 ns->eth.rx_unknown_protocol);
2406 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2407 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2408 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2409 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2410 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2411 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2413 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2414 ns->tx_dropped_link_down);
2415 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2416 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2418 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2419 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2420 ns->mac_local_faults);
2421 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2422 ns->mac_remote_faults);
2423 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2424 ns->rx_length_errors);
2425 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2426 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2427 for (i = 0; i < 8; i++) {
2428 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2429 i, ns->priority_xon_rx[i]);
2430 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2431 i, ns->priority_xoff_rx[i]);
2433 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2434 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2435 for (i = 0; i < 8; i++) {
2436 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2437 i, ns->priority_xon_tx[i]);
2438 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2439 i, ns->priority_xoff_tx[i]);
2440 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2441 i, ns->priority_xon_2_xoff[i]);
2443 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2444 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2445 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2446 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2447 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2448 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2449 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2450 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2451 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2452 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2453 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2454 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2455 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2456 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2457 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2458 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2459 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2460 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2461 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2462 ns->mac_short_packet_dropped);
2463 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2464 ns->checksum_error);
2465 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2466 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2469 /* Reset the statistics */
2471 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2473 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2474 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476 /* Mark PF and VSI stats to update the offset, aka "reset" */
2477 pf->offset_loaded = false;
2479 pf->main_vsi->offset_loaded = false;
2481 /* read the stats, reading current register values into offset */
2482 i40e_read_stats_registers(pf, hw);
2486 i40e_xstats_calc_num(void)
2488 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2489 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2490 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2493 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2494 struct rte_eth_xstat_name *xstats_names,
2495 __rte_unused unsigned limit)
2500 if (xstats_names == NULL)
2501 return i40e_xstats_calc_num();
2503 /* Note: limit checked in rte_eth_xstats_names() */
2505 /* Get stats from i40e_eth_stats struct */
2506 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2507 snprintf(xstats_names[count].name,
2508 sizeof(xstats_names[count].name),
2509 "%s", rte_i40e_stats_strings[i].name);
2513 /* Get individiual stats from i40e_hw_port struct */
2514 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2515 snprintf(xstats_names[count].name,
2516 sizeof(xstats_names[count].name),
2517 "%s", rte_i40e_hw_port_strings[i].name);
2521 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2522 for (prio = 0; prio < 8; prio++) {
2523 snprintf(xstats_names[count].name,
2524 sizeof(xstats_names[count].name),
2525 "rx_priority%u_%s", prio,
2526 rte_i40e_rxq_prio_strings[i].name);
2531 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2532 for (prio = 0; prio < 8; prio++) {
2533 snprintf(xstats_names[count].name,
2534 sizeof(xstats_names[count].name),
2535 "tx_priority%u_%s", prio,
2536 rte_i40e_txq_prio_strings[i].name);
2544 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2547 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2548 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549 unsigned i, count, prio;
2550 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2552 count = i40e_xstats_calc_num();
2556 i40e_read_stats_registers(pf, hw);
2563 /* Get stats from i40e_eth_stats struct */
2564 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2565 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2566 rte_i40e_stats_strings[i].offset);
2567 xstats[count].id = count;
2571 /* Get individiual stats from i40e_hw_port struct */
2572 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2573 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2574 rte_i40e_hw_port_strings[i].offset);
2575 xstats[count].id = count;
2579 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2580 for (prio = 0; prio < 8; prio++) {
2581 xstats[count].value =
2582 *(uint64_t *)(((char *)hw_stats) +
2583 rte_i40e_rxq_prio_strings[i].offset +
2584 (sizeof(uint64_t) * prio));
2585 xstats[count].id = count;
2590 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2591 for (prio = 0; prio < 8; prio++) {
2592 xstats[count].value =
2593 *(uint64_t *)(((char *)hw_stats) +
2594 rte_i40e_txq_prio_strings[i].offset +
2595 (sizeof(uint64_t) * prio));
2596 xstats[count].id = count;
2605 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2606 __rte_unused uint16_t queue_id,
2607 __rte_unused uint8_t stat_idx,
2608 __rte_unused uint8_t is_rx)
2610 PMD_INIT_FUNC_TRACE();
2616 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2618 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2619 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2620 struct i40e_vsi *vsi = pf->main_vsi;
2622 dev_info->max_rx_queues = vsi->nb_qps;
2623 dev_info->max_tx_queues = vsi->nb_qps;
2624 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2625 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2626 dev_info->max_mac_addrs = vsi->max_macaddrs;
2627 dev_info->max_vfs = dev->pci_dev->max_vfs;
2628 dev_info->rx_offload_capa =
2629 DEV_RX_OFFLOAD_VLAN_STRIP |
2630 DEV_RX_OFFLOAD_QINQ_STRIP |
2631 DEV_RX_OFFLOAD_IPV4_CKSUM |
2632 DEV_RX_OFFLOAD_UDP_CKSUM |
2633 DEV_RX_OFFLOAD_TCP_CKSUM;
2634 dev_info->tx_offload_capa =
2635 DEV_TX_OFFLOAD_VLAN_INSERT |
2636 DEV_TX_OFFLOAD_QINQ_INSERT |
2637 DEV_TX_OFFLOAD_IPV4_CKSUM |
2638 DEV_TX_OFFLOAD_UDP_CKSUM |
2639 DEV_TX_OFFLOAD_TCP_CKSUM |
2640 DEV_TX_OFFLOAD_SCTP_CKSUM |
2641 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2642 DEV_TX_OFFLOAD_TCP_TSO |
2643 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2644 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2645 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2646 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2647 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2649 dev_info->reta_size = pf->hash_lut_size;
2650 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2652 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2654 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2655 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2656 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2658 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2662 dev_info->default_txconf = (struct rte_eth_txconf) {
2664 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2665 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2666 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2668 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2669 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2670 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2671 ETH_TXQ_FLAGS_NOOFFLOADS,
2674 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2675 .nb_max = I40E_MAX_RING_DESC,
2676 .nb_min = I40E_MIN_RING_DESC,
2677 .nb_align = I40E_ALIGN_RING_DESC,
2680 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2681 .nb_max = I40E_MAX_RING_DESC,
2682 .nb_min = I40E_MIN_RING_DESC,
2683 .nb_align = I40E_ALIGN_RING_DESC,
2686 if (pf->flags & I40E_FLAG_VMDQ) {
2687 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2688 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2689 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2690 pf->max_nb_vmdq_vsi;
2691 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2692 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2693 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2696 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2698 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2699 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2701 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2704 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2708 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2710 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2711 struct i40e_vsi *vsi = pf->main_vsi;
2712 PMD_INIT_FUNC_TRACE();
2715 return i40e_vsi_add_vlan(vsi, vlan_id);
2717 return i40e_vsi_delete_vlan(vsi, vlan_id);
2721 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2722 enum rte_vlan_type vlan_type,
2725 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2726 uint64_t reg_r = 0, reg_w = 0;
2727 uint16_t reg_id = 0;
2729 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2731 switch (vlan_type) {
2732 case ETH_VLAN_TYPE_OUTER:
2738 case ETH_VLAN_TYPE_INNER:
2744 "Unsupported vlan type in single vlan.\n");
2750 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2753 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2755 if (ret != I40E_SUCCESS) {
2756 PMD_DRV_LOG(ERR, "Fail to debug read from "
2757 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2761 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2762 "0x%08"PRIx64"", reg_id, reg_r);
2764 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2765 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2766 if (reg_r == reg_w) {
2768 PMD_DRV_LOG(DEBUG, "No need to write");
2772 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2774 if (ret != I40E_SUCCESS) {
2776 PMD_DRV_LOG(ERR, "Fail to debug write to "
2777 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2780 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2781 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2787 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2789 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2790 struct i40e_vsi *vsi = pf->main_vsi;
2792 if (mask & ETH_VLAN_FILTER_MASK) {
2793 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2794 i40e_vsi_config_vlan_filter(vsi, TRUE);
2796 i40e_vsi_config_vlan_filter(vsi, FALSE);
2799 if (mask & ETH_VLAN_STRIP_MASK) {
2800 /* Enable or disable VLAN stripping */
2801 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2802 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2804 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2807 if (mask & ETH_VLAN_EXTEND_MASK) {
2808 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2809 i40e_vsi_config_double_vlan(vsi, TRUE);
2810 /* Set global registers with default ether type value */
2811 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2813 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2817 i40e_vsi_config_double_vlan(vsi, FALSE);
2822 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2823 __rte_unused uint16_t queue,
2824 __rte_unused int on)
2826 PMD_INIT_FUNC_TRACE();
2830 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2832 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2833 struct i40e_vsi *vsi = pf->main_vsi;
2834 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2835 struct i40e_vsi_vlan_pvid_info info;
2837 memset(&info, 0, sizeof(info));
2840 info.config.pvid = pvid;
2842 info.config.reject.tagged =
2843 data->dev_conf.txmode.hw_vlan_reject_tagged;
2844 info.config.reject.untagged =
2845 data->dev_conf.txmode.hw_vlan_reject_untagged;
2848 return i40e_vsi_vlan_pvid_set(vsi, &info);
2852 i40e_dev_led_on(struct rte_eth_dev *dev)
2854 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2855 uint32_t mode = i40e_led_get(hw);
2858 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2864 i40e_dev_led_off(struct rte_eth_dev *dev)
2866 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2867 uint32_t mode = i40e_led_get(hw);
2870 i40e_led_set(hw, 0, false);
2876 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2878 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2879 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2881 fc_conf->pause_time = pf->fc_conf.pause_time;
2882 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2883 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2885 /* Return current mode according to actual setting*/
2886 switch (hw->fc.current_mode) {
2888 fc_conf->mode = RTE_FC_FULL;
2890 case I40E_FC_TX_PAUSE:
2891 fc_conf->mode = RTE_FC_TX_PAUSE;
2893 case I40E_FC_RX_PAUSE:
2894 fc_conf->mode = RTE_FC_RX_PAUSE;
2898 fc_conf->mode = RTE_FC_NONE;
2905 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2907 uint32_t mflcn_reg, fctrl_reg, reg;
2908 uint32_t max_high_water;
2909 uint8_t i, aq_failure;
2913 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2914 [RTE_FC_NONE] = I40E_FC_NONE,
2915 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2916 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2917 [RTE_FC_FULL] = I40E_FC_FULL
2920 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2922 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2923 if ((fc_conf->high_water > max_high_water) ||
2924 (fc_conf->high_water < fc_conf->low_water)) {
2925 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2926 "High_water must <= %d.", max_high_water);
2930 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2931 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2932 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2934 pf->fc_conf.pause_time = fc_conf->pause_time;
2935 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2936 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2938 PMD_INIT_FUNC_TRACE();
2940 /* All the link flow control related enable/disable register
2941 * configuration is handle by the F/W
2943 err = i40e_set_fc(hw, &aq_failure, true);
2947 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
2948 /* Configure flow control refresh threshold,
2949 * the value for stat_tx_pause_refresh_timer[8]
2950 * is used for global pause operation.
2954 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2955 pf->fc_conf.pause_time);
2957 /* configure the timer value included in transmitted pause
2959 * the value for stat_tx_pause_quanta[8] is used for global
2962 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2963 pf->fc_conf.pause_time);
2965 fctrl_reg = I40E_READ_REG(hw,
2966 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2968 if (fc_conf->mac_ctrl_frame_fwd != 0)
2969 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2971 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2973 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2976 /* Configure pause time (2 TCs per register) */
2977 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2978 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2979 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2981 /* Configure flow control refresh threshold value */
2982 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2983 pf->fc_conf.pause_time / 2);
2985 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2987 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2988 *depending on configuration
2990 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2991 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2992 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2994 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2995 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2998 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3001 /* config the water marker both based on the packets and bytes */
3002 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3003 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3004 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3005 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3006 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3007 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3008 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3009 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3011 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3012 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3015 I40E_WRITE_FLUSH(hw);
3021 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3022 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3024 PMD_INIT_FUNC_TRACE();
3029 /* Add a MAC address, and update filters */
3031 i40e_macaddr_add(struct rte_eth_dev *dev,
3032 struct ether_addr *mac_addr,
3033 __rte_unused uint32_t index,
3036 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3037 struct i40e_mac_filter_info mac_filter;
3038 struct i40e_vsi *vsi;
3041 /* If VMDQ not enabled or configured, return */
3042 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3043 !pf->nb_cfg_vmdq_vsi)) {
3044 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3045 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3050 if (pool > pf->nb_cfg_vmdq_vsi) {
3051 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3052 pool, pf->nb_cfg_vmdq_vsi);
3056 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3057 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3058 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3060 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3065 vsi = pf->vmdq[pool - 1].vsi;
3067 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3068 if (ret != I40E_SUCCESS) {
3069 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3074 /* Remove a MAC address, and update filters */
3076 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3078 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3079 struct i40e_vsi *vsi;
3080 struct rte_eth_dev_data *data = dev->data;
3081 struct ether_addr *macaddr;
3086 macaddr = &(data->mac_addrs[index]);
3088 pool_sel = dev->data->mac_pool_sel[index];
3090 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3091 if (pool_sel & (1ULL << i)) {
3095 /* No VMDQ pool enabled or configured */
3096 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3097 (i > pf->nb_cfg_vmdq_vsi)) {
3098 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3102 vsi = pf->vmdq[i - 1].vsi;
3104 ret = i40e_vsi_delete_mac(vsi, macaddr);
3107 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3114 /* Set perfect match or hash match of MAC and VLAN for a VF */
3116 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3117 struct rte_eth_mac_filter *filter,
3121 struct i40e_mac_filter_info mac_filter;
3122 struct ether_addr old_mac;
3123 struct ether_addr *new_mac;
3124 struct i40e_pf_vf *vf = NULL;
3129 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3132 hw = I40E_PF_TO_HW(pf);
3134 if (filter == NULL) {
3135 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3139 new_mac = &filter->mac_addr;
3141 if (is_zero_ether_addr(new_mac)) {
3142 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3146 vf_id = filter->dst_id;
3148 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3149 PMD_DRV_LOG(ERR, "Invalid argument.");
3152 vf = &pf->vfs[vf_id];
3154 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3155 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3160 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3161 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3163 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3166 mac_filter.filter_type = filter->filter_type;
3167 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3168 if (ret != I40E_SUCCESS) {
3169 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3172 ether_addr_copy(new_mac, &pf->dev_addr);
3174 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3176 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3177 if (ret != I40E_SUCCESS) {
3178 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3182 /* Clear device address as it has been removed */
3183 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3184 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3190 /* MAC filter handle */
3192 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3195 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3196 struct rte_eth_mac_filter *filter;
3197 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3198 int ret = I40E_NOT_SUPPORTED;
3200 filter = (struct rte_eth_mac_filter *)(arg);
3202 switch (filter_op) {
3203 case RTE_ETH_FILTER_NOP:
3206 case RTE_ETH_FILTER_ADD:
3207 i40e_pf_disable_irq0(hw);
3209 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3210 i40e_pf_enable_irq0(hw);
3212 case RTE_ETH_FILTER_DELETE:
3213 i40e_pf_disable_irq0(hw);
3215 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3216 i40e_pf_enable_irq0(hw);
3219 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3220 ret = I40E_ERR_PARAM;
3228 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3230 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3231 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3237 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3238 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3241 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3245 uint32_t *lut_dw = (uint32_t *)lut;
3246 uint16_t i, lut_size_dw = lut_size / 4;
3248 for (i = 0; i < lut_size_dw; i++)
3249 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3256 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3265 pf = I40E_VSI_TO_PF(vsi);
3266 hw = I40E_VSI_TO_HW(vsi);
3268 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3269 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3272 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3276 uint32_t *lut_dw = (uint32_t *)lut;
3277 uint16_t i, lut_size_dw = lut_size / 4;
3279 for (i = 0; i < lut_size_dw; i++)
3280 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3281 I40E_WRITE_FLUSH(hw);
3288 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3289 struct rte_eth_rss_reta_entry64 *reta_conf,
3292 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3293 uint16_t i, lut_size = pf->hash_lut_size;
3294 uint16_t idx, shift;
3298 if (reta_size != lut_size ||
3299 reta_size > ETH_RSS_RETA_SIZE_512) {
3300 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3301 "(%d) doesn't match the number hardware can supported "
3302 "(%d)\n", reta_size, lut_size);
3306 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3308 PMD_DRV_LOG(ERR, "No memory can be allocated");
3311 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3314 for (i = 0; i < reta_size; i++) {
3315 idx = i / RTE_RETA_GROUP_SIZE;
3316 shift = i % RTE_RETA_GROUP_SIZE;
3317 if (reta_conf[idx].mask & (1ULL << shift))
3318 lut[i] = reta_conf[idx].reta[shift];
3320 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3329 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3330 struct rte_eth_rss_reta_entry64 *reta_conf,
3333 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3334 uint16_t i, lut_size = pf->hash_lut_size;
3335 uint16_t idx, shift;
3339 if (reta_size != lut_size ||
3340 reta_size > ETH_RSS_RETA_SIZE_512) {
3341 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3342 "(%d) doesn't match the number hardware can supported "
3343 "(%d)\n", reta_size, lut_size);
3347 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3349 PMD_DRV_LOG(ERR, "No memory can be allocated");
3353 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3356 for (i = 0; i < reta_size; i++) {
3357 idx = i / RTE_RETA_GROUP_SIZE;
3358 shift = i % RTE_RETA_GROUP_SIZE;
3359 if (reta_conf[idx].mask & (1ULL << shift))
3360 reta_conf[idx].reta[shift] = lut[i];
3370 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3371 * @hw: pointer to the HW structure
3372 * @mem: pointer to mem struct to fill out
3373 * @size: size of memory requested
3374 * @alignment: what to align the allocation to
3376 enum i40e_status_code
3377 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3378 struct i40e_dma_mem *mem,
3382 const struct rte_memzone *mz = NULL;
3383 char z_name[RTE_MEMZONE_NAMESIZE];
3386 return I40E_ERR_PARAM;
3388 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3389 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3390 alignment, RTE_PGSIZE_2M);
3392 return I40E_ERR_NO_MEMORY;
3396 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3397 mem->zone = (const void *)mz;
3398 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3399 "%"PRIu64, mz->name, mem->pa);
3401 return I40E_SUCCESS;
3405 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3406 * @hw: pointer to the HW structure
3407 * @mem: ptr to mem struct to free
3409 enum i40e_status_code
3410 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3411 struct i40e_dma_mem *mem)
3414 return I40E_ERR_PARAM;
3416 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3417 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3419 rte_memzone_free((const struct rte_memzone *)mem->zone);
3424 return I40E_SUCCESS;
3428 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3429 * @hw: pointer to the HW structure
3430 * @mem: pointer to mem struct to fill out
3431 * @size: size of memory requested
3433 enum i40e_status_code
3434 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3435 struct i40e_virt_mem *mem,
3439 return I40E_ERR_PARAM;
3442 mem->va = rte_zmalloc("i40e", size, 0);
3445 return I40E_SUCCESS;
3447 return I40E_ERR_NO_MEMORY;
3451 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3452 * @hw: pointer to the HW structure
3453 * @mem: pointer to mem struct to free
3455 enum i40e_status_code
3456 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3457 struct i40e_virt_mem *mem)
3460 return I40E_ERR_PARAM;
3465 return I40E_SUCCESS;
3469 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3471 rte_spinlock_init(&sp->spinlock);
3475 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3477 rte_spinlock_lock(&sp->spinlock);
3481 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3483 rte_spinlock_unlock(&sp->spinlock);
3487 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3493 * Get the hardware capabilities, which will be parsed
3494 * and saved into struct i40e_hw.
3497 i40e_get_cap(struct i40e_hw *hw)
3499 struct i40e_aqc_list_capabilities_element_resp *buf;
3500 uint16_t len, size = 0;
3503 /* Calculate a huge enough buff for saving response data temporarily */
3504 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3505 I40E_MAX_CAP_ELE_NUM;
3506 buf = rte_zmalloc("i40e", len, 0);
3508 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3509 return I40E_ERR_NO_MEMORY;
3512 /* Get, parse the capabilities and save it to hw */
3513 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3514 i40e_aqc_opc_list_func_capabilities, NULL);
3515 if (ret != I40E_SUCCESS)
3516 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3518 /* Free the temporary buffer after being used */
3525 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3527 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3528 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3529 uint16_t qp_count = 0, vsi_count = 0;
3531 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3532 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3535 /* Add the parameter init for LFC */
3536 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3537 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3538 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3540 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3541 pf->max_num_vsi = hw->func_caps.num_vsis;
3542 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3543 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3544 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3546 /* FDir queue/VSI allocation */
3547 pf->fdir_qp_offset = 0;
3548 if (hw->func_caps.fd) {
3549 pf->flags |= I40E_FLAG_FDIR;
3550 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3552 pf->fdir_nb_qps = 0;
3554 qp_count += pf->fdir_nb_qps;
3557 /* LAN queue/VSI allocation */
3558 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3559 if (!hw->func_caps.rss) {
3562 pf->flags |= I40E_FLAG_RSS;
3563 if (hw->mac.type == I40E_MAC_X722)
3564 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3565 pf->lan_nb_qps = pf->lan_nb_qp_max;
3567 qp_count += pf->lan_nb_qps;
3570 /* VF queue/VSI allocation */
3571 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3572 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3573 pf->flags |= I40E_FLAG_SRIOV;
3574 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3575 pf->vf_num = dev->pci_dev->max_vfs;
3576 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3577 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3578 pf->vf_nb_qps * pf->vf_num);
3583 qp_count += pf->vf_nb_qps * pf->vf_num;
3584 vsi_count += pf->vf_num;
3586 /* VMDq queue/VSI allocation */
3587 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3588 pf->vmdq_nb_qps = 0;
3589 pf->max_nb_vmdq_vsi = 0;
3590 if (hw->func_caps.vmdq) {
3591 if (qp_count < hw->func_caps.num_tx_qp &&
3592 vsi_count < hw->func_caps.num_vsis) {
3593 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3594 qp_count) / pf->vmdq_nb_qp_max;
3596 /* Limit the maximum number of VMDq vsi to the maximum
3597 * ethdev can support
3599 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3600 hw->func_caps.num_vsis - vsi_count);
3601 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3603 if (pf->max_nb_vmdq_vsi) {
3604 pf->flags |= I40E_FLAG_VMDQ;
3605 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3606 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3607 "per VMDQ VSI, in total %u queues",
3608 pf->max_nb_vmdq_vsi,
3609 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3610 pf->max_nb_vmdq_vsi);
3612 PMD_DRV_LOG(INFO, "No enough queues left for "
3616 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3619 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3620 vsi_count += pf->max_nb_vmdq_vsi;
3622 if (hw->func_caps.dcb)
3623 pf->flags |= I40E_FLAG_DCB;
3625 if (qp_count > hw->func_caps.num_tx_qp) {
3626 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3627 "the hardware maximum %u", qp_count,
3628 hw->func_caps.num_tx_qp);
3631 if (vsi_count > hw->func_caps.num_vsis) {
3632 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3633 "the hardware maximum %u", vsi_count,
3634 hw->func_caps.num_vsis);
3642 i40e_pf_get_switch_config(struct i40e_pf *pf)
3644 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3645 struct i40e_aqc_get_switch_config_resp *switch_config;
3646 struct i40e_aqc_switch_config_element_resp *element;
3647 uint16_t start_seid = 0, num_reported;
3650 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3651 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3652 if (!switch_config) {
3653 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3657 /* Get the switch configurations */
3658 ret = i40e_aq_get_switch_config(hw, switch_config,
3659 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3660 if (ret != I40E_SUCCESS) {
3661 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3664 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3665 if (num_reported != 1) { /* The number should be 1 */
3666 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3670 /* Parse the switch configuration elements */
3671 element = &(switch_config->element[0]);
3672 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3673 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3674 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3676 PMD_DRV_LOG(INFO, "Unknown element type");
3679 rte_free(switch_config);
3685 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3688 struct pool_entry *entry;
3690 if (pool == NULL || num == 0)
3693 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3694 if (entry == NULL) {
3695 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3699 /* queue heap initialize */
3700 pool->num_free = num;
3701 pool->num_alloc = 0;
3703 LIST_INIT(&pool->alloc_list);
3704 LIST_INIT(&pool->free_list);
3706 /* Initialize element */
3710 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3715 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3717 struct pool_entry *entry, *next_entry;
3722 for (entry = LIST_FIRST(&pool->alloc_list);
3723 entry && (next_entry = LIST_NEXT(entry, next), 1);
3724 entry = next_entry) {
3725 LIST_REMOVE(entry, next);
3729 for (entry = LIST_FIRST(&pool->free_list);
3730 entry && (next_entry = LIST_NEXT(entry, next), 1);
3731 entry = next_entry) {
3732 LIST_REMOVE(entry, next);
3737 pool->num_alloc = 0;
3739 LIST_INIT(&pool->alloc_list);
3740 LIST_INIT(&pool->free_list);
3744 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3747 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3748 uint32_t pool_offset;
3752 PMD_DRV_LOG(ERR, "Invalid parameter");
3756 pool_offset = base - pool->base;
3757 /* Lookup in alloc list */
3758 LIST_FOREACH(entry, &pool->alloc_list, next) {
3759 if (entry->base == pool_offset) {
3760 valid_entry = entry;
3761 LIST_REMOVE(entry, next);
3766 /* Not find, return */
3767 if (valid_entry == NULL) {
3768 PMD_DRV_LOG(ERR, "Failed to find entry");
3773 * Found it, move it to free list and try to merge.
3774 * In order to make merge easier, always sort it by qbase.
3775 * Find adjacent prev and last entries.
3778 LIST_FOREACH(entry, &pool->free_list, next) {
3779 if (entry->base > valid_entry->base) {
3787 /* Try to merge with next one*/
3789 /* Merge with next one */
3790 if (valid_entry->base + valid_entry->len == next->base) {
3791 next->base = valid_entry->base;
3792 next->len += valid_entry->len;
3793 rte_free(valid_entry);
3800 /* Merge with previous one */
3801 if (prev->base + prev->len == valid_entry->base) {
3802 prev->len += valid_entry->len;
3803 /* If it merge with next one, remove next node */
3805 LIST_REMOVE(valid_entry, next);
3806 rte_free(valid_entry);
3808 rte_free(valid_entry);
3814 /* Not find any entry to merge, insert */
3817 LIST_INSERT_AFTER(prev, valid_entry, next);
3818 else if (next != NULL)
3819 LIST_INSERT_BEFORE(next, valid_entry, next);
3820 else /* It's empty list, insert to head */
3821 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3824 pool->num_free += valid_entry->len;
3825 pool->num_alloc -= valid_entry->len;
3831 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3834 struct pool_entry *entry, *valid_entry;
3836 if (pool == NULL || num == 0) {
3837 PMD_DRV_LOG(ERR, "Invalid parameter");
3841 if (pool->num_free < num) {
3842 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3843 num, pool->num_free);
3848 /* Lookup in free list and find most fit one */
3849 LIST_FOREACH(entry, &pool->free_list, next) {
3850 if (entry->len >= num) {
3852 if (entry->len == num) {
3853 valid_entry = entry;
3856 if (valid_entry == NULL || valid_entry->len > entry->len)
3857 valid_entry = entry;
3861 /* Not find one to satisfy the request, return */
3862 if (valid_entry == NULL) {
3863 PMD_DRV_LOG(ERR, "No valid entry found");
3867 * The entry have equal queue number as requested,
3868 * remove it from alloc_list.
3870 if (valid_entry->len == num) {
3871 LIST_REMOVE(valid_entry, next);
3874 * The entry have more numbers than requested,
3875 * create a new entry for alloc_list and minus its
3876 * queue base and number in free_list.
3878 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3879 if (entry == NULL) {
3880 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3884 entry->base = valid_entry->base;
3886 valid_entry->base += num;
3887 valid_entry->len -= num;
3888 valid_entry = entry;
3891 /* Insert it into alloc list, not sorted */
3892 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3894 pool->num_free -= valid_entry->len;
3895 pool->num_alloc += valid_entry->len;
3897 return valid_entry->base + pool->base;
3901 * bitmap_is_subset - Check whether src2 is subset of src1
3904 bitmap_is_subset(uint8_t src1, uint8_t src2)
3906 return !((src1 ^ src2) & src2);
3909 static enum i40e_status_code
3910 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3912 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3914 /* If DCB is not supported, only default TC is supported */
3915 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3916 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3917 return I40E_NOT_SUPPORTED;
3920 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3921 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3922 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3924 return I40E_NOT_SUPPORTED;
3926 return I40E_SUCCESS;
3930 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3931 struct i40e_vsi_vlan_pvid_info *info)
3934 struct i40e_vsi_context ctxt;
3935 uint8_t vlan_flags = 0;
3938 if (vsi == NULL || info == NULL) {
3939 PMD_DRV_LOG(ERR, "invalid parameters");
3940 return I40E_ERR_PARAM;
3944 vsi->info.pvid = info->config.pvid;
3946 * If insert pvid is enabled, only tagged pkts are
3947 * allowed to be sent out.
3949 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3950 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3953 if (info->config.reject.tagged == 0)
3954 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3956 if (info->config.reject.untagged == 0)
3957 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3959 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3960 I40E_AQ_VSI_PVLAN_MODE_MASK);
3961 vsi->info.port_vlan_flags |= vlan_flags;
3962 vsi->info.valid_sections =
3963 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3964 memset(&ctxt, 0, sizeof(ctxt));
3965 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3966 ctxt.seid = vsi->seid;
3968 hw = I40E_VSI_TO_HW(vsi);
3969 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3970 if (ret != I40E_SUCCESS)
3971 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3977 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3979 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3981 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3983 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3984 if (ret != I40E_SUCCESS)
3988 PMD_DRV_LOG(ERR, "seid not valid");
3992 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3993 tc_bw_data.tc_valid_bits = enabled_tcmap;
3994 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3995 tc_bw_data.tc_bw_credits[i] =
3996 (enabled_tcmap & (1 << i)) ? 1 : 0;
3998 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3999 if (ret != I40E_SUCCESS) {
4000 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4004 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4005 sizeof(vsi->info.qs_handle));
4006 return I40E_SUCCESS;
4009 static enum i40e_status_code
4010 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4011 struct i40e_aqc_vsi_properties_data *info,
4012 uint8_t enabled_tcmap)
4014 enum i40e_status_code ret;
4015 int i, total_tc = 0;
4016 uint16_t qpnum_per_tc, bsf, qp_idx;
4018 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4019 if (ret != I40E_SUCCESS)
4022 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4023 if (enabled_tcmap & (1 << i))
4027 vsi->enabled_tc = enabled_tcmap;
4029 /* Number of queues per enabled TC */
4030 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4031 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4032 bsf = rte_bsf32(qpnum_per_tc);
4034 /* Adjust the queue number to actual queues that can be applied */
4035 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4036 vsi->nb_qps = qpnum_per_tc * total_tc;
4039 * Configure TC and queue mapping parameters, for enabled TC,
4040 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4041 * default queue will serve it.
4044 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4045 if (vsi->enabled_tc & (1 << i)) {
4046 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4047 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4048 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4049 qp_idx += qpnum_per_tc;
4051 info->tc_mapping[i] = 0;
4054 /* Associate queue number with VSI */
4055 if (vsi->type == I40E_VSI_SRIOV) {
4056 info->mapping_flags |=
4057 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4058 for (i = 0; i < vsi->nb_qps; i++)
4059 info->queue_mapping[i] =
4060 rte_cpu_to_le_16(vsi->base_queue + i);
4062 info->mapping_flags |=
4063 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4064 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4066 info->valid_sections |=
4067 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4069 return I40E_SUCCESS;
4073 i40e_veb_release(struct i40e_veb *veb)
4075 struct i40e_vsi *vsi;
4081 if (!TAILQ_EMPTY(&veb->head)) {
4082 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4085 /* associate_vsi field is NULL for floating VEB */
4086 if (veb->associate_vsi != NULL) {
4087 vsi = veb->associate_vsi;
4088 hw = I40E_VSI_TO_HW(vsi);
4090 vsi->uplink_seid = veb->uplink_seid;
4093 veb->associate_pf->main_vsi->floating_veb = NULL;
4094 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4097 i40e_aq_delete_element(hw, veb->seid, NULL);
4099 return I40E_SUCCESS;
4103 static struct i40e_veb *
4104 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4106 struct i40e_veb *veb;
4112 "veb setup failed, associated PF shouldn't null");
4115 hw = I40E_PF_TO_HW(pf);
4117 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4119 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4123 veb->associate_vsi = vsi;
4124 veb->associate_pf = pf;
4125 TAILQ_INIT(&veb->head);
4126 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4128 /* create floating veb if vsi is NULL */
4130 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4131 I40E_DEFAULT_TCMAP, false,
4132 &veb->seid, false, NULL);
4134 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4135 true, &veb->seid, false, NULL);
4138 if (ret != I40E_SUCCESS) {
4139 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4140 hw->aq.asq_last_status);
4143 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4145 /* get statistics index */
4146 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4147 &veb->stats_idx, NULL, NULL, NULL);
4148 if (ret != I40E_SUCCESS) {
4149 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4150 hw->aq.asq_last_status);
4153 /* Get VEB bandwidth, to be implemented */
4154 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4156 vsi->uplink_seid = veb->seid;
4165 i40e_vsi_release(struct i40e_vsi *vsi)
4169 struct i40e_vsi_list *vsi_list;
4172 struct i40e_mac_filter *f;
4173 uint16_t user_param;
4176 return I40E_SUCCESS;
4181 user_param = vsi->user_param;
4183 pf = I40E_VSI_TO_PF(vsi);
4184 hw = I40E_VSI_TO_HW(vsi);
4186 /* VSI has child to attach, release child first */
4188 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4189 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4192 i40e_veb_release(vsi->veb);
4195 if (vsi->floating_veb) {
4196 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4197 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4202 /* Remove all macvlan filters of the VSI */
4203 i40e_vsi_remove_all_macvlan_filter(vsi);
4204 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4207 if (vsi->type != I40E_VSI_MAIN &&
4208 ((vsi->type != I40E_VSI_SRIOV) ||
4209 !pf->floating_veb_list[user_param])) {
4210 /* Remove vsi from parent's sibling list */
4211 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4212 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4213 return I40E_ERR_PARAM;
4215 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4216 &vsi->sib_vsi_list, list);
4218 /* Remove all switch element of the VSI */
4219 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4220 if (ret != I40E_SUCCESS)
4221 PMD_DRV_LOG(ERR, "Failed to delete element");
4224 if ((vsi->type == I40E_VSI_SRIOV) &&
4225 pf->floating_veb_list[user_param]) {
4226 /* Remove vsi from parent's sibling list */
4227 if (vsi->parent_vsi == NULL ||
4228 vsi->parent_vsi->floating_veb == NULL) {
4229 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4230 return I40E_ERR_PARAM;
4232 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4233 &vsi->sib_vsi_list, list);
4235 /* Remove all switch element of the VSI */
4236 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4237 if (ret != I40E_SUCCESS)
4238 PMD_DRV_LOG(ERR, "Failed to delete element");
4241 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4243 if (vsi->type != I40E_VSI_SRIOV)
4244 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4247 return I40E_SUCCESS;
4251 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4253 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4254 struct i40e_aqc_remove_macvlan_element_data def_filter;
4255 struct i40e_mac_filter_info filter;
4258 if (vsi->type != I40E_VSI_MAIN)
4259 return I40E_ERR_CONFIG;
4260 memset(&def_filter, 0, sizeof(def_filter));
4261 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4263 def_filter.vlan_tag = 0;
4264 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4265 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4266 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4267 if (ret != I40E_SUCCESS) {
4268 struct i40e_mac_filter *f;
4269 struct ether_addr *mac;
4271 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4273 /* It needs to add the permanent mac into mac list */
4274 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4276 PMD_DRV_LOG(ERR, "failed to allocate memory");
4277 return I40E_ERR_NO_MEMORY;
4279 mac = &f->mac_info.mac_addr;
4280 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4282 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4283 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4288 (void)rte_memcpy(&filter.mac_addr,
4289 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4290 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4291 return i40e_vsi_add_mac(vsi, &filter);
4295 * i40e_vsi_get_bw_config - Query VSI BW Information
4296 * @vsi: the VSI to be queried
4298 * Returns 0 on success, negative value on failure
4300 static enum i40e_status_code
4301 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4303 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4304 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4305 struct i40e_hw *hw = &vsi->adapter->hw;
4310 memset(&bw_config, 0, sizeof(bw_config));
4311 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4312 if (ret != I40E_SUCCESS) {
4313 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4314 hw->aq.asq_last_status);
4318 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4319 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4320 &ets_sla_config, NULL);
4321 if (ret != I40E_SUCCESS) {
4322 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4323 "configuration %u", hw->aq.asq_last_status);
4327 /* store and print out BW info */
4328 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4329 vsi->bw_info.bw_max = bw_config.max_bw;
4330 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4331 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4332 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4333 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4335 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4336 vsi->bw_info.bw_ets_share_credits[i] =
4337 ets_sla_config.share_credits[i];
4338 vsi->bw_info.bw_ets_credits[i] =
4339 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4340 /* 4 bits per TC, 4th bit is reserved */
4341 vsi->bw_info.bw_ets_max[i] =
4342 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4343 RTE_LEN2MASK(3, uint8_t));
4344 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4345 vsi->bw_info.bw_ets_share_credits[i]);
4346 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4347 vsi->bw_info.bw_ets_credits[i]);
4348 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4349 vsi->bw_info.bw_ets_max[i]);
4352 return I40E_SUCCESS;
4355 /* i40e_enable_pf_lb
4356 * @pf: pointer to the pf structure
4358 * allow loopback on pf
4361 i40e_enable_pf_lb(struct i40e_pf *pf)
4363 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4364 struct i40e_vsi_context ctxt;
4367 /* Use the FW API if FW >= v5.0 */
4368 if (hw->aq.fw_maj_ver < 5) {
4369 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4373 memset(&ctxt, 0, sizeof(ctxt));
4374 ctxt.seid = pf->main_vsi_seid;
4375 ctxt.pf_num = hw->pf_id;
4376 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4378 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4379 ret, hw->aq.asq_last_status);
4382 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4383 ctxt.info.valid_sections =
4384 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4385 ctxt.info.switch_id |=
4386 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4388 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4390 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4391 hw->aq.asq_last_status);
4396 i40e_vsi_setup(struct i40e_pf *pf,
4397 enum i40e_vsi_type type,
4398 struct i40e_vsi *uplink_vsi,
4399 uint16_t user_param)
4401 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4402 struct i40e_vsi *vsi;
4403 struct i40e_mac_filter_info filter;
4405 struct i40e_vsi_context ctxt;
4406 struct ether_addr broadcast =
4407 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4409 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4410 uplink_vsi == NULL) {
4411 PMD_DRV_LOG(ERR, "VSI setup failed, "
4412 "VSI link shouldn't be NULL");
4416 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4417 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4418 "uplink VSI should be NULL");
4423 * 1.type is not MAIN and uplink vsi is not NULL
4424 * If uplink vsi didn't setup VEB, create one first under veb field
4425 * 2.type is SRIOV and the uplink is NULL
4426 * If floating VEB is NULL, create one veb under floating veb field
4429 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4430 uplink_vsi->veb == NULL) {
4431 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4433 if (uplink_vsi->veb == NULL) {
4434 PMD_DRV_LOG(ERR, "VEB setup failed");
4437 /* set ALLOWLOOPBACk on pf, when veb is created */
4438 i40e_enable_pf_lb(pf);
4441 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4442 pf->main_vsi->floating_veb == NULL) {
4443 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4445 if (pf->main_vsi->floating_veb == NULL) {
4446 PMD_DRV_LOG(ERR, "VEB setup failed");
4451 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4453 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4456 TAILQ_INIT(&vsi->mac_list);
4458 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4459 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4460 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4461 vsi->user_param = user_param;
4462 /* Allocate queues */
4463 switch (vsi->type) {
4464 case I40E_VSI_MAIN :
4465 vsi->nb_qps = pf->lan_nb_qps;
4467 case I40E_VSI_SRIOV :
4468 vsi->nb_qps = pf->vf_nb_qps;
4470 case I40E_VSI_VMDQ2:
4471 vsi->nb_qps = pf->vmdq_nb_qps;
4474 vsi->nb_qps = pf->fdir_nb_qps;
4480 * The filter status descriptor is reported in rx queue 0,
4481 * while the tx queue for fdir filter programming has no
4482 * such constraints, can be non-zero queues.
4483 * To simplify it, choose FDIR vsi use queue 0 pair.
4484 * To make sure it will use queue 0 pair, queue allocation
4485 * need be done before this function is called
4487 if (type != I40E_VSI_FDIR) {
4488 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4490 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4494 vsi->base_queue = ret;
4496 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4498 /* VF has MSIX interrupt in VF range, don't allocate here */
4499 if (type == I40E_VSI_MAIN) {
4500 ret = i40e_res_pool_alloc(&pf->msix_pool,
4501 RTE_MIN(vsi->nb_qps,
4502 RTE_MAX_RXTX_INTR_VEC_ID));
4504 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4506 goto fail_queue_alloc;
4508 vsi->msix_intr = ret;
4509 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4510 } else if (type != I40E_VSI_SRIOV) {
4511 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4513 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4514 goto fail_queue_alloc;
4516 vsi->msix_intr = ret;
4524 if (type == I40E_VSI_MAIN) {
4525 /* For main VSI, no need to add since it's default one */
4526 vsi->uplink_seid = pf->mac_seid;
4527 vsi->seid = pf->main_vsi_seid;
4528 /* Bind queues with specific MSIX interrupt */
4530 * Needs 2 interrupt at least, one for misc cause which will
4531 * enabled from OS side, Another for queues binding the
4532 * interrupt from device side only.
4535 /* Get default VSI parameters from hardware */
4536 memset(&ctxt, 0, sizeof(ctxt));
4537 ctxt.seid = vsi->seid;
4538 ctxt.pf_num = hw->pf_id;
4539 ctxt.uplink_seid = vsi->uplink_seid;
4541 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4542 if (ret != I40E_SUCCESS) {
4543 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4544 goto fail_msix_alloc;
4546 (void)rte_memcpy(&vsi->info, &ctxt.info,
4547 sizeof(struct i40e_aqc_vsi_properties_data));
4548 vsi->vsi_id = ctxt.vsi_number;
4549 vsi->info.valid_sections = 0;
4551 /* Configure tc, enabled TC0 only */
4552 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4554 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4555 goto fail_msix_alloc;
4558 /* TC, queue mapping */
4559 memset(&ctxt, 0, sizeof(ctxt));
4560 vsi->info.valid_sections |=
4561 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4562 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4563 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4564 (void)rte_memcpy(&ctxt.info, &vsi->info,
4565 sizeof(struct i40e_aqc_vsi_properties_data));
4566 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4567 I40E_DEFAULT_TCMAP);
4568 if (ret != I40E_SUCCESS) {
4569 PMD_DRV_LOG(ERR, "Failed to configure "
4570 "TC queue mapping");
4571 goto fail_msix_alloc;
4573 ctxt.seid = vsi->seid;
4574 ctxt.pf_num = hw->pf_id;
4575 ctxt.uplink_seid = vsi->uplink_seid;
4578 /* Update VSI parameters */
4579 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4580 if (ret != I40E_SUCCESS) {
4581 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4582 goto fail_msix_alloc;
4585 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4586 sizeof(vsi->info.tc_mapping));
4587 (void)rte_memcpy(&vsi->info.queue_mapping,
4588 &ctxt.info.queue_mapping,
4589 sizeof(vsi->info.queue_mapping));
4590 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4591 vsi->info.valid_sections = 0;
4593 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4597 * Updating default filter settings are necessary to prevent
4598 * reception of tagged packets.
4599 * Some old firmware configurations load a default macvlan
4600 * filter which accepts both tagged and untagged packets.
4601 * The updating is to use a normal filter instead if needed.
4602 * For NVM 4.2.2 or after, the updating is not needed anymore.
4603 * The firmware with correct configurations load the default
4604 * macvlan filter which is expected and cannot be removed.
4606 i40e_update_default_filter_setting(vsi);
4607 i40e_config_qinq(hw, vsi);
4608 } else if (type == I40E_VSI_SRIOV) {
4609 memset(&ctxt, 0, sizeof(ctxt));
4611 * For other VSI, the uplink_seid equals to uplink VSI's
4612 * uplink_seid since they share same VEB
4614 if (uplink_vsi == NULL)
4615 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4617 vsi->uplink_seid = uplink_vsi->uplink_seid;
4618 ctxt.pf_num = hw->pf_id;
4619 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4620 ctxt.uplink_seid = vsi->uplink_seid;
4621 ctxt.connection_type = 0x1;
4622 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4624 /* Use the VEB configuration if FW >= v5.0 */
4625 if (hw->aq.fw_maj_ver >= 5) {
4626 /* Configure switch ID */
4627 ctxt.info.valid_sections |=
4628 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4629 ctxt.info.switch_id =
4630 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4633 /* Configure port/vlan */
4634 ctxt.info.valid_sections |=
4635 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4636 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4637 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4638 I40E_DEFAULT_TCMAP);
4639 if (ret != I40E_SUCCESS) {
4640 PMD_DRV_LOG(ERR, "Failed to configure "
4641 "TC queue mapping");
4642 goto fail_msix_alloc;
4644 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4645 ctxt.info.valid_sections |=
4646 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4648 * Since VSI is not created yet, only configure parameter,
4649 * will add vsi below.
4652 i40e_config_qinq(hw, vsi);
4653 } else if (type == I40E_VSI_VMDQ2) {
4654 memset(&ctxt, 0, sizeof(ctxt));
4656 * For other VSI, the uplink_seid equals to uplink VSI's
4657 * uplink_seid since they share same VEB
4659 vsi->uplink_seid = uplink_vsi->uplink_seid;
4660 ctxt.pf_num = hw->pf_id;
4662 ctxt.uplink_seid = vsi->uplink_seid;
4663 ctxt.connection_type = 0x1;
4664 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4666 ctxt.info.valid_sections |=
4667 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4668 /* user_param carries flag to enable loop back */
4670 ctxt.info.switch_id =
4671 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4672 ctxt.info.switch_id |=
4673 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4676 /* Configure port/vlan */
4677 ctxt.info.valid_sections |=
4678 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4679 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4680 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4681 I40E_DEFAULT_TCMAP);
4682 if (ret != I40E_SUCCESS) {
4683 PMD_DRV_LOG(ERR, "Failed to configure "
4684 "TC queue mapping");
4685 goto fail_msix_alloc;
4687 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4688 ctxt.info.valid_sections |=
4689 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4690 } else if (type == I40E_VSI_FDIR) {
4691 memset(&ctxt, 0, sizeof(ctxt));
4692 vsi->uplink_seid = uplink_vsi->uplink_seid;
4693 ctxt.pf_num = hw->pf_id;
4695 ctxt.uplink_seid = vsi->uplink_seid;
4696 ctxt.connection_type = 0x1; /* regular data port */
4697 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4698 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4699 I40E_DEFAULT_TCMAP);
4700 if (ret != I40E_SUCCESS) {
4701 PMD_DRV_LOG(ERR, "Failed to configure "
4702 "TC queue mapping.");
4703 goto fail_msix_alloc;
4705 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4706 ctxt.info.valid_sections |=
4707 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4709 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4710 goto fail_msix_alloc;
4713 if (vsi->type != I40E_VSI_MAIN) {
4714 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4715 if (ret != I40E_SUCCESS) {
4716 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4717 hw->aq.asq_last_status);
4718 goto fail_msix_alloc;
4720 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4721 vsi->info.valid_sections = 0;
4722 vsi->seid = ctxt.seid;
4723 vsi->vsi_id = ctxt.vsi_number;
4724 vsi->sib_vsi_list.vsi = vsi;
4725 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4726 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4727 &vsi->sib_vsi_list, list);
4729 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4730 &vsi->sib_vsi_list, list);
4734 /* MAC/VLAN configuration */
4735 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4736 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4738 ret = i40e_vsi_add_mac(vsi, &filter);
4739 if (ret != I40E_SUCCESS) {
4740 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4741 goto fail_msix_alloc;
4744 /* Get VSI BW information */
4745 i40e_vsi_get_bw_config(vsi);
4748 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4750 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4756 /* Configure vlan filter on or off */
4758 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4761 struct i40e_mac_filter *f;
4763 struct i40e_mac_filter_info *mac_filter;
4764 enum rte_mac_filter_type desired_filter;
4765 int ret = I40E_SUCCESS;
4768 /* Filter to match MAC and VLAN */
4769 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4771 /* Filter to match only MAC */
4772 desired_filter = RTE_MAC_PERFECT_MATCH;
4777 mac_filter = rte_zmalloc("mac_filter_info_data",
4778 num * sizeof(*mac_filter), 0);
4779 if (mac_filter == NULL) {
4780 PMD_DRV_LOG(ERR, "failed to allocate memory");
4781 return I40E_ERR_NO_MEMORY;
4786 /* Remove all existing mac */
4787 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4788 mac_filter[i] = f->mac_info;
4789 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4791 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4792 on ? "enable" : "disable");
4798 /* Override with new filter */
4799 for (i = 0; i < num; i++) {
4800 mac_filter[i].filter_type = desired_filter;
4801 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4803 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4804 on ? "enable" : "disable");
4810 rte_free(mac_filter);
4814 /* Configure vlan stripping on or off */
4816 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4818 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4819 struct i40e_vsi_context ctxt;
4821 int ret = I40E_SUCCESS;
4823 /* Check if it has been already on or off */
4824 if (vsi->info.valid_sections &
4825 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4827 if ((vsi->info.port_vlan_flags &
4828 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4829 return 0; /* already on */
4831 if ((vsi->info.port_vlan_flags &
4832 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4833 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4834 return 0; /* already off */
4839 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4841 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4842 vsi->info.valid_sections =
4843 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4844 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4845 vsi->info.port_vlan_flags |= vlan_flags;
4846 ctxt.seid = vsi->seid;
4847 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4848 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4850 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4851 on ? "enable" : "disable");
4857 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4859 struct rte_eth_dev_data *data = dev->data;
4863 /* Apply vlan offload setting */
4864 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4865 i40e_vlan_offload_set(dev, mask);
4867 /* Apply double-vlan setting, not implemented yet */
4869 /* Apply pvid setting */
4870 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4871 data->dev_conf.txmode.hw_vlan_insert_pvid);
4873 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4879 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4881 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4883 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4887 i40e_update_flow_control(struct i40e_hw *hw)
4889 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4890 struct i40e_link_status link_status;
4891 uint32_t rxfc = 0, txfc = 0, reg;
4895 memset(&link_status, 0, sizeof(link_status));
4896 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4897 if (ret != I40E_SUCCESS) {
4898 PMD_DRV_LOG(ERR, "Failed to get link status information");
4899 goto write_reg; /* Disable flow control */
4902 an_info = hw->phy.link_info.an_info;
4903 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4904 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4905 ret = I40E_ERR_NOT_READY;
4906 goto write_reg; /* Disable flow control */
4909 * If link auto negotiation is enabled, flow control needs to
4910 * be configured according to it
4912 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4913 case I40E_LINK_PAUSE_RXTX:
4916 hw->fc.current_mode = I40E_FC_FULL;
4918 case I40E_AQ_LINK_PAUSE_RX:
4920 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4922 case I40E_AQ_LINK_PAUSE_TX:
4924 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4927 hw->fc.current_mode = I40E_FC_NONE;
4932 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4933 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4934 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4935 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4936 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4937 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4944 i40e_pf_setup(struct i40e_pf *pf)
4946 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4947 struct i40e_filter_control_settings settings;
4948 struct i40e_vsi *vsi;
4951 /* Clear all stats counters */
4952 pf->offset_loaded = FALSE;
4953 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4954 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4955 pf->internal_rx_bytes = 0;
4956 pf->internal_tx_bytes = 0;
4957 pf->internal_rx_bytes_offset = 0;
4958 pf->internal_tx_bytes_offset = 0;
4960 ret = i40e_pf_get_switch_config(pf);
4961 if (ret != I40E_SUCCESS) {
4962 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4965 if (pf->flags & I40E_FLAG_FDIR) {
4966 /* make queue allocated first, let FDIR use queue pair 0*/
4967 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4968 if (ret != I40E_FDIR_QUEUE_ID) {
4969 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4971 pf->flags &= ~I40E_FLAG_FDIR;
4974 /* main VSI setup */
4975 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4977 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4978 return I40E_ERR_NOT_READY;
4982 /* Configure filter control */
4983 memset(&settings, 0, sizeof(settings));
4984 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4985 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4986 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4987 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4989 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4990 hw->func_caps.rss_table_size);
4991 return I40E_ERR_PARAM;
4993 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4994 "size: %u\n", hw->func_caps.rss_table_size);
4995 pf->hash_lut_size = hw->func_caps.rss_table_size;
4997 /* Enable ethtype and macvlan filters */
4998 settings.enable_ethtype = TRUE;
4999 settings.enable_macvlan = TRUE;
5000 ret = i40e_set_filter_control(hw, &settings);
5002 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5005 /* Update flow control according to the auto negotiation */
5006 i40e_update_flow_control(hw);
5008 return I40E_SUCCESS;
5012 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5018 * Set or clear TX Queue Disable flags,
5019 * which is required by hardware.
5021 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5022 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5024 /* Wait until the request is finished */
5025 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5026 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5027 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5028 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5029 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5035 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5036 return I40E_SUCCESS; /* already on, skip next steps */
5038 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5039 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5041 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5042 return I40E_SUCCESS; /* already off, skip next steps */
5043 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5045 /* Write the register */
5046 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5047 /* Check the result */
5048 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5049 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5050 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5052 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5053 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5056 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5057 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5061 /* Check if it is timeout */
5062 if (j >= I40E_CHK_Q_ENA_COUNT) {
5063 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5064 (on ? "enable" : "disable"), q_idx);
5065 return I40E_ERR_TIMEOUT;
5068 return I40E_SUCCESS;
5071 /* Swith on or off the tx queues */
5073 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5075 struct rte_eth_dev_data *dev_data = pf->dev_data;
5076 struct i40e_tx_queue *txq;
5077 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5081 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5082 txq = dev_data->tx_queues[i];
5083 /* Don't operate the queue if not configured or
5084 * if starting only per queue */
5085 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5088 ret = i40e_dev_tx_queue_start(dev, i);
5090 ret = i40e_dev_tx_queue_stop(dev, i);
5091 if ( ret != I40E_SUCCESS)
5095 return I40E_SUCCESS;
5099 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5104 /* Wait until the request is finished */
5105 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5106 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5107 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5108 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5109 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5114 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5115 return I40E_SUCCESS; /* Already on, skip next steps */
5116 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5118 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5119 return I40E_SUCCESS; /* Already off, skip next steps */
5120 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5123 /* Write the register */
5124 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5125 /* Check the result */
5126 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5127 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5128 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5130 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5131 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5134 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5135 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5140 /* Check if it is timeout */
5141 if (j >= I40E_CHK_Q_ENA_COUNT) {
5142 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5143 (on ? "enable" : "disable"), q_idx);
5144 return I40E_ERR_TIMEOUT;
5147 return I40E_SUCCESS;
5149 /* Switch on or off the rx queues */
5151 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5153 struct rte_eth_dev_data *dev_data = pf->dev_data;
5154 struct i40e_rx_queue *rxq;
5155 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5159 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5160 rxq = dev_data->rx_queues[i];
5161 /* Don't operate the queue if not configured or
5162 * if starting only per queue */
5163 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5166 ret = i40e_dev_rx_queue_start(dev, i);
5168 ret = i40e_dev_rx_queue_stop(dev, i);
5169 if (ret != I40E_SUCCESS)
5173 return I40E_SUCCESS;
5176 /* Switch on or off all the rx/tx queues */
5178 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5183 /* enable rx queues before enabling tx queues */
5184 ret = i40e_dev_switch_rx_queues(pf, on);
5186 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5189 ret = i40e_dev_switch_tx_queues(pf, on);
5191 /* Stop tx queues before stopping rx queues */
5192 ret = i40e_dev_switch_tx_queues(pf, on);
5194 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5197 ret = i40e_dev_switch_rx_queues(pf, on);
5203 /* Initialize VSI for TX */
5205 i40e_dev_tx_init(struct i40e_pf *pf)
5207 struct rte_eth_dev_data *data = pf->dev_data;
5209 uint32_t ret = I40E_SUCCESS;
5210 struct i40e_tx_queue *txq;
5212 for (i = 0; i < data->nb_tx_queues; i++) {
5213 txq = data->tx_queues[i];
5214 if (!txq || !txq->q_set)
5216 ret = i40e_tx_queue_init(txq);
5217 if (ret != I40E_SUCCESS)
5220 if (ret == I40E_SUCCESS)
5221 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5227 /* Initialize VSI for RX */
5229 i40e_dev_rx_init(struct i40e_pf *pf)
5231 struct rte_eth_dev_data *data = pf->dev_data;
5232 int ret = I40E_SUCCESS;
5234 struct i40e_rx_queue *rxq;
5236 i40e_pf_config_mq_rx(pf);
5237 for (i = 0; i < data->nb_rx_queues; i++) {
5238 rxq = data->rx_queues[i];
5239 if (!rxq || !rxq->q_set)
5242 ret = i40e_rx_queue_init(rxq);
5243 if (ret != I40E_SUCCESS) {
5244 PMD_DRV_LOG(ERR, "Failed to do RX queue "
5249 if (ret == I40E_SUCCESS)
5250 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5257 i40e_dev_rxtx_init(struct i40e_pf *pf)
5261 err = i40e_dev_tx_init(pf);
5263 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5266 err = i40e_dev_rx_init(pf);
5268 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5276 i40e_vmdq_setup(struct rte_eth_dev *dev)
5278 struct rte_eth_conf *conf = &dev->data->dev_conf;
5279 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5280 int i, err, conf_vsis, j, loop;
5281 struct i40e_vsi *vsi;
5282 struct i40e_vmdq_info *vmdq_info;
5283 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5284 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5287 * Disable interrupt to avoid message from VF. Furthermore, it will
5288 * avoid race condition in VSI creation/destroy.
5290 i40e_pf_disable_irq0(hw);
5292 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5293 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5297 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5298 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5299 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5300 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5301 pf->max_nb_vmdq_vsi);
5305 if (pf->vmdq != NULL) {
5306 PMD_INIT_LOG(INFO, "VMDQ already configured");
5310 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5311 sizeof(*vmdq_info) * conf_vsis, 0);
5313 if (pf->vmdq == NULL) {
5314 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5318 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5320 /* Create VMDQ VSI */
5321 for (i = 0; i < conf_vsis; i++) {
5322 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5323 vmdq_conf->enable_loop_back);
5325 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5329 vmdq_info = &pf->vmdq[i];
5331 vmdq_info->vsi = vsi;
5333 pf->nb_cfg_vmdq_vsi = conf_vsis;
5335 /* Configure Vlan */
5336 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5337 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5338 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5339 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5340 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5341 vmdq_conf->pool_map[i].vlan_id, j);
5343 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5344 vmdq_conf->pool_map[i].vlan_id);
5346 PMD_INIT_LOG(ERR, "Failed to add vlan");
5354 i40e_pf_enable_irq0(hw);
5359 for (i = 0; i < conf_vsis; i++)
5360 if (pf->vmdq[i].vsi == NULL)
5363 i40e_vsi_release(pf->vmdq[i].vsi);
5367 i40e_pf_enable_irq0(hw);
5372 i40e_stat_update_32(struct i40e_hw *hw,
5380 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5384 if (new_data >= *offset)
5385 *stat = (uint64_t)(new_data - *offset);
5387 *stat = (uint64_t)((new_data +
5388 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5392 i40e_stat_update_48(struct i40e_hw *hw,
5401 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5402 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5403 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5408 if (new_data >= *offset)
5409 *stat = new_data - *offset;
5411 *stat = (uint64_t)((new_data +
5412 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5414 *stat &= I40E_48_BIT_MASK;
5419 i40e_pf_disable_irq0(struct i40e_hw *hw)
5421 /* Disable all interrupt types */
5422 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5423 I40E_WRITE_FLUSH(hw);
5428 i40e_pf_enable_irq0(struct i40e_hw *hw)
5430 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5431 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5432 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5433 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5434 I40E_WRITE_FLUSH(hw);
5438 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5440 /* read pending request and disable first */
5441 i40e_pf_disable_irq0(hw);
5442 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5443 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5444 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5447 /* Link no queues with irq0 */
5448 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5449 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5453 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5455 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5456 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5459 uint32_t index, offset, val;
5464 * Try to find which VF trigger a reset, use absolute VF id to access
5465 * since the reg is global register.
5467 for (i = 0; i < pf->vf_num; i++) {
5468 abs_vf_id = hw->func_caps.vf_base_id + i;
5469 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5470 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5471 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5472 /* VFR event occured */
5473 if (val & (0x1 << offset)) {
5476 /* Clear the event first */
5477 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5479 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5481 * Only notify a VF reset event occured,
5482 * don't trigger another SW reset
5484 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5485 if (ret != I40E_SUCCESS)
5486 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5492 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5494 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5495 struct i40e_virtchnl_pf_event event;
5498 event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5499 event.event_data.link_event.link_status =
5500 dev->data->dev_link.link_status;
5501 event.event_data.link_event.link_speed =
5502 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5504 for (i = 0; i < pf->vf_num; i++)
5505 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5506 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5510 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5512 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5513 struct i40e_arq_event_info info;
5514 uint16_t pending, opcode;
5517 info.buf_len = I40E_AQ_BUF_SZ;
5518 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5519 if (!info.msg_buf) {
5520 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5526 ret = i40e_clean_arq_element(hw, &info, &pending);
5528 if (ret != I40E_SUCCESS) {
5529 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5530 "aq_err: %u", hw->aq.asq_last_status);
5533 opcode = rte_le_to_cpu_16(info.desc.opcode);
5536 case i40e_aqc_opc_send_msg_to_pf:
5537 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5538 i40e_pf_host_handle_vf_msg(dev,
5539 rte_le_to_cpu_16(info.desc.retval),
5540 rte_le_to_cpu_32(info.desc.cookie_high),
5541 rte_le_to_cpu_32(info.desc.cookie_low),
5545 case i40e_aqc_opc_get_link_status:
5546 ret = i40e_dev_link_update(dev, 0);
5548 _rte_eth_dev_callback_process(dev,
5549 RTE_ETH_EVENT_INTR_LSC, NULL);
5552 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5557 rte_free(info.msg_buf);
5561 * Interrupt handler triggered by NIC for handling
5562 * specific interrupt.
5565 * Pointer to interrupt handle.
5567 * The address of parameter (struct rte_eth_dev *) regsitered before.
5573 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5576 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5577 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5580 /* Disable interrupt */
5581 i40e_pf_disable_irq0(hw);
5583 /* read out interrupt causes */
5584 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5586 /* No interrupt event indicated */
5587 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5588 PMD_DRV_LOG(INFO, "No interrupt event");
5591 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5592 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5593 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5594 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5595 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5596 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5597 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5598 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5599 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5600 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5601 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5602 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5603 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5604 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5605 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5606 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5608 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5609 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5610 i40e_dev_handle_vfr_event(dev);
5612 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5613 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5614 i40e_dev_handle_aq_msg(dev);
5618 /* Enable interrupt */
5619 i40e_pf_enable_irq0(hw);
5620 rte_intr_enable(&(dev->pci_dev->intr_handle));
5624 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5625 struct i40e_macvlan_filter *filter,
5628 int ele_num, ele_buff_size;
5629 int num, actual_num, i;
5631 int ret = I40E_SUCCESS;
5632 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5633 struct i40e_aqc_add_macvlan_element_data *req_list;
5635 if (filter == NULL || total == 0)
5636 return I40E_ERR_PARAM;
5637 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5638 ele_buff_size = hw->aq.asq_buf_size;
5640 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5641 if (req_list == NULL) {
5642 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5643 return I40E_ERR_NO_MEMORY;
5648 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5649 memset(req_list, 0, ele_buff_size);
5651 for (i = 0; i < actual_num; i++) {
5652 (void)rte_memcpy(req_list[i].mac_addr,
5653 &filter[num + i].macaddr, ETH_ADDR_LEN);
5654 req_list[i].vlan_tag =
5655 rte_cpu_to_le_16(filter[num + i].vlan_id);
5657 switch (filter[num + i].filter_type) {
5658 case RTE_MAC_PERFECT_MATCH:
5659 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5660 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5662 case RTE_MACVLAN_PERFECT_MATCH:
5663 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5665 case RTE_MAC_HASH_MATCH:
5666 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5667 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5669 case RTE_MACVLAN_HASH_MATCH:
5670 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5673 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5674 ret = I40E_ERR_PARAM;
5678 req_list[i].queue_number = 0;
5680 req_list[i].flags = rte_cpu_to_le_16(flags);
5683 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5685 if (ret != I40E_SUCCESS) {
5686 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5690 } while (num < total);
5698 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5699 struct i40e_macvlan_filter *filter,
5702 int ele_num, ele_buff_size;
5703 int num, actual_num, i;
5705 int ret = I40E_SUCCESS;
5706 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5707 struct i40e_aqc_remove_macvlan_element_data *req_list;
5709 if (filter == NULL || total == 0)
5710 return I40E_ERR_PARAM;
5712 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5713 ele_buff_size = hw->aq.asq_buf_size;
5715 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5716 if (req_list == NULL) {
5717 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5718 return I40E_ERR_NO_MEMORY;
5723 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5724 memset(req_list, 0, ele_buff_size);
5726 for (i = 0; i < actual_num; i++) {
5727 (void)rte_memcpy(req_list[i].mac_addr,
5728 &filter[num + i].macaddr, ETH_ADDR_LEN);
5729 req_list[i].vlan_tag =
5730 rte_cpu_to_le_16(filter[num + i].vlan_id);
5732 switch (filter[num + i].filter_type) {
5733 case RTE_MAC_PERFECT_MATCH:
5734 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5735 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5737 case RTE_MACVLAN_PERFECT_MATCH:
5738 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5740 case RTE_MAC_HASH_MATCH:
5741 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5742 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5744 case RTE_MACVLAN_HASH_MATCH:
5745 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5748 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5749 ret = I40E_ERR_PARAM;
5752 req_list[i].flags = rte_cpu_to_le_16(flags);
5755 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5757 if (ret != I40E_SUCCESS) {
5758 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5762 } while (num < total);
5769 /* Find out specific MAC filter */
5770 static struct i40e_mac_filter *
5771 i40e_find_mac_filter(struct i40e_vsi *vsi,
5772 struct ether_addr *macaddr)
5774 struct i40e_mac_filter *f;
5776 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5777 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5785 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5788 uint32_t vid_idx, vid_bit;
5790 if (vlan_id > ETH_VLAN_ID_MAX)
5793 vid_idx = I40E_VFTA_IDX(vlan_id);
5794 vid_bit = I40E_VFTA_BIT(vlan_id);
5796 if (vsi->vfta[vid_idx] & vid_bit)
5803 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5804 uint16_t vlan_id, bool on)
5806 uint32_t vid_idx, vid_bit;
5808 if (vlan_id > ETH_VLAN_ID_MAX)
5811 vid_idx = I40E_VFTA_IDX(vlan_id);
5812 vid_bit = I40E_VFTA_BIT(vlan_id);
5815 vsi->vfta[vid_idx] |= vid_bit;
5817 vsi->vfta[vid_idx] &= ~vid_bit;
5821 * Find all vlan options for specific mac addr,
5822 * return with actual vlan found.
5825 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5826 struct i40e_macvlan_filter *mv_f,
5827 int num, struct ether_addr *addr)
5833 * Not to use i40e_find_vlan_filter to decrease the loop time,
5834 * although the code looks complex.
5836 if (num < vsi->vlan_num)
5837 return I40E_ERR_PARAM;
5840 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5842 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5843 if (vsi->vfta[j] & (1 << k)) {
5845 PMD_DRV_LOG(ERR, "vlan number "
5847 return I40E_ERR_PARAM;
5849 (void)rte_memcpy(&mv_f[i].macaddr,
5850 addr, ETH_ADDR_LEN);
5852 j * I40E_UINT32_BIT_SIZE + k;
5858 return I40E_SUCCESS;
5862 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5863 struct i40e_macvlan_filter *mv_f,
5868 struct i40e_mac_filter *f;
5870 if (num < vsi->mac_num)
5871 return I40E_ERR_PARAM;
5873 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5875 PMD_DRV_LOG(ERR, "buffer number not match");
5876 return I40E_ERR_PARAM;
5878 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5880 mv_f[i].vlan_id = vlan;
5881 mv_f[i].filter_type = f->mac_info.filter_type;
5885 return I40E_SUCCESS;
5889 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5892 struct i40e_mac_filter *f;
5893 struct i40e_macvlan_filter *mv_f;
5894 int ret = I40E_SUCCESS;
5896 if (vsi == NULL || vsi->mac_num == 0)
5897 return I40E_ERR_PARAM;
5899 /* Case that no vlan is set */
5900 if (vsi->vlan_num == 0)
5903 num = vsi->mac_num * vsi->vlan_num;
5905 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5907 PMD_DRV_LOG(ERR, "failed to allocate memory");
5908 return I40E_ERR_NO_MEMORY;
5912 if (vsi->vlan_num == 0) {
5913 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5914 (void)rte_memcpy(&mv_f[i].macaddr,
5915 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5916 mv_f[i].filter_type = f->mac_info.filter_type;
5917 mv_f[i].vlan_id = 0;
5921 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5922 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5923 vsi->vlan_num, &f->mac_info.mac_addr);
5924 if (ret != I40E_SUCCESS)
5926 for (j = i; j < i + vsi->vlan_num; j++)
5927 mv_f[j].filter_type = f->mac_info.filter_type;
5932 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5940 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5942 struct i40e_macvlan_filter *mv_f;
5944 int ret = I40E_SUCCESS;
5946 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5947 return I40E_ERR_PARAM;
5949 /* If it's already set, just return */
5950 if (i40e_find_vlan_filter(vsi,vlan))
5951 return I40E_SUCCESS;
5953 mac_num = vsi->mac_num;
5956 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5957 return I40E_ERR_PARAM;
5960 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5963 PMD_DRV_LOG(ERR, "failed to allocate memory");
5964 return I40E_ERR_NO_MEMORY;
5967 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5969 if (ret != I40E_SUCCESS)
5972 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5974 if (ret != I40E_SUCCESS)
5977 i40e_set_vlan_filter(vsi, vlan, 1);
5987 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5989 struct i40e_macvlan_filter *mv_f;
5991 int ret = I40E_SUCCESS;
5994 * Vlan 0 is the generic filter for untagged packets
5995 * and can't be removed.
5997 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5998 return I40E_ERR_PARAM;
6000 /* If can't find it, just return */
6001 if (!i40e_find_vlan_filter(vsi, vlan))
6002 return I40E_ERR_PARAM;
6004 mac_num = vsi->mac_num;
6007 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6008 return I40E_ERR_PARAM;
6011 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6014 PMD_DRV_LOG(ERR, "failed to allocate memory");
6015 return I40E_ERR_NO_MEMORY;
6018 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6020 if (ret != I40E_SUCCESS)
6023 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6025 if (ret != I40E_SUCCESS)
6028 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6029 if (vsi->vlan_num == 1) {
6030 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6031 if (ret != I40E_SUCCESS)
6034 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6035 if (ret != I40E_SUCCESS)
6039 i40e_set_vlan_filter(vsi, vlan, 0);
6049 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6051 struct i40e_mac_filter *f;
6052 struct i40e_macvlan_filter *mv_f;
6053 int i, vlan_num = 0;
6054 int ret = I40E_SUCCESS;
6056 /* If it's add and we've config it, return */
6057 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6059 return I40E_SUCCESS;
6060 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6061 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6064 * If vlan_num is 0, that's the first time to add mac,
6065 * set mask for vlan_id 0.
6067 if (vsi->vlan_num == 0) {
6068 i40e_set_vlan_filter(vsi, 0, 1);
6071 vlan_num = vsi->vlan_num;
6072 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6073 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6076 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6078 PMD_DRV_LOG(ERR, "failed to allocate memory");
6079 return I40E_ERR_NO_MEMORY;
6082 for (i = 0; i < vlan_num; i++) {
6083 mv_f[i].filter_type = mac_filter->filter_type;
6084 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6088 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6089 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6090 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6091 &mac_filter->mac_addr);
6092 if (ret != I40E_SUCCESS)
6096 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6097 if (ret != I40E_SUCCESS)
6100 /* Add the mac addr into mac list */
6101 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6103 PMD_DRV_LOG(ERR, "failed to allocate memory");
6104 ret = I40E_ERR_NO_MEMORY;
6107 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6109 f->mac_info.filter_type = mac_filter->filter_type;
6110 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6121 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6123 struct i40e_mac_filter *f;
6124 struct i40e_macvlan_filter *mv_f;
6126 enum rte_mac_filter_type filter_type;
6127 int ret = I40E_SUCCESS;
6129 /* Can't find it, return an error */
6130 f = i40e_find_mac_filter(vsi, addr);
6132 return I40E_ERR_PARAM;
6134 vlan_num = vsi->vlan_num;
6135 filter_type = f->mac_info.filter_type;
6136 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6137 filter_type == RTE_MACVLAN_HASH_MATCH) {
6138 if (vlan_num == 0) {
6139 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6140 return I40E_ERR_PARAM;
6142 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6143 filter_type == RTE_MAC_HASH_MATCH)
6146 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6148 PMD_DRV_LOG(ERR, "failed to allocate memory");
6149 return I40E_ERR_NO_MEMORY;
6152 for (i = 0; i < vlan_num; i++) {
6153 mv_f[i].filter_type = filter_type;
6154 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6157 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6158 filter_type == RTE_MACVLAN_HASH_MATCH) {
6159 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6160 if (ret != I40E_SUCCESS)
6164 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6165 if (ret != I40E_SUCCESS)
6168 /* Remove the mac addr into mac list */
6169 TAILQ_REMOVE(&vsi->mac_list, f, next);
6179 /* Configure hash enable flags for RSS */
6181 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6188 if (flags & ETH_RSS_FRAG_IPV4)
6189 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6190 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6191 if (type == I40E_MAC_X722) {
6192 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6193 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6195 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6197 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6198 if (type == I40E_MAC_X722) {
6199 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6200 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6201 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6203 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6205 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6206 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6207 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6208 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6209 if (flags & ETH_RSS_FRAG_IPV6)
6210 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6211 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6212 if (type == I40E_MAC_X722) {
6213 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6214 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6216 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6218 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6219 if (type == I40E_MAC_X722) {
6220 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6221 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6222 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6224 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6226 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6227 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6228 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6229 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6230 if (flags & ETH_RSS_L2_PAYLOAD)
6231 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6236 /* Parse the hash enable flags */
6238 i40e_parse_hena(uint64_t flags)
6240 uint64_t rss_hf = 0;
6244 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6245 rss_hf |= ETH_RSS_FRAG_IPV4;
6246 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6247 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6249 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6250 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6252 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6253 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6255 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6256 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6257 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6258 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6260 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6261 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6262 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6263 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6264 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6265 rss_hf |= ETH_RSS_FRAG_IPV6;
6266 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6267 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6269 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6270 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6272 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6273 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6275 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6276 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6277 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6278 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6280 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6281 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6282 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6283 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6284 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6285 rss_hf |= ETH_RSS_L2_PAYLOAD;
6292 i40e_pf_disable_rss(struct i40e_pf *pf)
6294 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6297 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6298 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6299 if (hw->mac.type == I40E_MAC_X722)
6300 hena &= ~I40E_RSS_HENA_ALL_X722;
6302 hena &= ~I40E_RSS_HENA_ALL;
6303 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6304 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6305 I40E_WRITE_FLUSH(hw);
6309 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6311 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6312 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6315 if (!key || key_len == 0) {
6316 PMD_DRV_LOG(DEBUG, "No key to be configured");
6318 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6320 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6324 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6325 struct i40e_aqc_get_set_rss_key_data *key_dw =
6326 (struct i40e_aqc_get_set_rss_key_data *)key;
6328 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6330 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6333 uint32_t *hash_key = (uint32_t *)key;
6336 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6337 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6338 I40E_WRITE_FLUSH(hw);
6345 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6347 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6348 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6351 if (!key || !key_len)
6354 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6355 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6356 (struct i40e_aqc_get_set_rss_key_data *)key);
6358 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6362 uint32_t *key_dw = (uint32_t *)key;
6365 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6366 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6368 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6374 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6376 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6381 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6382 rss_conf->rss_key_len);
6386 rss_hf = rss_conf->rss_hf;
6387 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6388 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6389 if (hw->mac.type == I40E_MAC_X722)
6390 hena &= ~I40E_RSS_HENA_ALL_X722;
6392 hena &= ~I40E_RSS_HENA_ALL;
6393 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6394 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6395 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6396 I40E_WRITE_FLUSH(hw);
6402 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6403 struct rte_eth_rss_conf *rss_conf)
6405 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6406 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6407 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6410 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6411 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6412 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6413 ? I40E_RSS_HENA_ALL_X722
6414 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6415 if (rss_hf != 0) /* Enable RSS */
6417 return 0; /* Nothing to do */
6420 if (rss_hf == 0) /* Disable RSS */
6423 return i40e_hw_rss_hash_set(pf, rss_conf);
6427 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6428 struct rte_eth_rss_conf *rss_conf)
6430 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6431 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6434 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6435 &rss_conf->rss_key_len);
6437 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6438 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6439 rss_conf->rss_hf = i40e_parse_hena(hena);
6445 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6447 switch (filter_type) {
6448 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6449 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6451 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6452 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6454 case RTE_TUNNEL_FILTER_IMAC_TENID:
6455 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6457 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6458 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6460 case ETH_TUNNEL_FILTER_IMAC:
6461 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6463 case ETH_TUNNEL_FILTER_OIP:
6464 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6466 case ETH_TUNNEL_FILTER_IIP:
6467 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6470 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6478 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6479 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6484 uint8_t i, tun_type = 0;
6485 /* internal varialbe to convert ipv6 byte order */
6486 uint32_t convert_ipv6[4];
6488 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6489 struct i40e_vsi *vsi = pf->main_vsi;
6490 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6491 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6493 cld_filter = rte_zmalloc("tunnel_filter",
6494 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6497 if (NULL == cld_filter) {
6498 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6501 pfilter = cld_filter;
6503 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6504 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6506 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6507 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6508 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6509 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6510 rte_memcpy(&pfilter->ipaddr.v4.data,
6511 &rte_cpu_to_le_32(ipv4_addr),
6512 sizeof(pfilter->ipaddr.v4.data));
6514 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6515 for (i = 0; i < 4; i++) {
6517 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6519 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6520 sizeof(pfilter->ipaddr.v6.data));
6523 /* check tunneled type */
6524 switch (tunnel_filter->tunnel_type) {
6525 case RTE_TUNNEL_TYPE_VXLAN:
6526 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6528 case RTE_TUNNEL_TYPE_NVGRE:
6529 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6531 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6532 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6535 /* Other tunnel types is not supported. */
6536 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6537 rte_free(cld_filter);
6541 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6544 rte_free(cld_filter);
6548 pfilter->flags |= rte_cpu_to_le_16(
6549 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6550 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6551 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6552 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6555 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6557 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6560 rte_free(cld_filter);
6565 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6569 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6570 if (pf->vxlan_ports[i] == port)
6578 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6582 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6584 idx = i40e_get_vxlan_port_idx(pf, port);
6586 /* Check if port already exists */
6588 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6592 /* Now check if there is space to add the new port */
6593 idx = i40e_get_vxlan_port_idx(pf, 0);
6595 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6596 "not adding port %d", port);
6600 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6603 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6607 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6610 /* New port: add it and mark its index in the bitmap */
6611 pf->vxlan_ports[idx] = port;
6612 pf->vxlan_bitmap |= (1 << idx);
6614 if (!(pf->flags & I40E_FLAG_VXLAN))
6615 pf->flags |= I40E_FLAG_VXLAN;
6621 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6624 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6626 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6627 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6631 idx = i40e_get_vxlan_port_idx(pf, port);
6634 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6638 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6639 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6643 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6646 pf->vxlan_ports[idx] = 0;
6647 pf->vxlan_bitmap &= ~(1 << idx);
6649 if (!pf->vxlan_bitmap)
6650 pf->flags &= ~I40E_FLAG_VXLAN;
6655 /* Add UDP tunneling port */
6657 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6658 struct rte_eth_udp_tunnel *udp_tunnel)
6661 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6663 if (udp_tunnel == NULL)
6666 switch (udp_tunnel->prot_type) {
6667 case RTE_TUNNEL_TYPE_VXLAN:
6668 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6671 case RTE_TUNNEL_TYPE_GENEVE:
6672 case RTE_TUNNEL_TYPE_TEREDO:
6673 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6678 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6686 /* Remove UDP tunneling port */
6688 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6689 struct rte_eth_udp_tunnel *udp_tunnel)
6692 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6694 if (udp_tunnel == NULL)
6697 switch (udp_tunnel->prot_type) {
6698 case RTE_TUNNEL_TYPE_VXLAN:
6699 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6701 case RTE_TUNNEL_TYPE_GENEVE:
6702 case RTE_TUNNEL_TYPE_TEREDO:
6703 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6707 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6715 /* Calculate the maximum number of contiguous PF queues that are configured */
6717 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6719 struct rte_eth_dev_data *data = pf->dev_data;
6721 struct i40e_rx_queue *rxq;
6724 for (i = 0; i < pf->lan_nb_qps; i++) {
6725 rxq = data->rx_queues[i];
6726 if (rxq && rxq->q_set)
6737 i40e_pf_config_rss(struct i40e_pf *pf)
6739 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6740 struct rte_eth_rss_conf rss_conf;
6741 uint32_t i, lut = 0;
6745 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6746 * It's necessary to calulate the actual PF queues that are configured.
6748 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6749 num = i40e_pf_calc_configured_queues_num(pf);
6751 num = pf->dev_data->nb_rx_queues;
6753 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6754 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6758 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6762 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6765 lut = (lut << 8) | (j & ((0x1 <<
6766 hw->func_caps.rss_table_entry_width) - 1));
6768 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6771 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6772 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6773 i40e_pf_disable_rss(pf);
6776 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6777 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6778 /* Random default keys */
6779 static uint32_t rss_key_default[] = {0x6b793944,
6780 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6781 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6782 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6784 rss_conf.rss_key = (uint8_t *)rss_key_default;
6785 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6789 return i40e_hw_rss_hash_set(pf, &rss_conf);
6793 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6794 struct rte_eth_tunnel_filter_conf *filter)
6796 if (pf == NULL || filter == NULL) {
6797 PMD_DRV_LOG(ERR, "Invalid parameter");
6801 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6802 PMD_DRV_LOG(ERR, "Invalid queue ID");
6806 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6807 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6811 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6812 (is_zero_ether_addr(&filter->outer_mac))) {
6813 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6817 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6818 (is_zero_ether_addr(&filter->inner_mac))) {
6819 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6826 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6827 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6829 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6834 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6835 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6838 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6839 } else if (len == 4) {
6840 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6842 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6847 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6854 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6855 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6861 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6868 switch (cfg->cfg_type) {
6869 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6870 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6873 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6881 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6882 enum rte_filter_op filter_op,
6885 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6886 int ret = I40E_ERR_PARAM;
6888 switch (filter_op) {
6889 case RTE_ETH_FILTER_SET:
6890 ret = i40e_dev_global_config_set(hw,
6891 (struct rte_eth_global_cfg *)arg);
6894 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6902 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6903 enum rte_filter_op filter_op,
6906 struct rte_eth_tunnel_filter_conf *filter;
6907 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6908 int ret = I40E_SUCCESS;
6910 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6912 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6913 return I40E_ERR_PARAM;
6915 switch (filter_op) {
6916 case RTE_ETH_FILTER_NOP:
6917 if (!(pf->flags & I40E_FLAG_VXLAN))
6918 ret = I40E_NOT_SUPPORTED;
6920 case RTE_ETH_FILTER_ADD:
6921 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6923 case RTE_ETH_FILTER_DELETE:
6924 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6927 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6928 ret = I40E_ERR_PARAM;
6936 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6939 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6942 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6943 ret = i40e_pf_config_rss(pf);
6945 i40e_pf_disable_rss(pf);
6950 /* Get the symmetric hash enable configurations per port */
6952 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6954 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6956 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6959 /* Set the symmetric hash enable configurations per port */
6961 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6963 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6966 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6967 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6971 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6973 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6974 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6978 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6980 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6981 I40E_WRITE_FLUSH(hw);
6985 * Get global configurations of hash function type and symmetric hash enable
6986 * per flow type (pctype). Note that global configuration means it affects all
6987 * the ports on the same NIC.
6990 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6991 struct rte_eth_hash_global_conf *g_cfg)
6993 uint32_t reg, mask = I40E_FLOW_TYPES;
6995 enum i40e_filter_pctype pctype;
6997 memset(g_cfg, 0, sizeof(*g_cfg));
6998 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6999 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7000 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7002 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7003 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7004 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7006 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7007 if (!(mask & (1UL << i)))
7009 mask &= ~(1UL << i);
7010 /* Bit set indicats the coresponding flow type is supported */
7011 g_cfg->valid_bit_mask[0] |= (1UL << i);
7012 /* if flowtype is invalid, continue */
7013 if (!I40E_VALID_FLOW(i))
7015 pctype = i40e_flowtype_to_pctype(i);
7016 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7017 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7018 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7025 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7028 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7030 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7031 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7032 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7033 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7039 * As i40e supports less than 32 flow types, only first 32 bits need to
7042 mask0 = g_cfg->valid_bit_mask[0];
7043 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7045 /* Check if any unsupported flow type configured */
7046 if ((mask0 | i40e_mask) ^ i40e_mask)
7049 if (g_cfg->valid_bit_mask[i])
7057 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7063 * Set global configurations of hash function type and symmetric hash enable
7064 * per flow type (pctype). Note any modifying global configuration will affect
7065 * all the ports on the same NIC.
7068 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7069 struct rte_eth_hash_global_conf *g_cfg)
7074 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7075 enum i40e_filter_pctype pctype;
7077 /* Check the input parameters */
7078 ret = i40e_hash_global_config_check(g_cfg);
7082 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7083 if (!(mask0 & (1UL << i)))
7085 mask0 &= ~(1UL << i);
7086 /* if flowtype is invalid, continue */
7087 if (!I40E_VALID_FLOW(i))
7089 pctype = i40e_flowtype_to_pctype(i);
7090 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7091 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7092 if (hw->mac.type == I40E_MAC_X722) {
7093 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7094 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7095 I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7096 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7097 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7099 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7100 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7102 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7103 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7104 I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7105 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7106 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7108 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7109 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7110 I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7111 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7112 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7114 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7115 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7117 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7118 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7119 I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7120 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7121 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7124 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7128 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7132 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7133 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7135 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7136 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7140 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7141 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7143 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7144 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7148 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7150 /* Use the default, and keep it as it is */
7153 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7156 I40E_WRITE_FLUSH(hw);
7162 * Valid input sets for hash and flow director filters per PCTYPE
7165 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7166 enum rte_filter_type filter)
7170 static const uint64_t valid_hash_inset_table[] = {
7171 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7172 I40E_INSET_DMAC | I40E_INSET_SMAC |
7173 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7174 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7175 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7176 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7177 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7178 I40E_INSET_FLEX_PAYLOAD,
7179 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7180 I40E_INSET_DMAC | I40E_INSET_SMAC |
7181 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7182 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7183 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7184 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7185 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7186 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7187 I40E_INSET_FLEX_PAYLOAD,
7189 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7190 I40E_INSET_DMAC | I40E_INSET_SMAC |
7191 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7192 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7193 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7194 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7195 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7196 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7197 I40E_INSET_FLEX_PAYLOAD,
7198 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7199 I40E_INSET_DMAC | I40E_INSET_SMAC |
7200 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7201 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7202 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7203 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7204 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7205 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7206 I40E_INSET_FLEX_PAYLOAD,
7208 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7209 I40E_INSET_DMAC | I40E_INSET_SMAC |
7210 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7211 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7212 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7213 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7214 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7215 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7216 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7218 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7219 I40E_INSET_DMAC | I40E_INSET_SMAC |
7220 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7221 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7222 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7223 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7224 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7225 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7226 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7228 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7229 I40E_INSET_DMAC | I40E_INSET_SMAC |
7230 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7231 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7232 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7233 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7234 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7235 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7236 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7237 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7238 I40E_INSET_DMAC | I40E_INSET_SMAC |
7239 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7240 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7241 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7242 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7243 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7244 I40E_INSET_FLEX_PAYLOAD,
7245 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7246 I40E_INSET_DMAC | I40E_INSET_SMAC |
7247 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7248 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7249 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7250 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7251 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7252 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7253 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7254 I40E_INSET_DMAC | I40E_INSET_SMAC |
7255 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7256 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7257 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7258 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7259 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7260 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7262 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7263 I40E_INSET_DMAC | I40E_INSET_SMAC |
7264 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7265 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7266 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7267 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7268 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7269 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7270 I40E_INSET_FLEX_PAYLOAD,
7271 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7272 I40E_INSET_DMAC | I40E_INSET_SMAC |
7273 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7274 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7275 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7276 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7277 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7278 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7279 I40E_INSET_FLEX_PAYLOAD,
7281 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7282 I40E_INSET_DMAC | I40E_INSET_SMAC |
7283 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7284 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7285 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7286 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7287 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7288 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7289 I40E_INSET_FLEX_PAYLOAD,
7291 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7292 I40E_INSET_DMAC | I40E_INSET_SMAC |
7293 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7294 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7295 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7296 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7297 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7298 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7299 I40E_INSET_FLEX_PAYLOAD,
7301 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7302 I40E_INSET_DMAC | I40E_INSET_SMAC |
7303 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7304 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7305 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7306 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7307 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7308 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7309 I40E_INSET_FLEX_PAYLOAD,
7310 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7311 I40E_INSET_DMAC | I40E_INSET_SMAC |
7312 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7313 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7314 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7315 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7316 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7317 I40E_INSET_FLEX_PAYLOAD,
7318 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7319 I40E_INSET_DMAC | I40E_INSET_SMAC |
7320 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7321 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7322 I40E_INSET_FLEX_PAYLOAD,
7326 * Flow director supports only fields defined in
7327 * union rte_eth_fdir_flow.
7329 static const uint64_t valid_fdir_inset_table[] = {
7330 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7331 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7332 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7333 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7334 I40E_INSET_IPV4_TTL,
7335 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7336 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7337 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7338 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7339 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7341 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7342 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7343 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7344 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7345 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7346 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7347 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7348 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7349 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7350 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7352 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7353 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7354 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7355 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7356 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7358 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7359 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7360 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7361 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7362 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7364 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7365 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7366 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7367 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7368 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7370 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7371 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7372 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7373 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7374 I40E_INSET_IPV4_TTL,
7375 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7376 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7377 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7378 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7379 I40E_INSET_IPV6_HOP_LIMIT,
7380 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7381 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7382 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7383 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7384 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7386 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7387 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7388 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7389 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7390 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7391 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7392 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7393 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7394 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7395 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7397 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7398 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7399 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7400 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7401 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7403 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7404 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7405 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7406 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7407 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7409 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7410 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7411 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7412 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7413 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7415 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7416 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7417 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7418 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7419 I40E_INSET_IPV6_HOP_LIMIT,
7420 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7421 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7422 I40E_INSET_LAST_ETHER_TYPE,
7425 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7427 if (filter == RTE_ETH_FILTER_HASH)
7428 valid = valid_hash_inset_table[pctype];
7430 valid = valid_fdir_inset_table[pctype];
7436 * Validate if the input set is allowed for a specific PCTYPE
7439 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7440 enum rte_filter_type filter, uint64_t inset)
7444 valid = i40e_get_valid_input_set(pctype, filter);
7445 if (inset & (~valid))
7451 /* default input set fields combination per pctype */
7453 i40e_get_default_input_set(uint16_t pctype)
7455 static const uint64_t default_inset_table[] = {
7456 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7457 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7458 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7459 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7460 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7462 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7463 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7464 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7465 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7466 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7467 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7469 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7470 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7471 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7473 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7474 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7475 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7477 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7478 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7479 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7481 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7482 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7483 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7484 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7485 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7486 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7487 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7489 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7490 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7491 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7492 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7493 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7494 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7496 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7497 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7498 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7500 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7501 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7502 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7504 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7505 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7506 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7508 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7509 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7510 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7511 I40E_INSET_LAST_ETHER_TYPE,
7514 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7517 return default_inset_table[pctype];
7521 * Parse the input set from index to logical bit masks
7524 i40e_parse_input_set(uint64_t *inset,
7525 enum i40e_filter_pctype pctype,
7526 enum rte_eth_input_set_field *field,
7532 static const struct {
7533 enum rte_eth_input_set_field field;
7535 } inset_convert_table[] = {
7536 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7537 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7538 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7539 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7540 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7541 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7542 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7543 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7544 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7545 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7546 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7547 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7548 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7549 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7550 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7551 I40E_INSET_IPV6_NEXT_HDR},
7552 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7553 I40E_INSET_IPV6_HOP_LIMIT},
7554 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7555 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7556 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7557 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7558 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7559 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7560 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7561 I40E_INSET_SCTP_VT},
7562 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7563 I40E_INSET_TUNNEL_DMAC},
7564 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7565 I40E_INSET_VLAN_TUNNEL},
7566 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7567 I40E_INSET_TUNNEL_ID},
7568 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7569 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7570 I40E_INSET_FLEX_PAYLOAD_W1},
7571 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7572 I40E_INSET_FLEX_PAYLOAD_W2},
7573 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7574 I40E_INSET_FLEX_PAYLOAD_W3},
7575 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7576 I40E_INSET_FLEX_PAYLOAD_W4},
7577 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7578 I40E_INSET_FLEX_PAYLOAD_W5},
7579 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7580 I40E_INSET_FLEX_PAYLOAD_W6},
7581 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7582 I40E_INSET_FLEX_PAYLOAD_W7},
7583 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7584 I40E_INSET_FLEX_PAYLOAD_W8},
7587 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7590 /* Only one item allowed for default or all */
7592 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7593 *inset = i40e_get_default_input_set(pctype);
7595 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7596 *inset = I40E_INSET_NONE;
7601 for (i = 0, *inset = 0; i < size; i++) {
7602 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7603 if (field[i] == inset_convert_table[j].field) {
7604 *inset |= inset_convert_table[j].inset;
7609 /* It contains unsupported input set, return immediately */
7610 if (j == RTE_DIM(inset_convert_table))
7618 * Translate the input set from bit masks to register aware bit masks
7622 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7632 static const struct inset_map inset_map_common[] = {
7633 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7634 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7635 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7636 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7637 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7638 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7639 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7640 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7641 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7642 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7643 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7644 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7645 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7646 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7647 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7648 {I40E_INSET_TUNNEL_DMAC,
7649 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7650 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7651 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7652 {I40E_INSET_TUNNEL_SRC_PORT,
7653 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7654 {I40E_INSET_TUNNEL_DST_PORT,
7655 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7656 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7657 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7658 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7659 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7660 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7661 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7662 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7663 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7664 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7667 /* some different registers map in x722*/
7668 static const struct inset_map inset_map_diff_x722[] = {
7669 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7670 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7671 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7672 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7675 static const struct inset_map inset_map_diff_not_x722[] = {
7676 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7677 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7678 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7679 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7685 /* Translate input set to register aware inset */
7686 if (type == I40E_MAC_X722) {
7687 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7688 if (input & inset_map_diff_x722[i].inset)
7689 val |= inset_map_diff_x722[i].inset_reg;
7692 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7693 if (input & inset_map_diff_not_x722[i].inset)
7694 val |= inset_map_diff_not_x722[i].inset_reg;
7698 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7699 if (input & inset_map_common[i].inset)
7700 val |= inset_map_common[i].inset_reg;
7707 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7710 uint64_t inset_need_mask = inset;
7712 static const struct {
7715 } inset_mask_map[] = {
7716 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7717 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7718 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7719 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7720 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7721 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7722 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7723 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7726 if (!inset || !mask || !nb_elem)
7729 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7730 /* Clear the inset bit, if no MASK is required,
7731 * for example proto + ttl
7733 if ((inset & inset_mask_map[i].inset) ==
7734 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7735 inset_need_mask &= ~inset_mask_map[i].inset;
7736 if (!inset_need_mask)
7739 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7740 if ((inset_need_mask & inset_mask_map[i].inset) ==
7741 inset_mask_map[i].inset) {
7742 if (idx >= nb_elem) {
7743 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7746 mask[idx] = inset_mask_map[i].mask;
7755 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7757 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7759 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7761 i40e_write_rx_ctl(hw, addr, val);
7762 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7763 (uint32_t)i40e_read_rx_ctl(hw, addr));
7767 i40e_filter_input_set_init(struct i40e_pf *pf)
7769 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7770 enum i40e_filter_pctype pctype;
7771 uint64_t input_set, inset_reg;
7772 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7775 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7776 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7777 if (hw->mac.type == I40E_MAC_X722) {
7778 if (!I40E_VALID_PCTYPE_X722(pctype))
7781 if (!I40E_VALID_PCTYPE(pctype))
7785 input_set = i40e_get_default_input_set(pctype);
7787 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7788 I40E_INSET_MASK_NUM_REG);
7791 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7794 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7795 (uint32_t)(inset_reg & UINT32_MAX));
7796 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7797 (uint32_t)((inset_reg >>
7798 I40E_32_BIT_WIDTH) & UINT32_MAX));
7799 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7800 (uint32_t)(inset_reg & UINT32_MAX));
7801 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7802 (uint32_t)((inset_reg >>
7803 I40E_32_BIT_WIDTH) & UINT32_MAX));
7805 for (i = 0; i < num; i++) {
7806 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7808 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7811 /*clear unused mask registers of the pctype */
7812 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7813 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7815 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7818 I40E_WRITE_FLUSH(hw);
7820 /* store the default input set */
7821 pf->hash_input_set[pctype] = input_set;
7822 pf->fdir.input_set[pctype] = input_set;
7827 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7828 struct rte_eth_input_set_conf *conf)
7830 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7831 enum i40e_filter_pctype pctype;
7832 uint64_t input_set, inset_reg = 0;
7833 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7837 PMD_DRV_LOG(ERR, "Invalid pointer");
7840 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7841 conf->op != RTE_ETH_INPUT_SET_ADD) {
7842 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7846 if (!I40E_VALID_FLOW(conf->flow_type)) {
7847 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7851 if (hw->mac.type == I40E_MAC_X722) {
7852 /* get translated pctype value in fd pctype register */
7853 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7854 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7857 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7859 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7862 PMD_DRV_LOG(ERR, "Failed to parse input set");
7865 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7867 PMD_DRV_LOG(ERR, "Invalid input set");
7870 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7871 /* get inset value in register */
7872 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7873 inset_reg <<= I40E_32_BIT_WIDTH;
7874 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7875 input_set |= pf->hash_input_set[pctype];
7877 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7878 I40E_INSET_MASK_NUM_REG);
7882 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7884 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7885 (uint32_t)(inset_reg & UINT32_MAX));
7886 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7887 (uint32_t)((inset_reg >>
7888 I40E_32_BIT_WIDTH) & UINT32_MAX));
7890 for (i = 0; i < num; i++)
7891 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7893 /*clear unused mask registers of the pctype */
7894 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7895 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7897 I40E_WRITE_FLUSH(hw);
7899 pf->hash_input_set[pctype] = input_set;
7904 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7905 struct rte_eth_input_set_conf *conf)
7907 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7908 enum i40e_filter_pctype pctype;
7909 uint64_t input_set, inset_reg = 0;
7910 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7914 PMD_DRV_LOG(ERR, "Invalid pointer");
7917 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7918 conf->op != RTE_ETH_INPUT_SET_ADD) {
7919 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7923 if (!I40E_VALID_FLOW(conf->flow_type)) {
7924 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7928 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7930 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7933 PMD_DRV_LOG(ERR, "Failed to parse input set");
7936 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7938 PMD_DRV_LOG(ERR, "Invalid input set");
7942 /* get inset value in register */
7943 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7944 inset_reg <<= I40E_32_BIT_WIDTH;
7945 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7947 /* Can not change the inset reg for flex payload for fdir,
7948 * it is done by writing I40E_PRTQF_FD_FLXINSET
7949 * in i40e_set_flex_mask_on_pctype.
7951 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7952 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7954 input_set |= pf->fdir.input_set[pctype];
7955 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7956 I40E_INSET_MASK_NUM_REG);
7960 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7962 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7963 (uint32_t)(inset_reg & UINT32_MAX));
7964 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7965 (uint32_t)((inset_reg >>
7966 I40E_32_BIT_WIDTH) & UINT32_MAX));
7968 for (i = 0; i < num; i++)
7969 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7971 /*clear unused mask registers of the pctype */
7972 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7973 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7975 I40E_WRITE_FLUSH(hw);
7977 pf->fdir.input_set[pctype] = input_set;
7982 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7987 PMD_DRV_LOG(ERR, "Invalid pointer");
7991 switch (info->info_type) {
7992 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7993 i40e_get_symmetric_hash_enable_per_port(hw,
7994 &(info->info.enable));
7996 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7997 ret = i40e_get_hash_filter_global_config(hw,
7998 &(info->info.global_conf));
8001 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8011 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8016 PMD_DRV_LOG(ERR, "Invalid pointer");
8020 switch (info->info_type) {
8021 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8022 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8024 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8025 ret = i40e_set_hash_filter_global_config(hw,
8026 &(info->info.global_conf));
8028 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8029 ret = i40e_hash_filter_inset_select(hw,
8030 &(info->info.input_set_conf));
8034 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8043 /* Operations for hash function */
8045 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8046 enum rte_filter_op filter_op,
8049 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8052 switch (filter_op) {
8053 case RTE_ETH_FILTER_NOP:
8055 case RTE_ETH_FILTER_GET:
8056 ret = i40e_hash_filter_get(hw,
8057 (struct rte_eth_hash_filter_info *)arg);
8059 case RTE_ETH_FILTER_SET:
8060 ret = i40e_hash_filter_set(hw,
8061 (struct rte_eth_hash_filter_info *)arg);
8064 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8074 * Configure ethertype filter, which can director packet by filtering
8075 * with mac address and ether_type or only ether_type
8078 i40e_ethertype_filter_set(struct i40e_pf *pf,
8079 struct rte_eth_ethertype_filter *filter,
8082 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8083 struct i40e_control_filter_stats stats;
8087 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8088 PMD_DRV_LOG(ERR, "Invalid queue ID");
8091 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8092 filter->ether_type == ETHER_TYPE_IPv6) {
8093 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8094 " control packet filter.", filter->ether_type);
8097 if (filter->ether_type == ETHER_TYPE_VLAN)
8098 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8101 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8102 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8103 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8104 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8105 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8107 memset(&stats, 0, sizeof(stats));
8108 ret = i40e_aq_add_rem_control_packet_filter(hw,
8109 filter->mac_addr.addr_bytes,
8110 filter->ether_type, flags,
8112 filter->queue, add, &stats, NULL);
8114 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8115 " mac_etype_used = %u, etype_used = %u,"
8116 " mac_etype_free = %u, etype_free = %u\n",
8117 ret, stats.mac_etype_used, stats.etype_used,
8118 stats.mac_etype_free, stats.etype_free);
8125 * Handle operations for ethertype filter.
8128 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8129 enum rte_filter_op filter_op,
8132 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8135 if (filter_op == RTE_ETH_FILTER_NOP)
8139 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8144 switch (filter_op) {
8145 case RTE_ETH_FILTER_ADD:
8146 ret = i40e_ethertype_filter_set(pf,
8147 (struct rte_eth_ethertype_filter *)arg,
8150 case RTE_ETH_FILTER_DELETE:
8151 ret = i40e_ethertype_filter_set(pf,
8152 (struct rte_eth_ethertype_filter *)arg,
8156 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8164 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8165 enum rte_filter_type filter_type,
8166 enum rte_filter_op filter_op,
8174 switch (filter_type) {
8175 case RTE_ETH_FILTER_NONE:
8176 /* For global configuration */
8177 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8179 case RTE_ETH_FILTER_HASH:
8180 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8182 case RTE_ETH_FILTER_MACVLAN:
8183 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8185 case RTE_ETH_FILTER_ETHERTYPE:
8186 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8188 case RTE_ETH_FILTER_TUNNEL:
8189 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8191 case RTE_ETH_FILTER_FDIR:
8192 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8195 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8205 * Check and enable Extended Tag.
8206 * Enabling Extended Tag is important for 40G performance.
8209 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8214 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8217 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8221 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8222 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8227 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8230 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8234 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8235 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8238 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8239 ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8242 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8249 * As some registers wouldn't be reset unless a global hardware reset,
8250 * hardware initialization is needed to put those registers into an
8251 * expected initial state.
8254 i40e_hw_init(struct rte_eth_dev *dev)
8256 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8258 i40e_enable_extended_tag(dev);
8260 /* clear the PF Queue Filter control register */
8261 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8263 /* Disable symmetric hash per port */
8264 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8267 enum i40e_filter_pctype
8268 i40e_flowtype_to_pctype(uint16_t flow_type)
8270 static const enum i40e_filter_pctype pctype_table[] = {
8271 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8272 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8273 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8274 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8275 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8276 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8277 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8278 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8279 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8280 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8281 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8282 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8283 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8284 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8285 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8286 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8287 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8288 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8289 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8292 return pctype_table[flow_type];
8296 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8298 static const uint16_t flowtype_table[] = {
8299 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8300 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8301 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8303 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8304 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8305 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8306 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8308 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8309 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8311 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8312 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8314 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8315 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8316 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8317 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8318 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8319 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8320 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8322 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8323 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8324 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8325 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8327 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8328 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8330 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8331 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8333 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8334 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8335 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8336 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8337 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8340 return flowtype_table[pctype];
8344 * On X710, performance number is far from the expectation on recent firmware
8345 * versions; on XL710, performance number is also far from the expectation on
8346 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8347 * mode is enabled and port MAC address is equal to the packet destination MAC
8348 * address. The fix for this issue may not be integrated in the following
8349 * firmware version. So the workaround in software driver is needed. It needs
8350 * to modify the initial values of 3 internal only registers for both X710 and
8351 * XL710. Note that the values for X710 or XL710 could be different, and the
8352 * workaround can be removed when it is fixed in firmware in the future.
8355 /* For both X710 and XL710 */
8356 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
8357 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x20000200
8358 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
8360 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8361 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
8364 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
8365 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
8368 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
8370 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
8371 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
8374 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8376 enum i40e_status_code status;
8377 struct i40e_aq_get_phy_abilities_resp phy_ab;
8380 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8390 i40e_configure_registers(struct i40e_hw *hw)
8396 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
8397 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
8398 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8404 for (i = 0; i < RTE_DIM(reg_table); i++) {
8405 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
8406 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8408 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8409 else /* For X710/XL710/XXV710 */
8410 if (hw->aq.fw_maj_ver < 6)
8412 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
8415 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
8418 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
8419 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8421 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8422 else /* For X710/XL710/XXV710 */
8424 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8427 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8428 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8429 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8431 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8434 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8437 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8440 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8444 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8445 reg_table[i].addr, reg);
8446 if (reg == reg_table[i].val)
8449 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8450 reg_table[i].val, NULL);
8452 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8453 "address of 0x%"PRIx32, reg_table[i].val,
8457 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8458 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8462 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
8463 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
8464 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
8465 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8467 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8472 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8473 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8477 /* Configure for double VLAN RX stripping */
8478 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8479 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8480 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8481 ret = i40e_aq_debug_write_register(hw,
8482 I40E_VSI_TSR(vsi->vsi_id),
8485 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8487 return I40E_ERR_CONFIG;
8491 /* Configure for double VLAN TX insertion */
8492 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8493 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8494 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8495 ret = i40e_aq_debug_write_register(hw,
8496 I40E_VSI_L2TAGSTXVALID(
8497 vsi->vsi_id), reg, NULL);
8499 PMD_DRV_LOG(ERR, "Failed to update "
8500 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8501 return I40E_ERR_CONFIG;
8509 * i40e_aq_add_mirror_rule
8510 * @hw: pointer to the hardware structure
8511 * @seid: VEB seid to add mirror rule to
8512 * @dst_id: destination vsi seid
8513 * @entries: Buffer which contains the entities to be mirrored
8514 * @count: number of entities contained in the buffer
8515 * @rule_id:the rule_id of the rule to be added
8517 * Add a mirror rule for a given veb.
8520 static enum i40e_status_code
8521 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8522 uint16_t seid, uint16_t dst_id,
8523 uint16_t rule_type, uint16_t *entries,
8524 uint16_t count, uint16_t *rule_id)
8526 struct i40e_aq_desc desc;
8527 struct i40e_aqc_add_delete_mirror_rule cmd;
8528 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8529 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8532 enum i40e_status_code status;
8534 i40e_fill_default_direct_cmd_desc(&desc,
8535 i40e_aqc_opc_add_mirror_rule);
8536 memset(&cmd, 0, sizeof(cmd));
8538 buff_len = sizeof(uint16_t) * count;
8539 desc.datalen = rte_cpu_to_le_16(buff_len);
8541 desc.flags |= rte_cpu_to_le_16(
8542 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8543 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8544 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8545 cmd.num_entries = rte_cpu_to_le_16(count);
8546 cmd.seid = rte_cpu_to_le_16(seid);
8547 cmd.destination = rte_cpu_to_le_16(dst_id);
8549 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8550 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8551 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8553 " mirror_rules_used = %u, mirror_rules_free = %u,",
8554 hw->aq.asq_last_status, resp->rule_id,
8555 resp->mirror_rules_used, resp->mirror_rules_free);
8556 *rule_id = rte_le_to_cpu_16(resp->rule_id);
8562 * i40e_aq_del_mirror_rule
8563 * @hw: pointer to the hardware structure
8564 * @seid: VEB seid to add mirror rule to
8565 * @entries: Buffer which contains the entities to be mirrored
8566 * @count: number of entities contained in the buffer
8567 * @rule_id:the rule_id of the rule to be delete
8569 * Delete a mirror rule for a given veb.
8572 static enum i40e_status_code
8573 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8574 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8575 uint16_t count, uint16_t rule_id)
8577 struct i40e_aq_desc desc;
8578 struct i40e_aqc_add_delete_mirror_rule cmd;
8579 uint16_t buff_len = 0;
8580 enum i40e_status_code status;
8583 i40e_fill_default_direct_cmd_desc(&desc,
8584 i40e_aqc_opc_delete_mirror_rule);
8585 memset(&cmd, 0, sizeof(cmd));
8586 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8587 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8589 cmd.num_entries = count;
8590 buff_len = sizeof(uint16_t) * count;
8591 desc.datalen = rte_cpu_to_le_16(buff_len);
8592 buff = (void *)entries;
8594 /* rule id is filled in destination field for deleting mirror rule */
8595 cmd.destination = rte_cpu_to_le_16(rule_id);
8597 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8598 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8599 cmd.seid = rte_cpu_to_le_16(seid);
8601 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8602 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8608 * i40e_mirror_rule_set
8609 * @dev: pointer to the hardware structure
8610 * @mirror_conf: mirror rule info
8611 * @sw_id: mirror rule's sw_id
8612 * @on: enable/disable
8614 * set a mirror rule.
8618 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8619 struct rte_eth_mirror_conf *mirror_conf,
8620 uint8_t sw_id, uint8_t on)
8622 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8623 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8624 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8625 struct i40e_mirror_rule *parent = NULL;
8626 uint16_t seid, dst_seid, rule_id;
8630 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8632 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8633 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8634 " without veb or vfs.");
8637 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8638 PMD_DRV_LOG(ERR, "mirror table is full.");
8641 if (mirror_conf->dst_pool > pf->vf_num) {
8642 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8643 mirror_conf->dst_pool);
8647 seid = pf->main_vsi->veb->seid;
8649 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8650 if (sw_id <= it->index) {
8656 if (mirr_rule && sw_id == mirr_rule->index) {
8658 PMD_DRV_LOG(ERR, "mirror rule exists.");
8661 ret = i40e_aq_del_mirror_rule(hw, seid,
8662 mirr_rule->rule_type,
8664 mirr_rule->num_entries, mirr_rule->id);
8666 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8667 " ret = %d, aq_err = %d.",
8668 ret, hw->aq.asq_last_status);
8671 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8672 rte_free(mirr_rule);
8673 pf->nb_mirror_rule--;
8677 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8681 mirr_rule = rte_zmalloc("i40e_mirror_rule",
8682 sizeof(struct i40e_mirror_rule) , 0);
8684 PMD_DRV_LOG(ERR, "failed to allocate memory");
8685 return I40E_ERR_NO_MEMORY;
8687 switch (mirror_conf->rule_type) {
8688 case ETH_MIRROR_VLAN:
8689 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8690 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8691 mirr_rule->entries[j] =
8692 mirror_conf->vlan.vlan_id[i];
8697 PMD_DRV_LOG(ERR, "vlan is not specified.");
8698 rte_free(mirr_rule);
8701 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8703 case ETH_MIRROR_VIRTUAL_POOL_UP:
8704 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8705 /* check if the specified pool bit is out of range */
8706 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8707 PMD_DRV_LOG(ERR, "pool mask is out of range.");
8708 rte_free(mirr_rule);
8711 for (i = 0, j = 0; i < pf->vf_num; i++) {
8712 if (mirror_conf->pool_mask & (1ULL << i)) {
8713 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8717 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8718 /* add pf vsi to entries */
8719 mirr_rule->entries[j] = pf->main_vsi_seid;
8723 PMD_DRV_LOG(ERR, "pool is not specified.");
8724 rte_free(mirr_rule);
8727 /* egress and ingress in aq commands means from switch but not port */
8728 mirr_rule->rule_type =
8729 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8730 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8731 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8733 case ETH_MIRROR_UPLINK_PORT:
8734 /* egress and ingress in aq commands means from switch but not port*/
8735 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8737 case ETH_MIRROR_DOWNLINK_PORT:
8738 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8741 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8742 mirror_conf->rule_type);
8743 rte_free(mirr_rule);
8747 /* If the dst_pool is equal to vf_num, consider it as PF */
8748 if (mirror_conf->dst_pool == pf->vf_num)
8749 dst_seid = pf->main_vsi_seid;
8751 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8753 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8754 mirr_rule->rule_type, mirr_rule->entries,
8757 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8758 " ret = %d, aq_err = %d.",
8759 ret, hw->aq.asq_last_status);
8760 rte_free(mirr_rule);
8764 mirr_rule->index = sw_id;
8765 mirr_rule->num_entries = j;
8766 mirr_rule->id = rule_id;
8767 mirr_rule->dst_vsi_seid = dst_seid;
8770 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8772 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8774 pf->nb_mirror_rule++;
8779 * i40e_mirror_rule_reset
8780 * @dev: pointer to the device
8781 * @sw_id: mirror rule's sw_id
8783 * reset a mirror rule.
8787 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8789 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8790 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8791 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8795 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8797 seid = pf->main_vsi->veb->seid;
8799 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8800 if (sw_id == it->index) {
8806 ret = i40e_aq_del_mirror_rule(hw, seid,
8807 mirr_rule->rule_type,
8809 mirr_rule->num_entries, mirr_rule->id);
8811 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8812 " status = %d, aq_err = %d.",
8813 ret, hw->aq.asq_last_status);
8816 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8817 rte_free(mirr_rule);
8818 pf->nb_mirror_rule--;
8820 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8827 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8829 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8830 uint64_t systim_cycles;
8832 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8833 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8836 return systim_cycles;
8840 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8842 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8845 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8846 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8853 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8855 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8858 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8859 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8866 i40e_start_timecounters(struct rte_eth_dev *dev)
8868 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8869 struct i40e_adapter *adapter =
8870 (struct i40e_adapter *)dev->data->dev_private;
8871 struct rte_eth_link link;
8872 uint32_t tsync_inc_l;
8873 uint32_t tsync_inc_h;
8875 /* Get current link speed. */
8876 memset(&link, 0, sizeof(link));
8877 i40e_dev_link_update(dev, 1);
8878 rte_i40e_dev_atomic_read_link_status(dev, &link);
8880 switch (link.link_speed) {
8881 case ETH_SPEED_NUM_40G:
8882 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8883 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8885 case ETH_SPEED_NUM_10G:
8886 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8887 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8889 case ETH_SPEED_NUM_1G:
8890 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8891 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8898 /* Set the timesync increment value. */
8899 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8900 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8902 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8903 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8904 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8906 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8907 adapter->systime_tc.cc_shift = 0;
8908 adapter->systime_tc.nsec_mask = 0;
8910 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8911 adapter->rx_tstamp_tc.cc_shift = 0;
8912 adapter->rx_tstamp_tc.nsec_mask = 0;
8914 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8915 adapter->tx_tstamp_tc.cc_shift = 0;
8916 adapter->tx_tstamp_tc.nsec_mask = 0;
8920 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8922 struct i40e_adapter *adapter =
8923 (struct i40e_adapter *)dev->data->dev_private;
8925 adapter->systime_tc.nsec += delta;
8926 adapter->rx_tstamp_tc.nsec += delta;
8927 adapter->tx_tstamp_tc.nsec += delta;
8933 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8936 struct i40e_adapter *adapter =
8937 (struct i40e_adapter *)dev->data->dev_private;
8939 ns = rte_timespec_to_ns(ts);
8941 /* Set the timecounters to a new value. */
8942 adapter->systime_tc.nsec = ns;
8943 adapter->rx_tstamp_tc.nsec = ns;
8944 adapter->tx_tstamp_tc.nsec = ns;
8950 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8952 uint64_t ns, systime_cycles;
8953 struct i40e_adapter *adapter =
8954 (struct i40e_adapter *)dev->data->dev_private;
8956 systime_cycles = i40e_read_systime_cyclecounter(dev);
8957 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8958 *ts = rte_ns_to_timespec(ns);
8964 i40e_timesync_enable(struct rte_eth_dev *dev)
8966 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8967 uint32_t tsync_ctl_l;
8968 uint32_t tsync_ctl_h;
8970 /* Stop the timesync system time. */
8971 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8972 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8973 /* Reset the timesync system time value. */
8974 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8975 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8977 i40e_start_timecounters(dev);
8979 /* Clear timesync registers. */
8980 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8981 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8982 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8983 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8984 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8985 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8987 /* Enable timestamping of PTP packets. */
8988 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8989 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8991 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8992 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8993 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8995 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8996 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9002 i40e_timesync_disable(struct rte_eth_dev *dev)
9004 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9005 uint32_t tsync_ctl_l;
9006 uint32_t tsync_ctl_h;
9008 /* Disable timestamping of transmitted PTP packets. */
9009 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9010 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9012 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9013 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9015 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9016 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9018 /* Reset the timesync increment value. */
9019 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9020 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9026 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9027 struct timespec *timestamp, uint32_t flags)
9029 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9030 struct i40e_adapter *adapter =
9031 (struct i40e_adapter *)dev->data->dev_private;
9033 uint32_t sync_status;
9034 uint32_t index = flags & 0x03;
9035 uint64_t rx_tstamp_cycles;
9038 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9039 if ((sync_status & (1 << index)) == 0)
9042 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9043 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9044 *timestamp = rte_ns_to_timespec(ns);
9050 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9051 struct timespec *timestamp)
9053 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9054 struct i40e_adapter *adapter =
9055 (struct i40e_adapter *)dev->data->dev_private;
9057 uint32_t sync_status;
9058 uint64_t tx_tstamp_cycles;
9061 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9062 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9065 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9066 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9067 *timestamp = rte_ns_to_timespec(ns);
9073 * i40e_parse_dcb_configure - parse dcb configure from user
9074 * @dev: the device being configured
9075 * @dcb_cfg: pointer of the result of parse
9076 * @*tc_map: bit map of enabled traffic classes
9078 * Returns 0 on success, negative value on failure
9081 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9082 struct i40e_dcbx_config *dcb_cfg,
9085 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9086 uint8_t i, tc_bw, bw_lf;
9088 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9090 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9091 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9092 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9096 /* assume each tc has the same bw */
9097 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9098 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9099 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9100 /* to ensure the sum of tcbw is equal to 100 */
9101 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9102 for (i = 0; i < bw_lf; i++)
9103 dcb_cfg->etscfg.tcbwtable[i]++;
9105 /* assume each tc has the same Transmission Selection Algorithm */
9106 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9107 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9109 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9110 dcb_cfg->etscfg.prioritytable[i] =
9111 dcb_rx_conf->dcb_tc[i];
9113 /* FW needs one App to configure HW */
9114 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9115 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9116 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9117 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9119 if (dcb_rx_conf->nb_tcs == 0)
9120 *tc_map = 1; /* tc0 only */
9122 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9124 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9125 dcb_cfg->pfc.willing = 0;
9126 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9127 dcb_cfg->pfc.pfcenable = *tc_map;
9133 static enum i40e_status_code
9134 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9135 struct i40e_aqc_vsi_properties_data *info,
9136 uint8_t enabled_tcmap)
9138 enum i40e_status_code ret;
9139 int i, total_tc = 0;
9140 uint16_t qpnum_per_tc, bsf, qp_idx;
9141 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9142 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9143 uint16_t used_queues;
9145 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9146 if (ret != I40E_SUCCESS)
9149 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9150 if (enabled_tcmap & (1 << i))
9155 vsi->enabled_tc = enabled_tcmap;
9157 /* different VSI has different queues assigned */
9158 if (vsi->type == I40E_VSI_MAIN)
9159 used_queues = dev_data->nb_rx_queues -
9160 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9161 else if (vsi->type == I40E_VSI_VMDQ2)
9162 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9164 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9165 return I40E_ERR_NO_AVAILABLE_VSI;
9168 qpnum_per_tc = used_queues / total_tc;
9169 /* Number of queues per enabled TC */
9170 if (qpnum_per_tc == 0) {
9171 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9172 return I40E_ERR_INVALID_QP_ID;
9174 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9176 bsf = rte_bsf32(qpnum_per_tc);
9179 * Configure TC and queue mapping parameters, for enabled TC,
9180 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9181 * default queue will serve it.
9184 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9185 if (vsi->enabled_tc & (1 << i)) {
9186 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9187 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9188 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9189 qp_idx += qpnum_per_tc;
9191 info->tc_mapping[i] = 0;
9194 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9195 if (vsi->type == I40E_VSI_SRIOV) {
9196 info->mapping_flags |=
9197 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9198 for (i = 0; i < vsi->nb_qps; i++)
9199 info->queue_mapping[i] =
9200 rte_cpu_to_le_16(vsi->base_queue + i);
9202 info->mapping_flags |=
9203 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9204 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9206 info->valid_sections |=
9207 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9209 return I40E_SUCCESS;
9213 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9214 * @veb: VEB to be configured
9215 * @tc_map: enabled TC bitmap
9217 * Returns 0 on success, negative value on failure
9219 static enum i40e_status_code
9220 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9222 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9223 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9224 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9225 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9226 enum i40e_status_code ret = I40E_SUCCESS;
9230 /* Check if enabled_tc is same as existing or new TCs */
9231 if (veb->enabled_tc == tc_map)
9234 /* configure tc bandwidth */
9235 memset(&veb_bw, 0, sizeof(veb_bw));
9236 veb_bw.tc_valid_bits = tc_map;
9237 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9238 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9239 if (tc_map & BIT_ULL(i))
9240 veb_bw.tc_bw_share_credits[i] = 1;
9242 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9245 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9246 " per TC failed = %d",
9247 hw->aq.asq_last_status);
9251 memset(&ets_query, 0, sizeof(ets_query));
9252 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9254 if (ret != I40E_SUCCESS) {
9255 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9256 " configuration %u", hw->aq.asq_last_status);
9259 memset(&bw_query, 0, sizeof(bw_query));
9260 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9262 if (ret != I40E_SUCCESS) {
9263 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9264 " configuration %u", hw->aq.asq_last_status);
9268 /* store and print out BW info */
9269 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9270 veb->bw_info.bw_max = ets_query.tc_bw_max;
9271 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9272 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9273 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9274 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9276 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9277 veb->bw_info.bw_ets_share_credits[i] =
9278 bw_query.tc_bw_share_credits[i];
9279 veb->bw_info.bw_ets_credits[i] =
9280 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9281 /* 4 bits per TC, 4th bit is reserved */
9282 veb->bw_info.bw_ets_max[i] =
9283 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9284 RTE_LEN2MASK(3, uint8_t));
9285 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9286 veb->bw_info.bw_ets_share_credits[i]);
9287 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9288 veb->bw_info.bw_ets_credits[i]);
9289 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9290 veb->bw_info.bw_ets_max[i]);
9293 veb->enabled_tc = tc_map;
9300 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9301 * @vsi: VSI to be configured
9302 * @tc_map: enabled TC bitmap
9304 * Returns 0 on success, negative value on failure
9306 static enum i40e_status_code
9307 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9309 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9310 struct i40e_vsi_context ctxt;
9311 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9312 enum i40e_status_code ret = I40E_SUCCESS;
9315 /* Check if enabled_tc is same as existing or new TCs */
9316 if (vsi->enabled_tc == tc_map)
9319 /* configure tc bandwidth */
9320 memset(&bw_data, 0, sizeof(bw_data));
9321 bw_data.tc_valid_bits = tc_map;
9322 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9323 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9324 if (tc_map & BIT_ULL(i))
9325 bw_data.tc_bw_credits[i] = 1;
9327 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9329 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9330 " per TC failed = %d",
9331 hw->aq.asq_last_status);
9334 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9335 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9337 /* Update Queue Pairs Mapping for currently enabled UPs */
9338 ctxt.seid = vsi->seid;
9339 ctxt.pf_num = hw->pf_id;
9341 ctxt.uplink_seid = vsi->uplink_seid;
9342 ctxt.info = vsi->info;
9344 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9348 /* Update the VSI after updating the VSI queue-mapping information */
9349 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9351 PMD_INIT_LOG(ERR, "Failed to configure "
9352 "TC queue mapping = %d",
9353 hw->aq.asq_last_status);
9356 /* update the local VSI info with updated queue map */
9357 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9358 sizeof(vsi->info.tc_mapping));
9359 (void)rte_memcpy(&vsi->info.queue_mapping,
9360 &ctxt.info.queue_mapping,
9361 sizeof(vsi->info.queue_mapping));
9362 vsi->info.mapping_flags = ctxt.info.mapping_flags;
9363 vsi->info.valid_sections = 0;
9365 /* query and update current VSI BW information */
9366 ret = i40e_vsi_get_bw_config(vsi);
9369 "Failed updating vsi bw info, err %s aq_err %s",
9370 i40e_stat_str(hw, ret),
9371 i40e_aq_str(hw, hw->aq.asq_last_status));
9375 vsi->enabled_tc = tc_map;
9382 * i40e_dcb_hw_configure - program the dcb setting to hw
9383 * @pf: pf the configuration is taken on
9384 * @new_cfg: new configuration
9385 * @tc_map: enabled TC bitmap
9387 * Returns 0 on success, negative value on failure
9389 static enum i40e_status_code
9390 i40e_dcb_hw_configure(struct i40e_pf *pf,
9391 struct i40e_dcbx_config *new_cfg,
9394 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9395 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9396 struct i40e_vsi *main_vsi = pf->main_vsi;
9397 struct i40e_vsi_list *vsi_list;
9398 enum i40e_status_code ret;
9402 /* Use the FW API if FW > v4.4*/
9403 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9404 (hw->aq.fw_maj_ver >= 5))) {
9405 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9406 " to configure DCB");
9407 return I40E_ERR_FIRMWARE_API_VERSION;
9410 /* Check if need reconfiguration */
9411 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9412 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9413 return I40E_SUCCESS;
9416 /* Copy the new config to the current config */
9417 *old_cfg = *new_cfg;
9418 old_cfg->etsrec = old_cfg->etscfg;
9419 ret = i40e_set_dcb_config(hw);
9422 "Set DCB Config failed, err %s aq_err %s\n",
9423 i40e_stat_str(hw, ret),
9424 i40e_aq_str(hw, hw->aq.asq_last_status));
9427 /* set receive Arbiter to RR mode and ETS scheme by default */
9428 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9429 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9430 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
9431 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9432 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9433 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9434 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9435 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9436 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9437 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9438 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9439 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9440 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9442 /* get local mib to check whether it is configured correctly */
9444 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9445 /* Get Local DCB Config */
9446 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9447 &hw->local_dcbx_config);
9449 /* if Veb is created, need to update TC of it at first */
9450 if (main_vsi->veb) {
9451 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9453 PMD_INIT_LOG(WARNING,
9454 "Failed configuring TC for VEB seid=%d\n",
9455 main_vsi->veb->seid);
9457 /* Update each VSI */
9458 i40e_vsi_config_tc(main_vsi, tc_map);
9459 if (main_vsi->veb) {
9460 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9461 /* Beside main VSI and VMDQ VSIs, only enable default
9464 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9465 ret = i40e_vsi_config_tc(vsi_list->vsi,
9468 ret = i40e_vsi_config_tc(vsi_list->vsi,
9469 I40E_DEFAULT_TCMAP);
9471 PMD_INIT_LOG(WARNING,
9472 "Failed configuring TC for VSI seid=%d\n",
9473 vsi_list->vsi->seid);
9477 return I40E_SUCCESS;
9481 * i40e_dcb_init_configure - initial dcb config
9482 * @dev: device being configured
9483 * @sw_dcb: indicate whether dcb is sw configured or hw offload
9485 * Returns 0 on success, negative value on failure
9488 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9490 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9491 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9494 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9495 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9499 /* DCB initialization:
9500 * Update DCB configuration from the Firmware and configure
9501 * LLDP MIB change event.
9503 if (sw_dcb == TRUE) {
9504 ret = i40e_init_dcb(hw);
9505 /* If lldp agent is stopped, the return value from
9506 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9507 * adminq status. Otherwise, it should return success.
9509 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9510 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9511 memset(&hw->local_dcbx_config, 0,
9512 sizeof(struct i40e_dcbx_config));
9513 /* set dcb default configuration */
9514 hw->local_dcbx_config.etscfg.willing = 0;
9515 hw->local_dcbx_config.etscfg.maxtcs = 0;
9516 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9517 hw->local_dcbx_config.etscfg.tsatable[0] =
9519 hw->local_dcbx_config.etsrec =
9520 hw->local_dcbx_config.etscfg;
9521 hw->local_dcbx_config.pfc.willing = 0;
9522 hw->local_dcbx_config.pfc.pfccap =
9523 I40E_MAX_TRAFFIC_CLASS;
9524 /* FW needs one App to configure HW */
9525 hw->local_dcbx_config.numapps = 1;
9526 hw->local_dcbx_config.app[0].selector =
9527 I40E_APP_SEL_ETHTYPE;
9528 hw->local_dcbx_config.app[0].priority = 3;
9529 hw->local_dcbx_config.app[0].protocolid =
9530 I40E_APP_PROTOID_FCOE;
9531 ret = i40e_set_dcb_config(hw);
9533 PMD_INIT_LOG(ERR, "default dcb config fails."
9534 " err = %d, aq_err = %d.", ret,
9535 hw->aq.asq_last_status);
9539 PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9540 " err = %d, aq_err = %d.", ret,
9541 hw->aq.asq_last_status);
9545 ret = i40e_aq_start_lldp(hw, NULL);
9546 if (ret != I40E_SUCCESS)
9547 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9549 ret = i40e_init_dcb(hw);
9551 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9552 PMD_INIT_LOG(ERR, "HW doesn't support"
9557 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9558 " aq_err = %d.", ret,
9559 hw->aq.asq_last_status);
9567 * i40e_dcb_setup - setup dcb related config
9568 * @dev: device being configured
9570 * Returns 0 on success, negative value on failure
9573 i40e_dcb_setup(struct rte_eth_dev *dev)
9575 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9576 struct i40e_dcbx_config dcb_cfg;
9580 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9581 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9585 if (pf->vf_num != 0)
9586 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9588 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9590 PMD_INIT_LOG(ERR, "invalid dcb config");
9593 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9595 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9603 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9604 struct rte_eth_dcb_info *dcb_info)
9606 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9607 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9608 struct i40e_vsi *vsi = pf->main_vsi;
9609 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9610 uint16_t bsf, tc_mapping;
9613 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9614 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9616 dcb_info->nb_tcs = 1;
9617 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9618 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9619 for (i = 0; i < dcb_info->nb_tcs; i++)
9620 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9622 /* get queue mapping if vmdq is disabled */
9623 if (!pf->nb_cfg_vmdq_vsi) {
9624 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9625 if (!(vsi->enabled_tc & (1 << i)))
9627 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9628 dcb_info->tc_queue.tc_rxq[j][i].base =
9629 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9630 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9631 dcb_info->tc_queue.tc_txq[j][i].base =
9632 dcb_info->tc_queue.tc_rxq[j][i].base;
9633 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9634 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9635 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9636 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9637 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9642 /* get queue mapping if vmdq is enabled */
9644 vsi = pf->vmdq[j].vsi;
9645 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9646 if (!(vsi->enabled_tc & (1 << i)))
9648 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9649 dcb_info->tc_queue.tc_rxq[j][i].base =
9650 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9651 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9652 dcb_info->tc_queue.tc_txq[j][i].base =
9653 dcb_info->tc_queue.tc_rxq[j][i].base;
9654 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9655 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9656 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9657 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9658 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9661 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9666 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9668 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9669 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9671 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9674 msix_intr = intr_handle->intr_vec[queue_id];
9675 if (msix_intr == I40E_MISC_VEC_ID)
9676 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9677 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9678 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9679 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9681 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9684 I40E_PFINT_DYN_CTLN(msix_intr -
9686 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9687 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9688 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9690 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9692 I40E_WRITE_FLUSH(hw);
9693 rte_intr_enable(&dev->pci_dev->intr_handle);
9699 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9701 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9702 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9705 msix_intr = intr_handle->intr_vec[queue_id];
9706 if (msix_intr == I40E_MISC_VEC_ID)
9707 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9710 I40E_PFINT_DYN_CTLN(msix_intr -
9713 I40E_WRITE_FLUSH(hw);
9718 static int i40e_get_regs(struct rte_eth_dev *dev,
9719 struct rte_dev_reg_info *regs)
9721 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9722 uint32_t *ptr_data = regs->data;
9723 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9724 const struct i40e_reg_info *reg_info;
9726 if (ptr_data == NULL) {
9727 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9728 regs->width = sizeof(uint32_t);
9732 /* The first few registers have to be read using AQ operations */
9734 while (i40e_regs_adminq[reg_idx].name) {
9735 reg_info = &i40e_regs_adminq[reg_idx++];
9736 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9738 arr_idx2 <= reg_info->count2;
9740 reg_offset = arr_idx * reg_info->stride1 +
9741 arr_idx2 * reg_info->stride2;
9742 reg_offset += reg_info->base_addr;
9743 ptr_data[reg_offset >> 2] =
9744 i40e_read_rx_ctl(hw, reg_offset);
9748 /* The remaining registers can be read using primitives */
9750 while (i40e_regs_others[reg_idx].name) {
9751 reg_info = &i40e_regs_others[reg_idx++];
9752 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9754 arr_idx2 <= reg_info->count2;
9756 reg_offset = arr_idx * reg_info->stride1 +
9757 arr_idx2 * reg_info->stride2;
9758 reg_offset += reg_info->base_addr;
9759 ptr_data[reg_offset >> 2] =
9760 I40E_READ_REG(hw, reg_offset);
9767 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9769 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9771 /* Convert word count to byte count */
9772 return hw->nvm.sr_size << 1;
9775 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9776 struct rte_dev_eeprom_info *eeprom)
9778 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9779 uint16_t *data = eeprom->data;
9780 uint16_t offset, length, cnt_words;
9783 offset = eeprom->offset >> 1;
9784 length = eeprom->length >> 1;
9787 if (offset > hw->nvm.sr_size ||
9788 offset + length > hw->nvm.sr_size) {
9789 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9793 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9795 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9796 if (ret_code != I40E_SUCCESS || cnt_words != length) {
9797 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9804 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9805 struct ether_addr *mac_addr)
9807 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9809 if (!is_valid_assigned_ether_addr(mac_addr)) {
9810 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9814 /* Flags: 0x3 updates port address */
9815 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9819 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9821 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9822 struct rte_eth_dev_data *dev_data = pf->dev_data;
9823 uint32_t frame_size = mtu + ETHER_HDR_LEN
9824 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9827 /* check if mtu is within the allowed range */
9828 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9831 /* mtu setting is forbidden if port is start */
9832 if (dev_data->dev_started) {
9834 "port %d must be stopped before configuration\n",
9839 if (frame_size > ETHER_MAX_LEN)
9840 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9842 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9844 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;