drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_eth_ctrl.h>
  28 #include <rte_tailq.h>
  29 #include <rte_hash_crc.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  48
  49 #define I40E_CLEAR_PXE_WAIT_MS     200
  50
  51 /* Maximun number of capability elements */
  52 #define I40E_MAX_CAP_ELE_NUM       128
  53
  54 /* Wait count and interval */
  55 #define I40E_CHK_Q_ENA_COUNT       1000
  56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  57
  58 /* Maximun number of VSI */
  59 #define I40E_MAX_NUM_VSIS          (384UL)
  60
  61 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  62
  63 /* Flow control default timer */
  64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  65
  66 /* Flow control enable fwd bit */
  67 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  68
  69 /* Receive Packet Buffer size */
  70 #define I40E_RXPBSIZE (968 * 1024)
  71
  72 /* Kilobytes shift */
  73 #define I40E_KILOSHIFT 10
  74
  75 /* Flow control default high water */
  76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Flow control default low water */
  79 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  80
  81 /* Receive Average Packet Size in Byte*/
  82 #define I40E_PACKET_AVERAGE_SIZE 128
  83
  84 /* Mask of PF interrupt causes */
  85 #define I40E_PFINT_ICR0_ENA_MASK ( \
  86                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  87                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  90                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 /* Additional timesync values. */
 110 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 111 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 112 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 113 #define I40E_PRTTSYN_TSYNENA     0x80000000
 114 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 115 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 116
 117 /**
 118  * Below are values for writing un-exposed registers suggested
 119  * by silicon experts
 120  */
 121 /* Destination MAC address */
 122 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 123 /* Source MAC address */
 124 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 126 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 128 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 129 /* Single VLAN tag in the inner L2 header */
 130 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 131 /* Source IPv4 address */
 132 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 133 /* Destination IPv4 address */
 134 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 135 /* Source IPv4 address for X722 */
 136 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 137 /* Destination IPv4 address for X722 */
 138 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 139 /* IPv4 Protocol for X722 */
 140 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 141 /* IPv4 Time to Live for X722 */
 142 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 143 /* IPv4 Type of Service (TOS) */
 144 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 145 /* IPv4 Protocol */
 146 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 147 /* IPv4 Time to Live */
 148 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 149 /* Source IPv6 address */
 150 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 151 /* Destination IPv6 address */
 152 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 153 /* IPv6 Traffic Class (TC) */
 154 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 155 /* IPv6 Next Header */
 156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 157 /* IPv6 Hop Limit */
 158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 159 /* Source L4 port */
 160 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 161 /* Destination L4 port */
 162 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 163 /* SCTP verification tag */
 164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 167 /* Source port of tunneling UDP */
 168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 169 /* Destination port of tunneling UDP */
 170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 171 /* UDP Tunneling ID, NVGRE/GRE key */
 172 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 173 /* Last ether type */
 174 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 175 /* Tunneling outer destination IPv4 address */
 176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 177 /* Tunneling outer destination IPv6 address */
 178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 179 /* 1st word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 181 /* 2nd word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 183 /* 3rd word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 185 /* 4th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 187 /* 5th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 189 /* 6th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 191 /* 7th word of flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 193 /* 8th word of flex payload */
 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 195 /* all 8 words flex payload */
 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 197 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 198
 199 #define I40E_TRANSLATE_INSET 0
 200 #define I40E_TRANSLATE_REG   1
 201
 202 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 203 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 204 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 205 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 207 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 208
 209 /* PCI offset for querying capability */
 210 #define PCI_DEV_CAP_REG            0xA4
 211 /* PCI offset for enabling/disabling Extended Tag */
 212 #define PCI_DEV_CTRL_REG           0xA8
 213 /* Bit mask of Extended Tag capability */
 214 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 215 /* Bit shift of Extended Tag enable/disable */
 216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 217 /* Bit mask of Extended Tag enable/disable */
 218 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 219
 220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 222 static int i40e_dev_configure(struct rte_eth_dev *dev);
 223 static int i40e_dev_start(struct rte_eth_dev *dev);
 224 static void i40e_dev_stop(struct rte_eth_dev *dev);
 225 static void i40e_dev_close(struct rte_eth_dev *dev);
 226 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 227 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 228 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 229 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 230 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 234                                struct rte_eth_stats *stats);
 235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 236                                struct rte_eth_xstat *xstats, unsigned n);
 237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 238                                      struct rte_eth_xstat_name *xstats_names,
 239                                      unsigned limit);
 240 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 241 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 242                                             uint16_t queue_id,
 243                                             uint8_t stat_idx,
 244                                             uint8_t is_rx);
 245 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 246                                 char *fw_version, size_t fw_size);
 247 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 248                               struct rte_eth_dev_info *dev_info);
 249 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 250                                 uint16_t vlan_id,
 251                                 int on);
 252 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 253                               enum rte_vlan_type vlan_type,
 254                               uint16_t tpid);
 255 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 256 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 257                                       uint16_t queue,
 258                                       int on);
 259 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 260 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 261 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 262 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 263                               struct rte_eth_fc_conf *fc_conf);
 264 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 265                               struct rte_eth_fc_conf *fc_conf);
 266 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 267                                        struct rte_eth_pfc_conf *pfc_conf);
 268 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 269                             struct ether_addr *mac_addr,
 270                             uint32_t index,
 271                             uint32_t pool);
 272 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 273 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 274                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 275                                     uint16_t reta_size);
 276 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 277                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 278                                    uint16_t reta_size);
 279
 280 static int i40e_get_cap(struct i40e_hw *hw);
 281 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 282 static int i40e_pf_setup(struct i40e_pf *pf);
 283 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 284 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 285 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 286 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 287                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 288 static void i40e_stat_update_48(struct i40e_hw *hw,
 289                                uint32_t hireg,
 290                                uint32_t loreg,
 291                                bool offset_loaded,
 292                                uint64_t *offset,
 293                                uint64_t *stat);
 294 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 295 static void i40e_dev_interrupt_handler(void *param);
 296 static void i40e_dev_alarm_handler(void *param);
 297 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 298                                 uint32_t base, uint32_t num);
 299 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 300 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 301                         uint32_t base);
 302 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 303                         uint16_t num);
 304 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 305 static int i40e_veb_release(struct i40e_veb *veb);
 306 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 307                                                 struct i40e_vsi *vsi);
 308 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 309 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 310 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 311                                              struct i40e_macvlan_filter *mv_f,
 312                                              int num,
 313                                              uint16_t vlan);
 314 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 315 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 316                                     struct rte_eth_rss_conf *rss_conf);
 317 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 318                                       struct rte_eth_rss_conf *rss_conf);
 319 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 320                                         struct rte_eth_udp_tunnel *udp_tunnel);
 321 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 322                                         struct rte_eth_udp_tunnel *udp_tunnel);
 323 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 324 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 328                                 enum rte_filter_type filter_type,
 329                                 enum rte_filter_op filter_op,
 330                                 void *arg);
 331 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 332                                   struct rte_eth_dcb_info *dcb_info);
 333 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 334 static void i40e_configure_registers(struct i40e_hw *hw);
 335 static void i40e_hw_init(struct rte_eth_dev *dev);
 336 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 337 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 338                                                      uint16_t seid,
 339                                                      uint16_t rule_type,
 340                                                      uint16_t *entries,
 341                                                      uint16_t count,
 342                                                      uint16_t rule_id);
 343 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 344                         struct rte_eth_mirror_conf *mirror_conf,
 345                         uint8_t sw_id, uint8_t on);
 346 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 347
 348 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 349 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 350 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 351                                            struct timespec *timestamp,
 352                                            uint32_t flags);
 353 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 354                                            struct timespec *timestamp);
 355 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 356
 357 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 358
 359 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 360                                    struct timespec *timestamp);
 361 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 362                                     const struct timespec *timestamp);
 363
 364 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 365                                          uint16_t queue_id);
 366 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 367                                           uint16_t queue_id);
 368
 369 static int i40e_get_regs(struct rte_eth_dev *dev,
 370                          struct rte_dev_reg_info *regs);
 371
 372 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 373
 374 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 375                            struct rte_dev_eeprom_info *eeprom);
 376
 377 static int i40e_get_module_info(struct rte_eth_dev *dev,
 378                                 struct rte_eth_dev_module_info *modinfo);
 379 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 380                                   struct rte_dev_eeprom_info *info);
 381
 382 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 383                                       struct ether_addr *mac_addr);
 384
 385 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 386
 387 static int i40e_ethertype_filter_convert(
 388         const struct rte_eth_ethertype_filter *input,
 389         struct i40e_ethertype_filter *filter);
 390 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 391                                    struct i40e_ethertype_filter *filter);
 392
 393 static int i40e_tunnel_filter_convert(
 394         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 395         struct i40e_tunnel_filter *tunnel_filter);
 396 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 397                                 struct i40e_tunnel_filter *tunnel_filter);
 398 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 399
 400 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 401 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 402 static void i40e_filter_restore(struct i40e_pf *pf);
 403 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 404
 405 int i40e_logtype_init;
 406 int i40e_logtype_driver;
 407
 408 static const char *const valid_keys[] = {
 409         ETH_I40E_FLOATING_VEB_ARG,
 410         ETH_I40E_FLOATING_VEB_LIST_ARG,
 411         ETH_I40E_SUPPORT_MULTI_DRIVER,
 412         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 413         ETH_I40E_USE_LATEST_VEC,
 414         NULL};
 415
 416 static const struct rte_pci_id pci_id_i40e_map[] = {
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 437         { .vendor_id = 0, /* sentinel */ },
 438 };
 439
 440 static const struct eth_dev_ops i40e_eth_dev_ops = {
 441         .dev_configure                = i40e_dev_configure,
 442         .dev_start                    = i40e_dev_start,
 443         .dev_stop                     = i40e_dev_stop,
 444         .dev_close                    = i40e_dev_close,
 445         .dev_reset                    = i40e_dev_reset,
 446         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 447         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 448         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 449         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 450         .dev_set_link_up              = i40e_dev_set_link_up,
 451         .dev_set_link_down            = i40e_dev_set_link_down,
 452         .link_update                  = i40e_dev_link_update,
 453         .stats_get                    = i40e_dev_stats_get,
 454         .xstats_get                   = i40e_dev_xstats_get,
 455         .xstats_get_names             = i40e_dev_xstats_get_names,
 456         .stats_reset                  = i40e_dev_stats_reset,
 457         .xstats_reset                 = i40e_dev_stats_reset,
 458         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 459         .fw_version_get               = i40e_fw_version_get,
 460         .dev_infos_get                = i40e_dev_info_get,
 461         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 462         .vlan_filter_set              = i40e_vlan_filter_set,
 463         .vlan_tpid_set                = i40e_vlan_tpid_set,
 464         .vlan_offload_set             = i40e_vlan_offload_set,
 465         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 466         .vlan_pvid_set                = i40e_vlan_pvid_set,
 467         .rx_queue_start               = i40e_dev_rx_queue_start,
 468         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 469         .tx_queue_start               = i40e_dev_tx_queue_start,
 470         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 471         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 472         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 473         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 474         .rx_queue_release             = i40e_dev_rx_queue_release,
 475         .rx_queue_count               = i40e_dev_rx_queue_count,
 476         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 477         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 478         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 479         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 480         .tx_queue_release             = i40e_dev_tx_queue_release,
 481         .dev_led_on                   = i40e_dev_led_on,
 482         .dev_led_off                  = i40e_dev_led_off,
 483         .flow_ctrl_get                = i40e_flow_ctrl_get,
 484         .flow_ctrl_set                = i40e_flow_ctrl_set,
 485         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 486         .mac_addr_add                 = i40e_macaddr_add,
 487         .mac_addr_remove              = i40e_macaddr_remove,
 488         .reta_update                  = i40e_dev_rss_reta_update,
 489         .reta_query                   = i40e_dev_rss_reta_query,
 490         .rss_hash_update              = i40e_dev_rss_hash_update,
 491         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 492         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 493         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 494         .filter_ctrl                  = i40e_dev_filter_ctrl,
 495         .rxq_info_get                 = i40e_rxq_info_get,
 496         .txq_info_get                 = i40e_txq_info_get,
 497         .mirror_rule_set              = i40e_mirror_rule_set,
 498         .mirror_rule_reset            = i40e_mirror_rule_reset,
 499         .timesync_enable              = i40e_timesync_enable,
 500         .timesync_disable             = i40e_timesync_disable,
 501         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 502         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 503         .get_dcb_info                 = i40e_dev_get_dcb_info,
 504         .timesync_adjust_time         = i40e_timesync_adjust_time,
 505         .timesync_read_time           = i40e_timesync_read_time,
 506         .timesync_write_time          = i40e_timesync_write_time,
 507         .get_reg                      = i40e_get_regs,
 508         .get_eeprom_length            = i40e_get_eeprom_length,
 509         .get_eeprom                   = i40e_get_eeprom,
 510         .get_module_info              = i40e_get_module_info,
 511         .get_module_eeprom            = i40e_get_module_eeprom,
 512         .mac_addr_set                 = i40e_set_default_mac_addr,
 513         .mtu_set                      = i40e_dev_mtu_set,
 514         .tm_ops_get                   = i40e_tm_ops_get,
 515 };
 516
 517 /* store statistics names and its offset in stats structure */
 518 struct rte_i40e_xstats_name_off {
 519         char name[RTE_ETH_XSTATS_NAME_SIZE];
 520         unsigned offset;
 521 };
 522
 523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 524         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 525         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 526         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 527         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 528         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 529                 rx_unknown_protocol)},
 530         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 531         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 532         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 533         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 534 };
 535
 536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 537                 sizeof(rte_i40e_stats_strings[0]))
 538
 539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 540         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 541                 tx_dropped_link_down)},
 542         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 543         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 544                 illegal_bytes)},
 545         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 546         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 547                 mac_local_faults)},
 548         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_remote_faults)},
 550         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 551                 rx_length_errors)},
 552         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 553         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 554         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 555         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 556         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 557         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 558                 rx_size_127)},
 559         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_255)},
 561         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_511)},
 563         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_1023)},
 565         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1522)},
 567         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_big)},
 569         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 570                 rx_undersize)},
 571         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_oversize)},
 573         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 574                 mac_short_packet_dropped)},
 575         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_fragments)},
 577         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 578         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 579         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 580                 tx_size_127)},
 581         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_255)},
 583         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_511)},
 585         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_1023)},
 587         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1522)},
 589         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_big)},
 591         {"rx_flow_director_atr_match_packets",
 592                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 593         {"rx_flow_director_sb_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 595         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 596                 tx_lpi_status)},
 597         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 rx_lpi_status)},
 599         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 600                 tx_lpi_count)},
 601         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 rx_lpi_count)},
 603 };
 604
 605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 606                 sizeof(rte_i40e_hw_port_strings[0]))
 607
 608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 609         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xon_rx)},
 611         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xoff_rx)},
 613 };
 614
 615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 616                 sizeof(rte_i40e_rxq_prio_strings[0]))
 617
 618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 619         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xon_tx)},
 621         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xoff_tx)},
 623         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xon_2_xoff)},
 625 };
 626
 627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 628                 sizeof(rte_i40e_txq_prio_strings[0]))
 629
 630 static int
 631 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 632         struct rte_pci_device *pci_dev)
 633 {
 634         char name[RTE_ETH_NAME_MAX_LEN];
 635         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 636         int i, retval;
 637
 638         if (pci_dev->device.devargs) {
 639                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 640                                 &eth_da);
 641                 if (retval)
 642                         return retval;
 643         }
 644
 645         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 646                 sizeof(struct i40e_adapter),
 647                 eth_dev_pci_specific_init, pci_dev,
 648                 eth_i40e_dev_init, NULL);
 649
 650         if (retval || eth_da.nb_representor_ports < 1)
 651                 return retval;
 652
 653         /* probe VF representor ports */
 654         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 655                 pci_dev->device.name);
 656
 657         if (pf_ethdev == NULL)
 658                 return -ENODEV;
 659
 660         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 661                 struct i40e_vf_representor representor = {
 662                         .vf_id = eth_da.representor_ports[i],
 663                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 664                                 pf_ethdev->data->dev_private)->switch_domain_id,
 665                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 666                                 pf_ethdev->data->dev_private)
 667                 };
 668
 669                 /* representor port net_bdf_port */
 670                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 671                         pci_dev->device.name, eth_da.representor_ports[i]);
 672
 673                 retval = rte_eth_dev_create(&pci_dev->device, name,
 674                         sizeof(struct i40e_vf_representor), NULL, NULL,
 675                         i40e_vf_representor_init, &representor);
 676
 677                 if (retval)
 678                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 679                                 "representor %s.", name);
 680         }
 681
 682         return 0;
 683 }
 684
 685 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 686 {
 687         struct rte_eth_dev *ethdev;
 688
 689         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 690         if (!ethdev)
 691                 return -ENODEV;
 692
 693
 694         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 695                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 696         else
 697                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 698 }
 699
 700 static struct rte_pci_driver rte_i40e_pmd = {
 701         .id_table = pci_id_i40e_map,
 702         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 703                      RTE_PCI_DRV_IOVA_AS_VA,
 704         .probe = eth_i40e_pci_probe,
 705         .remove = eth_i40e_pci_remove,
 706 };
 707
 708 static inline void
 709 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 710                          uint32_t reg_val)
 711 {
 712         uint32_t ori_reg_val;
 713         struct rte_eth_dev *dev;
 714
 715         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 716         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 717         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 718         if (ori_reg_val != reg_val)
 719                 PMD_DRV_LOG(WARNING,
 720                             "i40e device %s changed global register [0x%08x]."
 721                             " original: 0x%08x, new: 0x%08x",
 722                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 723 }
 724
 725 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 726 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 727 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 728
 729 #ifndef I40E_GLQF_ORT
 730 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 731 #endif
 732 #ifndef I40E_GLQF_PIT
 733 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 734 #endif
 735 #ifndef I40E_GLQF_L3_MAP
 736 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 737 #endif
 738
 739 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 740 {
 741         /*
 742          * Initialize registers for parsing packet type of QinQ
 743          * This should be removed from code once proper
 744          * configuration API is added to avoid configuration conflicts
 745          * between ports of the same device.
 746          */
 747         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 748         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 749 }
 750
 751 static inline void i40e_config_automask(struct i40e_pf *pf)
 752 {
 753         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 754         uint32_t val;
 755
 756         /* INTENA flag is not auto-cleared for interrupt */
 757         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 758         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 759                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 760
 761         /* If support multi-driver, PF will use INT0. */
 762         if (!pf->support_multi_driver)
 763                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 764
 765         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 766 }
 767
 768 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 769
 770 /*
 771  * Add a ethertype filter to drop all flow control frames transmitted
 772  * from VSIs.
 773 */
 774 static void
 775 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 776 {
 777         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 778         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 779                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 780                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 781         int ret;
 782
 783         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 784                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 785                                 pf->main_vsi_seid, 0,
 786                                 TRUE, NULL, NULL);
 787         if (ret)
 788                 PMD_INIT_LOG(ERR,
 789                         "Failed to add filter to drop flow control frames from VSIs.");
 790 }
 791
 792 static int
 793 floating_veb_list_handler(__rte_unused const char *key,
 794                           const char *floating_veb_value,
 795                           void *opaque)
 796 {
 797         int idx = 0;
 798         unsigned int count = 0;
 799         char *end = NULL;
 800         int min, max;
 801         bool *vf_floating_veb = opaque;
 802
 803         while (isblank(*floating_veb_value))
 804                 floating_veb_value++;
 805
 806         /* Reset floating VEB configuration for VFs */
 807         for (idx = 0; idx < I40E_MAX_VF; idx++)
 808                 vf_floating_veb[idx] = false;
 809
 810         min = I40E_MAX_VF;
 811         do {
 812                 while (isblank(*floating_veb_value))
 813                         floating_veb_value++;
 814                 if (*floating_veb_value == '\0')
 815                         return -1;
 816                 errno = 0;
 817                 idx = strtoul(floating_veb_value, &end, 10);
 818                 if (errno || end == NULL)
 819                         return -1;
 820                 while (isblank(*end))
 821                         end++;
 822                 if (*end == '-') {
 823                         min = idx;
 824                 } else if ((*end == ';') || (*end == '\0')) {
 825                         max = idx;
 826                         if (min == I40E_MAX_VF)
 827                                 min = idx;
 828                         if (max >= I40E_MAX_VF)
 829                                 max = I40E_MAX_VF - 1;
 830                         for (idx = min; idx <= max; idx++) {
 831                                 vf_floating_veb[idx] = true;
 832                                 count++;
 833                         }
 834                         min = I40E_MAX_VF;
 835                 } else {
 836                         return -1;
 837                 }
 838                 floating_veb_value = end + 1;
 839         } while (*end != '\0');
 840
 841         if (count == 0)
 842                 return -1;
 843
 844         return 0;
 845 }
 846
 847 static void
 848 config_vf_floating_veb(struct rte_devargs *devargs,
 849                        uint16_t floating_veb,
 850                        bool *vf_floating_veb)
 851 {
 852         struct rte_kvargs *kvlist;
 853         int i;
 854         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 855
 856         if (!floating_veb)
 857                 return;
 858         /* All the VFs attach to the floating VEB by default
 859          * when the floating VEB is enabled.
 860          */
 861         for (i = 0; i < I40E_MAX_VF; i++)
 862                 vf_floating_veb[i] = true;
 863
 864         if (devargs == NULL)
 865                 return;
 866
 867         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 868         if (kvlist == NULL)
 869                 return;
 870
 871         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 872                 rte_kvargs_free(kvlist);
 873                 return;
 874         }
 875         /* When the floating_veb_list parameter exists, all the VFs
 876          * will attach to the legacy VEB firstly, then configure VFs
 877          * to the floating VEB according to the floating_veb_list.
 878          */
 879         if (rte_kvargs_process(kvlist, floating_veb_list,
 880                                floating_veb_list_handler,
 881                                vf_floating_veb) < 0) {
 882                 rte_kvargs_free(kvlist);
 883                 return;
 884         }
 885         rte_kvargs_free(kvlist);
 886 }
 887
 888 static int
 889 i40e_check_floating_handler(__rte_unused const char *key,
 890                             const char *value,
 891                             __rte_unused void *opaque)
 892 {
 893         if (strcmp(value, "1"))
 894                 return -1;
 895
 896         return 0;
 897 }
 898
 899 static int
 900 is_floating_veb_supported(struct rte_devargs *devargs)
 901 {
 902         struct rte_kvargs *kvlist;
 903         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 904
 905         if (devargs == NULL)
 906                 return 0;
 907
 908         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 909         if (kvlist == NULL)
 910                 return 0;
 911
 912         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 913                 rte_kvargs_free(kvlist);
 914                 return 0;
 915         }
 916         /* Floating VEB is enabled when there's key-value:
 917          * enable_floating_veb=1
 918          */
 919         if (rte_kvargs_process(kvlist, floating_veb_key,
 920                                i40e_check_floating_handler, NULL) < 0) {
 921                 rte_kvargs_free(kvlist);
 922                 return 0;
 923         }
 924         rte_kvargs_free(kvlist);
 925
 926         return 1;
 927 }
 928
 929 static void
 930 config_floating_veb(struct rte_eth_dev *dev)
 931 {
 932         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 933         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 934         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 935
 936         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 937
 938         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 939                 pf->floating_veb =
 940                         is_floating_veb_supported(pci_dev->device.devargs);
 941                 config_vf_floating_veb(pci_dev->device.devargs,
 942                                        pf->floating_veb,
 943                                        pf->floating_veb_list);
 944         } else {
 945                 pf->floating_veb = false;
 946         }
 947 }
 948
 949 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 950 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 951
 952 static int
 953 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 954 {
 955         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 956         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 957         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 958         int ret;
 959
 960         struct rte_hash_parameters ethertype_hash_params = {
 961                 .name = ethertype_hash_name,
 962                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 963                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 964                 .hash_func = rte_hash_crc,
 965                 .hash_func_init_val = 0,
 966                 .socket_id = rte_socket_id(),
 967         };
 968
 969         /* Initialize ethertype filter rule list and hash */
 970         TAILQ_INIT(&ethertype_rule->ethertype_list);
 971         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 972                  "ethertype_%s", dev->device->name);
 973         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 974         if (!ethertype_rule->hash_table) {
 975                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 976                 return -EINVAL;
 977         }
 978         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 979                                        sizeof(struct i40e_ethertype_filter *) *
 980                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 981                                        0);
 982         if (!ethertype_rule->hash_map) {
 983                 PMD_INIT_LOG(ERR,
 984                              "Failed to allocate memory for ethertype hash map!");
 985                 ret = -ENOMEM;
 986                 goto err_ethertype_hash_map_alloc;
 987         }
 988
 989         return 0;
 990
 991 err_ethertype_hash_map_alloc:
 992         rte_hash_free(ethertype_rule->hash_table);
 993
 994         return ret;
 995 }
 996
 997 static int
 998 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 999 {
1000         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1001         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1002         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1003         int ret;
1004
1005         struct rte_hash_parameters tunnel_hash_params = {
1006                 .name = tunnel_hash_name,
1007                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1008                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1009                 .hash_func = rte_hash_crc,
1010                 .hash_func_init_val = 0,
1011                 .socket_id = rte_socket_id(),
1012         };
1013
1014         /* Initialize tunnel filter rule list and hash */
1015         TAILQ_INIT(&tunnel_rule->tunnel_list);
1016         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1017                  "tunnel_%s", dev->device->name);
1018         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1019         if (!tunnel_rule->hash_table) {
1020                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1021                 return -EINVAL;
1022         }
1023         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1024                                     sizeof(struct i40e_tunnel_filter *) *
1025                                     I40E_MAX_TUNNEL_FILTER_NUM,
1026                                     0);
1027         if (!tunnel_rule->hash_map) {
1028                 PMD_INIT_LOG(ERR,
1029                              "Failed to allocate memory for tunnel hash map!");
1030                 ret = -ENOMEM;
1031                 goto err_tunnel_hash_map_alloc;
1032         }
1033
1034         return 0;
1035
1036 err_tunnel_hash_map_alloc:
1037         rte_hash_free(tunnel_rule->hash_table);
1038
1039         return ret;
1040 }
1041
1042 static int
1043 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1044 {
1045         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1046         struct i40e_fdir_info *fdir_info = &pf->fdir;
1047         char fdir_hash_name[RTE_HASH_NAMESIZE];
1048         int ret;
1049
1050         struct rte_hash_parameters fdir_hash_params = {
1051                 .name = fdir_hash_name,
1052                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1053                 .key_len = sizeof(struct i40e_fdir_input),
1054                 .hash_func = rte_hash_crc,
1055                 .hash_func_init_val = 0,
1056                 .socket_id = rte_socket_id(),
1057         };
1058
1059         /* Initialize flow director filter rule list and hash */
1060         TAILQ_INIT(&fdir_info->fdir_list);
1061         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1062                  "fdir_%s", dev->device->name);
1063         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1064         if (!fdir_info->hash_table) {
1065                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1066                 return -EINVAL;
1067         }
1068         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1069                                           sizeof(struct i40e_fdir_filter *) *
1070                                           I40E_MAX_FDIR_FILTER_NUM,
1071                                           0);
1072         if (!fdir_info->hash_map) {
1073                 PMD_INIT_LOG(ERR,
1074                              "Failed to allocate memory for fdir hash map!");
1075                 ret = -ENOMEM;
1076                 goto err_fdir_hash_map_alloc;
1077         }
1078         return 0;
1079
1080 err_fdir_hash_map_alloc:
1081         rte_hash_free(fdir_info->hash_table);
1082
1083         return ret;
1084 }
1085
1086 static void
1087 i40e_init_customized_info(struct i40e_pf *pf)
1088 {
1089         int i;
1090
1091         /* Initialize customized pctype */
1092         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1093                 pf->customized_pctype[i].index = i;
1094                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1095                 pf->customized_pctype[i].valid = false;
1096         }
1097
1098         pf->gtp_support = false;
1099 }
1100
1101 void
1102 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1103 {
1104         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1105         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1106         struct i40e_queue_regions *info = &pf->queue_region;
1107         uint16_t i;
1108
1109         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1110                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1111
1112         memset(info, 0, sizeof(struct i40e_queue_regions));
1113 }
1114
1115 static int
1116 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1117                                const char *value,
1118                                void *opaque)
1119 {
1120         struct i40e_pf *pf;
1121         unsigned long support_multi_driver;
1122         char *end;
1123
1124         pf = (struct i40e_pf *)opaque;
1125
1126         errno = 0;
1127         support_multi_driver = strtoul(value, &end, 10);
1128         if (errno != 0 || end == value || *end != 0) {
1129                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1130                 return -(EINVAL);
1131         }
1132
1133         if (support_multi_driver == 1 || support_multi_driver == 0)
1134                 pf->support_multi_driver = (bool)support_multi_driver;
1135         else
1136                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1137                             "enable global configuration by default."
1138                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1139         return 0;
1140 }
1141
1142 static int
1143 i40e_support_multi_driver(struct rte_eth_dev *dev)
1144 {
1145         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1146         struct rte_kvargs *kvlist;
1147         int kvargs_count;
1148
1149         /* Enable global configuration by default */
1150         pf->support_multi_driver = false;
1151
1152         if (!dev->device->devargs)
1153                 return 0;
1154
1155         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1156         if (!kvlist)
1157                 return -EINVAL;
1158
1159         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1160         if (!kvargs_count) {
1161                 rte_kvargs_free(kvlist);
1162                 return 0;
1163         }
1164
1165         if (kvargs_count > 1)
1166                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1167                             "the first invalid or last valid one is used !",
1168                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1169
1170         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1171                                i40e_parse_multi_drv_handler, pf) < 0) {
1172                 rte_kvargs_free(kvlist);
1173                 return -EINVAL;
1174         }
1175
1176         rte_kvargs_free(kvlist);
1177         return 0;
1178 }
1179
1180 static int
1181 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1182                                     uint32_t reg_addr, uint64_t reg_val,
1183                                     struct i40e_asq_cmd_details *cmd_details)
1184 {
1185         uint64_t ori_reg_val;
1186         struct rte_eth_dev *dev;
1187         int ret;
1188
1189         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1190         if (ret != I40E_SUCCESS) {
1191                 PMD_DRV_LOG(ERR,
1192                             "Fail to debug read from 0x%08x",
1193                             reg_addr);
1194                 return -EIO;
1195         }
1196         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1197
1198         if (ori_reg_val != reg_val)
1199                 PMD_DRV_LOG(WARNING,
1200                             "i40e device %s changed global register [0x%08x]."
1201                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1202                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1203
1204         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1205 }
1206
1207 static int
1208 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1209                                 const char *value,
1210                                 void *opaque)
1211 {
1212         struct i40e_adapter *ad;
1213         int use_latest_vec;
1214
1215         ad = (struct i40e_adapter *)opaque;
1216
1217         use_latest_vec = atoi(value);
1218
1219         if (use_latest_vec != 0 && use_latest_vec != 1)
1220                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1221
1222         ad->use_latest_vec = (uint8_t)use_latest_vec;
1223
1224         return 0;
1225 }
1226
1227 static int
1228 i40e_use_latest_vec(struct rte_eth_dev *dev)
1229 {
1230         struct i40e_adapter *ad =
1231                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1232         struct rte_kvargs *kvlist;
1233         int kvargs_count;
1234
1235         ad->use_latest_vec = false;
1236
1237         if (!dev->device->devargs)
1238                 return 0;
1239
1240         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1241         if (!kvlist)
1242                 return -EINVAL;
1243
1244         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1245         if (!kvargs_count) {
1246                 rte_kvargs_free(kvlist);
1247                 return 0;
1248         }
1249
1250         if (kvargs_count > 1)
1251                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1252                             "the first invalid or last valid one is used !",
1253                             ETH_I40E_USE_LATEST_VEC);
1254
1255         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1256                                 i40e_parse_latest_vec_handler, ad) < 0) {
1257                 rte_kvargs_free(kvlist);
1258                 return -EINVAL;
1259         }
1260
1261         rte_kvargs_free(kvlist);
1262         return 0;
1263 }
1264
1265 #define I40E_ALARM_INTERVAL 50000 /* us */
1266
1267 static int
1268 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1269 {
1270         struct rte_pci_device *pci_dev;
1271         struct rte_intr_handle *intr_handle;
1272         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1273         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274         struct i40e_vsi *vsi;
1275         int ret;
1276         uint32_t len, val;
1277         uint8_t aq_fail = 0;
1278
1279         PMD_INIT_FUNC_TRACE();
1280
1281         dev->dev_ops = &i40e_eth_dev_ops;
1282         dev->rx_pkt_burst = i40e_recv_pkts;
1283         dev->tx_pkt_burst = i40e_xmit_pkts;
1284         dev->tx_pkt_prepare = i40e_prep_pkts;
1285
1286         /* for secondary processes, we don't initialise any further as primary
1287          * has already done this work. Only check we don't need a different
1288          * RX function */
1289         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1290                 i40e_set_rx_function(dev);
1291                 i40e_set_tx_function(dev);
1292                 return 0;
1293         }
1294         i40e_set_default_ptype_table(dev);
1295         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1296         intr_handle = &pci_dev->intr_handle;
1297
1298         rte_eth_copy_pci_info(dev, pci_dev);
1299
1300         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1301         pf->adapter->eth_dev = dev;
1302         pf->dev_data = dev->data;
1303
1304         hw->back = I40E_PF_TO_ADAPTER(pf);
1305         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1306         if (!hw->hw_addr) {
1307                 PMD_INIT_LOG(ERR,
1308                         "Hardware is not available, as address is NULL");
1309                 return -ENODEV;
1310         }
1311
1312         hw->vendor_id = pci_dev->id.vendor_id;
1313         hw->device_id = pci_dev->id.device_id;
1314         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1315         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1316         hw->bus.device = pci_dev->addr.devid;
1317         hw->bus.func = pci_dev->addr.function;
1318         hw->adapter_stopped = 0;
1319         hw->adapter_closed = 0;
1320
1321         /*
1322          * Switch Tag value should not be identical to either the First Tag
1323          * or Second Tag values. So set something other than common Ethertype
1324          * for internal switching.
1325          */
1326         hw->switch_tag = 0xffff;
1327
1328         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1329         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1330                 PMD_INIT_LOG(ERR, "\nERROR: "
1331                         "Firmware recovery mode detected. Limiting functionality.\n"
1332                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1333                         "User Guide for details on firmware recovery mode.");
1334                 return -EIO;
1335         }
1336
1337         /* Check if need to support multi-driver */
1338         i40e_support_multi_driver(dev);
1339         /* Check if users want the latest supported vec path */
1340         i40e_use_latest_vec(dev);
1341
1342         /* Make sure all is clean before doing PF reset */
1343         i40e_clear_hw(hw);
1344
1345         /* Reset here to make sure all is clean for each PF */
1346         ret = i40e_pf_reset(hw);
1347         if (ret) {
1348                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1349                 return ret;
1350         }
1351
1352         /* Initialize the shared code (base driver) */
1353         ret = i40e_init_shared_code(hw);
1354         if (ret) {
1355                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1356                 return ret;
1357         }
1358
1359         /* Initialize the parameters for adminq */
1360         i40e_init_adminq_parameter(hw);
1361         ret = i40e_init_adminq(hw);
1362         if (ret != I40E_SUCCESS) {
1363                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1364                 return -EIO;
1365         }
1366         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1367                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1368                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1369                      ((hw->nvm.version >> 12) & 0xf),
1370                      ((hw->nvm.version >> 4) & 0xff),
1371                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1372
1373         /* Initialize the hardware */
1374         i40e_hw_init(dev);
1375
1376         i40e_config_automask(pf);
1377
1378         i40e_set_default_pctype_table(dev);
1379
1380         /*
1381          * To work around the NVM issue, initialize registers
1382          * for packet type of QinQ by software.
1383          * It should be removed once issues are fixed in NVM.
1384          */
1385         if (!pf->support_multi_driver)
1386                 i40e_GLQF_reg_init(hw);
1387
1388         /* Initialize the input set for filters (hash and fd) to default value */
1389         i40e_filter_input_set_init(pf);
1390
1391         /* initialise the L3_MAP register */
1392         if (!pf->support_multi_driver) {
1393                 ret = i40e_aq_debug_write_global_register(hw,
1394                                                    I40E_GLQF_L3_MAP(40),
1395                                                    0x00000028,  NULL);
1396                 if (ret)
1397                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1398                                      ret);
1399                 PMD_INIT_LOG(DEBUG,
1400                              "Global register 0x%08x is changed with 0x28",
1401                              I40E_GLQF_L3_MAP(40));
1402         }
1403
1404         /* Need the special FW version to support floating VEB */
1405         config_floating_veb(dev);
1406         /* Clear PXE mode */
1407         i40e_clear_pxe_mode(hw);
1408         i40e_dev_sync_phy_type(hw);
1409
1410         /*
1411          * On X710, performance number is far from the expectation on recent
1412          * firmware versions. The fix for this issue may not be integrated in
1413          * the following firmware version. So the workaround in software driver
1414          * is needed. It needs to modify the initial values of 3 internal only
1415          * registers. Note that the workaround can be removed when it is fixed
1416          * in firmware in the future.
1417          */
1418         i40e_configure_registers(hw);
1419
1420         /* Get hw capabilities */
1421         ret = i40e_get_cap(hw);
1422         if (ret != I40E_SUCCESS) {
1423                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1424                 goto err_get_capabilities;
1425         }
1426
1427         /* Initialize parameters for PF */
1428         ret = i40e_pf_parameter_init(dev);
1429         if (ret != 0) {
1430                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1431                 goto err_parameter_init;
1432         }
1433
1434         /* Initialize the queue management */
1435         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1436         if (ret < 0) {
1437                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1438                 goto err_qp_pool_init;
1439         }
1440         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1441                                 hw->func_caps.num_msix_vectors - 1);
1442         if (ret < 0) {
1443                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1444                 goto err_msix_pool_init;
1445         }
1446
1447         /* Initialize lan hmc */
1448         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1449                                 hw->func_caps.num_rx_qp, 0, 0);
1450         if (ret != I40E_SUCCESS) {
1451                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1452                 goto err_init_lan_hmc;
1453         }
1454
1455         /* Configure lan hmc */
1456         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1457         if (ret != I40E_SUCCESS) {
1458                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1459                 goto err_configure_lan_hmc;
1460         }
1461
1462         /* Get and check the mac address */
1463         i40e_get_mac_addr(hw, hw->mac.addr);
1464         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1465                 PMD_INIT_LOG(ERR, "mac address is not valid");
1466                 ret = -EIO;
1467                 goto err_get_mac_addr;
1468         }
1469         /* Copy the permanent MAC address */
1470         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1471                         (struct ether_addr *) hw->mac.perm_addr);
1472
1473         /* Disable flow control */
1474         hw->fc.requested_mode = I40E_FC_NONE;
1475         i40e_set_fc(hw, &aq_fail, TRUE);
1476
1477         /* Set the global registers with default ether type value */
1478         if (!pf->support_multi_driver) {
1479                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1480                                          ETHER_TYPE_VLAN);
1481                 if (ret != I40E_SUCCESS) {
1482                         PMD_INIT_LOG(ERR,
1483                                      "Failed to set the default outer "
1484                                      "VLAN ether type");
1485                         goto err_setup_pf_switch;
1486                 }
1487         }
1488
1489         /* PF setup, which includes VSI setup */
1490         ret = i40e_pf_setup(pf);
1491         if (ret) {
1492                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1493                 goto err_setup_pf_switch;
1494         }
1495
1496         vsi = pf->main_vsi;
1497
1498         /* Disable double vlan by default */
1499         i40e_vsi_config_double_vlan(vsi, FALSE);
1500
1501         /* Disable S-TAG identification when floating_veb is disabled */
1502         if (!pf->floating_veb) {
1503                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1504                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1505                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1506                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1507                 }
1508         }
1509
1510         if (!vsi->max_macaddrs)
1511                 len = ETHER_ADDR_LEN;
1512         else
1513                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1514
1515         /* Should be after VSI initialized */
1516         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1517         if (!dev->data->mac_addrs) {
1518                 PMD_INIT_LOG(ERR,
1519                         "Failed to allocated memory for storing mac address");
1520                 goto err_mac_alloc;
1521         }
1522         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1523                                         &dev->data->mac_addrs[0]);
1524
1525         /* Init dcb to sw mode by default */
1526         ret = i40e_dcb_init_configure(dev, TRUE);
1527         if (ret != I40E_SUCCESS) {
1528                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1529                 pf->flags &= ~I40E_FLAG_DCB;
1530         }
1531         /* Update HW struct after DCB configuration */
1532         i40e_get_cap(hw);
1533
1534         /* initialize pf host driver to setup SRIOV resource if applicable */
1535         i40e_pf_host_init(dev);
1536
1537         /* register callback func to eal lib */
1538         rte_intr_callback_register(intr_handle,
1539                                    i40e_dev_interrupt_handler, dev);
1540
1541         /* configure and enable device interrupt */
1542         i40e_pf_config_irq0(hw, TRUE);
1543         i40e_pf_enable_irq0(hw);
1544
1545         /* enable uio intr after callback register */
1546         rte_intr_enable(intr_handle);
1547
1548         /* By default disable flexible payload in global configuration */
1549         if (!pf->support_multi_driver)
1550                 i40e_flex_payload_reg_set_default(hw);
1551
1552         /*
1553          * Add an ethertype filter to drop all flow control frames transmitted
1554          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1555          * frames to wire.
1556          */
1557         i40e_add_tx_flow_control_drop_filter(pf);
1558
1559         /* Set the max frame size to 0x2600 by default,
1560          * in case other drivers changed the default value.
1561          */
1562         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1563
1564         /* initialize mirror rule list */
1565         TAILQ_INIT(&pf->mirror_list);
1566
1567         /* initialize Traffic Manager configuration */
1568         i40e_tm_conf_init(dev);
1569
1570         /* Initialize customized information */
1571         i40e_init_customized_info(pf);
1572
1573         ret = i40e_init_ethtype_filter_list(dev);
1574         if (ret < 0)
1575                 goto err_init_ethtype_filter_list;
1576         ret = i40e_init_tunnel_filter_list(dev);
1577         if (ret < 0)
1578                 goto err_init_tunnel_filter_list;
1579         ret = i40e_init_fdir_filter_list(dev);
1580         if (ret < 0)
1581                 goto err_init_fdir_filter_list;
1582
1583         /* initialize queue region configuration */
1584         i40e_init_queue_region_conf(dev);
1585
1586         /* initialize rss configuration from rte_flow */
1587         memset(&pf->rss_info, 0,
1588                 sizeof(struct i40e_rte_flow_rss_conf));
1589
1590         /* reset all stats of the device, including pf and main vsi */
1591         i40e_dev_stats_reset(dev);
1592
1593         return 0;
1594
1595 err_init_fdir_filter_list:
1596         rte_free(pf->tunnel.hash_table);
1597         rte_free(pf->tunnel.hash_map);
1598 err_init_tunnel_filter_list:
1599         rte_free(pf->ethertype.hash_table);
1600         rte_free(pf->ethertype.hash_map);
1601 err_init_ethtype_filter_list:
1602         rte_free(dev->data->mac_addrs);
1603 err_mac_alloc:
1604         i40e_vsi_release(pf->main_vsi);
1605 err_setup_pf_switch:
1606 err_get_mac_addr:
1607 err_configure_lan_hmc:
1608         (void)i40e_shutdown_lan_hmc(hw);
1609 err_init_lan_hmc:
1610         i40e_res_pool_destroy(&pf->msix_pool);
1611 err_msix_pool_init:
1612         i40e_res_pool_destroy(&pf->qp_pool);
1613 err_qp_pool_init:
1614 err_parameter_init:
1615 err_get_capabilities:
1616         (void)i40e_shutdown_adminq(hw);
1617
1618         return ret;
1619 }
1620
1621 static void
1622 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1623 {
1624         struct i40e_ethertype_filter *p_ethertype;
1625         struct i40e_ethertype_rule *ethertype_rule;
1626
1627         ethertype_rule = &pf->ethertype;
1628         /* Remove all ethertype filter rules and hash */
1629         if (ethertype_rule->hash_map)
1630                 rte_free(ethertype_rule->hash_map);
1631         if (ethertype_rule->hash_table)
1632                 rte_hash_free(ethertype_rule->hash_table);
1633
1634         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1635                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1636                              p_ethertype, rules);
1637                 rte_free(p_ethertype);
1638         }
1639 }
1640
1641 static void
1642 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1643 {
1644         struct i40e_tunnel_filter *p_tunnel;
1645         struct i40e_tunnel_rule *tunnel_rule;
1646
1647         tunnel_rule = &pf->tunnel;
1648         /* Remove all tunnel director rules and hash */
1649         if (tunnel_rule->hash_map)
1650                 rte_free(tunnel_rule->hash_map);
1651         if (tunnel_rule->hash_table)
1652                 rte_hash_free(tunnel_rule->hash_table);
1653
1654         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1655                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1656                 rte_free(p_tunnel);
1657         }
1658 }
1659
1660 static void
1661 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1662 {
1663         struct i40e_fdir_filter *p_fdir;
1664         struct i40e_fdir_info *fdir_info;
1665
1666         fdir_info = &pf->fdir;
1667         /* Remove all flow director rules and hash */
1668         if (fdir_info->hash_map)
1669                 rte_free(fdir_info->hash_map);
1670         if (fdir_info->hash_table)
1671                 rte_hash_free(fdir_info->hash_table);
1672
1673         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1674                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1675                 rte_free(p_fdir);
1676         }
1677 }
1678
1679 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1680 {
1681         /*
1682          * Disable by default flexible payload
1683          * for corresponding L2/L3/L4 layers.
1684          */
1685         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1686         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1687         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1688 }
1689
1690 static int
1691 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1692 {
1693         struct i40e_pf *pf;
1694         struct rte_pci_device *pci_dev;
1695         struct rte_intr_handle *intr_handle;
1696         struct i40e_hw *hw;
1697         struct i40e_filter_control_settings settings;
1698         struct rte_flow *p_flow;
1699         int ret;
1700         uint8_t aq_fail = 0;
1701         int retries = 0;
1702
1703         PMD_INIT_FUNC_TRACE();
1704
1705         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1706                 return 0;
1707
1708         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1709         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1710         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1711         intr_handle = &pci_dev->intr_handle;
1712
1713         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1714         if (ret)
1715                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1716
1717         if (hw->adapter_closed == 0)
1718                 i40e_dev_close(dev);
1719
1720         dev->dev_ops = NULL;
1721         dev->rx_pkt_burst = NULL;
1722         dev->tx_pkt_burst = NULL;
1723
1724         /* Clear PXE mode */
1725         i40e_clear_pxe_mode(hw);
1726
1727         /* Unconfigure filter control */
1728         memset(&settings, 0, sizeof(settings));
1729         ret = i40e_set_filter_control(hw, &settings);
1730         if (ret)
1731                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1732                                         ret);
1733
1734         /* Disable flow control */
1735         hw->fc.requested_mode = I40E_FC_NONE;
1736         i40e_set_fc(hw, &aq_fail, TRUE);
1737
1738         /* uninitialize pf host driver */
1739         i40e_pf_host_uninit(dev);
1740
1741         /* disable uio intr before callback unregister */
1742         rte_intr_disable(intr_handle);
1743
1744         /* unregister callback func to eal lib */
1745         do {
1746                 ret = rte_intr_callback_unregister(intr_handle,
1747                                 i40e_dev_interrupt_handler, dev);
1748                 if (ret >= 0) {
1749                         break;
1750                 } else if (ret != -EAGAIN) {
1751                         PMD_INIT_LOG(ERR,
1752                                  "intr callback unregister failed: %d",
1753                                  ret);
1754                         return ret;
1755                 }
1756                 i40e_msec_delay(500);
1757         } while (retries++ < 5);
1758
1759         i40e_rm_ethtype_filter_list(pf);
1760         i40e_rm_tunnel_filter_list(pf);
1761         i40e_rm_fdir_filter_list(pf);
1762
1763         /* Remove all flows */
1764         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1765                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1766                 rte_free(p_flow);
1767         }
1768
1769         /* Remove all Traffic Manager configuration */
1770         i40e_tm_conf_uninit(dev);
1771
1772         return 0;
1773 }
1774
1775 static int
1776 i40e_dev_configure(struct rte_eth_dev *dev)
1777 {
1778         struct i40e_adapter *ad =
1779                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1780         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1782         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1783         int i, ret;
1784
1785         ret = i40e_dev_sync_phy_type(hw);
1786         if (ret)
1787                 return ret;
1788
1789         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1790          * bulk allocation or vector Rx preconditions we will reset it.
1791          */
1792         ad->rx_bulk_alloc_allowed = true;
1793         ad->rx_vec_allowed = true;
1794         ad->tx_simple_allowed = true;
1795         ad->tx_vec_allowed = true;
1796
1797         /* Only legacy filter API needs the following fdir config. So when the
1798          * legacy filter API is deprecated, the following codes should also be
1799          * removed.
1800          */
1801         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1802                 ret = i40e_fdir_setup(pf);
1803                 if (ret != I40E_SUCCESS) {
1804                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1805                         return -ENOTSUP;
1806                 }
1807                 ret = i40e_fdir_configure(dev);
1808                 if (ret < 0) {
1809                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1810                         goto err;
1811                 }
1812         } else
1813                 i40e_fdir_teardown(pf);
1814
1815         ret = i40e_dev_init_vlan(dev);
1816         if (ret < 0)
1817                 goto err;
1818
1819         /* VMDQ setup.
1820          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1821          *  RSS setting have different requirements.
1822          *  General PMD driver call sequence are NIC init, configure,
1823          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1824          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1825          *  applicable. So, VMDQ setting has to be done before
1826          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1827          *  For RSS setting, it will try to calculate actual configured RX queue
1828          *  number, which will be available after rx_queue_setup(). dev_start()
1829          *  function is good to place RSS setup.
1830          */
1831         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1832                 ret = i40e_vmdq_setup(dev);
1833                 if (ret)
1834                         goto err;
1835         }
1836
1837         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1838                 ret = i40e_dcb_setup(dev);
1839                 if (ret) {
1840                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1841                         goto err_dcb;
1842                 }
1843         }
1844
1845         TAILQ_INIT(&pf->flow_list);
1846
1847         return 0;
1848
1849 err_dcb:
1850         /* need to release vmdq resource if exists */
1851         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1852                 i40e_vsi_release(pf->vmdq[i].vsi);
1853                 pf->vmdq[i].vsi = NULL;
1854         }
1855         rte_free(pf->vmdq);
1856         pf->vmdq = NULL;
1857 err:
1858         /* Need to release fdir resource if exists.
1859          * Only legacy filter API needs the following fdir config. So when the
1860          * legacy filter API is deprecated, the following code should also be
1861          * removed.
1862          */
1863         i40e_fdir_teardown(pf);
1864         return ret;
1865 }
1866
1867 void
1868 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1869 {
1870         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1871         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1872         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1873         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1874         uint16_t msix_vect = vsi->msix_intr;
1875         uint16_t i;
1876
1877         for (i = 0; i < vsi->nb_qps; i++) {
1878                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1879                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1880                 rte_wmb();
1881         }
1882
1883         if (vsi->type != I40E_VSI_SRIOV) {
1884                 if (!rte_intr_allow_others(intr_handle)) {
1885                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1886                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1887                         I40E_WRITE_REG(hw,
1888                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1889                                        0);
1890                 } else {
1891                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1892                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1893                         I40E_WRITE_REG(hw,
1894                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1895                                                        msix_vect - 1), 0);
1896                 }
1897         } else {
1898                 uint32_t reg;
1899                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1900                         vsi->user_param + (msix_vect - 1);
1901
1902                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1903                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1904         }
1905         I40E_WRITE_FLUSH(hw);
1906 }
1907
1908 static void
1909 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1910                        int base_queue, int nb_queue,
1911                        uint16_t itr_idx)
1912 {
1913         int i;
1914         uint32_t val;
1915         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1916         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1917
1918         /* Bind all RX queues to allocated MSIX interrupt */
1919         for (i = 0; i < nb_queue; i++) {
1920                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1921                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1922                         ((base_queue + i + 1) <<
1923                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1924                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1925                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1926
1927                 if (i == nb_queue - 1)
1928                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1929                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1930         }
1931
1932         /* Write first RX queue to Link list register as the head element */
1933         if (vsi->type != I40E_VSI_SRIOV) {
1934                 uint16_t interval =
1935                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1936
1937                 if (msix_vect == I40E_MISC_VEC_ID) {
1938                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1939                                        (base_queue <<
1940                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1941                                        (0x0 <<
1942                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1943                         I40E_WRITE_REG(hw,
1944                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1945                                        interval);
1946                 } else {
1947                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1948                                        (base_queue <<
1949                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1950                                        (0x0 <<
1951                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1952                         I40E_WRITE_REG(hw,
1953                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1954                                                        msix_vect - 1),
1955                                        interval);
1956                 }
1957         } else {
1958                 uint32_t reg;
1959
1960                 if (msix_vect == I40E_MISC_VEC_ID) {
1961                         I40E_WRITE_REG(hw,
1962                                        I40E_VPINT_LNKLST0(vsi->user_param),
1963                                        (base_queue <<
1964                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1965                                        (0x0 <<
1966                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1967                 } else {
1968                         /* num_msix_vectors_vf needs to minus irq0 */
1969                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1970                                 vsi->user_param + (msix_vect - 1);
1971
1972                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1973                                        (base_queue <<
1974                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1975                                        (0x0 <<
1976                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1977                 }
1978         }
1979
1980         I40E_WRITE_FLUSH(hw);
1981 }
1982
1983 void
1984 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1985 {
1986         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1987         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1988         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1989         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1990         uint16_t msix_vect = vsi->msix_intr;
1991         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1992         uint16_t queue_idx = 0;
1993         int record = 0;
1994         int i;
1995
1996         for (i = 0; i < vsi->nb_qps; i++) {
1997                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1998                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1999         }
2000
2001         /* VF bind interrupt */
2002         if (vsi->type == I40E_VSI_SRIOV) {
2003                 __vsi_queues_bind_intr(vsi, msix_vect,
2004                                        vsi->base_queue, vsi->nb_qps,
2005                                        itr_idx);
2006                 return;
2007         }
2008
2009         /* PF & VMDq bind interrupt */
2010         if (rte_intr_dp_is_en(intr_handle)) {
2011                 if (vsi->type == I40E_VSI_MAIN) {
2012                         queue_idx = 0;
2013                         record = 1;
2014                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2015                         struct i40e_vsi *main_vsi =
2016                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2017                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2018                         record = 1;
2019                 }
2020         }
2021
2022         for (i = 0; i < vsi->nb_used_qps; i++) {
2023                 if (nb_msix <= 1) {
2024                         if (!rte_intr_allow_others(intr_handle))
2025                                 /* allow to share MISC_VEC_ID */
2026                                 msix_vect = I40E_MISC_VEC_ID;
2027
2028                         /* no enough msix_vect, map all to one */
2029                         __vsi_queues_bind_intr(vsi, msix_vect,
2030                                                vsi->base_queue + i,
2031                                                vsi->nb_used_qps - i,
2032                                                itr_idx);
2033                         for (; !!record && i < vsi->nb_used_qps; i++)
2034                                 intr_handle->intr_vec[queue_idx + i] =
2035                                         msix_vect;
2036                         break;
2037                 }
2038                 /* 1:1 queue/msix_vect mapping */
2039                 __vsi_queues_bind_intr(vsi, msix_vect,
2040                                        vsi->base_queue + i, 1,
2041                                        itr_idx);
2042                 if (!!record)
2043                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2044
2045                 msix_vect++;
2046                 nb_msix--;
2047         }
2048 }
2049
2050 static void
2051 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2052 {
2053         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2054         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2055         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2056         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2057         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2058         uint16_t msix_intr, i;
2059
2060         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2061                 for (i = 0; i < vsi->nb_msix; i++) {
2062                         msix_intr = vsi->msix_intr + i;
2063                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2064                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2065                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2066                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2067                 }
2068         else
2069                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2070                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2071                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2072                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2073
2074         I40E_WRITE_FLUSH(hw);
2075 }
2076
2077 static void
2078 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2079 {
2080         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2081         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2082         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2083         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2084         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2085         uint16_t msix_intr, i;
2086
2087         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2088                 for (i = 0; i < vsi->nb_msix; i++) {
2089                         msix_intr = vsi->msix_intr + i;
2090                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2091                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2092                 }
2093         else
2094                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2095                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2096
2097         I40E_WRITE_FLUSH(hw);
2098 }
2099
2100 static inline uint8_t
2101 i40e_parse_link_speeds(uint16_t link_speeds)
2102 {
2103         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2104
2105         if (link_speeds & ETH_LINK_SPEED_40G)
2106                 link_speed |= I40E_LINK_SPEED_40GB;
2107         if (link_speeds & ETH_LINK_SPEED_25G)
2108                 link_speed |= I40E_LINK_SPEED_25GB;
2109         if (link_speeds & ETH_LINK_SPEED_20G)
2110                 link_speed |= I40E_LINK_SPEED_20GB;
2111         if (link_speeds & ETH_LINK_SPEED_10G)
2112                 link_speed |= I40E_LINK_SPEED_10GB;
2113         if (link_speeds & ETH_LINK_SPEED_1G)
2114                 link_speed |= I40E_LINK_SPEED_1GB;
2115         if (link_speeds & ETH_LINK_SPEED_100M)
2116                 link_speed |= I40E_LINK_SPEED_100MB;
2117
2118         return link_speed;
2119 }
2120
2121 static int
2122 i40e_phy_conf_link(struct i40e_hw *hw,
2123                    uint8_t abilities,
2124                    uint8_t force_speed,
2125                    bool is_up)
2126 {
2127         enum i40e_status_code status;
2128         struct i40e_aq_get_phy_abilities_resp phy_ab;
2129         struct i40e_aq_set_phy_config phy_conf;
2130         enum i40e_aq_phy_type cnt;
2131         uint8_t avail_speed;
2132         uint32_t phy_type_mask = 0;
2133
2134         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2135                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2136                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2137                         I40E_AQ_PHY_FLAG_LOW_POWER;
2138         int ret = -ENOTSUP;
2139
2140         /* To get phy capabilities of available speeds. */
2141         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2142                                               NULL);
2143         if (status) {
2144                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2145                                 status);
2146                 return ret;
2147         }
2148         avail_speed = phy_ab.link_speed;
2149
2150         /* To get the current phy config. */
2151         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2152                                               NULL);
2153         if (status) {
2154                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2155                                 status);
2156                 return ret;
2157         }
2158
2159         /* If link needs to go up and it is in autoneg mode the speed is OK,
2160          * no need to set up again.
2161          */
2162         if (is_up && phy_ab.phy_type != 0 &&
2163                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2164                      phy_ab.link_speed != 0)
2165                 return I40E_SUCCESS;
2166
2167         memset(&phy_conf, 0, sizeof(phy_conf));
2168
2169         /* bits 0-2 use the values from get_phy_abilities_resp */
2170         abilities &= ~mask;
2171         abilities |= phy_ab.abilities & mask;
2172
2173         phy_conf.abilities = abilities;
2174
2175         /* If link needs to go up, but the force speed is not supported,
2176          * Warn users and config the default available speeds.
2177          */
2178         if (is_up && !(force_speed & avail_speed)) {
2179                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2180                 phy_conf.link_speed = avail_speed;
2181         } else {
2182                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2183         }
2184
2185         /* PHY type mask needs to include each type except PHY type extension */
2186         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2187                 phy_type_mask |= 1 << cnt;
2188
2189         /* use get_phy_abilities_resp value for the rest */
2190         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2191         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2192                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2193                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2194         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2195         phy_conf.eee_capability = phy_ab.eee_capability;
2196         phy_conf.eeer = phy_ab.eeer_val;
2197         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2198
2199         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2200                     phy_ab.abilities, phy_ab.link_speed);
2201         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2202                     phy_conf.abilities, phy_conf.link_speed);
2203
2204         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2205         if (status)
2206                 return ret;
2207
2208         return I40E_SUCCESS;
2209 }
2210
2211 static int
2212 i40e_apply_link_speed(struct rte_eth_dev *dev)
2213 {
2214         uint8_t speed;
2215         uint8_t abilities = 0;
2216         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2217         struct rte_eth_conf *conf = &dev->data->dev_conf;
2218
2219         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2220                 conf->link_speeds = ETH_LINK_SPEED_40G |
2221                                     ETH_LINK_SPEED_25G |
2222                                     ETH_LINK_SPEED_20G |
2223                                     ETH_LINK_SPEED_10G |
2224                                     ETH_LINK_SPEED_1G |
2225                                     ETH_LINK_SPEED_100M;
2226         }
2227         speed = i40e_parse_link_speeds(conf->link_speeds);
2228         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2229                      I40E_AQ_PHY_AN_ENABLED |
2230                      I40E_AQ_PHY_LINK_ENABLED;
2231
2232         return i40e_phy_conf_link(hw, abilities, speed, true);
2233 }
2234
2235 static int
2236 i40e_dev_start(struct rte_eth_dev *dev)
2237 {
2238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2239         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240         struct i40e_vsi *main_vsi = pf->main_vsi;
2241         int ret, i;
2242         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2243         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2244         uint32_t intr_vector = 0;
2245         struct i40e_vsi *vsi;
2246
2247         hw->adapter_stopped = 0;
2248
2249         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2250                 PMD_INIT_LOG(ERR,
2251                 "Invalid link_speeds for port %u, autonegotiation disabled",
2252                               dev->data->port_id);
2253                 return -EINVAL;
2254         }
2255
2256         rte_intr_disable(intr_handle);
2257
2258         if ((rte_intr_cap_multiple(intr_handle) ||
2259              !RTE_ETH_DEV_SRIOV(dev).active) &&
2260             dev->data->dev_conf.intr_conf.rxq != 0) {
2261                 intr_vector = dev->data->nb_rx_queues;
2262                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2263                 if (ret)
2264                         return ret;
2265         }
2266
2267         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2268                 intr_handle->intr_vec =
2269                         rte_zmalloc("intr_vec",
2270                                     dev->data->nb_rx_queues * sizeof(int),
2271                                     0);
2272                 if (!intr_handle->intr_vec) {
2273                         PMD_INIT_LOG(ERR,
2274                                 "Failed to allocate %d rx_queues intr_vec",
2275                                 dev->data->nb_rx_queues);
2276                         return -ENOMEM;
2277                 }
2278         }
2279
2280         /* Initialize VSI */
2281         ret = i40e_dev_rxtx_init(pf);
2282         if (ret != I40E_SUCCESS) {
2283                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2284                 goto err_up;
2285         }
2286
2287         /* Map queues with MSIX interrupt */
2288         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2289                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2290         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2291         i40e_vsi_enable_queues_intr(main_vsi);
2292
2293         /* Map VMDQ VSI queues with MSIX interrupt */
2294         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2295                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2296                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2297                                           I40E_ITR_INDEX_DEFAULT);
2298                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2299         }
2300
2301         /* enable FDIR MSIX interrupt */
2302         if (pf->fdir.fdir_vsi) {
2303                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2304                                           I40E_ITR_INDEX_NONE);
2305                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2306         }
2307
2308         /* Enable all queues which have been configured */
2309         ret = i40e_dev_switch_queues(pf, TRUE);
2310         if (ret != I40E_SUCCESS) {
2311                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2312                 goto err_up;
2313         }
2314
2315         /* Enable receiving broadcast packets */
2316         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2317         if (ret != I40E_SUCCESS)
2318                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2319
2320         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2321                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2322                                                 true, NULL);
2323                 if (ret != I40E_SUCCESS)
2324                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2325         }
2326
2327         /* Enable the VLAN promiscuous mode. */
2328         if (pf->vfs) {
2329                 for (i = 0; i < pf->vf_num; i++) {
2330                         vsi = pf->vfs[i].vsi;
2331                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2332                                                      true, NULL);
2333                 }
2334         }
2335
2336         /* Enable mac loopback mode */
2337         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2338             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2339                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2340                 if (ret != I40E_SUCCESS) {
2341                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2342                         goto err_up;
2343                 }
2344         }
2345
2346         /* Apply link configure */
2347         ret = i40e_apply_link_speed(dev);
2348         if (I40E_SUCCESS != ret) {
2349                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2350                 goto err_up;
2351         }
2352
2353         if (!rte_intr_allow_others(intr_handle)) {
2354                 rte_intr_callback_unregister(intr_handle,
2355                                              i40e_dev_interrupt_handler,
2356                                              (void *)dev);
2357                 /* configure and enable device interrupt */
2358                 i40e_pf_config_irq0(hw, FALSE);
2359                 i40e_pf_enable_irq0(hw);
2360
2361                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2362                         PMD_INIT_LOG(INFO,
2363                                 "lsc won't enable because of no intr multiplex");
2364         } else {
2365                 ret = i40e_aq_set_phy_int_mask(hw,
2366                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2367                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2368                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2369                 if (ret != I40E_SUCCESS)
2370                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2371
2372                 /* Call get_link_info aq commond to enable/disable LSE */
2373                 i40e_dev_link_update(dev, 0);
2374         }
2375
2376         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2377                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2378                                   i40e_dev_alarm_handler, dev);
2379         } else {
2380                 /* enable uio intr after callback register */
2381                 rte_intr_enable(intr_handle);
2382         }
2383
2384         i40e_filter_restore(pf);
2385
2386         if (pf->tm_conf.root && !pf->tm_conf.committed)
2387                 PMD_DRV_LOG(WARNING,
2388                             "please call hierarchy_commit() "
2389                             "before starting the port");
2390
2391         return I40E_SUCCESS;
2392
2393 err_up:
2394         i40e_dev_switch_queues(pf, FALSE);
2395         i40e_dev_clear_queues(dev);
2396
2397         return ret;
2398 }
2399
2400 static void
2401 i40e_dev_stop(struct rte_eth_dev *dev)
2402 {
2403         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2404         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2405         struct i40e_vsi *main_vsi = pf->main_vsi;
2406         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2407         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2408         int i;
2409
2410         if (hw->adapter_stopped == 1)
2411                 return;
2412
2413         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2414                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2415                 rte_intr_enable(intr_handle);
2416         }
2417
2418         /* Disable all queues */
2419         i40e_dev_switch_queues(pf, FALSE);
2420
2421         /* un-map queues with interrupt registers */
2422         i40e_vsi_disable_queues_intr(main_vsi);
2423         i40e_vsi_queues_unbind_intr(main_vsi);
2424
2425         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2426                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2427                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2428         }
2429
2430         if (pf->fdir.fdir_vsi) {
2431                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2432                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2433         }
2434         /* Clear all queues and release memory */
2435         i40e_dev_clear_queues(dev);
2436
2437         /* Set link down */
2438         i40e_dev_set_link_down(dev);
2439
2440         if (!rte_intr_allow_others(intr_handle))
2441                 /* resume to the default handler */
2442                 rte_intr_callback_register(intr_handle,
2443                                            i40e_dev_interrupt_handler,
2444                                            (void *)dev);
2445
2446         /* Clean datapath event and queue/vec mapping */
2447         rte_intr_efd_disable(intr_handle);
2448         if (intr_handle->intr_vec) {
2449                 rte_free(intr_handle->intr_vec);
2450                 intr_handle->intr_vec = NULL;
2451         }
2452
2453         /* reset hierarchy commit */
2454         pf->tm_conf.committed = false;
2455
2456         hw->adapter_stopped = 1;
2457
2458         pf->adapter->rss_reta_updated = 0;
2459 }
2460
2461 static void
2462 i40e_dev_close(struct rte_eth_dev *dev)
2463 {
2464         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2465         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2467         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2468         struct i40e_mirror_rule *p_mirror;
2469         uint32_t reg;
2470         int i;
2471         int ret;
2472
2473         PMD_INIT_FUNC_TRACE();
2474
2475         i40e_dev_stop(dev);
2476
2477         /* Remove all mirror rules */
2478         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2479                 ret = i40e_aq_del_mirror_rule(hw,
2480                                               pf->main_vsi->veb->seid,
2481                                               p_mirror->rule_type,
2482                                               p_mirror->entries,
2483                                               p_mirror->num_entries,
2484                                               p_mirror->id);
2485                 if (ret < 0)
2486                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2487                                     "status = %d, aq_err = %d.", ret,
2488                                     hw->aq.asq_last_status);
2489
2490                 /* remove mirror software resource anyway */
2491                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2492                 rte_free(p_mirror);
2493                 pf->nb_mirror_rule--;
2494         }
2495
2496         i40e_dev_free_queues(dev);
2497
2498         /* Disable interrupt */
2499         i40e_pf_disable_irq0(hw);
2500         rte_intr_disable(intr_handle);
2501
2502         /*
2503          * Only legacy filter API needs the following fdir config. So when the
2504          * legacy filter API is deprecated, the following code should also be
2505          * removed.
2506          */
2507         i40e_fdir_teardown(pf);
2508
2509         /* shutdown and destroy the HMC */
2510         i40e_shutdown_lan_hmc(hw);
2511
2512         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2513                 i40e_vsi_release(pf->vmdq[i].vsi);
2514                 pf->vmdq[i].vsi = NULL;
2515         }
2516         rte_free(pf->vmdq);
2517         pf->vmdq = NULL;
2518
2519         /* release all the existing VSIs and VEBs */
2520         i40e_vsi_release(pf->main_vsi);
2521
2522         /* shutdown the adminq */
2523         i40e_aq_queue_shutdown(hw, true);
2524         i40e_shutdown_adminq(hw);
2525
2526         i40e_res_pool_destroy(&pf->qp_pool);
2527         i40e_res_pool_destroy(&pf->msix_pool);
2528
2529         /* Disable flexible payload in global configuration */
2530         if (!pf->support_multi_driver)
2531                 i40e_flex_payload_reg_set_default(hw);
2532
2533         /* force a PF reset to clean anything leftover */
2534         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2535         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2536                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2537         I40E_WRITE_FLUSH(hw);
2538
2539         hw->adapter_closed = 1;
2540 }
2541
2542 /*
2543  * Reset PF device only to re-initialize resources in PMD layer
2544  */
2545 static int
2546 i40e_dev_reset(struct rte_eth_dev *dev)
2547 {
2548         int ret;
2549
2550         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2551          * its VF to make them align with it. The detailed notification
2552          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2553          * To avoid unexpected behavior in VF, currently reset of PF with
2554          * SR-IOV activation is not supported. It might be supported later.
2555          */
2556         if (dev->data->sriov.active)
2557                 return -ENOTSUP;
2558
2559         ret = eth_i40e_dev_uninit(dev);
2560         if (ret)
2561                 return ret;
2562
2563         ret = eth_i40e_dev_init(dev, NULL);
2564
2565         return ret;
2566 }
2567
2568 static void
2569 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2570 {
2571         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2572         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2573         struct i40e_vsi *vsi = pf->main_vsi;
2574         int status;
2575
2576         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2577                                                      true, NULL, true);
2578         if (status != I40E_SUCCESS)
2579                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2580
2581         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2582                                                         TRUE, NULL);
2583         if (status != I40E_SUCCESS)
2584                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2585
2586 }
2587
2588 static void
2589 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2590 {
2591         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2592         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2593         struct i40e_vsi *vsi = pf->main_vsi;
2594         int status;
2595
2596         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2597                                                      false, NULL, true);
2598         if (status != I40E_SUCCESS)
2599                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2600
2601         /* must remain in all_multicast mode */
2602         if (dev->data->all_multicast == 1)
2603                 return;
2604
2605         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2606                                                         false, NULL);
2607         if (status != I40E_SUCCESS)
2608                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2609 }
2610
2611 static void
2612 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2613 {
2614         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616         struct i40e_vsi *vsi = pf->main_vsi;
2617         int ret;
2618
2619         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2620         if (ret != I40E_SUCCESS)
2621                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2622 }
2623
2624 static void
2625 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2626 {
2627         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2628         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2629         struct i40e_vsi *vsi = pf->main_vsi;
2630         int ret;
2631
2632         if (dev->data->promiscuous == 1)
2633                 return; /* must remain in all_multicast mode */
2634
2635         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2636                                 vsi->seid, FALSE, NULL);
2637         if (ret != I40E_SUCCESS)
2638                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2639 }
2640
2641 /*
2642  * Set device link up.
2643  */
2644 static int
2645 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2646 {
2647         /* re-apply link speed setting */
2648         return i40e_apply_link_speed(dev);
2649 }
2650
2651 /*
2652  * Set device link down.
2653  */
2654 static int
2655 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2656 {
2657         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2658         uint8_t abilities = 0;
2659         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2660
2661         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2662         return i40e_phy_conf_link(hw, abilities, speed, false);
2663 }
2664
2665 static __rte_always_inline void
2666 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2667 {
2668 /* Link status registers and values*/
2669 #define I40E_PRTMAC_LINKSTA             0x001E2420
2670 #define I40E_REG_LINK_UP                0x40000080
2671 #define I40E_PRTMAC_MACC                0x001E24E0
2672 #define I40E_REG_MACC_25GB              0x00020000
2673 #define I40E_REG_SPEED_MASK             0x38000000
2674 #define I40E_REG_SPEED_0                0x00000000
2675 #define I40E_REG_SPEED_1                0x08000000
2676 #define I40E_REG_SPEED_2                0x10000000
2677 #define I40E_REG_SPEED_3                0x18000000
2678 #define I40E_REG_SPEED_4                0x20000000
2679         uint32_t link_speed;
2680         uint32_t reg_val;
2681
2682         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2683         link_speed = reg_val & I40E_REG_SPEED_MASK;
2684         reg_val &= I40E_REG_LINK_UP;
2685         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2686
2687         if (unlikely(link->link_status == 0))
2688                 return;
2689
2690         /* Parse the link status */
2691         switch (link_speed) {
2692         case I40E_REG_SPEED_0:
2693                 link->link_speed = ETH_SPEED_NUM_100M;
2694                 break;
2695         case I40E_REG_SPEED_1:
2696                 link->link_speed = ETH_SPEED_NUM_1G;
2697                 break;
2698         case I40E_REG_SPEED_2:
2699                 if (hw->mac.type == I40E_MAC_X722)
2700                         link->link_speed = ETH_SPEED_NUM_2_5G;
2701                 else
2702                         link->link_speed = ETH_SPEED_NUM_10G;
2703                 break;
2704         case I40E_REG_SPEED_3:
2705                 if (hw->mac.type == I40E_MAC_X722) {
2706                         link->link_speed = ETH_SPEED_NUM_5G;
2707                 } else {
2708                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2709
2710                         if (reg_val & I40E_REG_MACC_25GB)
2711                                 link->link_speed = ETH_SPEED_NUM_25G;
2712                         else
2713                                 link->link_speed = ETH_SPEED_NUM_40G;
2714                 }
2715                 break;
2716         case I40E_REG_SPEED_4:
2717                 if (hw->mac.type == I40E_MAC_X722)
2718                         link->link_speed = ETH_SPEED_NUM_10G;
2719                 else
2720                         link->link_speed = ETH_SPEED_NUM_20G;
2721                 break;
2722         default:
2723                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2724                 break;
2725         }
2726 }
2727
2728 static __rte_always_inline void
2729 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2730         bool enable_lse, int wait_to_complete)
2731 {
2732 #define CHECK_INTERVAL             100  /* 100ms */
2733 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2734         uint32_t rep_cnt = MAX_REPEAT_TIME;
2735         struct i40e_link_status link_status;
2736         int status;
2737
2738         memset(&link_status, 0, sizeof(link_status));
2739
2740         do {
2741                 memset(&link_status, 0, sizeof(link_status));
2742
2743                 /* Get link status information from hardware */
2744                 status = i40e_aq_get_link_info(hw, enable_lse,
2745                                                 &link_status, NULL);
2746                 if (unlikely(status != I40E_SUCCESS)) {
2747                         link->link_speed = ETH_SPEED_NUM_100M;
2748                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2749                         PMD_DRV_LOG(ERR, "Failed to get link info");
2750                         return;
2751                 }
2752
2753                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2754                 if (!wait_to_complete || link->link_status)
2755                         break;
2756
2757                 rte_delay_ms(CHECK_INTERVAL);
2758         } while (--rep_cnt);
2759
2760         /* Parse the link status */
2761         switch (link_status.link_speed) {
2762         case I40E_LINK_SPEED_100MB:
2763                 link->link_speed = ETH_SPEED_NUM_100M;
2764                 break;
2765         case I40E_LINK_SPEED_1GB:
2766                 link->link_speed = ETH_SPEED_NUM_1G;
2767                 break;
2768         case I40E_LINK_SPEED_10GB:
2769                 link->link_speed = ETH_SPEED_NUM_10G;
2770                 break;
2771         case I40E_LINK_SPEED_20GB:
2772                 link->link_speed = ETH_SPEED_NUM_20G;
2773                 break;
2774         case I40E_LINK_SPEED_25GB:
2775                 link->link_speed = ETH_SPEED_NUM_25G;
2776                 break;
2777         case I40E_LINK_SPEED_40GB:
2778                 link->link_speed = ETH_SPEED_NUM_40G;
2779                 break;
2780         default:
2781                 link->link_speed = ETH_SPEED_NUM_100M;
2782                 break;
2783         }
2784 }
2785
2786 int
2787 i40e_dev_link_update(struct rte_eth_dev *dev,
2788                      int wait_to_complete)
2789 {
2790         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2791         struct rte_eth_link link;
2792         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2793         int ret;
2794
2795         memset(&link, 0, sizeof(link));
2796
2797         /* i40e uses full duplex only */
2798         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2799         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2800                         ETH_LINK_SPEED_FIXED);
2801
2802         if (!wait_to_complete && !enable_lse)
2803                 update_link_reg(hw, &link);
2804         else
2805                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2806
2807         ret = rte_eth_linkstatus_set(dev, &link);
2808         i40e_notify_all_vfs_link_status(dev);
2809
2810         return ret;
2811 }
2812
2813 /* Get all the statistics of a VSI */
2814 void
2815 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2816 {
2817         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2818         struct i40e_eth_stats *nes = &vsi->eth_stats;
2819         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2820         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2821
2822         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2823                             vsi->offset_loaded, &oes->rx_bytes,
2824                             &nes->rx_bytes);
2825         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2826                             vsi->offset_loaded, &oes->rx_unicast,
2827                             &nes->rx_unicast);
2828         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2829                             vsi->offset_loaded, &oes->rx_multicast,
2830                             &nes->rx_multicast);
2831         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2832                             vsi->offset_loaded, &oes->rx_broadcast,
2833                             &nes->rx_broadcast);
2834         /* exclude CRC bytes */
2835         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2836                 nes->rx_broadcast) * ETHER_CRC_LEN;
2837
2838         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2839                             &oes->rx_discards, &nes->rx_discards);
2840         /* GLV_REPC not supported */
2841         /* GLV_RMPC not supported */
2842         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2843                             &oes->rx_unknown_protocol,
2844                             &nes->rx_unknown_protocol);
2845         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2846                             vsi->offset_loaded, &oes->tx_bytes,
2847                             &nes->tx_bytes);
2848         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2849                             vsi->offset_loaded, &oes->tx_unicast,
2850                             &nes->tx_unicast);
2851         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2852                             vsi->offset_loaded, &oes->tx_multicast,
2853                             &nes->tx_multicast);
2854         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2855                             vsi->offset_loaded,  &oes->tx_broadcast,
2856                             &nes->tx_broadcast);
2857         /* GLV_TDPC not supported */
2858         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2859                             &oes->tx_errors, &nes->tx_errors);
2860         vsi->offset_loaded = true;
2861
2862         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2863                     vsi->vsi_id);
2864         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2865         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2866         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2867         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2868         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2869         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2870                     nes->rx_unknown_protocol);
2871         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2872         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2873         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2874         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2875         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2876         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2877         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2878                     vsi->vsi_id);
2879 }
2880
2881 static void
2882 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2883 {
2884         unsigned int i;
2885         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2886         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2887
2888         /* Get rx/tx bytes of internal transfer packets */
2889         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2890                         I40E_GLV_GORCL(hw->port),
2891                         pf->offset_loaded,
2892                         &pf->internal_stats_offset.rx_bytes,
2893                         &pf->internal_stats.rx_bytes);
2894
2895         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2896                         I40E_GLV_GOTCL(hw->port),
2897                         pf->offset_loaded,
2898                         &pf->internal_stats_offset.tx_bytes,
2899                         &pf->internal_stats.tx_bytes);
2900         /* Get total internal rx packet count */
2901         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2902                             I40E_GLV_UPRCL(hw->port),
2903                             pf->offset_loaded,
2904                             &pf->internal_stats_offset.rx_unicast,
2905                             &pf->internal_stats.rx_unicast);
2906         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2907                             I40E_GLV_MPRCL(hw->port),
2908                             pf->offset_loaded,
2909                             &pf->internal_stats_offset.rx_multicast,
2910                             &pf->internal_stats.rx_multicast);
2911         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2912                             I40E_GLV_BPRCL(hw->port),
2913                             pf->offset_loaded,
2914                             &pf->internal_stats_offset.rx_broadcast,
2915                             &pf->internal_stats.rx_broadcast);
2916         /* Get total internal tx packet count */
2917         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2918                             I40E_GLV_UPTCL(hw->port),
2919                             pf->offset_loaded,
2920                             &pf->internal_stats_offset.tx_unicast,
2921                             &pf->internal_stats.tx_unicast);
2922         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2923                             I40E_GLV_MPTCL(hw->port),
2924                             pf->offset_loaded,
2925                             &pf->internal_stats_offset.tx_multicast,
2926                             &pf->internal_stats.tx_multicast);
2927         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2928                             I40E_GLV_BPTCL(hw->port),
2929                             pf->offset_loaded,
2930                             &pf->internal_stats_offset.tx_broadcast,
2931                             &pf->internal_stats.tx_broadcast);
2932
2933         /* exclude CRC size */
2934         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2935                 pf->internal_stats.rx_multicast +
2936                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2937
2938         /* Get statistics of struct i40e_eth_stats */
2939         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2940                             I40E_GLPRT_GORCL(hw->port),
2941                             pf->offset_loaded, &os->eth.rx_bytes,
2942                             &ns->eth.rx_bytes);
2943         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2944                             I40E_GLPRT_UPRCL(hw->port),
2945                             pf->offset_loaded, &os->eth.rx_unicast,
2946                             &ns->eth.rx_unicast);
2947         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2948                             I40E_GLPRT_MPRCL(hw->port),
2949                             pf->offset_loaded, &os->eth.rx_multicast,
2950                             &ns->eth.rx_multicast);
2951         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2952                             I40E_GLPRT_BPRCL(hw->port),
2953                             pf->offset_loaded, &os->eth.rx_broadcast,
2954                             &ns->eth.rx_broadcast);
2955         /* Workaround: CRC size should not be included in byte statistics,
2956          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2957          */
2958         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2959                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2960
2961         /* exclude internal rx bytes
2962          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2963          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2964          * value.
2965          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2966          */
2967         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2968                 ns->eth.rx_bytes = 0;
2969         else
2970                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2971
2972         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2973                 ns->eth.rx_unicast = 0;
2974         else
2975                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2976
2977         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2978                 ns->eth.rx_multicast = 0;
2979         else
2980                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2981
2982         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2983                 ns->eth.rx_broadcast = 0;
2984         else
2985                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2986
2987         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2988                             pf->offset_loaded, &os->eth.rx_discards,
2989                             &ns->eth.rx_discards);
2990         /* GLPRT_REPC not supported */
2991         /* GLPRT_RMPC not supported */
2992         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2993                             pf->offset_loaded,
2994                             &os->eth.rx_unknown_protocol,
2995                             &ns->eth.rx_unknown_protocol);
2996         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2997                             I40E_GLPRT_GOTCL(hw->port),
2998                             pf->offset_loaded, &os->eth.tx_bytes,
2999                             &ns->eth.tx_bytes);
3000         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3001                             I40E_GLPRT_UPTCL(hw->port),
3002                             pf->offset_loaded, &os->eth.tx_unicast,
3003                             &ns->eth.tx_unicast);
3004         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3005                             I40E_GLPRT_MPTCL(hw->port),
3006                             pf->offset_loaded, &os->eth.tx_multicast,
3007                             &ns->eth.tx_multicast);
3008         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3009                             I40E_GLPRT_BPTCL(hw->port),
3010                             pf->offset_loaded, &os->eth.tx_broadcast,
3011                             &ns->eth.tx_broadcast);
3012         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3013                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
3014
3015         /* exclude internal tx bytes
3016          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3017          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3018          * value.
3019          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3020          */
3021         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3022                 ns->eth.tx_bytes = 0;
3023         else
3024                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3025
3026         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3027                 ns->eth.tx_unicast = 0;
3028         else
3029                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3030
3031         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3032                 ns->eth.tx_multicast = 0;
3033         else
3034                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3035
3036         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3037                 ns->eth.tx_broadcast = 0;
3038         else
3039                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3040
3041         /* GLPRT_TEPC not supported */
3042
3043         /* additional port specific stats */
3044         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3045                             pf->offset_loaded, &os->tx_dropped_link_down,
3046                             &ns->tx_dropped_link_down);
3047         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3048                             pf->offset_loaded, &os->crc_errors,
3049                             &ns->crc_errors);
3050         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3051                             pf->offset_loaded, &os->illegal_bytes,
3052                             &ns->illegal_bytes);
3053         /* GLPRT_ERRBC not supported */
3054         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3055                             pf->offset_loaded, &os->mac_local_faults,
3056                             &ns->mac_local_faults);
3057         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3058                             pf->offset_loaded, &os->mac_remote_faults,
3059                             &ns->mac_remote_faults);
3060         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3061                             pf->offset_loaded, &os->rx_length_errors,
3062                             &ns->rx_length_errors);
3063         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3064                             pf->offset_loaded, &os->link_xon_rx,
3065                             &ns->link_xon_rx);
3066         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3067                             pf->offset_loaded, &os->link_xoff_rx,
3068                             &ns->link_xoff_rx);
3069         for (i = 0; i < 8; i++) {
3070                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3071                                     pf->offset_loaded,
3072                                     &os->priority_xon_rx[i],
3073                                     &ns->priority_xon_rx[i]);
3074                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3075                                     pf->offset_loaded,
3076                                     &os->priority_xoff_rx[i],
3077                                     &ns->priority_xoff_rx[i]);
3078         }
3079         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3080                             pf->offset_loaded, &os->link_xon_tx,
3081                             &ns->link_xon_tx);
3082         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3083                             pf->offset_loaded, &os->link_xoff_tx,
3084                             &ns->link_xoff_tx);
3085         for (i = 0; i < 8; i++) {
3086                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3087                                     pf->offset_loaded,
3088                                     &os->priority_xon_tx[i],
3089                                     &ns->priority_xon_tx[i]);
3090                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3091                                     pf->offset_loaded,
3092                                     &os->priority_xoff_tx[i],
3093                                     &ns->priority_xoff_tx[i]);
3094                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3095                                     pf->offset_loaded,
3096                                     &os->priority_xon_2_xoff[i],
3097                                     &ns->priority_xon_2_xoff[i]);
3098         }
3099         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3100                             I40E_GLPRT_PRC64L(hw->port),
3101                             pf->offset_loaded, &os->rx_size_64,
3102                             &ns->rx_size_64);
3103         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3104                             I40E_GLPRT_PRC127L(hw->port),
3105                             pf->offset_loaded, &os->rx_size_127,
3106                             &ns->rx_size_127);
3107         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3108                             I40E_GLPRT_PRC255L(hw->port),
3109                             pf->offset_loaded, &os->rx_size_255,
3110                             &ns->rx_size_255);
3111         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3112                             I40E_GLPRT_PRC511L(hw->port),
3113                             pf->offset_loaded, &os->rx_size_511,
3114                             &ns->rx_size_511);
3115         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3116                             I40E_GLPRT_PRC1023L(hw->port),
3117                             pf->offset_loaded, &os->rx_size_1023,
3118                             &ns->rx_size_1023);
3119         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3120                             I40E_GLPRT_PRC1522L(hw->port),
3121                             pf->offset_loaded, &os->rx_size_1522,
3122                             &ns->rx_size_1522);
3123         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3124                             I40E_GLPRT_PRC9522L(hw->port),
3125                             pf->offset_loaded, &os->rx_size_big,
3126                             &ns->rx_size_big);
3127         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3128                             pf->offset_loaded, &os->rx_undersize,
3129                             &ns->rx_undersize);
3130         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3131                             pf->offset_loaded, &os->rx_fragments,
3132                             &ns->rx_fragments);
3133         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3134                             pf->offset_loaded, &os->rx_oversize,
3135                             &ns->rx_oversize);
3136         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3137                             pf->offset_loaded, &os->rx_jabber,
3138                             &ns->rx_jabber);
3139         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3140                             I40E_GLPRT_PTC64L(hw->port),
3141                             pf->offset_loaded, &os->tx_size_64,
3142                             &ns->tx_size_64);
3143         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3144                             I40E_GLPRT_PTC127L(hw->port),
3145                             pf->offset_loaded, &os->tx_size_127,
3146                             &ns->tx_size_127);
3147         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3148                             I40E_GLPRT_PTC255L(hw->port),
3149                             pf->offset_loaded, &os->tx_size_255,
3150                             &ns->tx_size_255);
3151         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3152                             I40E_GLPRT_PTC511L(hw->port),
3153                             pf->offset_loaded, &os->tx_size_511,
3154                             &ns->tx_size_511);
3155         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3156                             I40E_GLPRT_PTC1023L(hw->port),
3157                             pf->offset_loaded, &os->tx_size_1023,
3158                             &ns->tx_size_1023);
3159         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3160                             I40E_GLPRT_PTC1522L(hw->port),
3161                             pf->offset_loaded, &os->tx_size_1522,
3162                             &ns->tx_size_1522);
3163         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3164                             I40E_GLPRT_PTC9522L(hw->port),
3165                             pf->offset_loaded, &os->tx_size_big,
3166                             &ns->tx_size_big);
3167         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3168                            pf->offset_loaded,
3169                            &os->fd_sb_match, &ns->fd_sb_match);
3170         /* GLPRT_MSPDC not supported */
3171         /* GLPRT_XEC not supported */
3172
3173         pf->offset_loaded = true;
3174
3175         if (pf->main_vsi)
3176                 i40e_update_vsi_stats(pf->main_vsi);
3177 }
3178
3179 /* Get all statistics of a port */
3180 static int
3181 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3182 {
3183         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3184         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3185         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3186         struct i40e_vsi *vsi;
3187         unsigned i;
3188
3189         /* call read registers - updates values, now write them to struct */
3190         i40e_read_stats_registers(pf, hw);
3191
3192         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3193                         pf->main_vsi->eth_stats.rx_multicast +
3194                         pf->main_vsi->eth_stats.rx_broadcast -
3195                         pf->main_vsi->eth_stats.rx_discards;
3196         stats->opackets = ns->eth.tx_unicast +
3197                         ns->eth.tx_multicast +
3198                         ns->eth.tx_broadcast;
3199         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3200         stats->obytes   = ns->eth.tx_bytes;
3201         stats->oerrors  = ns->eth.tx_errors +
3202                         pf->main_vsi->eth_stats.tx_errors;
3203
3204         /* Rx Errors */
3205         stats->imissed  = ns->eth.rx_discards +
3206                         pf->main_vsi->eth_stats.rx_discards;
3207         stats->ierrors  = ns->crc_errors +
3208                         ns->rx_length_errors + ns->rx_undersize +
3209                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3210
3211         if (pf->vfs) {
3212                 for (i = 0; i < pf->vf_num; i++) {
3213                         vsi = pf->vfs[i].vsi;
3214                         i40e_update_vsi_stats(vsi);
3215
3216                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3217                                         vsi->eth_stats.rx_multicast +
3218                                         vsi->eth_stats.rx_broadcast -
3219                                         vsi->eth_stats.rx_discards);
3220                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3221                         stats->oerrors  += vsi->eth_stats.tx_errors;
3222                         stats->imissed  += vsi->eth_stats.rx_discards;
3223                 }
3224         }
3225
3226         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3227         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3228         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3229         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3230         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3231         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3232         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3233                     ns->eth.rx_unknown_protocol);
3234         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3235         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3236         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3237         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3238         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3239         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3240
3241         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3242                     ns->tx_dropped_link_down);
3243         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3244         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3245                     ns->illegal_bytes);
3246         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3247         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3248                     ns->mac_local_faults);
3249         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3250                     ns->mac_remote_faults);
3251         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3252                     ns->rx_length_errors);
3253         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3254         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3255         for (i = 0; i < 8; i++) {
3256                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3257                                 i, ns->priority_xon_rx[i]);
3258                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3259                                 i, ns->priority_xoff_rx[i]);
3260         }
3261         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3262         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3263         for (i = 0; i < 8; i++) {
3264                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3265                                 i, ns->priority_xon_tx[i]);
3266                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3267                                 i, ns->priority_xoff_tx[i]);
3268                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3269                                 i, ns->priority_xon_2_xoff[i]);
3270         }
3271         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3272         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3273         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3274         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3275         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3276         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3277         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3278         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3279         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3280         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3281         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3282         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3283         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3284         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3285         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3286         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3287         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3288         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3289         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3290                         ns->mac_short_packet_dropped);
3291         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3292                     ns->checksum_error);
3293         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3294         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3295         return 0;
3296 }
3297
3298 /* Reset the statistics */
3299 static void
3300 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3301 {
3302         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3303         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3304
3305         /* Mark PF and VSI stats to update the offset, aka "reset" */
3306         pf->offset_loaded = false;
3307         if (pf->main_vsi)
3308                 pf->main_vsi->offset_loaded = false;
3309
3310         /* read the stats, reading current register values into offset */
3311         i40e_read_stats_registers(pf, hw);
3312 }
3313
3314 static uint32_t
3315 i40e_xstats_calc_num(void)
3316 {
3317         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3318                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3319                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3320 }
3321
3322 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3323                                      struct rte_eth_xstat_name *xstats_names,
3324                                      __rte_unused unsigned limit)
3325 {
3326         unsigned count = 0;
3327         unsigned i, prio;
3328
3329         if (xstats_names == NULL)
3330                 return i40e_xstats_calc_num();
3331
3332         /* Note: limit checked in rte_eth_xstats_names() */
3333
3334         /* Get stats from i40e_eth_stats struct */
3335         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3336                 snprintf(xstats_names[count].name,
3337                          sizeof(xstats_names[count].name),
3338                          "%s", rte_i40e_stats_strings[i].name);
3339                 count++;
3340         }
3341
3342         /* Get individiual stats from i40e_hw_port struct */
3343         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3344                 snprintf(xstats_names[count].name,
3345                         sizeof(xstats_names[count].name),
3346                          "%s", rte_i40e_hw_port_strings[i].name);
3347                 count++;
3348         }
3349
3350         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3351                 for (prio = 0; prio < 8; prio++) {
3352                         snprintf(xstats_names[count].name,
3353                                  sizeof(xstats_names[count].name),
3354                                  "rx_priority%u_%s", prio,
3355                                  rte_i40e_rxq_prio_strings[i].name);
3356                         count++;
3357                 }
3358         }
3359
3360         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3361                 for (prio = 0; prio < 8; prio++) {
3362                         snprintf(xstats_names[count].name,
3363                                  sizeof(xstats_names[count].name),
3364                                  "tx_priority%u_%s", prio,
3365                                  rte_i40e_txq_prio_strings[i].name);
3366                         count++;
3367                 }
3368         }
3369         return count;
3370 }
3371
3372 static int
3373 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3374                     unsigned n)
3375 {
3376         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3377         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3378         unsigned i, count, prio;
3379         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3380
3381         count = i40e_xstats_calc_num();
3382         if (n < count)
3383                 return count;
3384
3385         i40e_read_stats_registers(pf, hw);
3386
3387         if (xstats == NULL)
3388                 return 0;
3389
3390         count = 0;
3391
3392         /* Get stats from i40e_eth_stats struct */
3393         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3394                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3395                         rte_i40e_stats_strings[i].offset);
3396                 xstats[count].id = count;
3397                 count++;
3398         }
3399
3400         /* Get individiual stats from i40e_hw_port struct */
3401         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3402                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3403                         rte_i40e_hw_port_strings[i].offset);
3404                 xstats[count].id = count;
3405                 count++;
3406         }
3407
3408         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3409                 for (prio = 0; prio < 8; prio++) {
3410                         xstats[count].value =
3411                                 *(uint64_t *)(((char *)hw_stats) +
3412                                 rte_i40e_rxq_prio_strings[i].offset +
3413                                 (sizeof(uint64_t) * prio));
3414                         xstats[count].id = count;
3415                         count++;
3416                 }
3417         }
3418
3419         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3420                 for (prio = 0; prio < 8; prio++) {
3421                         xstats[count].value =
3422                                 *(uint64_t *)(((char *)hw_stats) +
3423                                 rte_i40e_txq_prio_strings[i].offset +
3424                                 (sizeof(uint64_t) * prio));
3425                         xstats[count].id = count;
3426                         count++;
3427                 }
3428         }
3429
3430         return count;
3431 }
3432
3433 static int
3434 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3435                                  __rte_unused uint16_t queue_id,
3436                                  __rte_unused uint8_t stat_idx,
3437                                  __rte_unused uint8_t is_rx)
3438 {
3439         PMD_INIT_FUNC_TRACE();
3440
3441         return -ENOSYS;
3442 }
3443
3444 static int
3445 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3446 {
3447         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3448         u32 full_ver;
3449         u8 ver, patch;
3450         u16 build;
3451         int ret;
3452
3453         full_ver = hw->nvm.oem_ver;
3454         ver = (u8)(full_ver >> 24);
3455         build = (u16)((full_ver >> 8) & 0xffff);
3456         patch = (u8)(full_ver & 0xff);
3457
3458         ret = snprintf(fw_version, fw_size,
3459                  "%d.%d%d 0x%08x %d.%d.%d",
3460                  ((hw->nvm.version >> 12) & 0xf),
3461                  ((hw->nvm.version >> 4) & 0xff),
3462                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3463                  ver, build, patch);
3464
3465         ret += 1; /* add the size of '\0' */
3466         if (fw_size < (u32)ret)
3467                 return ret;
3468         else
3469                 return 0;
3470 }
3471
3472 /*
3473  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3474  * the Rx data path does not hang if the FW LLDP is stopped.
3475  * return true if lldp need to stop
3476  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3477  */
3478 static bool
3479 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3480 {
3481         double nvm_ver;
3482         char ver_str[64] = {0};
3483         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3484
3485         i40e_fw_version_get(dev, ver_str, 64);
3486         nvm_ver = atof(ver_str);
3487         if ((hw->mac.type == I40E_MAC_X722 ||
3488              hw->mac.type == I40E_MAC_X722_VF) &&
3489              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3490                 return true;
3491         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3492                 return true;
3493
3494         return false;
3495 }
3496
3497 static void
3498 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3499 {
3500         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3501         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3502         struct i40e_vsi *vsi = pf->main_vsi;
3503         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3504
3505         dev_info->max_rx_queues = vsi->nb_qps;
3506         dev_info->max_tx_queues = vsi->nb_qps;
3507         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3508         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3509         dev_info->max_mac_addrs = vsi->max_macaddrs;
3510         dev_info->max_vfs = pci_dev->max_vfs;
3511         dev_info->rx_queue_offload_capa = 0;
3512         dev_info->rx_offload_capa =
3513                 DEV_RX_OFFLOAD_VLAN_STRIP |
3514                 DEV_RX_OFFLOAD_QINQ_STRIP |
3515                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3516                 DEV_RX_OFFLOAD_UDP_CKSUM |
3517                 DEV_RX_OFFLOAD_TCP_CKSUM |
3518                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3519                 DEV_RX_OFFLOAD_KEEP_CRC |
3520                 DEV_RX_OFFLOAD_SCATTER |
3521                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3522                 DEV_RX_OFFLOAD_VLAN_FILTER |
3523                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3524
3525         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3526         dev_info->tx_offload_capa =
3527                 DEV_TX_OFFLOAD_VLAN_INSERT |
3528                 DEV_TX_OFFLOAD_QINQ_INSERT |
3529                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3530                 DEV_TX_OFFLOAD_UDP_CKSUM |
3531                 DEV_TX_OFFLOAD_TCP_CKSUM |
3532                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3533                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3534                 DEV_TX_OFFLOAD_TCP_TSO |
3535                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3536                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3537                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3538                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3539                 DEV_TX_OFFLOAD_MULTI_SEGS |
3540                 dev_info->tx_queue_offload_capa;
3541         dev_info->dev_capa =
3542                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3543                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3544
3545         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3546                                                 sizeof(uint32_t);
3547         dev_info->reta_size = pf->hash_lut_size;
3548         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3549
3550         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3551                 .rx_thresh = {
3552                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3553                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3554                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3555                 },
3556                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3557                 .rx_drop_en = 0,
3558                 .offloads = 0,
3559         };
3560
3561         dev_info->default_txconf = (struct rte_eth_txconf) {
3562                 .tx_thresh = {
3563                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3564                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3565                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3566                 },
3567                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3568                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3569                 .offloads = 0,
3570         };
3571
3572         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3573                 .nb_max = I40E_MAX_RING_DESC,
3574                 .nb_min = I40E_MIN_RING_DESC,
3575                 .nb_align = I40E_ALIGN_RING_DESC,
3576         };
3577
3578         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3579                 .nb_max = I40E_MAX_RING_DESC,
3580                 .nb_min = I40E_MIN_RING_DESC,
3581                 .nb_align = I40E_ALIGN_RING_DESC,
3582                 .nb_seg_max = I40E_TX_MAX_SEG,
3583                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3584         };
3585
3586         if (pf->flags & I40E_FLAG_VMDQ) {
3587                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3588                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3589                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3590                                                 pf->max_nb_vmdq_vsi;
3591                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3592                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3593                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3594         }
3595
3596         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3597                 /* For XL710 */
3598                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3599                 dev_info->default_rxportconf.nb_queues = 2;
3600                 dev_info->default_txportconf.nb_queues = 2;
3601                 if (dev->data->nb_rx_queues == 1)
3602                         dev_info->default_rxportconf.ring_size = 2048;
3603                 else
3604                         dev_info->default_rxportconf.ring_size = 1024;
3605                 if (dev->data->nb_tx_queues == 1)
3606                         dev_info->default_txportconf.ring_size = 1024;
3607                 else
3608                         dev_info->default_txportconf.ring_size = 512;
3609
3610         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3611                 /* For XXV710 */
3612                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3613                 dev_info->default_rxportconf.nb_queues = 1;
3614                 dev_info->default_txportconf.nb_queues = 1;
3615                 dev_info->default_rxportconf.ring_size = 256;
3616                 dev_info->default_txportconf.ring_size = 256;
3617         } else {
3618                 /* For X710 */
3619                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3620                 dev_info->default_rxportconf.nb_queues = 1;
3621                 dev_info->default_txportconf.nb_queues = 1;
3622                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3623                         dev_info->default_rxportconf.ring_size = 512;
3624                         dev_info->default_txportconf.ring_size = 256;
3625                 } else {
3626                         dev_info->default_rxportconf.ring_size = 256;
3627                         dev_info->default_txportconf.ring_size = 256;
3628                 }
3629         }
3630         dev_info->default_rxportconf.burst_size = 32;
3631         dev_info->default_txportconf.burst_size = 32;
3632 }
3633
3634 static int
3635 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3636 {
3637         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3638         struct i40e_vsi *vsi = pf->main_vsi;
3639         PMD_INIT_FUNC_TRACE();
3640
3641         if (on)
3642                 return i40e_vsi_add_vlan(vsi, vlan_id);
3643         else
3644                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3645 }
3646
3647 static int
3648 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3649                                 enum rte_vlan_type vlan_type,
3650                                 uint16_t tpid, int qinq)
3651 {
3652         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3653         uint64_t reg_r = 0;
3654         uint64_t reg_w = 0;
3655         uint16_t reg_id = 3;
3656         int ret;
3657
3658         if (qinq) {
3659                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3660                         reg_id = 2;
3661         }
3662
3663         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3664                                           &reg_r, NULL);
3665         if (ret != I40E_SUCCESS) {
3666                 PMD_DRV_LOG(ERR,
3667                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3668                            reg_id);
3669                 return -EIO;
3670         }
3671         PMD_DRV_LOG(DEBUG,
3672                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3673                     reg_id, reg_r);
3674
3675         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3676         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3677         if (reg_r == reg_w) {
3678                 PMD_DRV_LOG(DEBUG, "No need to write");
3679                 return 0;
3680         }
3681
3682         ret = i40e_aq_debug_write_global_register(hw,
3683                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3684                                            reg_w, NULL);
3685         if (ret != I40E_SUCCESS) {
3686                 PMD_DRV_LOG(ERR,
3687                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3688                             reg_id);
3689                 return -EIO;
3690         }
3691         PMD_DRV_LOG(DEBUG,
3692                     "Global register 0x%08x is changed with value 0x%08x",
3693                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3694
3695         return 0;
3696 }
3697
3698 static int
3699 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3700                    enum rte_vlan_type vlan_type,
3701                    uint16_t tpid)
3702 {
3703         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3704         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3705         int qinq = dev->data->dev_conf.rxmode.offloads &
3706                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3707         int ret = 0;
3708
3709         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3710              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3711             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3712                 PMD_DRV_LOG(ERR,
3713                             "Unsupported vlan type.");
3714                 return -EINVAL;
3715         }
3716
3717         if (pf->support_multi_driver) {
3718                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3719                 return -ENOTSUP;
3720         }
3721
3722         /* 802.1ad frames ability is added in NVM API 1.7*/
3723         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3724                 if (qinq) {
3725                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3726                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3727                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3728                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3729                 } else {
3730                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3731                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3732                 }
3733                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3734                 if (ret != I40E_SUCCESS) {
3735                         PMD_DRV_LOG(ERR,
3736                                     "Set switch config failed aq_err: %d",
3737                                     hw->aq.asq_last_status);
3738                         ret = -EIO;
3739                 }
3740         } else
3741                 /* If NVM API < 1.7, keep the register setting */
3742                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3743                                                       tpid, qinq);
3744
3745         return ret;
3746 }
3747
3748 static int
3749 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3750 {
3751         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3752         struct i40e_vsi *vsi = pf->main_vsi;
3753         struct rte_eth_rxmode *rxmode;
3754
3755         rxmode = &dev->data->dev_conf.rxmode;
3756         if (mask & ETH_VLAN_FILTER_MASK) {
3757                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3758                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3759                 else
3760                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3761         }
3762
3763         if (mask & ETH_VLAN_STRIP_MASK) {
3764                 /* Enable or disable VLAN stripping */
3765                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3766                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3767                 else
3768                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3769         }
3770
3771         if (mask & ETH_VLAN_EXTEND_MASK) {
3772                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3773                         i40e_vsi_config_double_vlan(vsi, TRUE);
3774                         /* Set global registers with default ethertype. */
3775                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3776                                            ETHER_TYPE_VLAN);
3777                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3778                                            ETHER_TYPE_VLAN);
3779                 }
3780                 else
3781                         i40e_vsi_config_double_vlan(vsi, FALSE);
3782         }
3783
3784         return 0;
3785 }
3786
3787 static void
3788 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3789                           __rte_unused uint16_t queue,
3790                           __rte_unused int on)
3791 {
3792         PMD_INIT_FUNC_TRACE();
3793 }
3794
3795 static int
3796 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3797 {
3798         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3799         struct i40e_vsi *vsi = pf->main_vsi;
3800         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3801         struct i40e_vsi_vlan_pvid_info info;
3802
3803         memset(&info, 0, sizeof(info));
3804         info.on = on;
3805         if (info.on)
3806                 info.config.pvid = pvid;
3807         else {
3808                 info.config.reject.tagged =
3809                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3810                 info.config.reject.untagged =
3811                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3812         }
3813
3814         return i40e_vsi_vlan_pvid_set(vsi, &info);
3815 }
3816
3817 static int
3818 i40e_dev_led_on(struct rte_eth_dev *dev)
3819 {
3820         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3821         uint32_t mode = i40e_led_get(hw);
3822
3823         if (mode == 0)
3824                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3825
3826         return 0;
3827 }
3828
3829 static int
3830 i40e_dev_led_off(struct rte_eth_dev *dev)
3831 {
3832         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3833         uint32_t mode = i40e_led_get(hw);
3834
3835         if (mode != 0)
3836                 i40e_led_set(hw, 0, false);
3837
3838         return 0;
3839 }
3840
3841 static int
3842 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3843 {
3844         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3845         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3846
3847         fc_conf->pause_time = pf->fc_conf.pause_time;
3848
3849         /* read out from register, in case they are modified by other port */
3850         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3851                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3852         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3853                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3854
3855         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3856         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3857
3858          /* Return current mode according to actual setting*/
3859         switch (hw->fc.current_mode) {
3860         case I40E_FC_FULL:
3861                 fc_conf->mode = RTE_FC_FULL;
3862                 break;
3863         case I40E_FC_TX_PAUSE:
3864                 fc_conf->mode = RTE_FC_TX_PAUSE;
3865                 break;
3866         case I40E_FC_RX_PAUSE:
3867                 fc_conf->mode = RTE_FC_RX_PAUSE;
3868                 break;
3869         case I40E_FC_NONE:
3870         default:
3871                 fc_conf->mode = RTE_FC_NONE;
3872         };
3873
3874         return 0;
3875 }
3876
3877 static int
3878 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3879 {
3880         uint32_t mflcn_reg, fctrl_reg, reg;
3881         uint32_t max_high_water;
3882         uint8_t i, aq_failure;
3883         int err;
3884         struct i40e_hw *hw;
3885         struct i40e_pf *pf;
3886         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3887                 [RTE_FC_NONE] = I40E_FC_NONE,
3888                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3889                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3890                 [RTE_FC_FULL] = I40E_FC_FULL
3891         };
3892
3893         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3894
3895         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3896         if ((fc_conf->high_water > max_high_water) ||
3897                         (fc_conf->high_water < fc_conf->low_water)) {
3898                 PMD_INIT_LOG(ERR,
3899                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3900                         max_high_water);
3901                 return -EINVAL;
3902         }
3903
3904         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3905         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3906         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3907
3908         pf->fc_conf.pause_time = fc_conf->pause_time;
3909         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3910         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3911
3912         PMD_INIT_FUNC_TRACE();
3913
3914         /* All the link flow control related enable/disable register
3915          * configuration is handle by the F/W
3916          */
3917         err = i40e_set_fc(hw, &aq_failure, true);
3918         if (err < 0)
3919                 return -ENOSYS;
3920
3921         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3922                 /* Configure flow control refresh threshold,
3923                  * the value for stat_tx_pause_refresh_timer[8]
3924                  * is used for global pause operation.
3925                  */
3926
3927                 I40E_WRITE_REG(hw,
3928                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3929                                pf->fc_conf.pause_time);
3930
3931                 /* configure the timer value included in transmitted pause
3932                  * frame,
3933                  * the value for stat_tx_pause_quanta[8] is used for global
3934                  * pause operation
3935                  */
3936                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3937                                pf->fc_conf.pause_time);
3938
3939                 fctrl_reg = I40E_READ_REG(hw,
3940                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3941
3942                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3943                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3944                 else
3945                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3946
3947                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3948                                fctrl_reg);
3949         } else {
3950                 /* Configure pause time (2 TCs per register) */
3951                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3952                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3953                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3954
3955                 /* Configure flow control refresh threshold value */
3956                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3957                                pf->fc_conf.pause_time / 2);
3958
3959                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3960
3961                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3962                  *depending on configuration
3963                  */
3964                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3965                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3966                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3967                 } else {
3968                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3969                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3970                 }
3971
3972                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3973         }
3974
3975         if (!pf->support_multi_driver) {
3976                 /* config water marker both based on the packets and bytes */
3977                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3978                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3979                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3980                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3981                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3982                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3983                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3984                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3985                                   << I40E_KILOSHIFT);
3986                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3987                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3988                                    << I40E_KILOSHIFT);
3989         } else {
3990                 PMD_DRV_LOG(ERR,
3991                             "Water marker configuration is not supported.");
3992         }
3993
3994         I40E_WRITE_FLUSH(hw);
3995
3996         return 0;
3997 }
3998
3999 static int
4000 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4001                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4002 {
4003         PMD_INIT_FUNC_TRACE();
4004
4005         return -ENOSYS;
4006 }
4007
4008 /* Add a MAC address, and update filters */
4009 static int
4010 i40e_macaddr_add(struct rte_eth_dev *dev,
4011                  struct ether_addr *mac_addr,
4012                  __rte_unused uint32_t index,
4013                  uint32_t pool)
4014 {
4015         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4016         struct i40e_mac_filter_info mac_filter;
4017         struct i40e_vsi *vsi;
4018         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4019         int ret;
4020
4021         /* If VMDQ not enabled or configured, return */
4022         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4023                           !pf->nb_cfg_vmdq_vsi)) {
4024                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4025                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4026                         pool);
4027                 return -ENOTSUP;
4028         }
4029
4030         if (pool > pf->nb_cfg_vmdq_vsi) {
4031                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4032                                 pool, pf->nb_cfg_vmdq_vsi);
4033                 return -EINVAL;
4034         }
4035
4036         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
4037         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4038                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4039         else
4040                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4041
4042         if (pool == 0)
4043                 vsi = pf->main_vsi;
4044         else
4045                 vsi = pf->vmdq[pool - 1].vsi;
4046
4047         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4048         if (ret != I40E_SUCCESS) {
4049                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4050                 return -ENODEV;
4051         }
4052         return 0;
4053 }
4054
4055 /* Remove a MAC address, and update filters */
4056 static void
4057 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4058 {
4059         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4060         struct i40e_vsi *vsi;
4061         struct rte_eth_dev_data *data = dev->data;
4062         struct ether_addr *macaddr;
4063         int ret;
4064         uint32_t i;
4065         uint64_t pool_sel;
4066
4067         macaddr = &(data->mac_addrs[index]);
4068
4069         pool_sel = dev->data->mac_pool_sel[index];
4070
4071         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4072                 if (pool_sel & (1ULL << i)) {
4073                         if (i == 0)
4074                                 vsi = pf->main_vsi;
4075                         else {
4076                                 /* No VMDQ pool enabled or configured */
4077                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4078                                         (i > pf->nb_cfg_vmdq_vsi)) {
4079                                         PMD_DRV_LOG(ERR,
4080                                                 "No VMDQ pool enabled/configured");
4081                                         return;
4082                                 }
4083                                 vsi = pf->vmdq[i - 1].vsi;
4084                         }
4085                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4086
4087                         if (ret) {
4088                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4089                                 return;
4090                         }
4091                 }
4092         }
4093 }
4094
4095 /* Set perfect match or hash match of MAC and VLAN for a VF */
4096 static int
4097 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4098                  struct rte_eth_mac_filter *filter,
4099                  bool add)
4100 {
4101         struct i40e_hw *hw;
4102         struct i40e_mac_filter_info mac_filter;
4103         struct ether_addr old_mac;
4104         struct ether_addr *new_mac;
4105         struct i40e_pf_vf *vf = NULL;
4106         uint16_t vf_id;
4107         int ret;
4108
4109         if (pf == NULL) {
4110                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4111                 return -EINVAL;
4112         }
4113         hw = I40E_PF_TO_HW(pf);
4114
4115         if (filter == NULL) {
4116                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4117                 return -EINVAL;
4118         }
4119
4120         new_mac = &filter->mac_addr;
4121
4122         if (is_zero_ether_addr(new_mac)) {
4123                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4124                 return -EINVAL;
4125         }
4126
4127         vf_id = filter->dst_id;
4128
4129         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4130                 PMD_DRV_LOG(ERR, "Invalid argument.");
4131                 return -EINVAL;
4132         }
4133         vf = &pf->vfs[vf_id];
4134
4135         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
4136                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4137                 return -EINVAL;
4138         }
4139
4140         if (add) {
4141                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
4142                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4143                                 ETHER_ADDR_LEN);
4144                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4145                                  ETHER_ADDR_LEN);
4146
4147                 mac_filter.filter_type = filter->filter_type;
4148                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4149                 if (ret != I40E_SUCCESS) {
4150                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4151                         return -1;
4152                 }
4153                 ether_addr_copy(new_mac, &pf->dev_addr);
4154         } else {
4155                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4156                                 ETHER_ADDR_LEN);
4157                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4158                 if (ret != I40E_SUCCESS) {
4159                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4160                         return -1;
4161                 }
4162
4163                 /* Clear device address as it has been removed */
4164                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
4165                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
4166         }
4167
4168         return 0;
4169 }
4170
4171 /* MAC filter handle */
4172 static int
4173 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4174                 void *arg)
4175 {
4176         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4177         struct rte_eth_mac_filter *filter;
4178         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4179         int ret = I40E_NOT_SUPPORTED;
4180
4181         filter = (struct rte_eth_mac_filter *)(arg);
4182
4183         switch (filter_op) {
4184         case RTE_ETH_FILTER_NOP:
4185                 ret = I40E_SUCCESS;
4186                 break;
4187         case RTE_ETH_FILTER_ADD:
4188                 i40e_pf_disable_irq0(hw);
4189                 if (filter->is_vf)
4190                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4191                 i40e_pf_enable_irq0(hw);
4192                 break;
4193         case RTE_ETH_FILTER_DELETE:
4194                 i40e_pf_disable_irq0(hw);
4195                 if (filter->is_vf)
4196                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4197                 i40e_pf_enable_irq0(hw);
4198                 break;
4199         default:
4200                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4201                 ret = I40E_ERR_PARAM;
4202                 break;
4203         }
4204
4205         return ret;
4206 }
4207
4208 static int
4209 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4210 {
4211         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4212         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4213         uint32_t reg;
4214         int ret;
4215
4216         if (!lut)
4217                 return -EINVAL;
4218
4219         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4220                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4221                                           vsi->type != I40E_VSI_SRIOV,
4222                                           lut, lut_size);
4223                 if (ret) {
4224                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4225                         return ret;
4226                 }
4227         } else {
4228                 uint32_t *lut_dw = (uint32_t *)lut;
4229                 uint16_t i, lut_size_dw = lut_size / 4;
4230
4231                 if (vsi->type == I40E_VSI_SRIOV) {
4232                         for (i = 0; i <= lut_size_dw; i++) {
4233                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4234                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4235                         }
4236                 } else {
4237                         for (i = 0; i < lut_size_dw; i++)
4238                                 lut_dw[i] = I40E_READ_REG(hw,
4239                                                           I40E_PFQF_HLUT(i));
4240                 }
4241         }
4242
4243         return 0;
4244 }
4245
4246 int
4247 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4248 {
4249         struct i40e_pf *pf;
4250         struct i40e_hw *hw;
4251         int ret;
4252
4253         if (!vsi || !lut)
4254                 return -EINVAL;
4255
4256         pf = I40E_VSI_TO_PF(vsi);
4257         hw = I40E_VSI_TO_HW(vsi);
4258
4259         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4260                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4261                                           vsi->type != I40E_VSI_SRIOV,
4262                                           lut, lut_size);
4263                 if (ret) {
4264                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4265                         return ret;
4266                 }
4267         } else {
4268                 uint32_t *lut_dw = (uint32_t *)lut;
4269                 uint16_t i, lut_size_dw = lut_size / 4;
4270
4271                 if (vsi->type == I40E_VSI_SRIOV) {
4272                         for (i = 0; i < lut_size_dw; i++)
4273                                 I40E_WRITE_REG(
4274                                         hw,
4275                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4276                                         lut_dw[i]);
4277                 } else {
4278                         for (i = 0; i < lut_size_dw; i++)
4279                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4280                                                lut_dw[i]);
4281                 }
4282                 I40E_WRITE_FLUSH(hw);
4283         }
4284
4285         return 0;
4286 }
4287
4288 static int
4289 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4290                          struct rte_eth_rss_reta_entry64 *reta_conf,
4291                          uint16_t reta_size)
4292 {
4293         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4294         uint16_t i, lut_size = pf->hash_lut_size;
4295         uint16_t idx, shift;
4296         uint8_t *lut;
4297         int ret;
4298
4299         if (reta_size != lut_size ||
4300                 reta_size > ETH_RSS_RETA_SIZE_512) {
4301                 PMD_DRV_LOG(ERR,
4302                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4303                         reta_size, lut_size);
4304                 return -EINVAL;
4305         }
4306
4307         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4308         if (!lut) {
4309                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4310                 return -ENOMEM;
4311         }
4312         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4313         if (ret)
4314                 goto out;
4315         for (i = 0; i < reta_size; i++) {
4316                 idx = i / RTE_RETA_GROUP_SIZE;
4317                 shift = i % RTE_RETA_GROUP_SIZE;
4318                 if (reta_conf[idx].mask & (1ULL << shift))
4319                         lut[i] = reta_conf[idx].reta[shift];
4320         }
4321         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4322
4323         pf->adapter->rss_reta_updated = 1;
4324
4325 out:
4326         rte_free(lut);
4327
4328         return ret;
4329 }
4330
4331 static int
4332 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4333                         struct rte_eth_rss_reta_entry64 *reta_conf,
4334                         uint16_t reta_size)
4335 {
4336         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4337         uint16_t i, lut_size = pf->hash_lut_size;
4338         uint16_t idx, shift;
4339         uint8_t *lut;
4340         int ret;
4341
4342         if (reta_size != lut_size ||
4343                 reta_size > ETH_RSS_RETA_SIZE_512) {
4344                 PMD_DRV_LOG(ERR,
4345                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4346                         reta_size, lut_size);
4347                 return -EINVAL;
4348         }
4349
4350         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4351         if (!lut) {
4352                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4353                 return -ENOMEM;
4354         }
4355
4356         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4357         if (ret)
4358                 goto out;
4359         for (i = 0; i < reta_size; i++) {
4360                 idx = i / RTE_RETA_GROUP_SIZE;
4361                 shift = i % RTE_RETA_GROUP_SIZE;
4362                 if (reta_conf[idx].mask & (1ULL << shift))
4363                         reta_conf[idx].reta[shift] = lut[i];
4364         }
4365
4366 out:
4367         rte_free(lut);
4368
4369         return ret;
4370 }
4371
4372 /**
4373  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4374  * @hw:   pointer to the HW structure
4375  * @mem:  pointer to mem struct to fill out
4376  * @size: size of memory requested
4377  * @alignment: what to align the allocation to
4378  **/
4379 enum i40e_status_code
4380 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4381                         struct i40e_dma_mem *mem,
4382                         u64 size,
4383                         u32 alignment)
4384 {
4385         const struct rte_memzone *mz = NULL;
4386         char z_name[RTE_MEMZONE_NAMESIZE];
4387
4388         if (!mem)
4389                 return I40E_ERR_PARAM;
4390
4391         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4392         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4393                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4394         if (!mz)
4395                 return I40E_ERR_NO_MEMORY;
4396
4397         mem->size = size;
4398         mem->va = mz->addr;
4399         mem->pa = mz->iova;
4400         mem->zone = (const void *)mz;
4401         PMD_DRV_LOG(DEBUG,
4402                 "memzone %s allocated with physical address: %"PRIu64,
4403                 mz->name, mem->pa);
4404
4405         return I40E_SUCCESS;
4406 }
4407
4408 /**
4409  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4410  * @hw:   pointer to the HW structure
4411  * @mem:  ptr to mem struct to free
4412  **/
4413 enum i40e_status_code
4414 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4415                     struct i40e_dma_mem *mem)
4416 {
4417         if (!mem)
4418                 return I40E_ERR_PARAM;
4419
4420         PMD_DRV_LOG(DEBUG,
4421                 "memzone %s to be freed with physical address: %"PRIu64,
4422                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4423         rte_memzone_free((const struct rte_memzone *)mem->zone);
4424         mem->zone = NULL;
4425         mem->va = NULL;
4426         mem->pa = (u64)0;
4427
4428         return I40E_SUCCESS;
4429 }
4430
4431 /**
4432  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4433  * @hw:   pointer to the HW structure
4434  * @mem:  pointer to mem struct to fill out
4435  * @size: size of memory requested
4436  **/
4437 enum i40e_status_code
4438 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4439                          struct i40e_virt_mem *mem,
4440                          u32 size)
4441 {
4442         if (!mem)
4443                 return I40E_ERR_PARAM;
4444
4445         mem->size = size;
4446         mem->va = rte_zmalloc("i40e", size, 0);
4447
4448         if (mem->va)
4449                 return I40E_SUCCESS;
4450         else
4451                 return I40E_ERR_NO_MEMORY;
4452 }
4453
4454 /**
4455  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4456  * @hw:   pointer to the HW structure
4457  * @mem:  pointer to mem struct to free
4458  **/
4459 enum i40e_status_code
4460 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4461                      struct i40e_virt_mem *mem)
4462 {
4463         if (!mem)
4464                 return I40E_ERR_PARAM;
4465
4466         rte_free(mem->va);
4467         mem->va = NULL;
4468
4469         return I40E_SUCCESS;
4470 }
4471
4472 void
4473 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4474 {
4475         rte_spinlock_init(&sp->spinlock);
4476 }
4477
4478 void
4479 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4480 {
4481         rte_spinlock_lock(&sp->spinlock);
4482 }
4483
4484 void
4485 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4486 {
4487         rte_spinlock_unlock(&sp->spinlock);
4488 }
4489
4490 void
4491 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4492 {
4493         return;
4494 }
4495
4496 /**
4497  * Get the hardware capabilities, which will be parsed
4498  * and saved into struct i40e_hw.
4499  */
4500 static int
4501 i40e_get_cap(struct i40e_hw *hw)
4502 {
4503         struct i40e_aqc_list_capabilities_element_resp *buf;
4504         uint16_t len, size = 0;
4505         int ret;
4506
4507         /* Calculate a huge enough buff for saving response data temporarily */
4508         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4509                                                 I40E_MAX_CAP_ELE_NUM;
4510         buf = rte_zmalloc("i40e", len, 0);
4511         if (!buf) {
4512                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4513                 return I40E_ERR_NO_MEMORY;
4514         }
4515
4516         /* Get, parse the capabilities and save it to hw */
4517         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4518                         i40e_aqc_opc_list_func_capabilities, NULL);
4519         if (ret != I40E_SUCCESS)
4520                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4521
4522         /* Free the temporary buffer after being used */
4523         rte_free(buf);
4524
4525         return ret;
4526 }
4527
4528 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4529
4530 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4531                 const char *value,
4532                 void *opaque)
4533 {
4534         struct i40e_pf *pf;
4535         unsigned long num;
4536         char *end;
4537
4538         pf = (struct i40e_pf *)opaque;
4539         RTE_SET_USED(key);
4540
4541         errno = 0;
4542         num = strtoul(value, &end, 0);
4543         if (errno != 0 || end == value || *end != 0) {
4544                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4545                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4546                 return -(EINVAL);
4547         }
4548
4549         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4550                 pf->vf_nb_qp_max = (uint16_t)num;
4551         else
4552                 /* here return 0 to make next valid same argument work */
4553                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4554                             "power of 2 and equal or less than 16 !, Now it is "
4555                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4556
4557         return 0;
4558 }
4559
4560 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4561 {
4562         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4563         struct rte_kvargs *kvlist;
4564         int kvargs_count;
4565
4566         /* set default queue number per VF as 4 */
4567         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4568
4569         if (dev->device->devargs == NULL)
4570                 return 0;
4571
4572         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4573         if (kvlist == NULL)
4574                 return -(EINVAL);
4575
4576         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4577         if (!kvargs_count) {
4578                 rte_kvargs_free(kvlist);
4579                 return 0;
4580         }
4581
4582         if (kvargs_count > 1)
4583                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4584                             "the first invalid or last valid one is used !",
4585                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4586
4587         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4588                            i40e_pf_parse_vf_queue_number_handler, pf);
4589
4590         rte_kvargs_free(kvlist);
4591
4592         return 0;
4593 }
4594
4595 static int
4596 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4597 {
4598         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4599         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4600         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4601         uint16_t qp_count = 0, vsi_count = 0;
4602
4603         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4604                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4605                 return -EINVAL;
4606         }
4607
4608         i40e_pf_config_vf_rxq_number(dev);
4609
4610         /* Add the parameter init for LFC */
4611         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4612         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4613         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4614
4615         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4616         pf->max_num_vsi = hw->func_caps.num_vsis;
4617         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4618         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4619
4620         /* FDir queue/VSI allocation */
4621         pf->fdir_qp_offset = 0;
4622         if (hw->func_caps.fd) {
4623                 pf->flags |= I40E_FLAG_FDIR;
4624                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4625         } else {
4626                 pf->fdir_nb_qps = 0;
4627         }
4628         qp_count += pf->fdir_nb_qps;
4629         vsi_count += 1;
4630
4631         /* LAN queue/VSI allocation */
4632         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4633         if (!hw->func_caps.rss) {
4634                 pf->lan_nb_qps = 1;
4635         } else {
4636                 pf->flags |= I40E_FLAG_RSS;
4637                 if (hw->mac.type == I40E_MAC_X722)
4638                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4639                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4640         }
4641         qp_count += pf->lan_nb_qps;
4642         vsi_count += 1;
4643
4644         /* VF queue/VSI allocation */
4645         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4646         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4647                 pf->flags |= I40E_FLAG_SRIOV;
4648                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4649                 pf->vf_num = pci_dev->max_vfs;
4650                 PMD_DRV_LOG(DEBUG,
4651                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4652                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4653         } else {
4654                 pf->vf_nb_qps = 0;
4655                 pf->vf_num = 0;
4656         }
4657         qp_count += pf->vf_nb_qps * pf->vf_num;
4658         vsi_count += pf->vf_num;
4659
4660         /* VMDq queue/VSI allocation */
4661         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4662         pf->vmdq_nb_qps = 0;
4663         pf->max_nb_vmdq_vsi = 0;
4664         if (hw->func_caps.vmdq) {
4665                 if (qp_count < hw->func_caps.num_tx_qp &&
4666                         vsi_count < hw->func_caps.num_vsis) {
4667                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4668                                 qp_count) / pf->vmdq_nb_qp_max;
4669
4670                         /* Limit the maximum number of VMDq vsi to the maximum
4671                          * ethdev can support
4672                          */
4673                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4674                                 hw->func_caps.num_vsis - vsi_count);
4675                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4676                                 ETH_64_POOLS);
4677                         if (pf->max_nb_vmdq_vsi) {
4678                                 pf->flags |= I40E_FLAG_VMDQ;
4679                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4680                                 PMD_DRV_LOG(DEBUG,
4681                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4682                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4683                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4684                         } else {
4685                                 PMD_DRV_LOG(INFO,
4686                                         "No enough queues left for VMDq");
4687                         }
4688                 } else {
4689                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4690                 }
4691         }
4692         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4693         vsi_count += pf->max_nb_vmdq_vsi;
4694
4695         if (hw->func_caps.dcb)
4696                 pf->flags |= I40E_FLAG_DCB;
4697
4698         if (qp_count > hw->func_caps.num_tx_qp) {
4699                 PMD_DRV_LOG(ERR,
4700                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4701                         qp_count, hw->func_caps.num_tx_qp);
4702                 return -EINVAL;
4703         }
4704         if (vsi_count > hw->func_caps.num_vsis) {
4705                 PMD_DRV_LOG(ERR,
4706                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4707                         vsi_count, hw->func_caps.num_vsis);
4708                 return -EINVAL;
4709         }
4710
4711         return 0;
4712 }
4713
4714 static int
4715 i40e_pf_get_switch_config(struct i40e_pf *pf)
4716 {
4717         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4718         struct i40e_aqc_get_switch_config_resp *switch_config;
4719         struct i40e_aqc_switch_config_element_resp *element;
4720         uint16_t start_seid = 0, num_reported;
4721         int ret;
4722
4723         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4724                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4725         if (!switch_config) {
4726                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4727                 return -ENOMEM;
4728         }
4729
4730         /* Get the switch configurations */
4731         ret = i40e_aq_get_switch_config(hw, switch_config,
4732                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4733         if (ret != I40E_SUCCESS) {
4734                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4735                 goto fail;
4736         }
4737         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4738         if (num_reported != 1) { /* The number should be 1 */
4739                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4740                 goto fail;
4741         }
4742
4743         /* Parse the switch configuration elements */
4744         element = &(switch_config->element[0]);
4745         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4746                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4747                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4748         } else
4749                 PMD_DRV_LOG(INFO, "Unknown element type");
4750
4751 fail:
4752         rte_free(switch_config);
4753
4754         return ret;
4755 }
4756
4757 static int
4758 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4759                         uint32_t num)
4760 {
4761         struct pool_entry *entry;
4762
4763         if (pool == NULL || num == 0)
4764                 return -EINVAL;
4765
4766         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4767         if (entry == NULL) {
4768                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4769                 return -ENOMEM;
4770         }
4771
4772         /* queue heap initialize */
4773         pool->num_free = num;
4774         pool->num_alloc = 0;
4775         pool->base = base;
4776         LIST_INIT(&pool->alloc_list);
4777         LIST_INIT(&pool->free_list);
4778
4779         /* Initialize element  */
4780         entry->base = 0;
4781         entry->len = num;
4782
4783         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4784         return 0;
4785 }
4786
4787 static void
4788 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4789 {
4790         struct pool_entry *entry, *next_entry;
4791
4792         if (pool == NULL)
4793                 return;
4794
4795         for (entry = LIST_FIRST(&pool->alloc_list);
4796                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4797                         entry = next_entry) {
4798                 LIST_REMOVE(entry, next);
4799                 rte_free(entry);
4800         }
4801
4802         for (entry = LIST_FIRST(&pool->free_list);
4803                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4804                         entry = next_entry) {
4805                 LIST_REMOVE(entry, next);
4806                 rte_free(entry);
4807         }
4808
4809         pool->num_free = 0;
4810         pool->num_alloc = 0;
4811         pool->base = 0;
4812         LIST_INIT(&pool->alloc_list);
4813         LIST_INIT(&pool->free_list);
4814 }
4815
4816 static int
4817 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4818                        uint32_t base)
4819 {
4820         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4821         uint32_t pool_offset;
4822         int insert;
4823
4824         if (pool == NULL) {
4825                 PMD_DRV_LOG(ERR, "Invalid parameter");
4826                 return -EINVAL;
4827         }
4828
4829         pool_offset = base - pool->base;
4830         /* Lookup in alloc list */
4831         LIST_FOREACH(entry, &pool->alloc_list, next) {
4832                 if (entry->base == pool_offset) {
4833                         valid_entry = entry;
4834                         LIST_REMOVE(entry, next);
4835                         break;
4836                 }
4837         }
4838
4839         /* Not find, return */
4840         if (valid_entry == NULL) {
4841                 PMD_DRV_LOG(ERR, "Failed to find entry");
4842                 return -EINVAL;
4843         }
4844
4845         /**
4846          * Found it, move it to free list  and try to merge.
4847          * In order to make merge easier, always sort it by qbase.
4848          * Find adjacent prev and last entries.
4849          */
4850         prev = next = NULL;
4851         LIST_FOREACH(entry, &pool->free_list, next) {
4852                 if (entry->base > valid_entry->base) {
4853                         next = entry;
4854                         break;
4855                 }
4856                 prev = entry;
4857         }
4858
4859         insert = 0;
4860         /* Try to merge with next one*/
4861         if (next != NULL) {
4862                 /* Merge with next one */
4863                 if (valid_entry->base + valid_entry->len == next->base) {
4864                         next->base = valid_entry->base;
4865                         next->len += valid_entry->len;
4866                         rte_free(valid_entry);
4867                         valid_entry = next;
4868                         insert = 1;
4869                 }
4870         }
4871
4872         if (prev != NULL) {
4873                 /* Merge with previous one */
4874                 if (prev->base + prev->len == valid_entry->base) {
4875                         prev->len += valid_entry->len;
4876                         /* If it merge with next one, remove next node */
4877                         if (insert == 1) {
4878                                 LIST_REMOVE(valid_entry, next);
4879                                 rte_free(valid_entry);
4880                         } else {
4881                                 rte_free(valid_entry);
4882                                 insert = 1;
4883                         }
4884                 }
4885         }
4886
4887         /* Not find any entry to merge, insert */
4888         if (insert == 0) {
4889                 if (prev != NULL)
4890                         LIST_INSERT_AFTER(prev, valid_entry, next);
4891                 else if (next != NULL)
4892                         LIST_INSERT_BEFORE(next, valid_entry, next);
4893                 else /* It's empty list, insert to head */
4894                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4895         }
4896
4897         pool->num_free += valid_entry->len;
4898         pool->num_alloc -= valid_entry->len;
4899
4900         return 0;
4901 }
4902
4903 static int
4904 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4905                        uint16_t num)
4906 {
4907         struct pool_entry *entry, *valid_entry;
4908
4909         if (pool == NULL || num == 0) {
4910                 PMD_DRV_LOG(ERR, "Invalid parameter");
4911                 return -EINVAL;
4912         }
4913
4914         if (pool->num_free < num) {
4915                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4916                             num, pool->num_free);
4917                 return -ENOMEM;
4918         }
4919
4920         valid_entry = NULL;
4921         /* Lookup  in free list and find most fit one */
4922         LIST_FOREACH(entry, &pool->free_list, next) {
4923                 if (entry->len >= num) {
4924                         /* Find best one */
4925                         if (entry->len == num) {
4926                                 valid_entry = entry;
4927                                 break;
4928                         }
4929                         if (valid_entry == NULL || valid_entry->len > entry->len)
4930                                 valid_entry = entry;
4931                 }
4932         }
4933
4934         /* Not find one to satisfy the request, return */
4935         if (valid_entry == NULL) {
4936                 PMD_DRV_LOG(ERR, "No valid entry found");
4937                 return -ENOMEM;
4938         }
4939         /**
4940          * The entry have equal queue number as requested,
4941          * remove it from alloc_list.
4942          */
4943         if (valid_entry->len == num) {
4944                 LIST_REMOVE(valid_entry, next);
4945         } else {
4946                 /**
4947                  * The entry have more numbers than requested,
4948                  * create a new entry for alloc_list and minus its
4949                  * queue base and number in free_list.
4950                  */
4951                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4952                 if (entry == NULL) {
4953                         PMD_DRV_LOG(ERR,
4954                                 "Failed to allocate memory for resource pool");
4955                         return -ENOMEM;
4956                 }
4957                 entry->base = valid_entry->base;
4958                 entry->len = num;
4959                 valid_entry->base += num;
4960                 valid_entry->len -= num;
4961                 valid_entry = entry;
4962         }
4963
4964         /* Insert it into alloc list, not sorted */
4965         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4966
4967         pool->num_free -= valid_entry->len;
4968         pool->num_alloc += valid_entry->len;
4969
4970         return valid_entry->base + pool->base;
4971 }
4972
4973 /**
4974  * bitmap_is_subset - Check whether src2 is subset of src1
4975  **/
4976 static inline int
4977 bitmap_is_subset(uint8_t src1, uint8_t src2)
4978 {
4979         return !((src1 ^ src2) & src2);
4980 }
4981
4982 static enum i40e_status_code
4983 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4984 {
4985         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4986
4987         /* If DCB is not supported, only default TC is supported */
4988         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4989                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4990                 return I40E_NOT_SUPPORTED;
4991         }
4992
4993         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4994                 PMD_DRV_LOG(ERR,
4995                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4996                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4997                 return I40E_NOT_SUPPORTED;
4998         }
4999         return I40E_SUCCESS;
5000 }
5001
5002 int
5003 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5004                                 struct i40e_vsi_vlan_pvid_info *info)
5005 {
5006         struct i40e_hw *hw;
5007         struct i40e_vsi_context ctxt;
5008         uint8_t vlan_flags = 0;
5009         int ret;
5010
5011         if (vsi == NULL || info == NULL) {
5012                 PMD_DRV_LOG(ERR, "invalid parameters");
5013                 return I40E_ERR_PARAM;
5014         }
5015
5016         if (info->on) {
5017                 vsi->info.pvid = info->config.pvid;
5018                 /**
5019                  * If insert pvid is enabled, only tagged pkts are
5020                  * allowed to be sent out.
5021                  */
5022                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5023                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5024         } else {
5025                 vsi->info.pvid = 0;
5026                 if (info->config.reject.tagged == 0)
5027                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5028
5029                 if (info->config.reject.untagged == 0)
5030                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5031         }
5032         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5033                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5034         vsi->info.port_vlan_flags |= vlan_flags;
5035         vsi->info.valid_sections =
5036                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5037         memset(&ctxt, 0, sizeof(ctxt));
5038         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5039         ctxt.seid = vsi->seid;
5040
5041         hw = I40E_VSI_TO_HW(vsi);
5042         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5043         if (ret != I40E_SUCCESS)
5044                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5045
5046         return ret;
5047 }
5048
5049 static int
5050 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5051 {
5052         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5053         int i, ret;
5054         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5055
5056         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5057         if (ret != I40E_SUCCESS)
5058                 return ret;
5059
5060         if (!vsi->seid) {
5061                 PMD_DRV_LOG(ERR, "seid not valid");
5062                 return -EINVAL;
5063         }
5064
5065         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5066         tc_bw_data.tc_valid_bits = enabled_tcmap;
5067         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5068                 tc_bw_data.tc_bw_credits[i] =
5069                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5070
5071         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5072         if (ret != I40E_SUCCESS) {
5073                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5074                 return ret;
5075         }
5076
5077         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5078                                         sizeof(vsi->info.qs_handle));
5079         return I40E_SUCCESS;
5080 }
5081
5082 static enum i40e_status_code
5083 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5084                                  struct i40e_aqc_vsi_properties_data *info,
5085                                  uint8_t enabled_tcmap)
5086 {
5087         enum i40e_status_code ret;
5088         int i, total_tc = 0;
5089         uint16_t qpnum_per_tc, bsf, qp_idx;
5090
5091         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5092         if (ret != I40E_SUCCESS)
5093                 return ret;
5094
5095         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5096                 if (enabled_tcmap & (1 << i))
5097                         total_tc++;
5098         if (total_tc == 0)
5099                 total_tc = 1;
5100         vsi->enabled_tc = enabled_tcmap;
5101
5102         /* Number of queues per enabled TC */
5103         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5104         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5105         bsf = rte_bsf32(qpnum_per_tc);
5106
5107         /* Adjust the queue number to actual queues that can be applied */
5108         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5109                 vsi->nb_qps = qpnum_per_tc * total_tc;
5110
5111         /**
5112          * Configure TC and queue mapping parameters, for enabled TC,
5113          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5114          * default queue will serve it.
5115          */
5116         qp_idx = 0;
5117         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5118                 if (vsi->enabled_tc & (1 << i)) {
5119                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5120                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5121                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5122                         qp_idx += qpnum_per_tc;
5123                 } else
5124                         info->tc_mapping[i] = 0;
5125         }
5126
5127         /* Associate queue number with VSI */
5128         if (vsi->type == I40E_VSI_SRIOV) {
5129                 info->mapping_flags |=
5130                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5131                 for (i = 0; i < vsi->nb_qps; i++)
5132                         info->queue_mapping[i] =
5133                                 rte_cpu_to_le_16(vsi->base_queue + i);
5134         } else {
5135                 info->mapping_flags |=
5136                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5137                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5138         }
5139         info->valid_sections |=
5140                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5141
5142         return I40E_SUCCESS;
5143 }
5144
5145 static int
5146 i40e_veb_release(struct i40e_veb *veb)
5147 {
5148         struct i40e_vsi *vsi;
5149         struct i40e_hw *hw;
5150
5151         if (veb == NULL)
5152                 return -EINVAL;
5153
5154         if (!TAILQ_EMPTY(&veb->head)) {
5155                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5156                 return -EACCES;
5157         }
5158         /* associate_vsi field is NULL for floating VEB */
5159         if (veb->associate_vsi != NULL) {
5160                 vsi = veb->associate_vsi;
5161                 hw = I40E_VSI_TO_HW(vsi);
5162
5163                 vsi->uplink_seid = veb->uplink_seid;
5164                 vsi->veb = NULL;
5165         } else {
5166                 veb->associate_pf->main_vsi->floating_veb = NULL;
5167                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5168         }
5169
5170         i40e_aq_delete_element(hw, veb->seid, NULL);
5171         rte_free(veb);
5172         return I40E_SUCCESS;
5173 }
5174
5175 /* Setup a veb */
5176 static struct i40e_veb *
5177 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5178 {
5179         struct i40e_veb *veb;
5180         int ret;
5181         struct i40e_hw *hw;
5182
5183         if (pf == NULL) {
5184                 PMD_DRV_LOG(ERR,
5185                             "veb setup failed, associated PF shouldn't null");
5186                 return NULL;
5187         }
5188         hw = I40E_PF_TO_HW(pf);
5189
5190         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5191         if (!veb) {
5192                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5193                 goto fail;
5194         }
5195
5196         veb->associate_vsi = vsi;
5197         veb->associate_pf = pf;
5198         TAILQ_INIT(&veb->head);
5199         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5200
5201         /* create floating veb if vsi is NULL */
5202         if (vsi != NULL) {
5203                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5204                                       I40E_DEFAULT_TCMAP, false,
5205                                       &veb->seid, false, NULL);
5206         } else {
5207                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5208                                       true, &veb->seid, false, NULL);
5209         }
5210
5211         if (ret != I40E_SUCCESS) {
5212                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5213                             hw->aq.asq_last_status);
5214                 goto fail;
5215         }
5216         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5217
5218         /* get statistics index */
5219         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5220                                 &veb->stats_idx, NULL, NULL, NULL);
5221         if (ret != I40E_SUCCESS) {
5222                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5223                             hw->aq.asq_last_status);
5224                 goto fail;
5225         }
5226         /* Get VEB bandwidth, to be implemented */
5227         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5228         if (vsi)
5229                 vsi->uplink_seid = veb->seid;
5230
5231         return veb;
5232 fail:
5233         rte_free(veb);
5234         return NULL;
5235 }
5236
5237 int
5238 i40e_vsi_release(struct i40e_vsi *vsi)
5239 {
5240         struct i40e_pf *pf;
5241         struct i40e_hw *hw;
5242         struct i40e_vsi_list *vsi_list;
5243         void *temp;
5244         int ret;
5245         struct i40e_mac_filter *f;
5246         uint16_t user_param;
5247
5248         if (!vsi)
5249                 return I40E_SUCCESS;
5250
5251         if (!vsi->adapter)
5252                 return -EFAULT;
5253
5254         user_param = vsi->user_param;
5255
5256         pf = I40E_VSI_TO_PF(vsi);
5257         hw = I40E_VSI_TO_HW(vsi);
5258
5259         /* VSI has child to attach, release child first */
5260         if (vsi->veb) {
5261                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5262                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5263                                 return -1;
5264                 }
5265                 i40e_veb_release(vsi->veb);
5266         }
5267
5268         if (vsi->floating_veb) {
5269                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5270                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5271                                 return -1;
5272                 }
5273         }
5274
5275         /* Remove all macvlan filters of the VSI */
5276         i40e_vsi_remove_all_macvlan_filter(vsi);
5277         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5278                 rte_free(f);
5279
5280         if (vsi->type != I40E_VSI_MAIN &&
5281             ((vsi->type != I40E_VSI_SRIOV) ||
5282             !pf->floating_veb_list[user_param])) {
5283                 /* Remove vsi from parent's sibling list */
5284                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5285                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5286                         return I40E_ERR_PARAM;
5287                 }
5288                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5289                                 &vsi->sib_vsi_list, list);
5290
5291                 /* Remove all switch element of the VSI */
5292                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5293                 if (ret != I40E_SUCCESS)
5294                         PMD_DRV_LOG(ERR, "Failed to delete element");
5295         }
5296
5297         if ((vsi->type == I40E_VSI_SRIOV) &&
5298             pf->floating_veb_list[user_param]) {
5299                 /* Remove vsi from parent's sibling list */
5300                 if (vsi->parent_vsi == NULL ||
5301                     vsi->parent_vsi->floating_veb == NULL) {
5302                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5303                         return I40E_ERR_PARAM;
5304                 }
5305                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5306                              &vsi->sib_vsi_list, list);
5307
5308                 /* Remove all switch element of the VSI */
5309                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5310                 if (ret != I40E_SUCCESS)
5311                         PMD_DRV_LOG(ERR, "Failed to delete element");
5312         }
5313
5314         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5315
5316         if (vsi->type != I40E_VSI_SRIOV)
5317                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5318         rte_free(vsi);
5319
5320         return I40E_SUCCESS;
5321 }
5322
5323 static int
5324 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5325 {
5326         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5327         struct i40e_aqc_remove_macvlan_element_data def_filter;
5328         struct i40e_mac_filter_info filter;
5329         int ret;
5330
5331         if (vsi->type != I40E_VSI_MAIN)
5332                 return I40E_ERR_CONFIG;
5333         memset(&def_filter, 0, sizeof(def_filter));
5334         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5335                                         ETH_ADDR_LEN);
5336         def_filter.vlan_tag = 0;
5337         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5338                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5339         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5340         if (ret != I40E_SUCCESS) {
5341                 struct i40e_mac_filter *f;
5342                 struct ether_addr *mac;
5343
5344                 PMD_DRV_LOG(DEBUG,
5345                             "Cannot remove the default macvlan filter");
5346                 /* It needs to add the permanent mac into mac list */
5347                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5348                 if (f == NULL) {
5349                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5350                         return I40E_ERR_NO_MEMORY;
5351                 }
5352                 mac = &f->mac_info.mac_addr;
5353                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5354                                 ETH_ADDR_LEN);
5355                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5356                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5357                 vsi->mac_num++;
5358
5359                 return ret;
5360         }
5361         rte_memcpy(&filter.mac_addr,
5362                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5363         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5364         return i40e_vsi_add_mac(vsi, &filter);
5365 }
5366
5367 /*
5368  * i40e_vsi_get_bw_config - Query VSI BW Information
5369  * @vsi: the VSI to be queried
5370  *
5371  * Returns 0 on success, negative value on failure
5372  */
5373 static enum i40e_status_code
5374 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5375 {
5376         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5377         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5378         struct i40e_hw *hw = &vsi->adapter->hw;
5379         i40e_status ret;
5380         int i;
5381         uint32_t bw_max;
5382
5383         memset(&bw_config, 0, sizeof(bw_config));
5384         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5385         if (ret != I40E_SUCCESS) {
5386                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5387                             hw->aq.asq_last_status);
5388                 return ret;
5389         }
5390
5391         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5392         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5393                                         &ets_sla_config, NULL);
5394         if (ret != I40E_SUCCESS) {
5395                 PMD_DRV_LOG(ERR,
5396                         "VSI failed to get TC bandwdith configuration %u",
5397                         hw->aq.asq_last_status);
5398                 return ret;
5399         }
5400
5401         /* store and print out BW info */
5402         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5403         vsi->bw_info.bw_max = bw_config.max_bw;
5404         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5405         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5406         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5407                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5408                      I40E_16_BIT_WIDTH);
5409         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5410                 vsi->bw_info.bw_ets_share_credits[i] =
5411                                 ets_sla_config.share_credits[i];
5412                 vsi->bw_info.bw_ets_credits[i] =
5413                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5414                 /* 4 bits per TC, 4th bit is reserved */
5415                 vsi->bw_info.bw_ets_max[i] =
5416                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5417                                   RTE_LEN2MASK(3, uint8_t));
5418                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5419                             vsi->bw_info.bw_ets_share_credits[i]);
5420                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5421                             vsi->bw_info.bw_ets_credits[i]);
5422                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5423                             vsi->bw_info.bw_ets_max[i]);
5424         }
5425
5426         return I40E_SUCCESS;
5427 }
5428
5429 /* i40e_enable_pf_lb
5430  * @pf: pointer to the pf structure
5431  *
5432  * allow loopback on pf
5433  */
5434 static inline void
5435 i40e_enable_pf_lb(struct i40e_pf *pf)
5436 {
5437         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5438         struct i40e_vsi_context ctxt;
5439         int ret;
5440
5441         /* Use the FW API if FW >= v5.0 */
5442         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5443                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5444                 return;
5445         }
5446
5447         memset(&ctxt, 0, sizeof(ctxt));
5448         ctxt.seid = pf->main_vsi_seid;
5449         ctxt.pf_num = hw->pf_id;
5450         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5451         if (ret) {
5452                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5453                             ret, hw->aq.asq_last_status);
5454                 return;
5455         }
5456         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5457         ctxt.info.valid_sections =
5458                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5459         ctxt.info.switch_id |=
5460                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5461
5462         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5463         if (ret)
5464                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5465                             hw->aq.asq_last_status);
5466 }
5467
5468 /* Setup a VSI */
5469 struct i40e_vsi *
5470 i40e_vsi_setup(struct i40e_pf *pf,
5471                enum i40e_vsi_type type,
5472                struct i40e_vsi *uplink_vsi,
5473                uint16_t user_param)
5474 {
5475         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5476         struct i40e_vsi *vsi;
5477         struct i40e_mac_filter_info filter;
5478         int ret;
5479         struct i40e_vsi_context ctxt;
5480         struct ether_addr broadcast =
5481                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5482
5483         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5484             uplink_vsi == NULL) {
5485                 PMD_DRV_LOG(ERR,
5486                         "VSI setup failed, VSI link shouldn't be NULL");
5487                 return NULL;
5488         }
5489
5490         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5491                 PMD_DRV_LOG(ERR,
5492                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5493                 return NULL;
5494         }
5495
5496         /* two situations
5497          * 1.type is not MAIN and uplink vsi is not NULL
5498          * If uplink vsi didn't setup VEB, create one first under veb field
5499          * 2.type is SRIOV and the uplink is NULL
5500          * If floating VEB is NULL, create one veb under floating veb field
5501          */
5502
5503         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5504             uplink_vsi->veb == NULL) {
5505                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5506
5507                 if (uplink_vsi->veb == NULL) {
5508                         PMD_DRV_LOG(ERR, "VEB setup failed");
5509                         return NULL;
5510                 }
5511                 /* set ALLOWLOOPBACk on pf, when veb is created */
5512                 i40e_enable_pf_lb(pf);
5513         }
5514
5515         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5516             pf->main_vsi->floating_veb == NULL) {
5517                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5518
5519                 if (pf->main_vsi->floating_veb == NULL) {
5520                         PMD_DRV_LOG(ERR, "VEB setup failed");
5521                         return NULL;
5522                 }
5523         }
5524
5525         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5526         if (!vsi) {
5527                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5528                 return NULL;
5529         }
5530         TAILQ_INIT(&vsi->mac_list);
5531         vsi->type = type;
5532         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5533         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5534         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5535         vsi->user_param = user_param;
5536         vsi->vlan_anti_spoof_on = 0;
5537         vsi->vlan_filter_on = 0;
5538         /* Allocate queues */
5539         switch (vsi->type) {
5540         case I40E_VSI_MAIN  :
5541                 vsi->nb_qps = pf->lan_nb_qps;
5542                 break;
5543         case I40E_VSI_SRIOV :
5544                 vsi->nb_qps = pf->vf_nb_qps;
5545                 break;
5546         case I40E_VSI_VMDQ2:
5547                 vsi->nb_qps = pf->vmdq_nb_qps;
5548                 break;
5549         case I40E_VSI_FDIR:
5550                 vsi->nb_qps = pf->fdir_nb_qps;
5551                 break;
5552         default:
5553                 goto fail_mem;
5554         }
5555         /*
5556          * The filter status descriptor is reported in rx queue 0,
5557          * while the tx queue for fdir filter programming has no
5558          * such constraints, can be non-zero queues.
5559          * To simplify it, choose FDIR vsi use queue 0 pair.
5560          * To make sure it will use queue 0 pair, queue allocation
5561          * need be done before this function is called
5562          */
5563         if (type != I40E_VSI_FDIR) {
5564                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5565                         if (ret < 0) {
5566                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5567                                                 vsi->seid, ret);
5568                                 goto fail_mem;
5569                         }
5570                         vsi->base_queue = ret;
5571         } else
5572                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5573
5574         /* VF has MSIX interrupt in VF range, don't allocate here */
5575         if (type == I40E_VSI_MAIN) {
5576                 if (pf->support_multi_driver) {
5577                         /* If support multi-driver, need to use INT0 instead of
5578                          * allocating from msix pool. The Msix pool is init from
5579                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5580                          * to 1 without calling i40e_res_pool_alloc.
5581                          */
5582                         vsi->msix_intr = 0;
5583                         vsi->nb_msix = 1;
5584                 } else {
5585                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5586                                                   RTE_MIN(vsi->nb_qps,
5587                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5588                         if (ret < 0) {
5589                                 PMD_DRV_LOG(ERR,
5590                                             "VSI MAIN %d get heap failed %d",
5591                                             vsi->seid, ret);
5592                                 goto fail_queue_alloc;
5593                         }
5594                         vsi->msix_intr = ret;
5595                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5596                                                RTE_MAX_RXTX_INTR_VEC_ID);
5597                 }
5598         } else if (type != I40E_VSI_SRIOV) {
5599                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5600                 if (ret < 0) {
5601                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5602                         goto fail_queue_alloc;
5603                 }
5604                 vsi->msix_intr = ret;
5605                 vsi->nb_msix = 1;
5606         } else {
5607                 vsi->msix_intr = 0;
5608                 vsi->nb_msix = 0;
5609         }
5610
5611         /* Add VSI */
5612         if (type == I40E_VSI_MAIN) {
5613                 /* For main VSI, no need to add since it's default one */
5614                 vsi->uplink_seid = pf->mac_seid;
5615                 vsi->seid = pf->main_vsi_seid;
5616                 /* Bind queues with specific MSIX interrupt */
5617                 /**
5618                  * Needs 2 interrupt at least, one for misc cause which will
5619                  * enabled from OS side, Another for queues binding the
5620                  * interrupt from device side only.
5621                  */
5622
5623                 /* Get default VSI parameters from hardware */
5624                 memset(&ctxt, 0, sizeof(ctxt));
5625                 ctxt.seid = vsi->seid;
5626                 ctxt.pf_num = hw->pf_id;
5627                 ctxt.uplink_seid = vsi->uplink_seid;
5628                 ctxt.vf_num = 0;
5629                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5630                 if (ret != I40E_SUCCESS) {
5631                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5632                         goto fail_msix_alloc;
5633                 }
5634                 rte_memcpy(&vsi->info, &ctxt.info,
5635                         sizeof(struct i40e_aqc_vsi_properties_data));
5636                 vsi->vsi_id = ctxt.vsi_number;
5637                 vsi->info.valid_sections = 0;
5638
5639                 /* Configure tc, enabled TC0 only */
5640                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5641                         I40E_SUCCESS) {
5642                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5643                         goto fail_msix_alloc;
5644                 }
5645
5646                 /* TC, queue mapping */
5647                 memset(&ctxt, 0, sizeof(ctxt));
5648                 vsi->info.valid_sections |=
5649                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5650                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5651                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5652                 rte_memcpy(&ctxt.info, &vsi->info,
5653                         sizeof(struct i40e_aqc_vsi_properties_data));
5654                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5655                                                 I40E_DEFAULT_TCMAP);
5656                 if (ret != I40E_SUCCESS) {
5657                         PMD_DRV_LOG(ERR,
5658                                 "Failed to configure TC queue mapping");
5659                         goto fail_msix_alloc;
5660                 }
5661                 ctxt.seid = vsi->seid;
5662                 ctxt.pf_num = hw->pf_id;
5663                 ctxt.uplink_seid = vsi->uplink_seid;
5664                 ctxt.vf_num = 0;
5665
5666                 /* Update VSI parameters */
5667                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5668                 if (ret != I40E_SUCCESS) {
5669                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5670                         goto fail_msix_alloc;
5671                 }
5672
5673                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5674                                                 sizeof(vsi->info.tc_mapping));
5675                 rte_memcpy(&vsi->info.queue_mapping,
5676                                 &ctxt.info.queue_mapping,
5677                         sizeof(vsi->info.queue_mapping));
5678                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5679                 vsi->info.valid_sections = 0;
5680
5681                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5682                                 ETH_ADDR_LEN);
5683
5684                 /**
5685                  * Updating default filter settings are necessary to prevent
5686                  * reception of tagged packets.
5687                  * Some old firmware configurations load a default macvlan
5688                  * filter which accepts both tagged and untagged packets.
5689                  * The updating is to use a normal filter instead if needed.
5690                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5691                  * The firmware with correct configurations load the default
5692                  * macvlan filter which is expected and cannot be removed.
5693                  */
5694                 i40e_update_default_filter_setting(vsi);
5695                 i40e_config_qinq(hw, vsi);
5696         } else if (type == I40E_VSI_SRIOV) {
5697                 memset(&ctxt, 0, sizeof(ctxt));
5698                 /**
5699                  * For other VSI, the uplink_seid equals to uplink VSI's
5700                  * uplink_seid since they share same VEB
5701                  */
5702                 if (uplink_vsi == NULL)
5703                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5704                 else
5705                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5706                 ctxt.pf_num = hw->pf_id;
5707                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5708                 ctxt.uplink_seid = vsi->uplink_seid;
5709                 ctxt.connection_type = 0x1;
5710                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5711
5712                 /* Use the VEB configuration if FW >= v5.0 */
5713                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5714                         /* Configure switch ID */
5715                         ctxt.info.valid_sections |=
5716                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5717                         ctxt.info.switch_id =
5718                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5719                 }
5720
5721                 /* Configure port/vlan */
5722                 ctxt.info.valid_sections |=
5723                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5724                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5725                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5726                                                 hw->func_caps.enabled_tcmap);
5727                 if (ret != I40E_SUCCESS) {
5728                         PMD_DRV_LOG(ERR,
5729                                 "Failed to configure TC queue mapping");
5730                         goto fail_msix_alloc;
5731                 }
5732
5733                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5734                 ctxt.info.valid_sections |=
5735                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5736                 /**
5737                  * Since VSI is not created yet, only configure parameter,
5738                  * will add vsi below.
5739                  */
5740
5741                 i40e_config_qinq(hw, vsi);
5742         } else if (type == I40E_VSI_VMDQ2) {
5743                 memset(&ctxt, 0, sizeof(ctxt));
5744                 /*
5745                  * For other VSI, the uplink_seid equals to uplink VSI's
5746                  * uplink_seid since they share same VEB
5747                  */
5748                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5749                 ctxt.pf_num = hw->pf_id;
5750                 ctxt.vf_num = 0;
5751                 ctxt.uplink_seid = vsi->uplink_seid;
5752                 ctxt.connection_type = 0x1;
5753                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5754
5755                 ctxt.info.valid_sections |=
5756                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5757                 /* user_param carries flag to enable loop back */
5758                 if (user_param) {
5759                         ctxt.info.switch_id =
5760                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5761                         ctxt.info.switch_id |=
5762                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5763                 }
5764
5765                 /* Configure port/vlan */
5766                 ctxt.info.valid_sections |=
5767                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5768                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5769                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5770                                                 I40E_DEFAULT_TCMAP);
5771                 if (ret != I40E_SUCCESS) {
5772                         PMD_DRV_LOG(ERR,
5773                                 "Failed to configure TC queue mapping");
5774                         goto fail_msix_alloc;
5775                 }
5776                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5777                 ctxt.info.valid_sections |=
5778                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5779         } else if (type == I40E_VSI_FDIR) {
5780                 memset(&ctxt, 0, sizeof(ctxt));
5781                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5782                 ctxt.pf_num = hw->pf_id;
5783                 ctxt.vf_num = 0;
5784                 ctxt.uplink_seid = vsi->uplink_seid;
5785                 ctxt.connection_type = 0x1;     /* regular data port */
5786                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5787                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5788                                                 I40E_DEFAULT_TCMAP);
5789                 if (ret != I40E_SUCCESS) {
5790                         PMD_DRV_LOG(ERR,
5791                                 "Failed to configure TC queue mapping.");
5792                         goto fail_msix_alloc;
5793                 }
5794                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5795                 ctxt.info.valid_sections |=
5796                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5797         } else {
5798                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5799                 goto fail_msix_alloc;
5800         }
5801
5802         if (vsi->type != I40E_VSI_MAIN) {
5803                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5804                 if (ret != I40E_SUCCESS) {
5805                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5806                                     hw->aq.asq_last_status);
5807                         goto fail_msix_alloc;
5808                 }
5809                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5810                 vsi->info.valid_sections = 0;
5811                 vsi->seid = ctxt.seid;
5812                 vsi->vsi_id = ctxt.vsi_number;
5813                 vsi->sib_vsi_list.vsi = vsi;
5814                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5815                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5816                                           &vsi->sib_vsi_list, list);
5817                 } else {
5818                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5819                                           &vsi->sib_vsi_list, list);
5820                 }
5821         }
5822
5823         /* MAC/VLAN configuration */
5824         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5825         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5826
5827         ret = i40e_vsi_add_mac(vsi, &filter);
5828         if (ret != I40E_SUCCESS) {
5829                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5830                 goto fail_msix_alloc;
5831         }
5832
5833         /* Get VSI BW information */
5834         i40e_vsi_get_bw_config(vsi);
5835         return vsi;
5836 fail_msix_alloc:
5837         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5838 fail_queue_alloc:
5839         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5840 fail_mem:
5841         rte_free(vsi);
5842         return NULL;
5843 }
5844
5845 /* Configure vlan filter on or off */
5846 int
5847 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5848 {
5849         int i, num;
5850         struct i40e_mac_filter *f;
5851         void *temp;
5852         struct i40e_mac_filter_info *mac_filter;
5853         enum rte_mac_filter_type desired_filter;
5854         int ret = I40E_SUCCESS;
5855
5856         if (on) {
5857                 /* Filter to match MAC and VLAN */
5858                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5859         } else {
5860                 /* Filter to match only MAC */
5861                 desired_filter = RTE_MAC_PERFECT_MATCH;
5862         }
5863
5864         num = vsi->mac_num;
5865
5866         mac_filter = rte_zmalloc("mac_filter_info_data",
5867                                  num * sizeof(*mac_filter), 0);
5868         if (mac_filter == NULL) {
5869                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5870                 return I40E_ERR_NO_MEMORY;
5871         }
5872
5873         i = 0;
5874
5875         /* Remove all existing mac */
5876         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5877                 mac_filter[i] = f->mac_info;
5878                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5879                 if (ret) {
5880                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5881                                     on ? "enable" : "disable");
5882                         goto DONE;
5883                 }
5884                 i++;
5885         }
5886
5887         /* Override with new filter */
5888         for (i = 0; i < num; i++) {
5889                 mac_filter[i].filter_type = desired_filter;
5890                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5891                 if (ret) {
5892                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5893                                     on ? "enable" : "disable");
5894                         goto DONE;
5895                 }
5896         }
5897
5898 DONE:
5899         rte_free(mac_filter);
5900         return ret;
5901 }
5902
5903 /* Configure vlan stripping on or off */
5904 int
5905 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5906 {
5907         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5908         struct i40e_vsi_context ctxt;
5909         uint8_t vlan_flags;
5910         int ret = I40E_SUCCESS;
5911
5912         /* Check if it has been already on or off */
5913         if (vsi->info.valid_sections &
5914                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5915                 if (on) {
5916                         if ((vsi->info.port_vlan_flags &
5917                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5918                                 return 0; /* already on */
5919                 } else {
5920                         if ((vsi->info.port_vlan_flags &
5921                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5922                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5923                                 return 0; /* already off */
5924                 }
5925         }
5926
5927         if (on)
5928                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5929         else
5930                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5931         vsi->info.valid_sections =
5932                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5933         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5934         vsi->info.port_vlan_flags |= vlan_flags;
5935         ctxt.seid = vsi->seid;
5936         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5937         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5938         if (ret)
5939                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5940                             on ? "enable" : "disable");
5941
5942         return ret;
5943 }
5944
5945 static int
5946 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5947 {
5948         struct rte_eth_dev_data *data = dev->data;
5949         int ret;
5950         int mask = 0;
5951
5952         /* Apply vlan offload setting */
5953         mask = ETH_VLAN_STRIP_MASK |
5954                ETH_VLAN_FILTER_MASK |
5955                ETH_VLAN_EXTEND_MASK;
5956         ret = i40e_vlan_offload_set(dev, mask);
5957         if (ret) {
5958                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5959                 return ret;
5960         }
5961
5962         /* Apply pvid setting */
5963         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5964                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5965         if (ret)
5966                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5967
5968         return ret;
5969 }
5970
5971 static int
5972 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5973 {
5974         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5975
5976         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5977 }
5978
5979 static int
5980 i40e_update_flow_control(struct i40e_hw *hw)
5981 {
5982 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5983         struct i40e_link_status link_status;
5984         uint32_t rxfc = 0, txfc = 0, reg;
5985         uint8_t an_info;
5986         int ret;
5987
5988         memset(&link_status, 0, sizeof(link_status));
5989         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5990         if (ret != I40E_SUCCESS) {
5991                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5992                 goto write_reg; /* Disable flow control */
5993         }
5994
5995         an_info = hw->phy.link_info.an_info;
5996         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5997                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5998                 ret = I40E_ERR_NOT_READY;
5999                 goto write_reg; /* Disable flow control */
6000         }
6001         /**
6002          * If link auto negotiation is enabled, flow control needs to
6003          * be configured according to it
6004          */
6005         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6006         case I40E_LINK_PAUSE_RXTX:
6007                 rxfc = 1;
6008                 txfc = 1;
6009                 hw->fc.current_mode = I40E_FC_FULL;
6010                 break;
6011         case I40E_AQ_LINK_PAUSE_RX:
6012                 rxfc = 1;
6013                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6014                 break;
6015         case I40E_AQ_LINK_PAUSE_TX:
6016                 txfc = 1;
6017                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6018                 break;
6019         default:
6020                 hw->fc.current_mode = I40E_FC_NONE;
6021                 break;
6022         }
6023
6024 write_reg:
6025         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6026                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6027         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6028         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6029         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6030         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6031
6032         return ret;
6033 }
6034
6035 /* PF setup */
6036 static int
6037 i40e_pf_setup(struct i40e_pf *pf)
6038 {
6039         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6040         struct i40e_filter_control_settings settings;
6041         struct i40e_vsi *vsi;
6042         int ret;
6043
6044         /* Clear all stats counters */
6045         pf->offset_loaded = FALSE;
6046         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6047         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6048         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6049         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6050
6051         ret = i40e_pf_get_switch_config(pf);
6052         if (ret != I40E_SUCCESS) {
6053                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6054                 return ret;
6055         }
6056
6057         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6058         if (ret)
6059                 PMD_INIT_LOG(WARNING,
6060                         "failed to allocate switch domain for device %d", ret);
6061
6062         if (pf->flags & I40E_FLAG_FDIR) {
6063                 /* make queue allocated first, let FDIR use queue pair 0*/
6064                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6065                 if (ret != I40E_FDIR_QUEUE_ID) {
6066                         PMD_DRV_LOG(ERR,
6067                                 "queue allocation fails for FDIR: ret =%d",
6068                                 ret);
6069                         pf->flags &= ~I40E_FLAG_FDIR;
6070                 }
6071         }
6072         /*  main VSI setup */
6073         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6074         if (!vsi) {
6075                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6076                 return I40E_ERR_NOT_READY;
6077         }
6078         pf->main_vsi = vsi;
6079
6080         /* Configure filter control */
6081         memset(&settings, 0, sizeof(settings));
6082         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6083                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6084         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6085                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6086         else {
6087                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6088                         hw->func_caps.rss_table_size);
6089                 return I40E_ERR_PARAM;
6090         }
6091         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6092                 hw->func_caps.rss_table_size);
6093         pf->hash_lut_size = hw->func_caps.rss_table_size;
6094
6095         /* Enable ethtype and macvlan filters */
6096         settings.enable_ethtype = TRUE;
6097         settings.enable_macvlan = TRUE;
6098         ret = i40e_set_filter_control(hw, &settings);
6099         if (ret)
6100                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6101                                                                 ret);
6102
6103         /* Update flow control according to the auto negotiation */
6104         i40e_update_flow_control(hw);
6105
6106         return I40E_SUCCESS;
6107 }
6108
6109 int
6110 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6111 {
6112         uint32_t reg;
6113         uint16_t j;
6114
6115         /**
6116          * Set or clear TX Queue Disable flags,
6117          * which is required by hardware.
6118          */
6119         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6120         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6121
6122         /* Wait until the request is finished */
6123         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6124                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6125                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6126                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6127                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6128                                                         & 0x1))) {
6129                         break;
6130                 }
6131         }
6132         if (on) {
6133                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6134                         return I40E_SUCCESS; /* already on, skip next steps */
6135
6136                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6137                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6138         } else {
6139                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6140                         return I40E_SUCCESS; /* already off, skip next steps */
6141                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6142         }
6143         /* Write the register */
6144         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6145         /* Check the result */
6146         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6147                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6148                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6149                 if (on) {
6150                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6151                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6152                                 break;
6153                 } else {
6154                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6155                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6156                                 break;
6157                 }
6158         }
6159         /* Check if it is timeout */
6160         if (j >= I40E_CHK_Q_ENA_COUNT) {
6161                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6162                             (on ? "enable" : "disable"), q_idx);
6163                 return I40E_ERR_TIMEOUT;
6164         }
6165
6166         return I40E_SUCCESS;
6167 }
6168
6169 /* Swith on or off the tx queues */
6170 static int
6171 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6172 {
6173         struct rte_eth_dev_data *dev_data = pf->dev_data;
6174         struct i40e_tx_queue *txq;
6175         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6176         uint16_t i;
6177         int ret;
6178
6179         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6180                 txq = dev_data->tx_queues[i];
6181                 /* Don't operate the queue if not configured or
6182                  * if starting only per queue */
6183                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6184                         continue;
6185                 if (on)
6186                         ret = i40e_dev_tx_queue_start(dev, i);
6187                 else
6188                         ret = i40e_dev_tx_queue_stop(dev, i);
6189                 if ( ret != I40E_SUCCESS)
6190                         return ret;
6191         }
6192
6193         return I40E_SUCCESS;
6194 }
6195
6196 int
6197 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6198 {
6199         uint32_t reg;
6200         uint16_t j;
6201
6202         /* Wait until the request is finished */
6203         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6204                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6205                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6206                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6207                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6208                         break;
6209         }
6210
6211         if (on) {
6212                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6213                         return I40E_SUCCESS; /* Already on, skip next steps */
6214                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6215         } else {
6216                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6217                         return I40E_SUCCESS; /* Already off, skip next steps */
6218                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6219         }
6220
6221         /* Write the register */
6222         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6223         /* Check the result */
6224         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6225                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6226                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6227                 if (on) {
6228                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6229                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6230                                 break;
6231                 } else {
6232                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6233                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6234                                 break;
6235                 }
6236         }
6237
6238         /* Check if it is timeout */
6239         if (j >= I40E_CHK_Q_ENA_COUNT) {
6240                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6241                             (on ? "enable" : "disable"), q_idx);
6242                 return I40E_ERR_TIMEOUT;
6243         }
6244
6245         return I40E_SUCCESS;
6246 }
6247 /* Switch on or off the rx queues */
6248 static int
6249 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6250 {
6251         struct rte_eth_dev_data *dev_data = pf->dev_data;
6252         struct i40e_rx_queue *rxq;
6253         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6254         uint16_t i;
6255         int ret;
6256
6257         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6258                 rxq = dev_data->rx_queues[i];
6259                 /* Don't operate the queue if not configured or
6260                  * if starting only per queue */
6261                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6262                         continue;
6263                 if (on)
6264                         ret = i40e_dev_rx_queue_start(dev, i);
6265                 else
6266                         ret = i40e_dev_rx_queue_stop(dev, i);
6267                 if (ret != I40E_SUCCESS)
6268                         return ret;
6269         }
6270
6271         return I40E_SUCCESS;
6272 }
6273
6274 /* Switch on or off all the rx/tx queues */
6275 int
6276 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6277 {
6278         int ret;
6279
6280         if (on) {
6281                 /* enable rx queues before enabling tx queues */
6282                 ret = i40e_dev_switch_rx_queues(pf, on);
6283                 if (ret) {
6284                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6285                         return ret;
6286                 }
6287                 ret = i40e_dev_switch_tx_queues(pf, on);
6288         } else {
6289                 /* Stop tx queues before stopping rx queues */
6290                 ret = i40e_dev_switch_tx_queues(pf, on);
6291                 if (ret) {
6292                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6293                         return ret;
6294                 }
6295                 ret = i40e_dev_switch_rx_queues(pf, on);
6296         }
6297
6298         return ret;
6299 }
6300
6301 /* Initialize VSI for TX */
6302 static int
6303 i40e_dev_tx_init(struct i40e_pf *pf)
6304 {
6305         struct rte_eth_dev_data *data = pf->dev_data;
6306         uint16_t i;
6307         uint32_t ret = I40E_SUCCESS;
6308         struct i40e_tx_queue *txq;
6309
6310         for (i = 0; i < data->nb_tx_queues; i++) {
6311                 txq = data->tx_queues[i];
6312                 if (!txq || !txq->q_set)
6313                         continue;
6314                 ret = i40e_tx_queue_init(txq);
6315                 if (ret != I40E_SUCCESS)
6316                         break;
6317         }
6318         if (ret == I40E_SUCCESS)
6319                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6320                                      ->eth_dev);
6321
6322         return ret;
6323 }
6324
6325 /* Initialize VSI for RX */
6326 static int
6327 i40e_dev_rx_init(struct i40e_pf *pf)
6328 {
6329         struct rte_eth_dev_data *data = pf->dev_data;
6330         int ret = I40E_SUCCESS;
6331         uint16_t i;
6332         struct i40e_rx_queue *rxq;
6333
6334         i40e_pf_config_mq_rx(pf);
6335         for (i = 0; i < data->nb_rx_queues; i++) {
6336                 rxq = data->rx_queues[i];
6337                 if (!rxq || !rxq->q_set)
6338                         continue;
6339
6340                 ret = i40e_rx_queue_init(rxq);
6341                 if (ret != I40E_SUCCESS) {
6342                         PMD_DRV_LOG(ERR,
6343                                 "Failed to do RX queue initialization");
6344                         break;
6345                 }
6346         }
6347         if (ret == I40E_SUCCESS)
6348                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6349                                      ->eth_dev);
6350
6351         return ret;
6352 }
6353
6354 static int
6355 i40e_dev_rxtx_init(struct i40e_pf *pf)
6356 {
6357         int err;
6358
6359         err = i40e_dev_tx_init(pf);
6360         if (err) {
6361                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6362                 return err;
6363         }
6364         err = i40e_dev_rx_init(pf);
6365         if (err) {
6366                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6367                 return err;
6368         }
6369
6370         return err;
6371 }
6372
6373 static int
6374 i40e_vmdq_setup(struct rte_eth_dev *dev)
6375 {
6376         struct rte_eth_conf *conf = &dev->data->dev_conf;
6377         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6378         int i, err, conf_vsis, j, loop;
6379         struct i40e_vsi *vsi;
6380         struct i40e_vmdq_info *vmdq_info;
6381         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6382         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6383
6384         /*
6385          * Disable interrupt to avoid message from VF. Furthermore, it will
6386          * avoid race condition in VSI creation/destroy.
6387          */
6388         i40e_pf_disable_irq0(hw);
6389
6390         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6391                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6392                 return -ENOTSUP;
6393         }
6394
6395         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6396         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6397                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6398                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6399                         pf->max_nb_vmdq_vsi);
6400                 return -ENOTSUP;
6401         }
6402
6403         if (pf->vmdq != NULL) {
6404                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6405                 return 0;
6406         }
6407
6408         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6409                                 sizeof(*vmdq_info) * conf_vsis, 0);
6410
6411         if (pf->vmdq == NULL) {
6412                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6413                 return -ENOMEM;
6414         }
6415
6416         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6417
6418         /* Create VMDQ VSI */
6419         for (i = 0; i < conf_vsis; i++) {
6420                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6421                                 vmdq_conf->enable_loop_back);
6422                 if (vsi == NULL) {
6423                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6424                         err = -1;
6425                         goto err_vsi_setup;
6426                 }
6427                 vmdq_info = &pf->vmdq[i];
6428                 vmdq_info->pf = pf;
6429                 vmdq_info->vsi = vsi;
6430         }
6431         pf->nb_cfg_vmdq_vsi = conf_vsis;
6432
6433         /* Configure Vlan */
6434         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6435         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6436                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6437                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6438                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6439                                         vmdq_conf->pool_map[i].vlan_id, j);
6440
6441                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6442                                                 vmdq_conf->pool_map[i].vlan_id);
6443                                 if (err) {
6444                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6445                                         err = -1;
6446                                         goto err_vsi_setup;
6447                                 }
6448                         }
6449                 }
6450         }
6451
6452         i40e_pf_enable_irq0(hw);
6453
6454         return 0;
6455
6456 err_vsi_setup:
6457         for (i = 0; i < conf_vsis; i++)
6458                 if (pf->vmdq[i].vsi == NULL)
6459                         break;
6460                 else
6461                         i40e_vsi_release(pf->vmdq[i].vsi);
6462
6463         rte_free(pf->vmdq);
6464         pf->vmdq = NULL;
6465         i40e_pf_enable_irq0(hw);
6466         return err;
6467 }
6468
6469 static void
6470 i40e_stat_update_32(struct i40e_hw *hw,
6471                    uint32_t reg,
6472                    bool offset_loaded,
6473                    uint64_t *offset,
6474                    uint64_t *stat)
6475 {
6476         uint64_t new_data;
6477
6478         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6479         if (!offset_loaded)
6480                 *offset = new_data;
6481
6482         if (new_data >= *offset)
6483                 *stat = (uint64_t)(new_data - *offset);
6484         else
6485                 *stat = (uint64_t)((new_data +
6486                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6487 }
6488
6489 static void
6490 i40e_stat_update_48(struct i40e_hw *hw,
6491                    uint32_t hireg,
6492                    uint32_t loreg,
6493                    bool offset_loaded,
6494                    uint64_t *offset,
6495                    uint64_t *stat)
6496 {
6497         uint64_t new_data;
6498
6499         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6500         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6501                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6502
6503         if (!offset_loaded)
6504                 *offset = new_data;
6505
6506         if (new_data >= *offset)
6507                 *stat = new_data - *offset;
6508         else
6509                 *stat = (uint64_t)((new_data +
6510                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6511
6512         *stat &= I40E_48_BIT_MASK;
6513 }
6514
6515 /* Disable IRQ0 */
6516 void
6517 i40e_pf_disable_irq0(struct i40e_hw *hw)
6518 {
6519         /* Disable all interrupt types */
6520         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6521                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6522         I40E_WRITE_FLUSH(hw);
6523 }
6524
6525 /* Enable IRQ0 */
6526 void
6527 i40e_pf_enable_irq0(struct i40e_hw *hw)
6528 {
6529         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6530                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6531                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6532                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6533         I40E_WRITE_FLUSH(hw);
6534 }
6535
6536 static void
6537 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6538 {
6539         /* read pending request and disable first */
6540         i40e_pf_disable_irq0(hw);
6541         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6542         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6543                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6544
6545         if (no_queue)
6546                 /* Link no queues with irq0 */
6547                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6548                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6549 }
6550
6551 static void
6552 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6553 {
6554         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6555         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6556         int i;
6557         uint16_t abs_vf_id;
6558         uint32_t index, offset, val;
6559
6560         if (!pf->vfs)
6561                 return;
6562         /**
6563          * Try to find which VF trigger a reset, use absolute VF id to access
6564          * since the reg is global register.
6565          */
6566         for (i = 0; i < pf->vf_num; i++) {
6567                 abs_vf_id = hw->func_caps.vf_base_id + i;
6568                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6569                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6570                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6571                 /* VFR event occurred */
6572                 if (val & (0x1 << offset)) {
6573                         int ret;
6574
6575                         /* Clear the event first */
6576                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6577                                                         (0x1 << offset));
6578                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6579                         /**
6580                          * Only notify a VF reset event occurred,
6581                          * don't trigger another SW reset
6582                          */
6583                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6584                         if (ret != I40E_SUCCESS)
6585                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6586                 }
6587         }
6588 }
6589
6590 static void
6591 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6592 {
6593         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6594         int i;
6595
6596         for (i = 0; i < pf->vf_num; i++)
6597                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6598 }
6599
6600 static void
6601 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6602 {
6603         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6604         struct i40e_arq_event_info info;
6605         uint16_t pending, opcode;
6606         int ret;
6607
6608         info.buf_len = I40E_AQ_BUF_SZ;
6609         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6610         if (!info.msg_buf) {
6611                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6612                 return;
6613         }
6614
6615         pending = 1;
6616         while (pending) {
6617                 ret = i40e_clean_arq_element(hw, &info, &pending);
6618
6619                 if (ret != I40E_SUCCESS) {
6620                         PMD_DRV_LOG(INFO,
6621                                 "Failed to read msg from AdminQ, aq_err: %u",
6622                                 hw->aq.asq_last_status);
6623                         break;
6624                 }
6625                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6626
6627                 switch (opcode) {
6628                 case i40e_aqc_opc_send_msg_to_pf:
6629                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6630                         i40e_pf_host_handle_vf_msg(dev,
6631                                         rte_le_to_cpu_16(info.desc.retval),
6632                                         rte_le_to_cpu_32(info.desc.cookie_high),
6633                                         rte_le_to_cpu_32(info.desc.cookie_low),
6634                                         info.msg_buf,
6635                                         info.msg_len);
6636                         break;
6637                 case i40e_aqc_opc_get_link_status:
6638                         ret = i40e_dev_link_update(dev, 0);
6639                         if (!ret)
6640                                 _rte_eth_dev_callback_process(dev,
6641                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6642                         break;
6643                 default:
6644                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6645                                     opcode);
6646                         break;
6647                 }
6648         }
6649         rte_free(info.msg_buf);
6650 }
6651
6652 /**
6653  * Interrupt handler triggered by NIC  for handling
6654  * specific interrupt.
6655  *
6656  * @param handle
6657  *  Pointer to interrupt handle.
6658  * @param param
6659  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6660  *
6661  * @return
6662  *  void
6663  */
6664 static void
6665 i40e_dev_interrupt_handler(void *param)
6666 {
6667         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6668         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6669         uint32_t icr0;
6670
6671         /* Disable interrupt */
6672         i40e_pf_disable_irq0(hw);
6673
6674         /* read out interrupt causes */
6675         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6676
6677         /* No interrupt event indicated */
6678         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6679                 PMD_DRV_LOG(INFO, "No interrupt event");
6680                 goto done;
6681         }
6682         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6683                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6684         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6685                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6686         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6687                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6688         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6689                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6690         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6691                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6692         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6693                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6694         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6695                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6696
6697         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6698                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6699                 i40e_dev_handle_vfr_event(dev);
6700         }
6701         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6702                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6703                 i40e_dev_handle_aq_msg(dev);
6704         }
6705
6706 done:
6707         /* Enable interrupt */
6708         i40e_pf_enable_irq0(hw);
6709 }
6710
6711 static void
6712 i40e_dev_alarm_handler(void *param)
6713 {
6714         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6715         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6716         uint32_t icr0;
6717
6718         /* Disable interrupt */
6719         i40e_pf_disable_irq0(hw);
6720
6721         /* read out interrupt causes */
6722         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6723
6724         /* No interrupt event indicated */
6725         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6726                 goto done;
6727         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6728                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6729         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6730                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6731         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6732                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6733         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6734                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6735         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6736                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6737         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6738                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6739         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6740                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6741
6742         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6743                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6744                 i40e_dev_handle_vfr_event(dev);
6745         }
6746         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6747                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6748                 i40e_dev_handle_aq_msg(dev);
6749         }
6750
6751 done:
6752         /* Enable interrupt */
6753         i40e_pf_enable_irq0(hw);
6754         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6755                           i40e_dev_alarm_handler, dev);
6756 }
6757
6758 int
6759 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6760                          struct i40e_macvlan_filter *filter,
6761                          int total)
6762 {
6763         int ele_num, ele_buff_size;
6764         int num, actual_num, i;
6765         uint16_t flags;
6766         int ret = I40E_SUCCESS;
6767         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6768         struct i40e_aqc_add_macvlan_element_data *req_list;
6769
6770         if (filter == NULL  || total == 0)
6771                 return I40E_ERR_PARAM;
6772         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6773         ele_buff_size = hw->aq.asq_buf_size;
6774
6775         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6776         if (req_list == NULL) {
6777                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6778                 return I40E_ERR_NO_MEMORY;
6779         }
6780
6781         num = 0;
6782         do {
6783                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6784                 memset(req_list, 0, ele_buff_size);
6785
6786                 for (i = 0; i < actual_num; i++) {
6787                         rte_memcpy(req_list[i].mac_addr,
6788                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6789                         req_list[i].vlan_tag =
6790                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6791
6792                         switch (filter[num + i].filter_type) {
6793                         case RTE_MAC_PERFECT_MATCH:
6794                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6795                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6796                                 break;
6797                         case RTE_MACVLAN_PERFECT_MATCH:
6798                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6799                                 break;
6800                         case RTE_MAC_HASH_MATCH:
6801                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6802                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6803                                 break;
6804                         case RTE_MACVLAN_HASH_MATCH:
6805                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6806                                 break;
6807                         default:
6808                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6809                                 ret = I40E_ERR_PARAM;
6810                                 goto DONE;
6811                         }
6812
6813                         req_list[i].queue_number = 0;
6814
6815                         req_list[i].flags = rte_cpu_to_le_16(flags);
6816                 }
6817
6818                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6819                                                 actual_num, NULL);
6820                 if (ret != I40E_SUCCESS) {
6821                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6822                         goto DONE;
6823                 }
6824                 num += actual_num;
6825         } while (num < total);
6826
6827 DONE:
6828         rte_free(req_list);
6829         return ret;
6830 }
6831
6832 int
6833 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6834                             struct i40e_macvlan_filter *filter,
6835                             int total)
6836 {
6837         int ele_num, ele_buff_size;
6838         int num, actual_num, i;
6839         uint16_t flags;
6840         int ret = I40E_SUCCESS;
6841         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6842         struct i40e_aqc_remove_macvlan_element_data *req_list;
6843
6844         if (filter == NULL  || total == 0)
6845                 return I40E_ERR_PARAM;
6846
6847         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6848         ele_buff_size = hw->aq.asq_buf_size;
6849
6850         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6851         if (req_list == NULL) {
6852                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6853                 return I40E_ERR_NO_MEMORY;
6854         }
6855
6856         num = 0;
6857         do {
6858                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6859                 memset(req_list, 0, ele_buff_size);
6860
6861                 for (i = 0; i < actual_num; i++) {
6862                         rte_memcpy(req_list[i].mac_addr,
6863                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6864                         req_list[i].vlan_tag =
6865                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6866
6867                         switch (filter[num + i].filter_type) {
6868                         case RTE_MAC_PERFECT_MATCH:
6869                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6870                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6871                                 break;
6872                         case RTE_MACVLAN_PERFECT_MATCH:
6873                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6874                                 break;
6875                         case RTE_MAC_HASH_MATCH:
6876                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6877                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6878                                 break;
6879                         case RTE_MACVLAN_HASH_MATCH:
6880                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6881                                 break;
6882                         default:
6883                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6884                                 ret = I40E_ERR_PARAM;
6885                                 goto DONE;
6886                         }
6887                         req_list[i].flags = rte_cpu_to_le_16(flags);
6888                 }
6889
6890                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6891                                                 actual_num, NULL);
6892                 if (ret != I40E_SUCCESS) {
6893                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6894                         goto DONE;
6895                 }
6896                 num += actual_num;
6897         } while (num < total);
6898
6899 DONE:
6900         rte_free(req_list);
6901         return ret;
6902 }
6903
6904 /* Find out specific MAC filter */
6905 static struct i40e_mac_filter *
6906 i40e_find_mac_filter(struct i40e_vsi *vsi,
6907                          struct ether_addr *macaddr)
6908 {
6909         struct i40e_mac_filter *f;
6910
6911         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6912                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6913                         return f;
6914         }
6915
6916         return NULL;
6917 }
6918
6919 static bool
6920 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6921                          uint16_t vlan_id)
6922 {
6923         uint32_t vid_idx, vid_bit;
6924
6925         if (vlan_id > ETH_VLAN_ID_MAX)
6926                 return 0;
6927
6928         vid_idx = I40E_VFTA_IDX(vlan_id);
6929         vid_bit = I40E_VFTA_BIT(vlan_id);
6930
6931         if (vsi->vfta[vid_idx] & vid_bit)
6932                 return 1;
6933         else
6934                 return 0;
6935 }
6936
6937 static void
6938 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6939                        uint16_t vlan_id, bool on)
6940 {
6941         uint32_t vid_idx, vid_bit;
6942
6943         vid_idx = I40E_VFTA_IDX(vlan_id);
6944         vid_bit = I40E_VFTA_BIT(vlan_id);
6945
6946         if (on)
6947                 vsi->vfta[vid_idx] |= vid_bit;
6948         else
6949                 vsi->vfta[vid_idx] &= ~vid_bit;
6950 }
6951
6952 void
6953 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6954                      uint16_t vlan_id, bool on)
6955 {
6956         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6957         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6958         int ret;
6959
6960         if (vlan_id > ETH_VLAN_ID_MAX)
6961                 return;
6962
6963         i40e_store_vlan_filter(vsi, vlan_id, on);
6964
6965         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6966                 return;
6967
6968         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6969
6970         if (on) {
6971                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6972                                        &vlan_data, 1, NULL);
6973                 if (ret != I40E_SUCCESS)
6974                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6975         } else {
6976                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6977                                           &vlan_data, 1, NULL);
6978                 if (ret != I40E_SUCCESS)
6979                         PMD_DRV_LOG(ERR,
6980                                     "Failed to remove vlan filter");
6981         }
6982 }
6983
6984 /**
6985  * Find all vlan options for specific mac addr,
6986  * return with actual vlan found.
6987  */
6988 int
6989 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6990                            struct i40e_macvlan_filter *mv_f,
6991                            int num, struct ether_addr *addr)
6992 {
6993         int i;
6994         uint32_t j, k;
6995
6996         /**
6997          * Not to use i40e_find_vlan_filter to decrease the loop time,
6998          * although the code looks complex.
6999           */
7000         if (num < vsi->vlan_num)
7001                 return I40E_ERR_PARAM;
7002
7003         i = 0;
7004         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7005                 if (vsi->vfta[j]) {
7006                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7007                                 if (vsi->vfta[j] & (1 << k)) {
7008                                         if (i > num - 1) {
7009                                                 PMD_DRV_LOG(ERR,
7010                                                         "vlan number doesn't match");
7011                                                 return I40E_ERR_PARAM;
7012                                         }
7013                                         rte_memcpy(&mv_f[i].macaddr,
7014                                                         addr, ETH_ADDR_LEN);
7015                                         mv_f[i].vlan_id =
7016                                                 j * I40E_UINT32_BIT_SIZE + k;
7017                                         i++;
7018                                 }
7019                         }
7020                 }
7021         }
7022         return I40E_SUCCESS;
7023 }
7024
7025 static inline int
7026 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7027                            struct i40e_macvlan_filter *mv_f,
7028                            int num,
7029                            uint16_t vlan)
7030 {
7031         int i = 0;
7032         struct i40e_mac_filter *f;
7033
7034         if (num < vsi->mac_num)
7035                 return I40E_ERR_PARAM;
7036
7037         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7038                 if (i > num - 1) {
7039                         PMD_DRV_LOG(ERR, "buffer number not match");
7040                         return I40E_ERR_PARAM;
7041                 }
7042                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7043                                 ETH_ADDR_LEN);
7044                 mv_f[i].vlan_id = vlan;
7045                 mv_f[i].filter_type = f->mac_info.filter_type;
7046                 i++;
7047         }
7048
7049         return I40E_SUCCESS;
7050 }
7051
7052 static int
7053 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7054 {
7055         int i, j, num;
7056         struct i40e_mac_filter *f;
7057         struct i40e_macvlan_filter *mv_f;
7058         int ret = I40E_SUCCESS;
7059
7060         if (vsi == NULL || vsi->mac_num == 0)
7061                 return I40E_ERR_PARAM;
7062
7063         /* Case that no vlan is set */
7064         if (vsi->vlan_num == 0)
7065                 num = vsi->mac_num;
7066         else
7067                 num = vsi->mac_num * vsi->vlan_num;
7068
7069         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7070         if (mv_f == NULL) {
7071                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7072                 return I40E_ERR_NO_MEMORY;
7073         }
7074
7075         i = 0;
7076         if (vsi->vlan_num == 0) {
7077                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7078                         rte_memcpy(&mv_f[i].macaddr,
7079                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7080                         mv_f[i].filter_type = f->mac_info.filter_type;
7081                         mv_f[i].vlan_id = 0;
7082                         i++;
7083                 }
7084         } else {
7085                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7086                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7087                                         vsi->vlan_num, &f->mac_info.mac_addr);
7088                         if (ret != I40E_SUCCESS)
7089                                 goto DONE;
7090                         for (j = i; j < i + vsi->vlan_num; j++)
7091                                 mv_f[j].filter_type = f->mac_info.filter_type;
7092                         i += vsi->vlan_num;
7093                 }
7094         }
7095
7096         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7097 DONE:
7098         rte_free(mv_f);
7099
7100         return ret;
7101 }
7102
7103 int
7104 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7105 {
7106         struct i40e_macvlan_filter *mv_f;
7107         int mac_num;
7108         int ret = I40E_SUCCESS;
7109
7110         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
7111                 return I40E_ERR_PARAM;
7112
7113         /* If it's already set, just return */
7114         if (i40e_find_vlan_filter(vsi,vlan))
7115                 return I40E_SUCCESS;
7116
7117         mac_num = vsi->mac_num;
7118
7119         if (mac_num == 0) {
7120                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7121                 return I40E_ERR_PARAM;
7122         }
7123
7124         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7125
7126         if (mv_f == NULL) {
7127                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7128                 return I40E_ERR_NO_MEMORY;
7129         }
7130
7131         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7132
7133         if (ret != I40E_SUCCESS)
7134                 goto DONE;
7135
7136         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7137
7138         if (ret != I40E_SUCCESS)
7139                 goto DONE;
7140
7141         i40e_set_vlan_filter(vsi, vlan, 1);
7142
7143         vsi->vlan_num++;
7144         ret = I40E_SUCCESS;
7145 DONE:
7146         rte_free(mv_f);
7147         return ret;
7148 }
7149
7150 int
7151 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7152 {
7153         struct i40e_macvlan_filter *mv_f;
7154         int mac_num;
7155         int ret = I40E_SUCCESS;
7156
7157         /**
7158          * Vlan 0 is the generic filter for untagged packets
7159          * and can't be removed.
7160          */
7161         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
7162                 return I40E_ERR_PARAM;
7163
7164         /* If can't find it, just return */
7165         if (!i40e_find_vlan_filter(vsi, vlan))
7166                 return I40E_ERR_PARAM;
7167
7168         mac_num = vsi->mac_num;
7169
7170         if (mac_num == 0) {
7171                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7172                 return I40E_ERR_PARAM;
7173         }
7174
7175         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7176
7177         if (mv_f == NULL) {
7178                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7179                 return I40E_ERR_NO_MEMORY;
7180         }
7181
7182         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7183
7184         if (ret != I40E_SUCCESS)
7185                 goto DONE;
7186
7187         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7188
7189         if (ret != I40E_SUCCESS)
7190                 goto DONE;
7191
7192         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7193         if (vsi->vlan_num == 1) {
7194                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7195                 if (ret != I40E_SUCCESS)
7196                         goto DONE;
7197
7198                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7199                 if (ret != I40E_SUCCESS)
7200                         goto DONE;
7201         }
7202
7203         i40e_set_vlan_filter(vsi, vlan, 0);
7204
7205         vsi->vlan_num--;
7206         ret = I40E_SUCCESS;
7207 DONE:
7208         rte_free(mv_f);
7209         return ret;
7210 }
7211
7212 int
7213 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7214 {
7215         struct i40e_mac_filter *f;
7216         struct i40e_macvlan_filter *mv_f;
7217         int i, vlan_num = 0;
7218         int ret = I40E_SUCCESS;
7219
7220         /* If it's add and we've config it, return */
7221         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7222         if (f != NULL)
7223                 return I40E_SUCCESS;
7224         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7225                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7226
7227                 /**
7228                  * If vlan_num is 0, that's the first time to add mac,
7229                  * set mask for vlan_id 0.
7230                  */
7231                 if (vsi->vlan_num == 0) {
7232                         i40e_set_vlan_filter(vsi, 0, 1);
7233                         vsi->vlan_num = 1;
7234                 }
7235                 vlan_num = vsi->vlan_num;
7236         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7237                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7238                 vlan_num = 1;
7239
7240         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7241         if (mv_f == NULL) {
7242                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7243                 return I40E_ERR_NO_MEMORY;
7244         }
7245
7246         for (i = 0; i < vlan_num; i++) {
7247                 mv_f[i].filter_type = mac_filter->filter_type;
7248                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7249                                 ETH_ADDR_LEN);
7250         }
7251
7252         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7253                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7254                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7255                                         &mac_filter->mac_addr);
7256                 if (ret != I40E_SUCCESS)
7257                         goto DONE;
7258         }
7259
7260         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7261         if (ret != I40E_SUCCESS)
7262                 goto DONE;
7263
7264         /* Add the mac addr into mac list */
7265         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7266         if (f == NULL) {
7267                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7268                 ret = I40E_ERR_NO_MEMORY;
7269                 goto DONE;
7270         }
7271         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7272                         ETH_ADDR_LEN);
7273         f->mac_info.filter_type = mac_filter->filter_type;
7274         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7275         vsi->mac_num++;
7276
7277         ret = I40E_SUCCESS;
7278 DONE:
7279         rte_free(mv_f);
7280
7281         return ret;
7282 }
7283
7284 int
7285 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7286 {
7287         struct i40e_mac_filter *f;
7288         struct i40e_macvlan_filter *mv_f;
7289         int i, vlan_num;
7290         enum rte_mac_filter_type filter_type;
7291         int ret = I40E_SUCCESS;
7292
7293         /* Can't find it, return an error */
7294         f = i40e_find_mac_filter(vsi, addr);
7295         if (f == NULL)
7296                 return I40E_ERR_PARAM;
7297
7298         vlan_num = vsi->vlan_num;
7299         filter_type = f->mac_info.filter_type;
7300         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7301                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7302                 if (vlan_num == 0) {
7303                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7304                         return I40E_ERR_PARAM;
7305                 }
7306         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7307                         filter_type == RTE_MAC_HASH_MATCH)
7308                 vlan_num = 1;
7309
7310         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7311         if (mv_f == NULL) {
7312                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7313                 return I40E_ERR_NO_MEMORY;
7314         }
7315
7316         for (i = 0; i < vlan_num; i++) {
7317                 mv_f[i].filter_type = filter_type;
7318                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7319                                 ETH_ADDR_LEN);
7320         }
7321         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7322                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7323                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7324                 if (ret != I40E_SUCCESS)
7325                         goto DONE;
7326         }
7327
7328         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7329         if (ret != I40E_SUCCESS)
7330                 goto DONE;
7331
7332         /* Remove the mac addr into mac list */
7333         TAILQ_REMOVE(&vsi->mac_list, f, next);
7334         rte_free(f);
7335         vsi->mac_num--;
7336
7337         ret = I40E_SUCCESS;
7338 DONE:
7339         rte_free(mv_f);
7340         return ret;
7341 }
7342
7343 /* Configure hash enable flags for RSS */
7344 uint64_t
7345 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7346 {
7347         uint64_t hena = 0;
7348         int i;
7349
7350         if (!flags)
7351                 return hena;
7352
7353         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7354                 if (flags & (1ULL << i))
7355                         hena |= adapter->pctypes_tbl[i];
7356         }
7357
7358         return hena;
7359 }
7360
7361 /* Parse the hash enable flags */
7362 uint64_t
7363 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7364 {
7365         uint64_t rss_hf = 0;
7366
7367         if (!flags)
7368                 return rss_hf;
7369         int i;
7370
7371         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7372                 if (flags & adapter->pctypes_tbl[i])
7373                         rss_hf |= (1ULL << i);
7374         }
7375         return rss_hf;
7376 }
7377
7378 /* Disable RSS */
7379 static void
7380 i40e_pf_disable_rss(struct i40e_pf *pf)
7381 {
7382         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7383
7384         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7385         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7386         I40E_WRITE_FLUSH(hw);
7387 }
7388
7389 int
7390 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7391 {
7392         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7393         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7394         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7395                            I40E_VFQF_HKEY_MAX_INDEX :
7396                            I40E_PFQF_HKEY_MAX_INDEX;
7397         int ret = 0;
7398
7399         if (!key || key_len == 0) {
7400                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7401                 return 0;
7402         } else if (key_len != (key_idx + 1) *
7403                 sizeof(uint32_t)) {
7404                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7405                 return -EINVAL;
7406         }
7407
7408         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7409                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7410                         (struct i40e_aqc_get_set_rss_key_data *)key;
7411
7412                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7413                 if (ret)
7414                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7415         } else {
7416                 uint32_t *hash_key = (uint32_t *)key;
7417                 uint16_t i;
7418
7419                 if (vsi->type == I40E_VSI_SRIOV) {
7420                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7421                                 I40E_WRITE_REG(
7422                                         hw,
7423                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7424                                         hash_key[i]);
7425
7426                 } else {
7427                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7428                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7429                                                hash_key[i]);
7430                 }
7431                 I40E_WRITE_FLUSH(hw);
7432         }
7433
7434         return ret;
7435 }
7436
7437 static int
7438 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7439 {
7440         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7441         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7442         uint32_t reg;
7443         int ret;
7444
7445         if (!key || !key_len)
7446                 return 0;
7447
7448         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7449                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7450                         (struct i40e_aqc_get_set_rss_key_data *)key);
7451                 if (ret) {
7452                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7453                         return ret;
7454                 }
7455         } else {
7456                 uint32_t *key_dw = (uint32_t *)key;
7457                 uint16_t i;
7458
7459                 if (vsi->type == I40E_VSI_SRIOV) {
7460                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7461                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7462                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7463                         }
7464                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7465                                    sizeof(uint32_t);
7466                 } else {
7467                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7468                                 reg = I40E_PFQF_HKEY(i);
7469                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7470                         }
7471                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7472                                    sizeof(uint32_t);
7473                 }
7474         }
7475         return 0;
7476 }
7477
7478 static int
7479 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7480 {
7481         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7482         uint64_t hena;
7483         int ret;
7484
7485         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7486                                rss_conf->rss_key_len);
7487         if (ret)
7488                 return ret;
7489
7490         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7491         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7492         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7493         I40E_WRITE_FLUSH(hw);
7494
7495         return 0;
7496 }
7497
7498 static int
7499 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7500                          struct rte_eth_rss_conf *rss_conf)
7501 {
7502         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7503         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7504         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7505         uint64_t hena;
7506
7507         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7508         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7509
7510         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7511                 if (rss_hf != 0) /* Enable RSS */
7512                         return -EINVAL;
7513                 return 0; /* Nothing to do */
7514         }
7515         /* RSS enabled */
7516         if (rss_hf == 0) /* Disable RSS */
7517                 return -EINVAL;
7518
7519         return i40e_hw_rss_hash_set(pf, rss_conf);
7520 }
7521
7522 static int
7523 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7524                            struct rte_eth_rss_conf *rss_conf)
7525 {
7526         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7527         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7528         uint64_t hena;
7529         int ret;
7530
7531         if (!rss_conf)
7532                 return -EINVAL;
7533
7534         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7535                          &rss_conf->rss_key_len);
7536         if (ret)
7537                 return ret;
7538
7539         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7540         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7541         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7542
7543         return 0;
7544 }
7545
7546 static int
7547 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7548 {
7549         switch (filter_type) {
7550         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7551                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7552                 break;
7553         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7554                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7555                 break;
7556         case RTE_TUNNEL_FILTER_IMAC_TENID:
7557                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7558                 break;
7559         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7560                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7561                 break;
7562         case ETH_TUNNEL_FILTER_IMAC:
7563                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7564                 break;
7565         case ETH_TUNNEL_FILTER_OIP:
7566                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7567                 break;
7568         case ETH_TUNNEL_FILTER_IIP:
7569                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7570                 break;
7571         default:
7572                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7573                 return -EINVAL;
7574         }
7575
7576         return 0;
7577 }
7578
7579 /* Convert tunnel filter structure */
7580 static int
7581 i40e_tunnel_filter_convert(
7582         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7583         struct i40e_tunnel_filter *tunnel_filter)
7584 {
7585         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7586                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7587         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7588                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7589         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7590         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7591              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7592             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7593                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7594         else
7595                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7596         tunnel_filter->input.flags = cld_filter->element.flags;
7597         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7598         tunnel_filter->queue = cld_filter->element.queue_number;
7599         rte_memcpy(tunnel_filter->input.general_fields,
7600                    cld_filter->general_fields,
7601                    sizeof(cld_filter->general_fields));
7602
7603         return 0;
7604 }
7605
7606 /* Check if there exists the tunnel filter */
7607 struct i40e_tunnel_filter *
7608 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7609                              const struct i40e_tunnel_filter_input *input)
7610 {
7611         int ret;
7612
7613         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7614         if (ret < 0)
7615                 return NULL;
7616
7617         return tunnel_rule->hash_map[ret];
7618 }
7619
7620 /* Add a tunnel filter into the SW list */
7621 static int
7622 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7623                              struct i40e_tunnel_filter *tunnel_filter)
7624 {
7625         struct i40e_tunnel_rule *rule = &pf->tunnel;
7626         int ret;
7627
7628         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7629         if (ret < 0) {
7630                 PMD_DRV_LOG(ERR,
7631                             "Failed to insert tunnel filter to hash table %d!",
7632                             ret);
7633                 return ret;
7634         }
7635         rule->hash_map[ret] = tunnel_filter;
7636
7637         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7638
7639         return 0;
7640 }
7641
7642 /* Delete a tunnel filter from the SW list */
7643 int
7644 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7645                           struct i40e_tunnel_filter_input *input)
7646 {
7647         struct i40e_tunnel_rule *rule = &pf->tunnel;
7648         struct i40e_tunnel_filter *tunnel_filter;
7649         int ret;
7650
7651         ret = rte_hash_del_key(rule->hash_table, input);
7652         if (ret < 0) {
7653                 PMD_DRV_LOG(ERR,
7654                             "Failed to delete tunnel filter to hash table %d!",
7655                             ret);
7656                 return ret;
7657         }
7658         tunnel_filter = rule->hash_map[ret];
7659         rule->hash_map[ret] = NULL;
7660
7661         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7662         rte_free(tunnel_filter);
7663
7664         return 0;
7665 }
7666
7667 int
7668 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7669                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7670                         uint8_t add)
7671 {
7672         uint16_t ip_type;
7673         uint32_t ipv4_addr, ipv4_addr_le;
7674         uint8_t i, tun_type = 0;
7675         /* internal varialbe to convert ipv6 byte order */
7676         uint32_t convert_ipv6[4];
7677         int val, ret = 0;
7678         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7679         struct i40e_vsi *vsi = pf->main_vsi;
7680         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7681         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7682         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7683         struct i40e_tunnel_filter *tunnel, *node;
7684         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7685
7686         cld_filter = rte_zmalloc("tunnel_filter",
7687                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7688         0);
7689
7690         if (NULL == cld_filter) {
7691                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7692                 return -ENOMEM;
7693         }
7694         pfilter = cld_filter;
7695
7696         ether_addr_copy(&tunnel_filter->outer_mac,
7697                         (struct ether_addr *)&pfilter->element.outer_mac);
7698         ether_addr_copy(&tunnel_filter->inner_mac,
7699                         (struct ether_addr *)&pfilter->element.inner_mac);
7700
7701         pfilter->element.inner_vlan =
7702                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7703         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7704                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7705                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7706                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7707                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7708                                 &ipv4_addr_le,
7709                                 sizeof(pfilter->element.ipaddr.v4.data));
7710         } else {
7711                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7712                 for (i = 0; i < 4; i++) {
7713                         convert_ipv6[i] =
7714                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7715                 }
7716                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7717                            &convert_ipv6,
7718                            sizeof(pfilter->element.ipaddr.v6.data));
7719         }
7720
7721         /* check tunneled type */
7722         switch (tunnel_filter->tunnel_type) {
7723         case RTE_TUNNEL_TYPE_VXLAN:
7724                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7725                 break;
7726         case RTE_TUNNEL_TYPE_NVGRE:
7727                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7728                 break;
7729         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7730                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7731                 break;
7732         default:
7733                 /* Other tunnel types is not supported. */
7734                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7735                 rte_free(cld_filter);
7736                 return -EINVAL;
7737         }
7738
7739         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7740                                        &pfilter->element.flags);
7741         if (val < 0) {
7742                 rte_free(cld_filter);
7743                 return -EINVAL;
7744         }
7745
7746         pfilter->element.flags |= rte_cpu_to_le_16(
7747                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7748                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7749         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7750         pfilter->element.queue_number =
7751                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7752
7753         /* Check if there is the filter in SW list */
7754         memset(&check_filter, 0, sizeof(check_filter));
7755         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7756         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7757         if (add && node) {
7758                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7759                 rte_free(cld_filter);
7760                 return -EINVAL;
7761         }
7762
7763         if (!add && !node) {
7764                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7765                 rte_free(cld_filter);
7766                 return -EINVAL;
7767         }
7768
7769         if (add) {
7770                 ret = i40e_aq_add_cloud_filters(hw,
7771                                         vsi->seid, &cld_filter->element, 1);
7772                 if (ret < 0) {
7773                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7774                         rte_free(cld_filter);
7775                         return -ENOTSUP;
7776                 }
7777                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7778                 if (tunnel == NULL) {
7779                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7780                         rte_free(cld_filter);
7781                         return -ENOMEM;
7782                 }
7783
7784                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7785                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7786                 if (ret < 0)
7787                         rte_free(tunnel);
7788         } else {
7789                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7790                                                    &cld_filter->element, 1);
7791                 if (ret < 0) {
7792                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7793                         rte_free(cld_filter);
7794                         return -ENOTSUP;
7795                 }
7796                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7797         }
7798
7799         rte_free(cld_filter);
7800         return ret;
7801 }
7802
7803 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7804 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7805 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7806 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7807 #define I40E_TR_GRE_KEY_MASK                    0x400
7808 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7809 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7810
7811 static enum
7812 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7813 {
7814         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7815         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7816         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7817         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7818         enum i40e_status_code status = I40E_SUCCESS;
7819
7820         if (pf->support_multi_driver) {
7821                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7822                 return I40E_NOT_SUPPORTED;
7823         }
7824
7825         memset(&filter_replace, 0,
7826                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7827         memset(&filter_replace_buf, 0,
7828                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7829
7830         /* create L1 filter */
7831         filter_replace.old_filter_type =
7832                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7833         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7834         filter_replace.tr_bit = 0;
7835
7836         /* Prepare the buffer, 3 entries */
7837         filter_replace_buf.data[0] =
7838                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7839         filter_replace_buf.data[0] |=
7840                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7841         filter_replace_buf.data[2] = 0xFF;
7842         filter_replace_buf.data[3] = 0xFF;
7843         filter_replace_buf.data[4] =
7844                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7845         filter_replace_buf.data[4] |=
7846                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7847         filter_replace_buf.data[7] = 0xF0;
7848         filter_replace_buf.data[8]
7849                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7850         filter_replace_buf.data[8] |=
7851                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7852         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7853                 I40E_TR_GENEVE_KEY_MASK |
7854                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7855         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7856                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7857                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7858
7859         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7860                                                &filter_replace_buf);
7861         if (!status && (filter_replace.old_filter_type !=
7862                         filter_replace.new_filter_type))
7863                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7864                             " original: 0x%x, new: 0x%x",
7865                             dev->device->name,
7866                             filter_replace.old_filter_type,
7867                             filter_replace.new_filter_type);
7868
7869         return status;
7870 }
7871
7872 static enum
7873 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7874 {
7875         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7876         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7877         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7878         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7879         enum i40e_status_code status = I40E_SUCCESS;
7880
7881         if (pf->support_multi_driver) {
7882                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7883                 return I40E_NOT_SUPPORTED;
7884         }
7885
7886         /* For MPLSoUDP */
7887         memset(&filter_replace, 0,
7888                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7889         memset(&filter_replace_buf, 0,
7890                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7891         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7892                 I40E_AQC_MIRROR_CLOUD_FILTER;
7893         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7894         filter_replace.new_filter_type =
7895                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7896         /* Prepare the buffer, 2 entries */
7897         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7898         filter_replace_buf.data[0] |=
7899                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7900         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7901         filter_replace_buf.data[4] |=
7902                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7903         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7904                                                &filter_replace_buf);
7905         if (status < 0)
7906                 return status;
7907         if (filter_replace.old_filter_type !=
7908             filter_replace.new_filter_type)
7909                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7910                             " original: 0x%x, new: 0x%x",
7911                             dev->device->name,
7912                             filter_replace.old_filter_type,
7913                             filter_replace.new_filter_type);
7914
7915         /* For MPLSoGRE */
7916         memset(&filter_replace, 0,
7917                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7918         memset(&filter_replace_buf, 0,
7919                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7920
7921         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7922                 I40E_AQC_MIRROR_CLOUD_FILTER;
7923         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7924         filter_replace.new_filter_type =
7925                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7926         /* Prepare the buffer, 2 entries */
7927         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7928         filter_replace_buf.data[0] |=
7929                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7930         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7931         filter_replace_buf.data[4] |=
7932                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7933
7934         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7935                                                &filter_replace_buf);
7936         if (!status && (filter_replace.old_filter_type !=
7937                         filter_replace.new_filter_type))
7938                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7939                             " original: 0x%x, new: 0x%x",
7940                             dev->device->name,
7941                             filter_replace.old_filter_type,
7942                             filter_replace.new_filter_type);
7943
7944         return status;
7945 }
7946
7947 static enum i40e_status_code
7948 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7949 {
7950         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7951         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7952         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7953         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7954         enum i40e_status_code status = I40E_SUCCESS;
7955
7956         if (pf->support_multi_driver) {
7957                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7958                 return I40E_NOT_SUPPORTED;
7959         }
7960
7961         /* For GTP-C */
7962         memset(&filter_replace, 0,
7963                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7964         memset(&filter_replace_buf, 0,
7965                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7966         /* create L1 filter */
7967         filter_replace.old_filter_type =
7968                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7969         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7970         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7971                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7972         /* Prepare the buffer, 2 entries */
7973         filter_replace_buf.data[0] =
7974                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7975         filter_replace_buf.data[0] |=
7976                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7977         filter_replace_buf.data[2] = 0xFF;
7978         filter_replace_buf.data[3] = 0xFF;
7979         filter_replace_buf.data[4] =
7980                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7981         filter_replace_buf.data[4] |=
7982                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7983         filter_replace_buf.data[6] = 0xFF;
7984         filter_replace_buf.data[7] = 0xFF;
7985         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7986                                                &filter_replace_buf);
7987         if (status < 0)
7988                 return status;
7989         if (filter_replace.old_filter_type !=
7990             filter_replace.new_filter_type)
7991                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7992                             " original: 0x%x, new: 0x%x",
7993                             dev->device->name,
7994                             filter_replace.old_filter_type,
7995                             filter_replace.new_filter_type);
7996
7997         /* for GTP-U */
7998         memset(&filter_replace, 0,
7999                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8000         memset(&filter_replace_buf, 0,
8001                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8002         /* create L1 filter */
8003         filter_replace.old_filter_type =
8004                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8005         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8006         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8007                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8008         /* Prepare the buffer, 2 entries */
8009         filter_replace_buf.data[0] =
8010                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8011         filter_replace_buf.data[0] |=
8012                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8013         filter_replace_buf.data[2] = 0xFF;
8014         filter_replace_buf.data[3] = 0xFF;
8015         filter_replace_buf.data[4] =
8016                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8017         filter_replace_buf.data[4] |=
8018                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8019         filter_replace_buf.data[6] = 0xFF;
8020         filter_replace_buf.data[7] = 0xFF;
8021
8022         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8023                                                &filter_replace_buf);
8024         if (!status && (filter_replace.old_filter_type !=
8025                         filter_replace.new_filter_type))
8026                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8027                             " original: 0x%x, new: 0x%x",
8028                             dev->device->name,
8029                             filter_replace.old_filter_type,
8030                             filter_replace.new_filter_type);
8031
8032         return status;
8033 }
8034
8035 static enum
8036 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8037 {
8038         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8039         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8040         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8041         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8042         enum i40e_status_code status = I40E_SUCCESS;
8043
8044         if (pf->support_multi_driver) {
8045                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8046                 return I40E_NOT_SUPPORTED;
8047         }
8048
8049         /* for GTP-C */
8050         memset(&filter_replace, 0,
8051                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8052         memset(&filter_replace_buf, 0,
8053                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8054         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8055         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8056         filter_replace.new_filter_type =
8057                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8058         /* Prepare the buffer, 2 entries */
8059         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8060         filter_replace_buf.data[0] |=
8061                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8062         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8063         filter_replace_buf.data[4] |=
8064                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8065         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8066                                                &filter_replace_buf);
8067         if (status < 0)
8068                 return status;
8069         if (filter_replace.old_filter_type !=
8070             filter_replace.new_filter_type)
8071                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8072                             " original: 0x%x, new: 0x%x",
8073                             dev->device->name,
8074                             filter_replace.old_filter_type,
8075                             filter_replace.new_filter_type);
8076
8077         /* for GTP-U */
8078         memset(&filter_replace, 0,
8079                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8080         memset(&filter_replace_buf, 0,
8081                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8082         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8083         filter_replace.old_filter_type =
8084                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8085         filter_replace.new_filter_type =
8086                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8087         /* Prepare the buffer, 2 entries */
8088         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8089         filter_replace_buf.data[0] |=
8090                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8091         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8092         filter_replace_buf.data[4] |=
8093                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8094
8095         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8096                                                &filter_replace_buf);
8097         if (!status && (filter_replace.old_filter_type !=
8098                         filter_replace.new_filter_type))
8099                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8100                             " original: 0x%x, new: 0x%x",
8101                             dev->device->name,
8102                             filter_replace.old_filter_type,
8103                             filter_replace.new_filter_type);
8104
8105         return status;
8106 }
8107
8108 int
8109 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8110                       struct i40e_tunnel_filter_conf *tunnel_filter,
8111                       uint8_t add)
8112 {
8113         uint16_t ip_type;
8114         uint32_t ipv4_addr, ipv4_addr_le;
8115         uint8_t i, tun_type = 0;
8116         /* internal variable to convert ipv6 byte order */
8117         uint32_t convert_ipv6[4];
8118         int val, ret = 0;
8119         struct i40e_pf_vf *vf = NULL;
8120         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8121         struct i40e_vsi *vsi;
8122         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8123         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8124         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8125         struct i40e_tunnel_filter *tunnel, *node;
8126         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8127         uint32_t teid_le;
8128         bool big_buffer = 0;
8129
8130         cld_filter = rte_zmalloc("tunnel_filter",
8131                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8132                          0);
8133
8134         if (cld_filter == NULL) {
8135                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8136                 return -ENOMEM;
8137         }
8138         pfilter = cld_filter;
8139
8140         ether_addr_copy(&tunnel_filter->outer_mac,
8141                         (struct ether_addr *)&pfilter->element.outer_mac);
8142         ether_addr_copy(&tunnel_filter->inner_mac,
8143                         (struct ether_addr *)&pfilter->element.inner_mac);
8144
8145         pfilter->element.inner_vlan =
8146                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8147         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8148                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8149                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8150                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8151                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8152                                 &ipv4_addr_le,
8153                                 sizeof(pfilter->element.ipaddr.v4.data));
8154         } else {
8155                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8156                 for (i = 0; i < 4; i++) {
8157                         convert_ipv6[i] =
8158                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8159                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8160                 }
8161                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8162                            &convert_ipv6,
8163                            sizeof(pfilter->element.ipaddr.v6.data));
8164         }
8165
8166         /* check tunneled type */
8167         switch (tunnel_filter->tunnel_type) {
8168         case I40E_TUNNEL_TYPE_VXLAN:
8169                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8170                 break;
8171         case I40E_TUNNEL_TYPE_NVGRE:
8172                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8173                 break;
8174         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8175                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8176                 break;
8177         case I40E_TUNNEL_TYPE_MPLSoUDP:
8178                 if (!pf->mpls_replace_flag) {
8179                         i40e_replace_mpls_l1_filter(pf);
8180                         i40e_replace_mpls_cloud_filter(pf);
8181                         pf->mpls_replace_flag = 1;
8182                 }
8183                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8184                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8185                         teid_le >> 4;
8186                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8187                         (teid_le & 0xF) << 12;
8188                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8189                         0x40;
8190                 big_buffer = 1;
8191                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8192                 break;
8193         case I40E_TUNNEL_TYPE_MPLSoGRE:
8194                 if (!pf->mpls_replace_flag) {
8195                         i40e_replace_mpls_l1_filter(pf);
8196                         i40e_replace_mpls_cloud_filter(pf);
8197                         pf->mpls_replace_flag = 1;
8198                 }
8199                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8200                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8201                         teid_le >> 4;
8202                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8203                         (teid_le & 0xF) << 12;
8204                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8205                         0x0;
8206                 big_buffer = 1;
8207                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8208                 break;
8209         case I40E_TUNNEL_TYPE_GTPC:
8210                 if (!pf->gtp_replace_flag) {
8211                         i40e_replace_gtp_l1_filter(pf);
8212                         i40e_replace_gtp_cloud_filter(pf);
8213                         pf->gtp_replace_flag = 1;
8214                 }
8215                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8216                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8217                         (teid_le >> 16) & 0xFFFF;
8218                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8219                         teid_le & 0xFFFF;
8220                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8221                         0x0;
8222                 big_buffer = 1;
8223                 break;
8224         case I40E_TUNNEL_TYPE_GTPU:
8225                 if (!pf->gtp_replace_flag) {
8226                         i40e_replace_gtp_l1_filter(pf);
8227                         i40e_replace_gtp_cloud_filter(pf);
8228                         pf->gtp_replace_flag = 1;
8229                 }
8230                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8231                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8232                         (teid_le >> 16) & 0xFFFF;
8233                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8234                         teid_le & 0xFFFF;
8235                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8236                         0x0;
8237                 big_buffer = 1;
8238                 break;
8239         case I40E_TUNNEL_TYPE_QINQ:
8240                 if (!pf->qinq_replace_flag) {
8241                         ret = i40e_cloud_filter_qinq_create(pf);
8242                         if (ret < 0)
8243                                 PMD_DRV_LOG(DEBUG,
8244                                             "QinQ tunnel filter already created.");
8245                         pf->qinq_replace_flag = 1;
8246                 }
8247                 /*      Add in the General fields the values of
8248                  *      the Outer and Inner VLAN
8249                  *      Big Buffer should be set, see changes in
8250                  *      i40e_aq_add_cloud_filters
8251                  */
8252                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8253                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8254                 big_buffer = 1;
8255                 break;
8256         default:
8257                 /* Other tunnel types is not supported. */
8258                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8259                 rte_free(cld_filter);
8260                 return -EINVAL;
8261         }
8262
8263         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8264                 pfilter->element.flags =
8265                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8266         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8267                 pfilter->element.flags =
8268                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8269         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8270                 pfilter->element.flags =
8271                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8272         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8273                 pfilter->element.flags =
8274                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8275         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8276                 pfilter->element.flags |=
8277                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8278         else {
8279                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8280                                                 &pfilter->element.flags);
8281                 if (val < 0) {
8282                         rte_free(cld_filter);
8283                         return -EINVAL;
8284                 }
8285         }
8286
8287         pfilter->element.flags |= rte_cpu_to_le_16(
8288                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8289                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8290         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8291         pfilter->element.queue_number =
8292                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8293
8294         if (!tunnel_filter->is_to_vf)
8295                 vsi = pf->main_vsi;
8296         else {
8297                 if (tunnel_filter->vf_id >= pf->vf_num) {
8298                         PMD_DRV_LOG(ERR, "Invalid argument.");
8299                         rte_free(cld_filter);
8300                         return -EINVAL;
8301                 }
8302                 vf = &pf->vfs[tunnel_filter->vf_id];
8303                 vsi = vf->vsi;
8304         }
8305
8306         /* Check if there is the filter in SW list */
8307         memset(&check_filter, 0, sizeof(check_filter));
8308         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8309         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8310         check_filter.vf_id = tunnel_filter->vf_id;
8311         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8312         if (add && node) {
8313                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8314                 rte_free(cld_filter);
8315                 return -EINVAL;
8316         }
8317
8318         if (!add && !node) {
8319                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8320                 rte_free(cld_filter);
8321                 return -EINVAL;
8322         }
8323
8324         if (add) {
8325                 if (big_buffer)
8326                         ret = i40e_aq_add_cloud_filters_bb(hw,
8327                                                    vsi->seid, cld_filter, 1);
8328                 else
8329                         ret = i40e_aq_add_cloud_filters(hw,
8330                                         vsi->seid, &cld_filter->element, 1);
8331                 if (ret < 0) {
8332                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8333                         rte_free(cld_filter);
8334                         return -ENOTSUP;
8335                 }
8336                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8337                 if (tunnel == NULL) {
8338                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8339                         rte_free(cld_filter);
8340                         return -ENOMEM;
8341                 }
8342
8343                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8344                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8345                 if (ret < 0)
8346                         rte_free(tunnel);
8347         } else {
8348                 if (big_buffer)
8349                         ret = i40e_aq_rem_cloud_filters_bb(
8350                                 hw, vsi->seid, cld_filter, 1);
8351                 else
8352                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8353                                                 &cld_filter->element, 1);
8354                 if (ret < 0) {
8355                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8356                         rte_free(cld_filter);
8357                         return -ENOTSUP;
8358                 }
8359                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8360         }
8361
8362         rte_free(cld_filter);
8363         return ret;
8364 }
8365
8366 static int
8367 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8368 {
8369         uint8_t i;
8370
8371         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8372                 if (pf->vxlan_ports[i] == port)
8373                         return i;
8374         }
8375
8376         return -1;
8377 }
8378
8379 static int
8380 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8381 {
8382         int  idx, ret;
8383         uint8_t filter_idx;
8384         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8385
8386         idx = i40e_get_vxlan_port_idx(pf, port);
8387
8388         /* Check if port already exists */
8389         if (idx >= 0) {
8390                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8391                 return -EINVAL;
8392         }
8393
8394         /* Now check if there is space to add the new port */
8395         idx = i40e_get_vxlan_port_idx(pf, 0);
8396         if (idx < 0) {
8397                 PMD_DRV_LOG(ERR,
8398                         "Maximum number of UDP ports reached, not adding port %d",
8399                         port);
8400                 return -ENOSPC;
8401         }
8402
8403         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8404                                         &filter_idx, NULL);
8405         if (ret < 0) {
8406                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8407                 return -1;
8408         }
8409
8410         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8411                          port,  filter_idx);
8412
8413         /* New port: add it and mark its index in the bitmap */
8414         pf->vxlan_ports[idx] = port;
8415         pf->vxlan_bitmap |= (1 << idx);
8416
8417         if (!(pf->flags & I40E_FLAG_VXLAN))
8418                 pf->flags |= I40E_FLAG_VXLAN;
8419
8420         return 0;
8421 }
8422
8423 static int
8424 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8425 {
8426         int idx;
8427         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8428
8429         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8430                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8431                 return -EINVAL;
8432         }
8433
8434         idx = i40e_get_vxlan_port_idx(pf, port);
8435
8436         if (idx < 0) {
8437                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8438                 return -EINVAL;
8439         }
8440
8441         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8442                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8443                 return -1;
8444         }
8445
8446         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8447                         port, idx);
8448
8449         pf->vxlan_ports[idx] = 0;
8450         pf->vxlan_bitmap &= ~(1 << idx);
8451
8452         if (!pf->vxlan_bitmap)
8453                 pf->flags &= ~I40E_FLAG_VXLAN;
8454
8455         return 0;
8456 }
8457
8458 /* Add UDP tunneling port */
8459 static int
8460 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8461                              struct rte_eth_udp_tunnel *udp_tunnel)
8462 {
8463         int ret = 0;
8464         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8465
8466         if (udp_tunnel == NULL)
8467                 return -EINVAL;
8468
8469         switch (udp_tunnel->prot_type) {
8470         case RTE_TUNNEL_TYPE_VXLAN:
8471                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8472                 break;
8473
8474         case RTE_TUNNEL_TYPE_GENEVE:
8475         case RTE_TUNNEL_TYPE_TEREDO:
8476                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8477                 ret = -1;
8478                 break;
8479
8480         default:
8481                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8482                 ret = -1;
8483                 break;
8484         }
8485
8486         return ret;
8487 }
8488
8489 /* Remove UDP tunneling port */
8490 static int
8491 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8492                              struct rte_eth_udp_tunnel *udp_tunnel)
8493 {
8494         int ret = 0;
8495         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8496
8497         if (udp_tunnel == NULL)
8498                 return -EINVAL;
8499
8500         switch (udp_tunnel->prot_type) {
8501         case RTE_TUNNEL_TYPE_VXLAN:
8502                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8503                 break;
8504         case RTE_TUNNEL_TYPE_GENEVE:
8505         case RTE_TUNNEL_TYPE_TEREDO:
8506                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8507                 ret = -1;
8508                 break;
8509         default:
8510                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8511                 ret = -1;
8512                 break;
8513         }
8514
8515         return ret;
8516 }
8517
8518 /* Calculate the maximum number of contiguous PF queues that are configured */
8519 static int
8520 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8521 {
8522         struct rte_eth_dev_data *data = pf->dev_data;
8523         int i, num;
8524         struct i40e_rx_queue *rxq;
8525
8526         num = 0;
8527         for (i = 0; i < pf->lan_nb_qps; i++) {
8528                 rxq = data->rx_queues[i];
8529                 if (rxq && rxq->q_set)
8530                         num++;
8531                 else
8532                         break;
8533         }
8534
8535         return num;
8536 }
8537
8538 /* Configure RSS */
8539 static int
8540 i40e_pf_config_rss(struct i40e_pf *pf)
8541 {
8542         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8543         struct rte_eth_rss_conf rss_conf;
8544         uint32_t i, lut = 0;
8545         uint16_t j, num;
8546
8547         /*
8548          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8549          * It's necessary to calculate the actual PF queues that are configured.
8550          */
8551         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8552                 num = i40e_pf_calc_configured_queues_num(pf);
8553         else
8554                 num = pf->dev_data->nb_rx_queues;
8555
8556         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8557         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8558                         num);
8559
8560         if (num == 0) {
8561                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8562                 return -ENOTSUP;
8563         }
8564
8565         if (pf->adapter->rss_reta_updated == 0) {
8566                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8567                         if (j == num)
8568                                 j = 0;
8569                         lut = (lut << 8) | (j & ((0x1 <<
8570                                 hw->func_caps.rss_table_entry_width) - 1));
8571                         if ((i & 3) == 3)
8572                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8573                                                rte_bswap32(lut));
8574                 }
8575         }
8576
8577         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8578         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8579                 i40e_pf_disable_rss(pf);
8580                 return 0;
8581         }
8582         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8583                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8584                 /* Random default keys */
8585                 static uint32_t rss_key_default[] = {0x6b793944,
8586                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8587                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8588                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8589
8590                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8591                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8592                                                         sizeof(uint32_t);
8593         }
8594
8595         return i40e_hw_rss_hash_set(pf, &rss_conf);
8596 }
8597
8598 static int
8599 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8600                                struct rte_eth_tunnel_filter_conf *filter)
8601 {
8602         if (pf == NULL || filter == NULL) {
8603                 PMD_DRV_LOG(ERR, "Invalid parameter");
8604                 return -EINVAL;
8605         }
8606
8607         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8608                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8609                 return -EINVAL;
8610         }
8611
8612         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8613                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8614                 return -EINVAL;
8615         }
8616
8617         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8618                 (is_zero_ether_addr(&filter->outer_mac))) {
8619                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8620                 return -EINVAL;
8621         }
8622
8623         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8624                 (is_zero_ether_addr(&filter->inner_mac))) {
8625                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8626                 return -EINVAL;
8627         }
8628
8629         return 0;
8630 }
8631
8632 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8633 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8634 static int
8635 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8636 {
8637         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8638         uint32_t val, reg;
8639         int ret = -EINVAL;
8640
8641         if (pf->support_multi_driver) {
8642                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8643                 return -ENOTSUP;
8644         }
8645
8646         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8647         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8648
8649         if (len == 3) {
8650                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8651         } else if (len == 4) {
8652                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8653         } else {
8654                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8655                 return ret;
8656         }
8657
8658         if (reg != val) {
8659                 ret = i40e_aq_debug_write_global_register(hw,
8660                                                    I40E_GL_PRS_FVBM(2),
8661                                                    reg, NULL);
8662                 if (ret != 0)
8663                         return ret;
8664                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8665                             "with value 0x%08x",
8666                             I40E_GL_PRS_FVBM(2), reg);
8667         } else {
8668                 ret = 0;
8669         }
8670         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8671                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8672
8673         return ret;
8674 }
8675
8676 static int
8677 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8678 {
8679         int ret = -EINVAL;
8680
8681         if (!hw || !cfg)
8682                 return -EINVAL;
8683
8684         switch (cfg->cfg_type) {
8685         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8686                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8687                 break;
8688         default:
8689                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8690                 break;
8691         }
8692
8693         return ret;
8694 }
8695
8696 static int
8697 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8698                                enum rte_filter_op filter_op,
8699                                void *arg)
8700 {
8701         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8702         int ret = I40E_ERR_PARAM;
8703
8704         switch (filter_op) {
8705         case RTE_ETH_FILTER_SET:
8706                 ret = i40e_dev_global_config_set(hw,
8707                         (struct rte_eth_global_cfg *)arg);
8708                 break;
8709         default:
8710                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8711                 break;
8712         }
8713
8714         return ret;
8715 }
8716
8717 static int
8718 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8719                           enum rte_filter_op filter_op,
8720                           void *arg)
8721 {
8722         struct rte_eth_tunnel_filter_conf *filter;
8723         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8724         int ret = I40E_SUCCESS;
8725
8726         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8727
8728         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8729                 return I40E_ERR_PARAM;
8730
8731         switch (filter_op) {
8732         case RTE_ETH_FILTER_NOP:
8733                 if (!(pf->flags & I40E_FLAG_VXLAN))
8734                         ret = I40E_NOT_SUPPORTED;
8735                 break;
8736         case RTE_ETH_FILTER_ADD:
8737                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8738                 break;
8739         case RTE_ETH_FILTER_DELETE:
8740                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8741                 break;
8742         default:
8743                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8744                 ret = I40E_ERR_PARAM;
8745                 break;
8746         }
8747
8748         return ret;
8749 }
8750
8751 static int
8752 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8753 {
8754         int ret = 0;
8755         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8756
8757         /* RSS setup */
8758         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8759                 ret = i40e_pf_config_rss(pf);
8760         else
8761                 i40e_pf_disable_rss(pf);
8762
8763         return ret;
8764 }
8765
8766 /* Get the symmetric hash enable configurations per port */
8767 static void
8768 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8769 {
8770         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8771
8772         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8773 }
8774
8775 /* Set the symmetric hash enable configurations per port */
8776 static void
8777 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8778 {
8779         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8780
8781         if (enable > 0) {
8782                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8783                         PMD_DRV_LOG(INFO,
8784                                 "Symmetric hash has already been enabled");
8785                         return;
8786                 }
8787                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8788         } else {
8789                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8790                         PMD_DRV_LOG(INFO,
8791                                 "Symmetric hash has already been disabled");
8792                         return;
8793                 }
8794                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8795         }
8796         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8797         I40E_WRITE_FLUSH(hw);
8798 }
8799
8800 /*
8801  * Get global configurations of hash function type and symmetric hash enable
8802  * per flow type (pctype). Note that global configuration means it affects all
8803  * the ports on the same NIC.
8804  */
8805 static int
8806 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8807                                    struct rte_eth_hash_global_conf *g_cfg)
8808 {
8809         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8810         uint32_t reg;
8811         uint16_t i, j;
8812
8813         memset(g_cfg, 0, sizeof(*g_cfg));
8814         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8815         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8816                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8817         else
8818                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8819         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8820                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8821
8822         /*
8823          * As i40e supports less than 64 flow types, only first 64 bits need to
8824          * be checked.
8825          */
8826         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8827                 g_cfg->valid_bit_mask[i] = 0ULL;
8828                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8829         }
8830
8831         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8832
8833         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8834                 if (!adapter->pctypes_tbl[i])
8835                         continue;
8836                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8837                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8838                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8839                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8840                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8841                                         g_cfg->sym_hash_enable_mask[0] |=
8842                                                                 (1ULL << i);
8843                                 }
8844                         }
8845                 }
8846         }
8847
8848         return 0;
8849 }
8850
8851 static int
8852 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8853                               const struct rte_eth_hash_global_conf *g_cfg)
8854 {
8855         uint32_t i;
8856         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8857
8858         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8859                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8860                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8861                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8862                                                 g_cfg->hash_func);
8863                 return -EINVAL;
8864         }
8865
8866         /*
8867          * As i40e supports less than 64 flow types, only first 64 bits need to
8868          * be checked.
8869          */
8870         mask0 = g_cfg->valid_bit_mask[0];
8871         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8872                 if (i == 0) {
8873                         /* Check if any unsupported flow type configured */
8874                         if ((mask0 | i40e_mask) ^ i40e_mask)
8875                                 goto mask_err;
8876                 } else {
8877                         if (g_cfg->valid_bit_mask[i])
8878                                 goto mask_err;
8879                 }
8880         }
8881
8882         return 0;
8883
8884 mask_err:
8885         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8886
8887         return -EINVAL;
8888 }
8889
8890 /*
8891  * Set global configurations of hash function type and symmetric hash enable
8892  * per flow type (pctype). Note any modifying global configuration will affect
8893  * all the ports on the same NIC.
8894  */
8895 static int
8896 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8897                                    struct rte_eth_hash_global_conf *g_cfg)
8898 {
8899         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8900         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8901         int ret;
8902         uint16_t i, j;
8903         uint32_t reg;
8904         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8905
8906         if (pf->support_multi_driver) {
8907                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8908                 return -ENOTSUP;
8909         }
8910
8911         /* Check the input parameters */
8912         ret = i40e_hash_global_config_check(adapter, g_cfg);
8913         if (ret < 0)
8914                 return ret;
8915
8916         /*
8917          * As i40e supports less than 64 flow types, only first 64 bits need to
8918          * be configured.
8919          */
8920         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8921                 if (mask0 & (1UL << i)) {
8922                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8923                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8924
8925                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8926                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8927                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8928                                         i40e_write_global_rx_ctl(hw,
8929                                                           I40E_GLQF_HSYM(j),
8930                                                           reg);
8931                         }
8932                 }
8933         }
8934
8935         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8936         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8937                 /* Toeplitz */
8938                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8939                         PMD_DRV_LOG(DEBUG,
8940                                 "Hash function already set to Toeplitz");
8941                         goto out;
8942                 }
8943                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8944         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8945                 /* Simple XOR */
8946                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8947                         PMD_DRV_LOG(DEBUG,
8948                                 "Hash function already set to Simple XOR");
8949                         goto out;
8950                 }
8951                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8952         } else
8953                 /* Use the default, and keep it as it is */
8954                 goto out;
8955
8956         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8957
8958 out:
8959         I40E_WRITE_FLUSH(hw);
8960
8961         return 0;
8962 }
8963
8964 /**
8965  * Valid input sets for hash and flow director filters per PCTYPE
8966  */
8967 static uint64_t
8968 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8969                 enum rte_filter_type filter)
8970 {
8971         uint64_t valid;
8972
8973         static const uint64_t valid_hash_inset_table[] = {
8974                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8975                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8976                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8977                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8978                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8979                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8980                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8981                         I40E_INSET_FLEX_PAYLOAD,
8982                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8983                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8984                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8985                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8986                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8987                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8988                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8989                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8990                         I40E_INSET_FLEX_PAYLOAD,
8991                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8992                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8993                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8994                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8995                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8996                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8997                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8998                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8999                         I40E_INSET_FLEX_PAYLOAD,
9000                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9001                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9002                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9003                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9004                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9005                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9006                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9007                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9008                         I40E_INSET_FLEX_PAYLOAD,
9009                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9010                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9011                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9012                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9013                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9014                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9015                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9016                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9017                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9018                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9019                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9020                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9021                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9022                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9023                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9024                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9025                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9026                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9027                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9028                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9029                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9030                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9031                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9032                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9033                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9034                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9035                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9036                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9037                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9038                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9039                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9040                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9041                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9042                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9043                         I40E_INSET_FLEX_PAYLOAD,
9044                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9045                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9046                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9047                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9048                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9049                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9050                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9051                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9052                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9053                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9054                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9055                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9056                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9057                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9058                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9059                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9060                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9061                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9062                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9063                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9064                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9065                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9066                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9067                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9068                         I40E_INSET_FLEX_PAYLOAD,
9069                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9070                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9071                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9072                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9073                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9074                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9075                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9076                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9077                         I40E_INSET_FLEX_PAYLOAD,
9078                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9079                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9080                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9081                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9082                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9083                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9084                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9085                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9086                         I40E_INSET_FLEX_PAYLOAD,
9087                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9088                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9089                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9090                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9091                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9092                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9093                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9094                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9095                         I40E_INSET_FLEX_PAYLOAD,
9096                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9097                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9098                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9099                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9100                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9101                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9102                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9103                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9104                         I40E_INSET_FLEX_PAYLOAD,
9105                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9106                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9107                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9108                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9109                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9110                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9111                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9112                         I40E_INSET_FLEX_PAYLOAD,
9113                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9114                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9115                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9116                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9117                         I40E_INSET_FLEX_PAYLOAD,
9118         };
9119
9120         /**
9121          * Flow director supports only fields defined in
9122          * union rte_eth_fdir_flow.
9123          */
9124         static const uint64_t valid_fdir_inset_table[] = {
9125                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9126                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9127                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9128                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9129                 I40E_INSET_IPV4_TTL,
9130                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9131                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9132                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9133                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9134                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9135                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9136                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9137                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9138                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9139                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9140                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9141                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9142                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9143                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9144                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9145                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9146                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9147                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9148                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9149                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9150                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9151                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9152                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9153                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9154                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9155                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9156                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9157                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9158                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9159                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9160                 I40E_INSET_SCTP_VT,
9161                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9162                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9163                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9164                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9165                 I40E_INSET_IPV4_TTL,
9166                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9167                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9168                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9169                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9170                 I40E_INSET_IPV6_HOP_LIMIT,
9171                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9172                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9173                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9174                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9175                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9176                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9177                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9178                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9179                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9180                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9181                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9182                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9183                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9184                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9185                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9186                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9187                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9188                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9189                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9190                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9191                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9192                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9193                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9194                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9195                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9196                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9197                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9198                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9199                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9200                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9201                 I40E_INSET_SCTP_VT,
9202                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9203                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9204                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9205                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9206                 I40E_INSET_IPV6_HOP_LIMIT,
9207                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9208                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9209                 I40E_INSET_LAST_ETHER_TYPE,
9210         };
9211
9212         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9213                 return 0;
9214         if (filter == RTE_ETH_FILTER_HASH)
9215                 valid = valid_hash_inset_table[pctype];
9216         else
9217                 valid = valid_fdir_inset_table[pctype];
9218
9219         return valid;
9220 }
9221
9222 /**
9223  * Validate if the input set is allowed for a specific PCTYPE
9224  */
9225 int
9226 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9227                 enum rte_filter_type filter, uint64_t inset)
9228 {
9229         uint64_t valid;
9230
9231         valid = i40e_get_valid_input_set(pctype, filter);
9232         if (inset & (~valid))
9233                 return -EINVAL;
9234
9235         return 0;
9236 }
9237
9238 /* default input set fields combination per pctype */
9239 uint64_t
9240 i40e_get_default_input_set(uint16_t pctype)
9241 {
9242         static const uint64_t default_inset_table[] = {
9243                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9244                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9245                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9246                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9247                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9248                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9249                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9250                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9251                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9252                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9253                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9254                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9255                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9256                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9257                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9258                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9259                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9260                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9261                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9262                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9263                         I40E_INSET_SCTP_VT,
9264                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9265                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9266                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9267                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9268                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9269                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9270                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9271                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9272                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9273                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9274                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9275                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9276                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9277                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9278                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9279                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9280                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9281                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9282                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9283                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9284                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9285                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9286                         I40E_INSET_SCTP_VT,
9287                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9288                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9289                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9290                         I40E_INSET_LAST_ETHER_TYPE,
9291         };
9292
9293         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9294                 return 0;
9295
9296         return default_inset_table[pctype];
9297 }
9298
9299 /**
9300  * Parse the input set from index to logical bit masks
9301  */
9302 static int
9303 i40e_parse_input_set(uint64_t *inset,
9304                      enum i40e_filter_pctype pctype,
9305                      enum rte_eth_input_set_field *field,
9306                      uint16_t size)
9307 {
9308         uint16_t i, j;
9309         int ret = -EINVAL;
9310
9311         static const struct {
9312                 enum rte_eth_input_set_field field;
9313                 uint64_t inset;
9314         } inset_convert_table[] = {
9315                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9316                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9317                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9318                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9319                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9320                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9321                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9322                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9323                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9324                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9325                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9326                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9327                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9328                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9329                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9330                         I40E_INSET_IPV6_NEXT_HDR},
9331                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9332                         I40E_INSET_IPV6_HOP_LIMIT},
9333                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9334                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9335                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9336                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9337                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9338                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9339                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9340                         I40E_INSET_SCTP_VT},
9341                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9342                         I40E_INSET_TUNNEL_DMAC},
9343                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9344                         I40E_INSET_VLAN_TUNNEL},
9345                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9346                         I40E_INSET_TUNNEL_ID},
9347                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9348                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9349                         I40E_INSET_FLEX_PAYLOAD_W1},
9350                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9351                         I40E_INSET_FLEX_PAYLOAD_W2},
9352                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9353                         I40E_INSET_FLEX_PAYLOAD_W3},
9354                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9355                         I40E_INSET_FLEX_PAYLOAD_W4},
9356                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9357                         I40E_INSET_FLEX_PAYLOAD_W5},
9358                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9359                         I40E_INSET_FLEX_PAYLOAD_W6},
9360                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9361                         I40E_INSET_FLEX_PAYLOAD_W7},
9362                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9363                         I40E_INSET_FLEX_PAYLOAD_W8},
9364         };
9365
9366         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9367                 return ret;
9368
9369         /* Only one item allowed for default or all */
9370         if (size == 1) {
9371                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9372                         *inset = i40e_get_default_input_set(pctype);
9373                         return 0;
9374                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9375                         *inset = I40E_INSET_NONE;
9376                         return 0;
9377                 }
9378         }
9379
9380         for (i = 0, *inset = 0; i < size; i++) {
9381                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9382                         if (field[i] == inset_convert_table[j].field) {
9383                                 *inset |= inset_convert_table[j].inset;
9384                                 break;
9385                         }
9386                 }
9387
9388                 /* It contains unsupported input set, return immediately */
9389                 if (j == RTE_DIM(inset_convert_table))
9390                         return ret;
9391         }
9392
9393         return 0;
9394 }
9395
9396 /**
9397  * Translate the input set from bit masks to register aware bit masks
9398  * and vice versa
9399  */
9400 uint64_t
9401 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9402 {
9403         uint64_t val = 0;
9404         uint16_t i;
9405
9406         struct inset_map {
9407                 uint64_t inset;
9408                 uint64_t inset_reg;
9409         };
9410
9411         static const struct inset_map inset_map_common[] = {
9412                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9413                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9414                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9415                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9416                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9417                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9418                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9419                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9420                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9421                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9422                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9423                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9424                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9425                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9426                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9427                 {I40E_INSET_TUNNEL_DMAC,
9428                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9429                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9430                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9431                 {I40E_INSET_TUNNEL_SRC_PORT,
9432                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9433                 {I40E_INSET_TUNNEL_DST_PORT,
9434                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9435                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9436                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9437                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9438                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9439                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9440                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9441                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9442                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9443                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9444         };
9445
9446     /* some different registers map in x722*/
9447         static const struct inset_map inset_map_diff_x722[] = {
9448                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9449                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9450                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9451                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9452         };
9453
9454         static const struct inset_map inset_map_diff_not_x722[] = {
9455                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9456                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9457                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9458                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9459         };
9460
9461         if (input == 0)
9462                 return val;
9463
9464         /* Translate input set to register aware inset */
9465         if (type == I40E_MAC_X722) {
9466                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9467                         if (input & inset_map_diff_x722[i].inset)
9468                                 val |= inset_map_diff_x722[i].inset_reg;
9469                 }
9470         } else {
9471                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9472                         if (input & inset_map_diff_not_x722[i].inset)
9473                                 val |= inset_map_diff_not_x722[i].inset_reg;
9474                 }
9475         }
9476
9477         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9478                 if (input & inset_map_common[i].inset)
9479                         val |= inset_map_common[i].inset_reg;
9480         }
9481
9482         return val;
9483 }
9484
9485 int
9486 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9487 {
9488         uint8_t i, idx = 0;
9489         uint64_t inset_need_mask = inset;
9490
9491         static const struct {
9492                 uint64_t inset;
9493                 uint32_t mask;
9494         } inset_mask_map[] = {
9495                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9496                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9497                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9498                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9499                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9500                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9501                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9502                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9503         };
9504
9505         if (!inset || !mask || !nb_elem)
9506                 return 0;
9507
9508         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9509                 /* Clear the inset bit, if no MASK is required,
9510                  * for example proto + ttl
9511                  */
9512                 if ((inset & inset_mask_map[i].inset) ==
9513                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9514                         inset_need_mask &= ~inset_mask_map[i].inset;
9515                 if (!inset_need_mask)
9516                         return 0;
9517         }
9518         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9519                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9520                     inset_mask_map[i].inset) {
9521                         if (idx >= nb_elem) {
9522                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9523                                 return -EINVAL;
9524                         }
9525                         mask[idx] = inset_mask_map[i].mask;
9526                         idx++;
9527                 }
9528         }
9529
9530         return idx;
9531 }
9532
9533 void
9534 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9535 {
9536         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9537
9538         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9539         if (reg != val)
9540                 i40e_write_rx_ctl(hw, addr, val);
9541         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9542                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9543 }
9544
9545 void
9546 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9547 {
9548         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9549         struct rte_eth_dev *dev;
9550
9551         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9552         if (reg != val) {
9553                 i40e_write_rx_ctl(hw, addr, val);
9554                 PMD_DRV_LOG(WARNING,
9555                             "i40e device %s changed global register [0x%08x]."
9556                             " original: 0x%08x, new: 0x%08x",
9557                             dev->device->name, addr, reg,
9558                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9559         }
9560 }
9561
9562 static void
9563 i40e_filter_input_set_init(struct i40e_pf *pf)
9564 {
9565         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9566         enum i40e_filter_pctype pctype;
9567         uint64_t input_set, inset_reg;
9568         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9569         int num, i;
9570         uint16_t flow_type;
9571
9572         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9573              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9574                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9575
9576                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9577                         continue;
9578
9579                 input_set = i40e_get_default_input_set(pctype);
9580
9581                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9582                                                    I40E_INSET_MASK_NUM_REG);
9583                 if (num < 0)
9584                         return;
9585                 if (pf->support_multi_driver && num > 0) {
9586                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9587                         return;
9588                 }
9589                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9590                                         input_set);
9591
9592                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9593                                       (uint32_t)(inset_reg & UINT32_MAX));
9594                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9595                                      (uint32_t)((inset_reg >>
9596                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9597                 if (!pf->support_multi_driver) {
9598                         i40e_check_write_global_reg(hw,
9599                                             I40E_GLQF_HASH_INSET(0, pctype),
9600                                             (uint32_t)(inset_reg & UINT32_MAX));
9601                         i40e_check_write_global_reg(hw,
9602                                              I40E_GLQF_HASH_INSET(1, pctype),
9603                                              (uint32_t)((inset_reg >>
9604                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9605
9606                         for (i = 0; i < num; i++) {
9607                                 i40e_check_write_global_reg(hw,
9608                                                     I40E_GLQF_FD_MSK(i, pctype),
9609                                                     mask_reg[i]);
9610                                 i40e_check_write_global_reg(hw,
9611                                                   I40E_GLQF_HASH_MSK(i, pctype),
9612                                                   mask_reg[i]);
9613                         }
9614                         /*clear unused mask registers of the pctype */
9615                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9616                                 i40e_check_write_global_reg(hw,
9617                                                     I40E_GLQF_FD_MSK(i, pctype),
9618                                                     0);
9619                                 i40e_check_write_global_reg(hw,
9620                                                   I40E_GLQF_HASH_MSK(i, pctype),
9621                                                   0);
9622                         }
9623                 } else {
9624                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9625                 }
9626                 I40E_WRITE_FLUSH(hw);
9627
9628                 /* store the default input set */
9629                 if (!pf->support_multi_driver)
9630                         pf->hash_input_set[pctype] = input_set;
9631                 pf->fdir.input_set[pctype] = input_set;
9632         }
9633 }
9634
9635 int
9636 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9637                          struct rte_eth_input_set_conf *conf)
9638 {
9639         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9640         enum i40e_filter_pctype pctype;
9641         uint64_t input_set, inset_reg = 0;
9642         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9643         int ret, i, num;
9644
9645         if (!conf) {
9646                 PMD_DRV_LOG(ERR, "Invalid pointer");
9647                 return -EFAULT;
9648         }
9649         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9650             conf->op != RTE_ETH_INPUT_SET_ADD) {
9651                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9652                 return -EINVAL;
9653         }
9654
9655         if (pf->support_multi_driver) {
9656                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9657                 return -ENOTSUP;
9658         }
9659
9660         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9661         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9662                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9663                 return -EINVAL;
9664         }
9665
9666         if (hw->mac.type == I40E_MAC_X722) {
9667                 /* get translated pctype value in fd pctype register */
9668                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9669                         I40E_GLQF_FD_PCTYPES((int)pctype));
9670         }
9671
9672         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9673                                    conf->inset_size);
9674         if (ret) {
9675                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9676                 return -EINVAL;
9677         }
9678
9679         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9680                 /* get inset value in register */
9681                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9682                 inset_reg <<= I40E_32_BIT_WIDTH;
9683                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9684                 input_set |= pf->hash_input_set[pctype];
9685         }
9686         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9687                                            I40E_INSET_MASK_NUM_REG);
9688         if (num < 0)
9689                 return -EINVAL;
9690
9691         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9692
9693         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9694                                     (uint32_t)(inset_reg & UINT32_MAX));
9695         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9696                                     (uint32_t)((inset_reg >>
9697                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9698
9699         for (i = 0; i < num; i++)
9700                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9701                                             mask_reg[i]);
9702         /*clear unused mask registers of the pctype */
9703         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9704                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9705                                             0);
9706         I40E_WRITE_FLUSH(hw);
9707
9708         pf->hash_input_set[pctype] = input_set;
9709         return 0;
9710 }
9711
9712 int
9713 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9714                          struct rte_eth_input_set_conf *conf)
9715 {
9716         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9717         enum i40e_filter_pctype pctype;
9718         uint64_t input_set, inset_reg = 0;
9719         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9720         int ret, i, num;
9721
9722         if (!hw || !conf) {
9723                 PMD_DRV_LOG(ERR, "Invalid pointer");
9724                 return -EFAULT;
9725         }
9726         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9727             conf->op != RTE_ETH_INPUT_SET_ADD) {
9728                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9729                 return -EINVAL;
9730         }
9731
9732         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9733
9734         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9735                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9736                 return -EINVAL;
9737         }
9738
9739         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9740                                    conf->inset_size);
9741         if (ret) {
9742                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9743                 return -EINVAL;
9744         }
9745
9746         /* get inset value in register */
9747         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9748         inset_reg <<= I40E_32_BIT_WIDTH;
9749         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9750
9751         /* Can not change the inset reg for flex payload for fdir,
9752          * it is done by writing I40E_PRTQF_FD_FLXINSET
9753          * in i40e_set_flex_mask_on_pctype.
9754          */
9755         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9756                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9757         else
9758                 input_set |= pf->fdir.input_set[pctype];
9759         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9760                                            I40E_INSET_MASK_NUM_REG);
9761         if (num < 0)
9762                 return -EINVAL;
9763         if (pf->support_multi_driver && num > 0) {
9764                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9765                 return -ENOTSUP;
9766         }
9767
9768         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9769
9770         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9771                               (uint32_t)(inset_reg & UINT32_MAX));
9772         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9773                              (uint32_t)((inset_reg >>
9774                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9775
9776         if (!pf->support_multi_driver) {
9777                 for (i = 0; i < num; i++)
9778                         i40e_check_write_global_reg(hw,
9779                                                     I40E_GLQF_FD_MSK(i, pctype),
9780                                                     mask_reg[i]);
9781                 /*clear unused mask registers of the pctype */
9782                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9783                         i40e_check_write_global_reg(hw,
9784                                                     I40E_GLQF_FD_MSK(i, pctype),
9785                                                     0);
9786         } else {
9787                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9788         }
9789         I40E_WRITE_FLUSH(hw);
9790
9791         pf->fdir.input_set[pctype] = input_set;
9792         return 0;
9793 }
9794
9795 static int
9796 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9797 {
9798         int ret = 0;
9799
9800         if (!hw || !info) {
9801                 PMD_DRV_LOG(ERR, "Invalid pointer");
9802                 return -EFAULT;
9803         }
9804
9805         switch (info->info_type) {
9806         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9807                 i40e_get_symmetric_hash_enable_per_port(hw,
9808                                         &(info->info.enable));
9809                 break;
9810         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9811                 ret = i40e_get_hash_filter_global_config(hw,
9812                                 &(info->info.global_conf));
9813                 break;
9814         default:
9815                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9816                                                         info->info_type);
9817                 ret = -EINVAL;
9818                 break;
9819         }
9820
9821         return ret;
9822 }
9823
9824 static int
9825 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9826 {
9827         int ret = 0;
9828
9829         if (!hw || !info) {
9830                 PMD_DRV_LOG(ERR, "Invalid pointer");
9831                 return -EFAULT;
9832         }
9833
9834         switch (info->info_type) {
9835         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9836                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9837                 break;
9838         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9839                 ret = i40e_set_hash_filter_global_config(hw,
9840                                 &(info->info.global_conf));
9841                 break;
9842         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9843                 ret = i40e_hash_filter_inset_select(hw,
9844                                                &(info->info.input_set_conf));
9845                 break;
9846
9847         default:
9848                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9849                                                         info->info_type);
9850                 ret = -EINVAL;
9851                 break;
9852         }
9853
9854         return ret;
9855 }
9856
9857 /* Operations for hash function */
9858 static int
9859 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9860                       enum rte_filter_op filter_op,
9861                       void *arg)
9862 {
9863         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9864         int ret = 0;
9865
9866         switch (filter_op) {
9867         case RTE_ETH_FILTER_NOP:
9868                 break;
9869         case RTE_ETH_FILTER_GET:
9870                 ret = i40e_hash_filter_get(hw,
9871                         (struct rte_eth_hash_filter_info *)arg);
9872                 break;
9873         case RTE_ETH_FILTER_SET:
9874                 ret = i40e_hash_filter_set(hw,
9875                         (struct rte_eth_hash_filter_info *)arg);
9876                 break;
9877         default:
9878                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9879                                                                 filter_op);
9880                 ret = -ENOTSUP;
9881                 break;
9882         }
9883
9884         return ret;
9885 }
9886
9887 /* Convert ethertype filter structure */
9888 static int
9889 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9890                               struct i40e_ethertype_filter *filter)
9891 {
9892         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9893         filter->input.ether_type = input->ether_type;
9894         filter->flags = input->flags;
9895         filter->queue = input->queue;
9896
9897         return 0;
9898 }
9899
9900 /* Check if there exists the ehtertype filter */
9901 struct i40e_ethertype_filter *
9902 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9903                                 const struct i40e_ethertype_filter_input *input)
9904 {
9905         int ret;
9906
9907         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9908         if (ret < 0)
9909                 return NULL;
9910
9911         return ethertype_rule->hash_map[ret];
9912 }
9913
9914 /* Add ethertype filter in SW list */
9915 static int
9916 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9917                                 struct i40e_ethertype_filter *filter)
9918 {
9919         struct i40e_ethertype_rule *rule = &pf->ethertype;
9920         int ret;
9921
9922         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9923         if (ret < 0) {
9924                 PMD_DRV_LOG(ERR,
9925                             "Failed to insert ethertype filter"
9926                             " to hash table %d!",
9927                             ret);
9928                 return ret;
9929         }
9930         rule->hash_map[ret] = filter;
9931
9932         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9933
9934         return 0;
9935 }
9936
9937 /* Delete ethertype filter in SW list */
9938 int
9939 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9940                              struct i40e_ethertype_filter_input *input)
9941 {
9942         struct i40e_ethertype_rule *rule = &pf->ethertype;
9943         struct i40e_ethertype_filter *filter;
9944         int ret;
9945
9946         ret = rte_hash_del_key(rule->hash_table, input);
9947         if (ret < 0) {
9948                 PMD_DRV_LOG(ERR,
9949                             "Failed to delete ethertype filter"
9950                             " to hash table %d!",
9951                             ret);
9952                 return ret;
9953         }
9954         filter = rule->hash_map[ret];
9955         rule->hash_map[ret] = NULL;
9956
9957         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9958         rte_free(filter);
9959
9960         return 0;
9961 }
9962
9963 /*
9964  * Configure ethertype filter, which can director packet by filtering
9965  * with mac address and ether_type or only ether_type
9966  */
9967 int
9968 i40e_ethertype_filter_set(struct i40e_pf *pf,
9969                         struct rte_eth_ethertype_filter *filter,
9970                         bool add)
9971 {
9972         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9973         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9974         struct i40e_ethertype_filter *ethertype_filter, *node;
9975         struct i40e_ethertype_filter check_filter;
9976         struct i40e_control_filter_stats stats;
9977         uint16_t flags = 0;
9978         int ret;
9979
9980         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9981                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9982                 return -EINVAL;
9983         }
9984         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9985                 filter->ether_type == ETHER_TYPE_IPv6) {
9986                 PMD_DRV_LOG(ERR,
9987                         "unsupported ether_type(0x%04x) in control packet filter.",
9988                         filter->ether_type);
9989                 return -EINVAL;
9990         }
9991         if (filter->ether_type == ETHER_TYPE_VLAN)
9992                 PMD_DRV_LOG(WARNING,
9993                         "filter vlan ether_type in first tag is not supported.");
9994
9995         /* Check if there is the filter in SW list */
9996         memset(&check_filter, 0, sizeof(check_filter));
9997         i40e_ethertype_filter_convert(filter, &check_filter);
9998         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9999                                                &check_filter.input);
10000         if (add && node) {
10001                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10002                 return -EINVAL;
10003         }
10004
10005         if (!add && !node) {
10006                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10007                 return -EINVAL;
10008         }
10009
10010         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10011                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10012         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10013                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10014         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10015
10016         memset(&stats, 0, sizeof(stats));
10017         ret = i40e_aq_add_rem_control_packet_filter(hw,
10018                         filter->mac_addr.addr_bytes,
10019                         filter->ether_type, flags,
10020                         pf->main_vsi->seid,
10021                         filter->queue, add, &stats, NULL);
10022
10023         PMD_DRV_LOG(INFO,
10024                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10025                 ret, stats.mac_etype_used, stats.etype_used,
10026                 stats.mac_etype_free, stats.etype_free);
10027         if (ret < 0)
10028                 return -ENOSYS;
10029
10030         /* Add or delete a filter in SW list */
10031         if (add) {
10032                 ethertype_filter = rte_zmalloc("ethertype_filter",
10033                                        sizeof(*ethertype_filter), 0);
10034                 if (ethertype_filter == NULL) {
10035                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10036                         return -ENOMEM;
10037                 }
10038
10039                 rte_memcpy(ethertype_filter, &check_filter,
10040                            sizeof(check_filter));
10041                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10042                 if (ret < 0)
10043                         rte_free(ethertype_filter);
10044         } else {
10045                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10046         }
10047
10048         return ret;
10049 }
10050
10051 /*
10052  * Handle operations for ethertype filter.
10053  */
10054 static int
10055 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10056                                 enum rte_filter_op filter_op,
10057                                 void *arg)
10058 {
10059         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10060         int ret = 0;
10061
10062         if (filter_op == RTE_ETH_FILTER_NOP)
10063                 return ret;
10064
10065         if (arg == NULL) {
10066                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10067                             filter_op);
10068                 return -EINVAL;
10069         }
10070
10071         switch (filter_op) {
10072         case RTE_ETH_FILTER_ADD:
10073                 ret = i40e_ethertype_filter_set(pf,
10074                         (struct rte_eth_ethertype_filter *)arg,
10075                         TRUE);
10076                 break;
10077         case RTE_ETH_FILTER_DELETE:
10078                 ret = i40e_ethertype_filter_set(pf,
10079                         (struct rte_eth_ethertype_filter *)arg,
10080                         FALSE);
10081                 break;
10082         default:
10083                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10084                 ret = -ENOSYS;
10085                 break;
10086         }
10087         return ret;
10088 }
10089
10090 static int
10091 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10092                      enum rte_filter_type filter_type,
10093                      enum rte_filter_op filter_op,
10094                      void *arg)
10095 {
10096         int ret = 0;
10097
10098         if (dev == NULL)
10099                 return -EINVAL;
10100
10101         switch (filter_type) {
10102         case RTE_ETH_FILTER_NONE:
10103                 /* For global configuration */
10104                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10105                 break;
10106         case RTE_ETH_FILTER_HASH:
10107                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10108                 break;
10109         case RTE_ETH_FILTER_MACVLAN:
10110                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10111                 break;
10112         case RTE_ETH_FILTER_ETHERTYPE:
10113                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10114                 break;
10115         case RTE_ETH_FILTER_TUNNEL:
10116                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10117                 break;
10118         case RTE_ETH_FILTER_FDIR:
10119                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10120                 break;
10121         case RTE_ETH_FILTER_GENERIC:
10122                 if (filter_op != RTE_ETH_FILTER_GET)
10123                         return -EINVAL;
10124                 *(const void **)arg = &i40e_flow_ops;
10125                 break;
10126         default:
10127                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10128                                                         filter_type);
10129                 ret = -EINVAL;
10130                 break;
10131         }
10132
10133         return ret;
10134 }
10135
10136 /*
10137  * Check and enable Extended Tag.
10138  * Enabling Extended Tag is important for 40G performance.
10139  */
10140 static void
10141 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10142 {
10143         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10144         uint32_t buf = 0;
10145         int ret;
10146
10147         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10148                                       PCI_DEV_CAP_REG);
10149         if (ret < 0) {
10150                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10151                             PCI_DEV_CAP_REG);
10152                 return;
10153         }
10154         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10155                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10156                 return;
10157         }
10158
10159         buf = 0;
10160         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10161                                       PCI_DEV_CTRL_REG);
10162         if (ret < 0) {
10163                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10164                             PCI_DEV_CTRL_REG);
10165                 return;
10166         }
10167         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10168                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10169                 return;
10170         }
10171         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10172         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10173                                        PCI_DEV_CTRL_REG);
10174         if (ret < 0) {
10175                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10176                             PCI_DEV_CTRL_REG);
10177                 return;
10178         }
10179 }
10180
10181 /*
10182  * As some registers wouldn't be reset unless a global hardware reset,
10183  * hardware initialization is needed to put those registers into an
10184  * expected initial state.
10185  */
10186 static void
10187 i40e_hw_init(struct rte_eth_dev *dev)
10188 {
10189         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10190
10191         i40e_enable_extended_tag(dev);
10192
10193         /* clear the PF Queue Filter control register */
10194         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10195
10196         /* Disable symmetric hash per port */
10197         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10198 }
10199
10200 /*
10201  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10202  * however this function will return only one highest pctype index,
10203  * which is not quite correct. This is known problem of i40e driver
10204  * and needs to be fixed later.
10205  */
10206 enum i40e_filter_pctype
10207 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10208 {
10209         int i;
10210         uint64_t pctype_mask;
10211
10212         if (flow_type < I40E_FLOW_TYPE_MAX) {
10213                 pctype_mask = adapter->pctypes_tbl[flow_type];
10214                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10215                         if (pctype_mask & (1ULL << i))
10216                                 return (enum i40e_filter_pctype)i;
10217                 }
10218         }
10219         return I40E_FILTER_PCTYPE_INVALID;
10220 }
10221
10222 uint16_t
10223 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10224                         enum i40e_filter_pctype pctype)
10225 {
10226         uint16_t flowtype;
10227         uint64_t pctype_mask = 1ULL << pctype;
10228
10229         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10230              flowtype++) {
10231                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10232                         return flowtype;
10233         }
10234
10235         return RTE_ETH_FLOW_UNKNOWN;
10236 }
10237
10238 /*
10239  * On X710, performance number is far from the expectation on recent firmware
10240  * versions; on XL710, performance number is also far from the expectation on
10241  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10242  * mode is enabled and port MAC address is equal to the packet destination MAC
10243  * address. The fix for this issue may not be integrated in the following
10244  * firmware version. So the workaround in software driver is needed. It needs
10245  * to modify the initial values of 3 internal only registers for both X710 and
10246  * XL710. Note that the values for X710 or XL710 could be different, and the
10247  * workaround can be removed when it is fixed in firmware in the future.
10248  */
10249
10250 /* For both X710 and XL710 */
10251 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10252 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10253 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10254
10255 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10256 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10257
10258 /* For X722 */
10259 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10260 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10261
10262 /* For X710 */
10263 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10264 /* For XL710 */
10265 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10266 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10267
10268 /*
10269  * GL_SWR_PM_UP_THR:
10270  * The value is not impacted from the link speed, its value is set according
10271  * to the total number of ports for a better pipe-monitor configuration.
10272  */
10273 static bool
10274 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10275 {
10276 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10277                 .device_id = (dev),   \
10278                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10279
10280 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10281                 .device_id = (dev),   \
10282                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10283
10284         static const struct {
10285                 uint16_t device_id;
10286                 uint32_t val;
10287         } swr_pm_table[] = {
10288                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10289                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10290                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10291                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10292
10293                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10294                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10295                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10296                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10297                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10298                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10299                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10300         };
10301         uint32_t i;
10302
10303         if (value == NULL) {
10304                 PMD_DRV_LOG(ERR, "value is NULL");
10305                 return false;
10306         }
10307
10308         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10309                 if (hw->device_id == swr_pm_table[i].device_id) {
10310                         *value = swr_pm_table[i].val;
10311
10312                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10313                                     "value - 0x%08x",
10314                                     hw->device_id, *value);
10315                         return true;
10316                 }
10317         }
10318
10319         return false;
10320 }
10321
10322 static int
10323 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10324 {
10325         enum i40e_status_code status;
10326         struct i40e_aq_get_phy_abilities_resp phy_ab;
10327         int ret = -ENOTSUP;
10328         int retries = 0;
10329
10330         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10331                                               NULL);
10332
10333         while (status) {
10334                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10335                         status);
10336                 retries++;
10337                 rte_delay_us(100000);
10338                 if  (retries < 5)
10339                         status = i40e_aq_get_phy_capabilities(hw, false,
10340                                         true, &phy_ab, NULL);
10341                 else
10342                         return ret;
10343         }
10344         return 0;
10345 }
10346
10347 static void
10348 i40e_configure_registers(struct i40e_hw *hw)
10349 {
10350         static struct {
10351                 uint32_t addr;
10352                 uint64_t val;
10353         } reg_table[] = {
10354                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10355                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10356                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10357         };
10358         uint64_t reg;
10359         uint32_t i;
10360         int ret;
10361
10362         for (i = 0; i < RTE_DIM(reg_table); i++) {
10363                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10364                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10365                                 reg_table[i].val =
10366                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10367                         else /* For X710/XL710/XXV710 */
10368                                 if (hw->aq.fw_maj_ver < 6)
10369                                         reg_table[i].val =
10370                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10371                                 else
10372                                         reg_table[i].val =
10373                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10374                 }
10375
10376                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10377                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10378                                 reg_table[i].val =
10379                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10380                         else /* For X710/XL710/XXV710 */
10381                                 reg_table[i].val =
10382                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10383                 }
10384
10385                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10386                         uint32_t cfg_val;
10387
10388                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10389                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10390                                             "GL_SWR_PM_UP_THR value fixup",
10391                                             hw->device_id);
10392                                 continue;
10393                         }
10394
10395                         reg_table[i].val = cfg_val;
10396                 }
10397
10398                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10399                                                         &reg, NULL);
10400                 if (ret < 0) {
10401                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10402                                                         reg_table[i].addr);
10403                         break;
10404                 }
10405                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10406                                                 reg_table[i].addr, reg);
10407                 if (reg == reg_table[i].val)
10408                         continue;
10409
10410                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10411                                                 reg_table[i].val, NULL);
10412                 if (ret < 0) {
10413                         PMD_DRV_LOG(ERR,
10414                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10415                                 reg_table[i].val, reg_table[i].addr);
10416                         break;
10417                 }
10418                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10419                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10420         }
10421 }
10422
10423 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10424 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10425 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10426 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10427 static int
10428 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10429 {
10430         uint32_t reg;
10431         int ret;
10432
10433         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10434                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10435                 return -EINVAL;
10436         }
10437
10438         /* Configure for double VLAN RX stripping */
10439         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10440         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10441                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10442                 ret = i40e_aq_debug_write_register(hw,
10443                                                    I40E_VSI_TSR(vsi->vsi_id),
10444                                                    reg, NULL);
10445                 if (ret < 0) {
10446                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10447                                     vsi->vsi_id);
10448                         return I40E_ERR_CONFIG;
10449                 }
10450         }
10451
10452         /* Configure for double VLAN TX insertion */
10453         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10454         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10455                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10456                 ret = i40e_aq_debug_write_register(hw,
10457                                                    I40E_VSI_L2TAGSTXVALID(
10458                                                    vsi->vsi_id), reg, NULL);
10459                 if (ret < 0) {
10460                         PMD_DRV_LOG(ERR,
10461                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10462                                 vsi->vsi_id);
10463                         return I40E_ERR_CONFIG;
10464                 }
10465         }
10466
10467         return 0;
10468 }
10469
10470 /**
10471  * i40e_aq_add_mirror_rule
10472  * @hw: pointer to the hardware structure
10473  * @seid: VEB seid to add mirror rule to
10474  * @dst_id: destination vsi seid
10475  * @entries: Buffer which contains the entities to be mirrored
10476  * @count: number of entities contained in the buffer
10477  * @rule_id:the rule_id of the rule to be added
10478  *
10479  * Add a mirror rule for a given veb.
10480  *
10481  **/
10482 static enum i40e_status_code
10483 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10484                         uint16_t seid, uint16_t dst_id,
10485                         uint16_t rule_type, uint16_t *entries,
10486                         uint16_t count, uint16_t *rule_id)
10487 {
10488         struct i40e_aq_desc desc;
10489         struct i40e_aqc_add_delete_mirror_rule cmd;
10490         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10491                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10492                 &desc.params.raw;
10493         uint16_t buff_len;
10494         enum i40e_status_code status;
10495
10496         i40e_fill_default_direct_cmd_desc(&desc,
10497                                           i40e_aqc_opc_add_mirror_rule);
10498         memset(&cmd, 0, sizeof(cmd));
10499
10500         buff_len = sizeof(uint16_t) * count;
10501         desc.datalen = rte_cpu_to_le_16(buff_len);
10502         if (buff_len > 0)
10503                 desc.flags |= rte_cpu_to_le_16(
10504                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10505         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10506                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10507         cmd.num_entries = rte_cpu_to_le_16(count);
10508         cmd.seid = rte_cpu_to_le_16(seid);
10509         cmd.destination = rte_cpu_to_le_16(dst_id);
10510
10511         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10512         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10513         PMD_DRV_LOG(INFO,
10514                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10515                 hw->aq.asq_last_status, resp->rule_id,
10516                 resp->mirror_rules_used, resp->mirror_rules_free);
10517         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10518
10519         return status;
10520 }
10521
10522 /**
10523  * i40e_aq_del_mirror_rule
10524  * @hw: pointer to the hardware structure
10525  * @seid: VEB seid to add mirror rule to
10526  * @entries: Buffer which contains the entities to be mirrored
10527  * @count: number of entities contained in the buffer
10528  * @rule_id:the rule_id of the rule to be delete
10529  *
10530  * Delete a mirror rule for a given veb.
10531  *
10532  **/
10533 static enum i40e_status_code
10534 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10535                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10536                 uint16_t count, uint16_t rule_id)
10537 {
10538         struct i40e_aq_desc desc;
10539         struct i40e_aqc_add_delete_mirror_rule cmd;
10540         uint16_t buff_len = 0;
10541         enum i40e_status_code status;
10542         void *buff = NULL;
10543
10544         i40e_fill_default_direct_cmd_desc(&desc,
10545                                           i40e_aqc_opc_delete_mirror_rule);
10546         memset(&cmd, 0, sizeof(cmd));
10547         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10548                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10549                                                           I40E_AQ_FLAG_RD));
10550                 cmd.num_entries = count;
10551                 buff_len = sizeof(uint16_t) * count;
10552                 desc.datalen = rte_cpu_to_le_16(buff_len);
10553                 buff = (void *)entries;
10554         } else
10555                 /* rule id is filled in destination field for deleting mirror rule */
10556                 cmd.destination = rte_cpu_to_le_16(rule_id);
10557
10558         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10559                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10560         cmd.seid = rte_cpu_to_le_16(seid);
10561
10562         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10563         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10564
10565         return status;
10566 }
10567
10568 /**
10569  * i40e_mirror_rule_set
10570  * @dev: pointer to the hardware structure
10571  * @mirror_conf: mirror rule info
10572  * @sw_id: mirror rule's sw_id
10573  * @on: enable/disable
10574  *
10575  * set a mirror rule.
10576  *
10577  **/
10578 static int
10579 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10580                         struct rte_eth_mirror_conf *mirror_conf,
10581                         uint8_t sw_id, uint8_t on)
10582 {
10583         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10584         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10585         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10586         struct i40e_mirror_rule *parent = NULL;
10587         uint16_t seid, dst_seid, rule_id;
10588         uint16_t i, j = 0;
10589         int ret;
10590
10591         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10592
10593         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10594                 PMD_DRV_LOG(ERR,
10595                         "mirror rule can not be configured without veb or vfs.");
10596                 return -ENOSYS;
10597         }
10598         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10599                 PMD_DRV_LOG(ERR, "mirror table is full.");
10600                 return -ENOSPC;
10601         }
10602         if (mirror_conf->dst_pool > pf->vf_num) {
10603                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10604                                  mirror_conf->dst_pool);
10605                 return -EINVAL;
10606         }
10607
10608         seid = pf->main_vsi->veb->seid;
10609
10610         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10611                 if (sw_id <= it->index) {
10612                         mirr_rule = it;
10613                         break;
10614                 }
10615                 parent = it;
10616         }
10617         if (mirr_rule && sw_id == mirr_rule->index) {
10618                 if (on) {
10619                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10620                         return -EEXIST;
10621                 } else {
10622                         ret = i40e_aq_del_mirror_rule(hw, seid,
10623                                         mirr_rule->rule_type,
10624                                         mirr_rule->entries,
10625                                         mirr_rule->num_entries, mirr_rule->id);
10626                         if (ret < 0) {
10627                                 PMD_DRV_LOG(ERR,
10628                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10629                                         ret, hw->aq.asq_last_status);
10630                                 return -ENOSYS;
10631                         }
10632                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10633                         rte_free(mirr_rule);
10634                         pf->nb_mirror_rule--;
10635                         return 0;
10636                 }
10637         } else if (!on) {
10638                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10639                 return -ENOENT;
10640         }
10641
10642         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10643                                 sizeof(struct i40e_mirror_rule) , 0);
10644         if (!mirr_rule) {
10645                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10646                 return I40E_ERR_NO_MEMORY;
10647         }
10648         switch (mirror_conf->rule_type) {
10649         case ETH_MIRROR_VLAN:
10650                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10651                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10652                                 mirr_rule->entries[j] =
10653                                         mirror_conf->vlan.vlan_id[i];
10654                                 j++;
10655                         }
10656                 }
10657                 if (j == 0) {
10658                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10659                         rte_free(mirr_rule);
10660                         return -EINVAL;
10661                 }
10662                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10663                 break;
10664         case ETH_MIRROR_VIRTUAL_POOL_UP:
10665         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10666                 /* check if the specified pool bit is out of range */
10667                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10668                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10669                         rte_free(mirr_rule);
10670                         return -EINVAL;
10671                 }
10672                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10673                         if (mirror_conf->pool_mask & (1ULL << i)) {
10674                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10675                                 j++;
10676                         }
10677                 }
10678                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10679                         /* add pf vsi to entries */
10680                         mirr_rule->entries[j] = pf->main_vsi_seid;
10681                         j++;
10682                 }
10683                 if (j == 0) {
10684                         PMD_DRV_LOG(ERR, "pool is not specified.");
10685                         rte_free(mirr_rule);
10686                         return -EINVAL;
10687                 }
10688                 /* egress and ingress in aq commands means from switch but not port */
10689                 mirr_rule->rule_type =
10690                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10691                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10692                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10693                 break;
10694         case ETH_MIRROR_UPLINK_PORT:
10695                 /* egress and ingress in aq commands means from switch but not port*/
10696                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10697                 break;
10698         case ETH_MIRROR_DOWNLINK_PORT:
10699                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10700                 break;
10701         default:
10702                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10703                         mirror_conf->rule_type);
10704                 rte_free(mirr_rule);
10705                 return -EINVAL;
10706         }
10707
10708         /* If the dst_pool is equal to vf_num, consider it as PF */
10709         if (mirror_conf->dst_pool == pf->vf_num)
10710                 dst_seid = pf->main_vsi_seid;
10711         else
10712                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10713
10714         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10715                                       mirr_rule->rule_type, mirr_rule->entries,
10716                                       j, &rule_id);
10717         if (ret < 0) {
10718                 PMD_DRV_LOG(ERR,
10719                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10720                         ret, hw->aq.asq_last_status);
10721                 rte_free(mirr_rule);
10722                 return -ENOSYS;
10723         }
10724
10725         mirr_rule->index = sw_id;
10726         mirr_rule->num_entries = j;
10727         mirr_rule->id = rule_id;
10728         mirr_rule->dst_vsi_seid = dst_seid;
10729
10730         if (parent)
10731                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10732         else
10733                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10734
10735         pf->nb_mirror_rule++;
10736         return 0;
10737 }
10738
10739 /**
10740  * i40e_mirror_rule_reset
10741  * @dev: pointer to the device
10742  * @sw_id: mirror rule's sw_id
10743  *
10744  * reset a mirror rule.
10745  *
10746  **/
10747 static int
10748 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10749 {
10750         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10751         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10752         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10753         uint16_t seid;
10754         int ret;
10755
10756         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10757
10758         seid = pf->main_vsi->veb->seid;
10759
10760         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10761                 if (sw_id == it->index) {
10762                         mirr_rule = it;
10763                         break;
10764                 }
10765         }
10766         if (mirr_rule) {
10767                 ret = i40e_aq_del_mirror_rule(hw, seid,
10768                                 mirr_rule->rule_type,
10769                                 mirr_rule->entries,
10770                                 mirr_rule->num_entries, mirr_rule->id);
10771                 if (ret < 0) {
10772                         PMD_DRV_LOG(ERR,
10773                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10774                                 ret, hw->aq.asq_last_status);
10775                         return -ENOSYS;
10776                 }
10777                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10778                 rte_free(mirr_rule);
10779                 pf->nb_mirror_rule--;
10780         } else {
10781                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10782                 return -ENOENT;
10783         }
10784         return 0;
10785 }
10786
10787 static uint64_t
10788 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10789 {
10790         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10791         uint64_t systim_cycles;
10792
10793         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10794         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10795                         << 32;
10796
10797         return systim_cycles;
10798 }
10799
10800 static uint64_t
10801 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10802 {
10803         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10804         uint64_t rx_tstamp;
10805
10806         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10807         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10808                         << 32;
10809
10810         return rx_tstamp;
10811 }
10812
10813 static uint64_t
10814 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10815 {
10816         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10817         uint64_t tx_tstamp;
10818
10819         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10820         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10821                         << 32;
10822
10823         return tx_tstamp;
10824 }
10825
10826 static void
10827 i40e_start_timecounters(struct rte_eth_dev *dev)
10828 {
10829         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10830         struct i40e_adapter *adapter =
10831                         (struct i40e_adapter *)dev->data->dev_private;
10832         struct rte_eth_link link;
10833         uint32_t tsync_inc_l;
10834         uint32_t tsync_inc_h;
10835
10836         /* Get current link speed. */
10837         i40e_dev_link_update(dev, 1);
10838         rte_eth_linkstatus_get(dev, &link);
10839
10840         switch (link.link_speed) {
10841         case ETH_SPEED_NUM_40G:
10842         case ETH_SPEED_NUM_25G:
10843                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10844                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10845                 break;
10846         case ETH_SPEED_NUM_10G:
10847                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10848                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10849                 break;
10850         case ETH_SPEED_NUM_1G:
10851                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10852                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10853                 break;
10854         default:
10855                 tsync_inc_l = 0x0;
10856                 tsync_inc_h = 0x0;
10857         }
10858
10859         /* Set the timesync increment value. */
10860         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10861         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10862
10863         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10864         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10865         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10866
10867         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10868         adapter->systime_tc.cc_shift = 0;
10869         adapter->systime_tc.nsec_mask = 0;
10870
10871         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10872         adapter->rx_tstamp_tc.cc_shift = 0;
10873         adapter->rx_tstamp_tc.nsec_mask = 0;
10874
10875         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10876         adapter->tx_tstamp_tc.cc_shift = 0;
10877         adapter->tx_tstamp_tc.nsec_mask = 0;
10878 }
10879
10880 static int
10881 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10882 {
10883         struct i40e_adapter *adapter =
10884                         (struct i40e_adapter *)dev->data->dev_private;
10885
10886         adapter->systime_tc.nsec += delta;
10887         adapter->rx_tstamp_tc.nsec += delta;
10888         adapter->tx_tstamp_tc.nsec += delta;
10889
10890         return 0;
10891 }
10892
10893 static int
10894 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10895 {
10896         uint64_t ns;
10897         struct i40e_adapter *adapter =
10898                         (struct i40e_adapter *)dev->data->dev_private;
10899
10900         ns = rte_timespec_to_ns(ts);
10901
10902         /* Set the timecounters to a new value. */
10903         adapter->systime_tc.nsec = ns;
10904         adapter->rx_tstamp_tc.nsec = ns;
10905         adapter->tx_tstamp_tc.nsec = ns;
10906
10907         return 0;
10908 }
10909
10910 static int
10911 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10912 {
10913         uint64_t ns, systime_cycles;
10914         struct i40e_adapter *adapter =
10915                         (struct i40e_adapter *)dev->data->dev_private;
10916
10917         systime_cycles = i40e_read_systime_cyclecounter(dev);
10918         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10919         *ts = rte_ns_to_timespec(ns);
10920
10921         return 0;
10922 }
10923
10924 static int
10925 i40e_timesync_enable(struct rte_eth_dev *dev)
10926 {
10927         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10928         uint32_t tsync_ctl_l;
10929         uint32_t tsync_ctl_h;
10930
10931         /* Stop the timesync system time. */
10932         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10933         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10934         /* Reset the timesync system time value. */
10935         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10936         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10937
10938         i40e_start_timecounters(dev);
10939
10940         /* Clear timesync registers. */
10941         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10942         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10943         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10944         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10945         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10946         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10947
10948         /* Enable timestamping of PTP packets. */
10949         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10950         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10951
10952         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10953         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10954         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10955
10956         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10957         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10958
10959         return 0;
10960 }
10961
10962 static int
10963 i40e_timesync_disable(struct rte_eth_dev *dev)
10964 {
10965         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10966         uint32_t tsync_ctl_l;
10967         uint32_t tsync_ctl_h;
10968
10969         /* Disable timestamping of transmitted PTP packets. */
10970         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10971         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10972
10973         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10974         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10975
10976         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10977         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10978
10979         /* Reset the timesync increment value. */
10980         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10981         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10982
10983         return 0;
10984 }
10985
10986 static int
10987 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10988                                 struct timespec *timestamp, uint32_t flags)
10989 {
10990         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10991         struct i40e_adapter *adapter =
10992                 (struct i40e_adapter *)dev->data->dev_private;
10993
10994         uint32_t sync_status;
10995         uint32_t index = flags & 0x03;
10996         uint64_t rx_tstamp_cycles;
10997         uint64_t ns;
10998
10999         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11000         if ((sync_status & (1 << index)) == 0)
11001                 return -EINVAL;
11002
11003         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11004         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11005         *timestamp = rte_ns_to_timespec(ns);
11006
11007         return 0;
11008 }
11009
11010 static int
11011 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11012                                 struct timespec *timestamp)
11013 {
11014         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11015         struct i40e_adapter *adapter =
11016                 (struct i40e_adapter *)dev->data->dev_private;
11017
11018         uint32_t sync_status;
11019         uint64_t tx_tstamp_cycles;
11020         uint64_t ns;
11021
11022         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11023         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11024                 return -EINVAL;
11025
11026         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11027         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11028         *timestamp = rte_ns_to_timespec(ns);
11029
11030         return 0;
11031 }
11032
11033 /*
11034  * i40e_parse_dcb_configure - parse dcb configure from user
11035  * @dev: the device being configured
11036  * @dcb_cfg: pointer of the result of parse
11037  * @*tc_map: bit map of enabled traffic classes
11038  *
11039  * Returns 0 on success, negative value on failure
11040  */
11041 static int
11042 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11043                          struct i40e_dcbx_config *dcb_cfg,
11044                          uint8_t *tc_map)
11045 {
11046         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11047         uint8_t i, tc_bw, bw_lf;
11048
11049         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11050
11051         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11052         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11053                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11054                 return -EINVAL;
11055         }
11056
11057         /* assume each tc has the same bw */
11058         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11059         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11060                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11061         /* to ensure the sum of tcbw is equal to 100 */
11062         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11063         for (i = 0; i < bw_lf; i++)
11064                 dcb_cfg->etscfg.tcbwtable[i]++;
11065
11066         /* assume each tc has the same Transmission Selection Algorithm */
11067         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11068                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11069
11070         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11071                 dcb_cfg->etscfg.prioritytable[i] =
11072                                 dcb_rx_conf->dcb_tc[i];
11073
11074         /* FW needs one App to configure HW */
11075         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11076         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11077         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11078         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11079
11080         if (dcb_rx_conf->nb_tcs == 0)
11081                 *tc_map = 1; /* tc0 only */
11082         else
11083                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11084
11085         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11086                 dcb_cfg->pfc.willing = 0;
11087                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11088                 dcb_cfg->pfc.pfcenable = *tc_map;
11089         }
11090         return 0;
11091 }
11092
11093
11094 static enum i40e_status_code
11095 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11096                               struct i40e_aqc_vsi_properties_data *info,
11097                               uint8_t enabled_tcmap)
11098 {
11099         enum i40e_status_code ret;
11100         int i, total_tc = 0;
11101         uint16_t qpnum_per_tc, bsf, qp_idx;
11102         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11103         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11104         uint16_t used_queues;
11105
11106         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11107         if (ret != I40E_SUCCESS)
11108                 return ret;
11109
11110         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11111                 if (enabled_tcmap & (1 << i))
11112                         total_tc++;
11113         }
11114         if (total_tc == 0)
11115                 total_tc = 1;
11116         vsi->enabled_tc = enabled_tcmap;
11117
11118         /* different VSI has different queues assigned */
11119         if (vsi->type == I40E_VSI_MAIN)
11120                 used_queues = dev_data->nb_rx_queues -
11121                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11122         else if (vsi->type == I40E_VSI_VMDQ2)
11123                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11124         else {
11125                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11126                 return I40E_ERR_NO_AVAILABLE_VSI;
11127         }
11128
11129         qpnum_per_tc = used_queues / total_tc;
11130         /* Number of queues per enabled TC */
11131         if (qpnum_per_tc == 0) {
11132                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11133                 return I40E_ERR_INVALID_QP_ID;
11134         }
11135         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11136                                 I40E_MAX_Q_PER_TC);
11137         bsf = rte_bsf32(qpnum_per_tc);
11138
11139         /**
11140          * Configure TC and queue mapping parameters, for enabled TC,
11141          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11142          * default queue will serve it.
11143          */
11144         qp_idx = 0;
11145         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11146                 if (vsi->enabled_tc & (1 << i)) {
11147                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11148                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11149                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11150                         qp_idx += qpnum_per_tc;
11151                 } else
11152                         info->tc_mapping[i] = 0;
11153         }
11154
11155         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11156         if (vsi->type == I40E_VSI_SRIOV) {
11157                 info->mapping_flags |=
11158                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11159                 for (i = 0; i < vsi->nb_qps; i++)
11160                         info->queue_mapping[i] =
11161                                 rte_cpu_to_le_16(vsi->base_queue + i);
11162         } else {
11163                 info->mapping_flags |=
11164                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11165                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11166         }
11167         info->valid_sections |=
11168                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11169
11170         return I40E_SUCCESS;
11171 }
11172
11173 /*
11174  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11175  * @veb: VEB to be configured
11176  * @tc_map: enabled TC bitmap
11177  *
11178  * Returns 0 on success, negative value on failure
11179  */
11180 static enum i40e_status_code
11181 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11182 {
11183         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11184         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11185         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11186         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11187         enum i40e_status_code ret = I40E_SUCCESS;
11188         int i;
11189         uint32_t bw_max;
11190
11191         /* Check if enabled_tc is same as existing or new TCs */
11192         if (veb->enabled_tc == tc_map)
11193                 return ret;
11194
11195         /* configure tc bandwidth */
11196         memset(&veb_bw, 0, sizeof(veb_bw));
11197         veb_bw.tc_valid_bits = tc_map;
11198         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11199         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11200                 if (tc_map & BIT_ULL(i))
11201                         veb_bw.tc_bw_share_credits[i] = 1;
11202         }
11203         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11204                                                    &veb_bw, NULL);
11205         if (ret) {
11206                 PMD_INIT_LOG(ERR,
11207                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11208                         hw->aq.asq_last_status);
11209                 return ret;
11210         }
11211
11212         memset(&ets_query, 0, sizeof(ets_query));
11213         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11214                                                    &ets_query, NULL);
11215         if (ret != I40E_SUCCESS) {
11216                 PMD_DRV_LOG(ERR,
11217                         "Failed to get switch_comp ETS configuration %u",
11218                         hw->aq.asq_last_status);
11219                 return ret;
11220         }
11221         memset(&bw_query, 0, sizeof(bw_query));
11222         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11223                                                   &bw_query, NULL);
11224         if (ret != I40E_SUCCESS) {
11225                 PMD_DRV_LOG(ERR,
11226                         "Failed to get switch_comp bandwidth configuration %u",
11227                         hw->aq.asq_last_status);
11228                 return ret;
11229         }
11230
11231         /* store and print out BW info */
11232         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11233         veb->bw_info.bw_max = ets_query.tc_bw_max;
11234         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11235         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11236         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11237                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11238                      I40E_16_BIT_WIDTH);
11239         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11240                 veb->bw_info.bw_ets_share_credits[i] =
11241                                 bw_query.tc_bw_share_credits[i];
11242                 veb->bw_info.bw_ets_credits[i] =
11243                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11244                 /* 4 bits per TC, 4th bit is reserved */
11245                 veb->bw_info.bw_ets_max[i] =
11246                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11247                                   RTE_LEN2MASK(3, uint8_t));
11248                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11249                             veb->bw_info.bw_ets_share_credits[i]);
11250                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11251                             veb->bw_info.bw_ets_credits[i]);
11252                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11253                             veb->bw_info.bw_ets_max[i]);
11254         }
11255
11256         veb->enabled_tc = tc_map;
11257
11258         return ret;
11259 }
11260
11261
11262 /*
11263  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11264  * @vsi: VSI to be configured
11265  * @tc_map: enabled TC bitmap
11266  *
11267  * Returns 0 on success, negative value on failure
11268  */
11269 static enum i40e_status_code
11270 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11271 {
11272         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11273         struct i40e_vsi_context ctxt;
11274         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11275         enum i40e_status_code ret = I40E_SUCCESS;
11276         int i;
11277
11278         /* Check if enabled_tc is same as existing or new TCs */
11279         if (vsi->enabled_tc == tc_map)
11280                 return ret;
11281
11282         /* configure tc bandwidth */
11283         memset(&bw_data, 0, sizeof(bw_data));
11284         bw_data.tc_valid_bits = tc_map;
11285         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11286         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11287                 if (tc_map & BIT_ULL(i))
11288                         bw_data.tc_bw_credits[i] = 1;
11289         }
11290         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11291         if (ret) {
11292                 PMD_INIT_LOG(ERR,
11293                         "AQ command Config VSI BW allocation per TC failed = %d",
11294                         hw->aq.asq_last_status);
11295                 goto out;
11296         }
11297         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11298                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11299
11300         /* Update Queue Pairs Mapping for currently enabled UPs */
11301         ctxt.seid = vsi->seid;
11302         ctxt.pf_num = hw->pf_id;
11303         ctxt.vf_num = 0;
11304         ctxt.uplink_seid = vsi->uplink_seid;
11305         ctxt.info = vsi->info;
11306         i40e_get_cap(hw);
11307         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11308         if (ret)
11309                 goto out;
11310
11311         /* Update the VSI after updating the VSI queue-mapping information */
11312         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11313         if (ret) {
11314                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11315                         hw->aq.asq_last_status);
11316                 goto out;
11317         }
11318         /* update the local VSI info with updated queue map */
11319         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11320                                         sizeof(vsi->info.tc_mapping));
11321         rte_memcpy(&vsi->info.queue_mapping,
11322                         &ctxt.info.queue_mapping,
11323                 sizeof(vsi->info.queue_mapping));
11324         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11325         vsi->info.valid_sections = 0;
11326
11327         /* query and update current VSI BW information */
11328         ret = i40e_vsi_get_bw_config(vsi);
11329         if (ret) {
11330                 PMD_INIT_LOG(ERR,
11331                          "Failed updating vsi bw info, err %s aq_err %s",
11332                          i40e_stat_str(hw, ret),
11333                          i40e_aq_str(hw, hw->aq.asq_last_status));
11334                 goto out;
11335         }
11336
11337         vsi->enabled_tc = tc_map;
11338
11339 out:
11340         return ret;
11341 }
11342
11343 /*
11344  * i40e_dcb_hw_configure - program the dcb setting to hw
11345  * @pf: pf the configuration is taken on
11346  * @new_cfg: new configuration
11347  * @tc_map: enabled TC bitmap
11348  *
11349  * Returns 0 on success, negative value on failure
11350  */
11351 static enum i40e_status_code
11352 i40e_dcb_hw_configure(struct i40e_pf *pf,
11353                       struct i40e_dcbx_config *new_cfg,
11354                       uint8_t tc_map)
11355 {
11356         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11357         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11358         struct i40e_vsi *main_vsi = pf->main_vsi;
11359         struct i40e_vsi_list *vsi_list;
11360         enum i40e_status_code ret;
11361         int i;
11362         uint32_t val;
11363
11364         /* Use the FW API if FW > v4.4*/
11365         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11366               (hw->aq.fw_maj_ver >= 5))) {
11367                 PMD_INIT_LOG(ERR,
11368                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11369                 return I40E_ERR_FIRMWARE_API_VERSION;
11370         }
11371
11372         /* Check if need reconfiguration */
11373         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11374                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11375                 return I40E_SUCCESS;
11376         }
11377
11378         /* Copy the new config to the current config */
11379         *old_cfg = *new_cfg;
11380         old_cfg->etsrec = old_cfg->etscfg;
11381         ret = i40e_set_dcb_config(hw);
11382         if (ret) {
11383                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11384                          i40e_stat_str(hw, ret),
11385                          i40e_aq_str(hw, hw->aq.asq_last_status));
11386                 return ret;
11387         }
11388         /* set receive Arbiter to RR mode and ETS scheme by default */
11389         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11390                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11391                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11392                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11393                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11394                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11395                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11396                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11397                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11398                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11399                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11400                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11401                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11402         }
11403         /* get local mib to check whether it is configured correctly */
11404         /* IEEE mode */
11405         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11406         /* Get Local DCB Config */
11407         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11408                                      &hw->local_dcbx_config);
11409
11410         /* if Veb is created, need to update TC of it at first */
11411         if (main_vsi->veb) {
11412                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11413                 if (ret)
11414                         PMD_INIT_LOG(WARNING,
11415                                  "Failed configuring TC for VEB seid=%d",
11416                                  main_vsi->veb->seid);
11417         }
11418         /* Update each VSI */
11419         i40e_vsi_config_tc(main_vsi, tc_map);
11420         if (main_vsi->veb) {
11421                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11422                         /* Beside main VSI and VMDQ VSIs, only enable default
11423                          * TC for other VSIs
11424                          */
11425                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11426                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11427                                                          tc_map);
11428                         else
11429                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11430                                                          I40E_DEFAULT_TCMAP);
11431                         if (ret)
11432                                 PMD_INIT_LOG(WARNING,
11433                                         "Failed configuring TC for VSI seid=%d",
11434                                         vsi_list->vsi->seid);
11435                         /* continue */
11436                 }
11437         }
11438         return I40E_SUCCESS;
11439 }
11440
11441 /*
11442  * i40e_dcb_init_configure - initial dcb config
11443  * @dev: device being configured
11444  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11445  *
11446  * Returns 0 on success, negative value on failure
11447  */
11448 int
11449 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11450 {
11451         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11452         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11453         int i, ret = 0;
11454
11455         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11456                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11457                 return -ENOTSUP;
11458         }
11459
11460         /* DCB initialization:
11461          * Update DCB configuration from the Firmware and configure
11462          * LLDP MIB change event.
11463          */
11464         if (sw_dcb == TRUE) {
11465                 if (i40e_need_stop_lldp(dev)) {
11466                         ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11467                         if (ret != I40E_SUCCESS)
11468                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11469                 }
11470
11471                 ret = i40e_init_dcb(hw);
11472                 /* If lldp agent is stopped, the return value from
11473                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11474                  * adminq status. Otherwise, it should return success.
11475                  */
11476                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11477                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11478                         memset(&hw->local_dcbx_config, 0,
11479                                 sizeof(struct i40e_dcbx_config));
11480                         /* set dcb default configuration */
11481                         hw->local_dcbx_config.etscfg.willing = 0;
11482                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11483                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11484                         hw->local_dcbx_config.etscfg.tsatable[0] =
11485                                                 I40E_IEEE_TSA_ETS;
11486                         /* all UPs mapping to TC0 */
11487                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11488                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11489                         hw->local_dcbx_config.etsrec =
11490                                 hw->local_dcbx_config.etscfg;
11491                         hw->local_dcbx_config.pfc.willing = 0;
11492                         hw->local_dcbx_config.pfc.pfccap =
11493                                                 I40E_MAX_TRAFFIC_CLASS;
11494                         /* FW needs one App to configure HW */
11495                         hw->local_dcbx_config.numapps = 1;
11496                         hw->local_dcbx_config.app[0].selector =
11497                                                 I40E_APP_SEL_ETHTYPE;
11498                         hw->local_dcbx_config.app[0].priority = 3;
11499                         hw->local_dcbx_config.app[0].protocolid =
11500                                                 I40E_APP_PROTOID_FCOE;
11501                         ret = i40e_set_dcb_config(hw);
11502                         if (ret) {
11503                                 PMD_INIT_LOG(ERR,
11504                                         "default dcb config fails. err = %d, aq_err = %d.",
11505                                         ret, hw->aq.asq_last_status);
11506                                 return -ENOSYS;
11507                         }
11508                 } else {
11509                         PMD_INIT_LOG(ERR,
11510                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11511                                 ret, hw->aq.asq_last_status);
11512                         return -ENOTSUP;
11513                 }
11514         } else {
11515                 ret = i40e_aq_start_lldp(hw, NULL);
11516                 if (ret != I40E_SUCCESS)
11517                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11518
11519                 ret = i40e_init_dcb(hw);
11520                 if (!ret) {
11521                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11522                                 PMD_INIT_LOG(ERR,
11523                                         "HW doesn't support DCBX offload.");
11524                                 return -ENOTSUP;
11525                         }
11526                 } else {
11527                         PMD_INIT_LOG(ERR,
11528                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11529                                 ret, hw->aq.asq_last_status);
11530                         return -ENOTSUP;
11531                 }
11532         }
11533         return 0;
11534 }
11535
11536 /*
11537  * i40e_dcb_setup - setup dcb related config
11538  * @dev: device being configured
11539  *
11540  * Returns 0 on success, negative value on failure
11541  */
11542 static int
11543 i40e_dcb_setup(struct rte_eth_dev *dev)
11544 {
11545         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11546         struct i40e_dcbx_config dcb_cfg;
11547         uint8_t tc_map = 0;
11548         int ret = 0;
11549
11550         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11551                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11552                 return -ENOTSUP;
11553         }
11554
11555         if (pf->vf_num != 0)
11556                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11557
11558         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11559         if (ret) {
11560                 PMD_INIT_LOG(ERR, "invalid dcb config");
11561                 return -EINVAL;
11562         }
11563         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11564         if (ret) {
11565                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11566                 return -ENOSYS;
11567         }
11568
11569         return 0;
11570 }
11571
11572 static int
11573 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11574                       struct rte_eth_dcb_info *dcb_info)
11575 {
11576         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11577         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11578         struct i40e_vsi *vsi = pf->main_vsi;
11579         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11580         uint16_t bsf, tc_mapping;
11581         int i, j = 0;
11582
11583         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11584                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11585         else
11586                 dcb_info->nb_tcs = 1;
11587         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11588                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11589         for (i = 0; i < dcb_info->nb_tcs; i++)
11590                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11591
11592         /* get queue mapping if vmdq is disabled */
11593         if (!pf->nb_cfg_vmdq_vsi) {
11594                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11595                         if (!(vsi->enabled_tc & (1 << i)))
11596                                 continue;
11597                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11598                         dcb_info->tc_queue.tc_rxq[j][i].base =
11599                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11600                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11601                         dcb_info->tc_queue.tc_txq[j][i].base =
11602                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11603                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11604                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11605                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11606                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11607                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11608                 }
11609                 return 0;
11610         }
11611
11612         /* get queue mapping if vmdq is enabled */
11613         do {
11614                 vsi = pf->vmdq[j].vsi;
11615                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11616                         if (!(vsi->enabled_tc & (1 << i)))
11617                                 continue;
11618                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11619                         dcb_info->tc_queue.tc_rxq[j][i].base =
11620                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11621                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11622                         dcb_info->tc_queue.tc_txq[j][i].base =
11623                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11624                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11625                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11626                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11627                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11628                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11629                 }
11630                 j++;
11631         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11632         return 0;
11633 }
11634
11635 static int
11636 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11637 {
11638         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11639         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11640         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11641         uint16_t msix_intr;
11642
11643         msix_intr = intr_handle->intr_vec[queue_id];
11644         if (msix_intr == I40E_MISC_VEC_ID)
11645                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11646                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11647                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11648                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11649         else
11650                 I40E_WRITE_REG(hw,
11651                                I40E_PFINT_DYN_CTLN(msix_intr -
11652                                                    I40E_RX_VEC_START),
11653                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11654                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11655                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11656
11657         I40E_WRITE_FLUSH(hw);
11658         rte_intr_enable(&pci_dev->intr_handle);
11659
11660         return 0;
11661 }
11662
11663 static int
11664 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11665 {
11666         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11667         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11668         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11669         uint16_t msix_intr;
11670
11671         msix_intr = intr_handle->intr_vec[queue_id];
11672         if (msix_intr == I40E_MISC_VEC_ID)
11673                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11674                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11675         else
11676                 I40E_WRITE_REG(hw,
11677                                I40E_PFINT_DYN_CTLN(msix_intr -
11678                                                    I40E_RX_VEC_START),
11679                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11680         I40E_WRITE_FLUSH(hw);
11681
11682         return 0;
11683 }
11684
11685 /**
11686  * This function is used to check if the register is valid.
11687  * Below is the valid registers list for X722 only:
11688  * 0x2b800--0x2bb00
11689  * 0x38700--0x38a00
11690  * 0x3d800--0x3db00
11691  * 0x208e00--0x209000
11692  * 0x20be00--0x20c000
11693  * 0x263c00--0x264000
11694  * 0x265c00--0x266000
11695  */
11696 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11697 {
11698         if ((type != I40E_MAC_X722) &&
11699             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11700              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11701              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11702              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11703              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11704              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11705              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11706                 return 0;
11707         else
11708                 return 1;
11709 }
11710
11711 static int i40e_get_regs(struct rte_eth_dev *dev,
11712                          struct rte_dev_reg_info *regs)
11713 {
11714         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11715         uint32_t *ptr_data = regs->data;
11716         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11717         const struct i40e_reg_info *reg_info;
11718
11719         if (ptr_data == NULL) {
11720                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11721                 regs->width = sizeof(uint32_t);
11722                 return 0;
11723         }
11724
11725         /* The first few registers have to be read using AQ operations */
11726         reg_idx = 0;
11727         while (i40e_regs_adminq[reg_idx].name) {
11728                 reg_info = &i40e_regs_adminq[reg_idx++];
11729                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11730                         for (arr_idx2 = 0;
11731                                         arr_idx2 <= reg_info->count2;
11732                                         arr_idx2++) {
11733                                 reg_offset = arr_idx * reg_info->stride1 +
11734                                         arr_idx2 * reg_info->stride2;
11735                                 reg_offset += reg_info->base_addr;
11736                                 ptr_data[reg_offset >> 2] =
11737                                         i40e_read_rx_ctl(hw, reg_offset);
11738                         }
11739         }
11740
11741         /* The remaining registers can be read using primitives */
11742         reg_idx = 0;
11743         while (i40e_regs_others[reg_idx].name) {
11744                 reg_info = &i40e_regs_others[reg_idx++];
11745                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11746                         for (arr_idx2 = 0;
11747                                         arr_idx2 <= reg_info->count2;
11748                                         arr_idx2++) {
11749                                 reg_offset = arr_idx * reg_info->stride1 +
11750                                         arr_idx2 * reg_info->stride2;
11751                                 reg_offset += reg_info->base_addr;
11752                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11753                                         ptr_data[reg_offset >> 2] = 0;
11754                                 else
11755                                         ptr_data[reg_offset >> 2] =
11756                                                 I40E_READ_REG(hw, reg_offset);
11757                         }
11758         }
11759
11760         return 0;
11761 }
11762
11763 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11764 {
11765         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11766
11767         /* Convert word count to byte count */
11768         return hw->nvm.sr_size << 1;
11769 }
11770
11771 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11772                            struct rte_dev_eeprom_info *eeprom)
11773 {
11774         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11775         uint16_t *data = eeprom->data;
11776         uint16_t offset, length, cnt_words;
11777         int ret_code;
11778
11779         offset = eeprom->offset >> 1;
11780         length = eeprom->length >> 1;
11781         cnt_words = length;
11782
11783         if (offset > hw->nvm.sr_size ||
11784                 offset + length > hw->nvm.sr_size) {
11785                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11786                 return -EINVAL;
11787         }
11788
11789         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11790
11791         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11792         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11793                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11794                 return -EIO;
11795         }
11796
11797         return 0;
11798 }
11799
11800 static int i40e_get_module_info(struct rte_eth_dev *dev,
11801                                 struct rte_eth_dev_module_info *modinfo)
11802 {
11803         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11804         uint32_t sff8472_comp = 0;
11805         uint32_t sff8472_swap = 0;
11806         uint32_t sff8636_rev = 0;
11807         i40e_status status;
11808         uint32_t type = 0;
11809
11810         /* Check if firmware supports reading module EEPROM. */
11811         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11812                 PMD_DRV_LOG(ERR,
11813                             "Module EEPROM memory read not supported. "
11814                             "Please update the NVM image.\n");
11815                 return -EINVAL;
11816         }
11817
11818         status = i40e_update_link_info(hw);
11819         if (status)
11820                 return -EIO;
11821
11822         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11823                 PMD_DRV_LOG(ERR,
11824                             "Cannot read module EEPROM memory. "
11825                             "No module connected.\n");
11826                 return -EINVAL;
11827         }
11828
11829         type = hw->phy.link_info.module_type[0];
11830
11831         switch (type) {
11832         case I40E_MODULE_TYPE_SFP:
11833                 status = i40e_aq_get_phy_register(hw,
11834                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11835                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11836                                 I40E_MODULE_SFF_8472_COMP,
11837                                 &sff8472_comp, NULL);
11838                 if (status)
11839                         return -EIO;
11840
11841                 status = i40e_aq_get_phy_register(hw,
11842                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11843                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11844                                 I40E_MODULE_SFF_8472_SWAP,
11845                                 &sff8472_swap, NULL);
11846                 if (status)
11847                         return -EIO;
11848
11849                 /* Check if the module requires address swap to access
11850                  * the other EEPROM memory page.
11851                  */
11852                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11853                         PMD_DRV_LOG(WARNING,
11854                                     "Module address swap to access "
11855                                     "page 0xA2 is not supported.\n");
11856                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11857                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11858                 } else if (sff8472_comp == 0x00) {
11859                         /* Module is not SFF-8472 compliant */
11860                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11861                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11862                 } else {
11863                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11864                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11865                 }
11866                 break;
11867         case I40E_MODULE_TYPE_QSFP_PLUS:
11868                 /* Read from memory page 0. */
11869                 status = i40e_aq_get_phy_register(hw,
11870                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11871                                 0, 1,
11872                                 I40E_MODULE_REVISION_ADDR,
11873                                 &sff8636_rev, NULL);
11874                 if (status)
11875                         return -EIO;
11876                 /* Determine revision compliance byte */
11877                 if (sff8636_rev > 0x02) {
11878                         /* Module is SFF-8636 compliant */
11879                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11880                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11881                 } else {
11882                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11883                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11884                 }
11885                 break;
11886         case I40E_MODULE_TYPE_QSFP28:
11887                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11888                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11889                 break;
11890         default:
11891                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11892                 return -EINVAL;
11893         }
11894         return 0;
11895 }
11896
11897 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11898                                   struct rte_dev_eeprom_info *info)
11899 {
11900         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11901         bool is_sfp = false;
11902         i40e_status status;
11903         uint8_t *data;
11904         uint32_t value = 0;
11905         uint32_t i;
11906
11907         if (!info || !info->length || !info->data)
11908                 return -EINVAL;
11909
11910         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11911                 is_sfp = true;
11912
11913         data = info->data;
11914         for (i = 0; i < info->length; i++) {
11915                 u32 offset = i + info->offset;
11916                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11917
11918                 /* Check if we need to access the other memory page */
11919                 if (is_sfp) {
11920                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11921                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11922                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11923                         }
11924                 } else {
11925                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11926                                 /* Compute memory page number and offset. */
11927                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11928                                 addr++;
11929                         }
11930                 }
11931                 status = i40e_aq_get_phy_register(hw,
11932                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11933                                 addr, offset, 1, &value, NULL);
11934                 if (status)
11935                         return -EIO;
11936                 data[i] = (uint8_t)value;
11937         }
11938         return 0;
11939 }
11940
11941 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11942                                      struct ether_addr *mac_addr)
11943 {
11944         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11945         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11946         struct i40e_vsi *vsi = pf->main_vsi;
11947         struct i40e_mac_filter_info mac_filter;
11948         struct i40e_mac_filter *f;
11949         int ret;
11950
11951         if (!is_valid_assigned_ether_addr(mac_addr)) {
11952                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11953                 return -EINVAL;
11954         }
11955
11956         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11957                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11958                         break;
11959         }
11960
11961         if (f == NULL) {
11962                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11963                 return -EIO;
11964         }
11965
11966         mac_filter = f->mac_info;
11967         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11968         if (ret != I40E_SUCCESS) {
11969                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11970                 return -EIO;
11971         }
11972         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11973         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11974         if (ret != I40E_SUCCESS) {
11975                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11976                 return -EIO;
11977         }
11978         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11979
11980         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11981                                         mac_addr->addr_bytes, NULL);
11982         if (ret != I40E_SUCCESS) {
11983                 PMD_DRV_LOG(ERR, "Failed to change mac");
11984                 return -EIO;
11985         }
11986
11987         return 0;
11988 }
11989
11990 static int
11991 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11992 {
11993         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11994         struct rte_eth_dev_data *dev_data = pf->dev_data;
11995         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11996         int ret = 0;
11997
11998         /* check if mtu is within the allowed range */
11999         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
12000                 return -EINVAL;
12001
12002         /* mtu setting is forbidden if port is start */
12003         if (dev_data->dev_started) {
12004                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12005                             dev_data->port_id);
12006                 return -EBUSY;
12007         }
12008
12009         if (frame_size > ETHER_MAX_LEN)
12010                 dev_data->dev_conf.rxmode.offloads |=
12011                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12012         else
12013                 dev_data->dev_conf.rxmode.offloads &=
12014                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12015
12016         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12017
12018         return ret;
12019 }
12020
12021 /* Restore ethertype filter */
12022 static void
12023 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12024 {
12025         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12026         struct i40e_ethertype_filter_list
12027                 *ethertype_list = &pf->ethertype.ethertype_list;
12028         struct i40e_ethertype_filter *f;
12029         struct i40e_control_filter_stats stats;
12030         uint16_t flags;
12031
12032         TAILQ_FOREACH(f, ethertype_list, rules) {
12033                 flags = 0;
12034                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12035                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12036                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12037                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12038                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12039
12040                 memset(&stats, 0, sizeof(stats));
12041                 i40e_aq_add_rem_control_packet_filter(hw,
12042                                             f->input.mac_addr.addr_bytes,
12043                                             f->input.ether_type,
12044                                             flags, pf->main_vsi->seid,
12045                                             f->queue, 1, &stats, NULL);
12046         }
12047         PMD_DRV_LOG(INFO, "Ethertype filter:"
12048                     " mac_etype_used = %u, etype_used = %u,"
12049                     " mac_etype_free = %u, etype_free = %u",
12050                     stats.mac_etype_used, stats.etype_used,
12051                     stats.mac_etype_free, stats.etype_free);
12052 }
12053
12054 /* Restore tunnel filter */
12055 static void
12056 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12057 {
12058         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12059         struct i40e_vsi *vsi;
12060         struct i40e_pf_vf *vf;
12061         struct i40e_tunnel_filter_list
12062                 *tunnel_list = &pf->tunnel.tunnel_list;
12063         struct i40e_tunnel_filter *f;
12064         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12065         bool big_buffer = 0;
12066
12067         TAILQ_FOREACH(f, tunnel_list, rules) {
12068                 if (!f->is_to_vf)
12069                         vsi = pf->main_vsi;
12070                 else {
12071                         vf = &pf->vfs[f->vf_id];
12072                         vsi = vf->vsi;
12073                 }
12074                 memset(&cld_filter, 0, sizeof(cld_filter));
12075                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
12076                         (struct ether_addr *)&cld_filter.element.outer_mac);
12077                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
12078                         (struct ether_addr *)&cld_filter.element.inner_mac);
12079                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12080                 cld_filter.element.flags = f->input.flags;
12081                 cld_filter.element.tenant_id = f->input.tenant_id;
12082                 cld_filter.element.queue_number = f->queue;
12083                 rte_memcpy(cld_filter.general_fields,
12084                            f->input.general_fields,
12085                            sizeof(f->input.general_fields));
12086
12087                 if (((f->input.flags &
12088                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12089                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12090                     ((f->input.flags &
12091                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12092                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12093                     ((f->input.flags &
12094                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12095                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12096                         big_buffer = 1;
12097
12098                 if (big_buffer)
12099                         i40e_aq_add_cloud_filters_bb(hw,
12100                                         vsi->seid, &cld_filter, 1);
12101                 else
12102                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12103                                                   &cld_filter.element, 1);
12104         }
12105 }
12106
12107 /* Restore rss filter */
12108 static inline void
12109 i40e_rss_filter_restore(struct i40e_pf *pf)
12110 {
12111         struct i40e_rte_flow_rss_conf *conf =
12112                                         &pf->rss_info;
12113         if (conf->conf.queue_num)
12114                 i40e_config_rss_filter(pf, conf, TRUE);
12115 }
12116
12117 static void
12118 i40e_filter_restore(struct i40e_pf *pf)
12119 {
12120         i40e_ethertype_filter_restore(pf);
12121         i40e_tunnel_filter_restore(pf);
12122         i40e_fdir_filter_restore(pf);
12123         i40e_rss_filter_restore(pf);
12124 }
12125
12126 static bool
12127 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12128 {
12129         if (strcmp(dev->device->driver->name, drv->driver.name))
12130                 return false;
12131
12132         return true;
12133 }
12134
12135 bool
12136 is_i40e_supported(struct rte_eth_dev *dev)
12137 {
12138         return is_device_supported(dev, &rte_i40e_pmd);
12139 }
12140
12141 struct i40e_customized_pctype*
12142 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12143 {
12144         int i;
12145
12146         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12147                 if (pf->customized_pctype[i].index == index)
12148                         return &pf->customized_pctype[i];
12149         }
12150         return NULL;
12151 }
12152
12153 static int
12154 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12155                               uint32_t pkg_size, uint32_t proto_num,
12156                               struct rte_pmd_i40e_proto_info *proto,
12157                               enum rte_pmd_i40e_package_op op)
12158 {
12159         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12160         uint32_t pctype_num;
12161         struct rte_pmd_i40e_ptype_info *pctype;
12162         uint32_t buff_size;
12163         struct i40e_customized_pctype *new_pctype = NULL;
12164         uint8_t proto_id;
12165         uint8_t pctype_value;
12166         char name[64];
12167         uint32_t i, j, n;
12168         int ret;
12169
12170         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12171             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12172                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12173                 return -1;
12174         }
12175
12176         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12177                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12178                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12179         if (ret) {
12180                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12181                 return -1;
12182         }
12183         if (!pctype_num) {
12184                 PMD_DRV_LOG(INFO, "No new pctype added");
12185                 return -1;
12186         }
12187
12188         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12189         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12190         if (!pctype) {
12191                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12192                 return -1;
12193         }
12194         /* get information about new pctype list */
12195         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12196                                         (uint8_t *)pctype, buff_size,
12197                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12198         if (ret) {
12199                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12200                 rte_free(pctype);
12201                 return -1;
12202         }
12203
12204         /* Update customized pctype. */
12205         for (i = 0; i < pctype_num; i++) {
12206                 pctype_value = pctype[i].ptype_id;
12207                 memset(name, 0, sizeof(name));
12208                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12209                         proto_id = pctype[i].protocols[j];
12210                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12211                                 continue;
12212                         for (n = 0; n < proto_num; n++) {
12213                                 if (proto[n].proto_id != proto_id)
12214                                         continue;
12215                                 strlcat(name, proto[n].name, sizeof(name));
12216                                 strlcat(name, "_", sizeof(name));
12217                                 break;
12218                         }
12219                 }
12220                 name[strlen(name) - 1] = '\0';
12221                 if (!strcmp(name, "GTPC"))
12222                         new_pctype =
12223                                 i40e_find_customized_pctype(pf,
12224                                                       I40E_CUSTOMIZED_GTPC);
12225                 else if (!strcmp(name, "GTPU_IPV4"))
12226                         new_pctype =
12227                                 i40e_find_customized_pctype(pf,
12228                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12229                 else if (!strcmp(name, "GTPU_IPV6"))
12230                         new_pctype =
12231                                 i40e_find_customized_pctype(pf,
12232                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12233                 else if (!strcmp(name, "GTPU"))
12234                         new_pctype =
12235                                 i40e_find_customized_pctype(pf,
12236                                                       I40E_CUSTOMIZED_GTPU);
12237                 if (new_pctype) {
12238                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12239                                 new_pctype->pctype = pctype_value;
12240                                 new_pctype->valid = true;
12241                         } else {
12242                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12243                                 new_pctype->valid = false;
12244                         }
12245                 }
12246         }
12247
12248         rte_free(pctype);
12249         return 0;
12250 }
12251
12252 static int
12253 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12254                              uint32_t pkg_size, uint32_t proto_num,
12255                              struct rte_pmd_i40e_proto_info *proto,
12256                              enum rte_pmd_i40e_package_op op)
12257 {
12258         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12259         uint16_t port_id = dev->data->port_id;
12260         uint32_t ptype_num;
12261         struct rte_pmd_i40e_ptype_info *ptype;
12262         uint32_t buff_size;
12263         uint8_t proto_id;
12264         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12265         uint32_t i, j, n;
12266         bool in_tunnel;
12267         int ret;
12268
12269         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12270             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12271                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12272                 return -1;
12273         }
12274
12275         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12276                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12277                 return 0;
12278         }
12279
12280         /* get information about new ptype num */
12281         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12282                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12283                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12284         if (ret) {
12285                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12286                 return ret;
12287         }
12288         if (!ptype_num) {
12289                 PMD_DRV_LOG(INFO, "No new ptype added");
12290                 return -1;
12291         }
12292
12293         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12294         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12295         if (!ptype) {
12296                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12297                 return -1;
12298         }
12299
12300         /* get information about new ptype list */
12301         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12302                                         (uint8_t *)ptype, buff_size,
12303                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12304         if (ret) {
12305                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12306                 rte_free(ptype);
12307                 return ret;
12308         }
12309
12310         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12311         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12312         if (!ptype_mapping) {
12313                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12314                 rte_free(ptype);
12315                 return -1;
12316         }
12317
12318         /* Update ptype mapping table. */
12319         for (i = 0; i < ptype_num; i++) {
12320                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12321                 ptype_mapping[i].sw_ptype = 0;
12322                 in_tunnel = false;
12323                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12324                         proto_id = ptype[i].protocols[j];
12325                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12326                                 continue;
12327                         for (n = 0; n < proto_num; n++) {
12328                                 if (proto[n].proto_id != proto_id)
12329                                         continue;
12330                                 memset(name, 0, sizeof(name));
12331                                 strcpy(name, proto[n].name);
12332                                 if (!strncasecmp(name, "PPPOE", 5))
12333                                         ptype_mapping[i].sw_ptype |=
12334                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12335                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12336                                          !in_tunnel) {
12337                                         ptype_mapping[i].sw_ptype |=
12338                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12339                                         ptype_mapping[i].sw_ptype |=
12340                                                 RTE_PTYPE_L4_FRAG;
12341                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12342                                            in_tunnel) {
12343                                         ptype_mapping[i].sw_ptype |=
12344                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12345                                         ptype_mapping[i].sw_ptype |=
12346                                                 RTE_PTYPE_INNER_L4_FRAG;
12347                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12348                                         ptype_mapping[i].sw_ptype |=
12349                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12350                                         in_tunnel = true;
12351                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12352                                            !in_tunnel)
12353                                         ptype_mapping[i].sw_ptype |=
12354                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12355                                 else if (!strncasecmp(name, "IPV4", 4) &&
12356                                          in_tunnel)
12357                                         ptype_mapping[i].sw_ptype |=
12358                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12359                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12360                                          !in_tunnel) {
12361                                         ptype_mapping[i].sw_ptype |=
12362                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12363                                         ptype_mapping[i].sw_ptype |=
12364                                                 RTE_PTYPE_L4_FRAG;
12365                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12366                                            in_tunnel) {
12367                                         ptype_mapping[i].sw_ptype |=
12368                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12369                                         ptype_mapping[i].sw_ptype |=
12370                                                 RTE_PTYPE_INNER_L4_FRAG;
12371                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12372                                         ptype_mapping[i].sw_ptype |=
12373                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12374                                         in_tunnel = true;
12375                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12376                                            !in_tunnel)
12377                                         ptype_mapping[i].sw_ptype |=
12378                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12379                                 else if (!strncasecmp(name, "IPV6", 4) &&
12380                                          in_tunnel)
12381                                         ptype_mapping[i].sw_ptype |=
12382                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12383                                 else if (!strncasecmp(name, "UDP", 3) &&
12384                                          !in_tunnel)
12385                                         ptype_mapping[i].sw_ptype |=
12386                                                 RTE_PTYPE_L4_UDP;
12387                                 else if (!strncasecmp(name, "UDP", 3) &&
12388                                          in_tunnel)
12389                                         ptype_mapping[i].sw_ptype |=
12390                                                 RTE_PTYPE_INNER_L4_UDP;
12391                                 else if (!strncasecmp(name, "TCP", 3) &&
12392                                          !in_tunnel)
12393                                         ptype_mapping[i].sw_ptype |=
12394                                                 RTE_PTYPE_L4_TCP;
12395                                 else if (!strncasecmp(name, "TCP", 3) &&
12396                                          in_tunnel)
12397                                         ptype_mapping[i].sw_ptype |=
12398                                                 RTE_PTYPE_INNER_L4_TCP;
12399                                 else if (!strncasecmp(name, "SCTP", 4) &&
12400                                          !in_tunnel)
12401                                         ptype_mapping[i].sw_ptype |=
12402                                                 RTE_PTYPE_L4_SCTP;
12403                                 else if (!strncasecmp(name, "SCTP", 4) &&
12404                                          in_tunnel)
12405                                         ptype_mapping[i].sw_ptype |=
12406                                                 RTE_PTYPE_INNER_L4_SCTP;
12407                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12408                                           !strncasecmp(name, "ICMPV6", 6)) &&
12409                                          !in_tunnel)
12410                                         ptype_mapping[i].sw_ptype |=
12411                                                 RTE_PTYPE_L4_ICMP;
12412                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12413                                           !strncasecmp(name, "ICMPV6", 6)) &&
12414                                          in_tunnel)
12415                                         ptype_mapping[i].sw_ptype |=
12416                                                 RTE_PTYPE_INNER_L4_ICMP;
12417                                 else if (!strncasecmp(name, "GTPC", 4)) {
12418                                         ptype_mapping[i].sw_ptype |=
12419                                                 RTE_PTYPE_TUNNEL_GTPC;
12420                                         in_tunnel = true;
12421                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12422                                         ptype_mapping[i].sw_ptype |=
12423                                                 RTE_PTYPE_TUNNEL_GTPU;
12424                                         in_tunnel = true;
12425                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12426                                         ptype_mapping[i].sw_ptype |=
12427                                                 RTE_PTYPE_TUNNEL_GRENAT;
12428                                         in_tunnel = true;
12429                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12430                                            !strncasecmp(name, "L2TPV2", 6)) {
12431                                         ptype_mapping[i].sw_ptype |=
12432                                                 RTE_PTYPE_TUNNEL_L2TP;
12433                                         in_tunnel = true;
12434                                 }
12435
12436                                 break;
12437                         }
12438                 }
12439         }
12440
12441         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12442                                                 ptype_num, 0);
12443         if (ret)
12444                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12445
12446         rte_free(ptype_mapping);
12447         rte_free(ptype);
12448         return ret;
12449 }
12450
12451 void
12452 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12453                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12454 {
12455         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12456         uint32_t proto_num;
12457         struct rte_pmd_i40e_proto_info *proto;
12458         uint32_t buff_size;
12459         uint32_t i;
12460         int ret;
12461
12462         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12463             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12464                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12465                 return;
12466         }
12467
12468         /* get information about protocol number */
12469         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12470                                        (uint8_t *)&proto_num, sizeof(proto_num),
12471                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12472         if (ret) {
12473                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12474                 return;
12475         }
12476         if (!proto_num) {
12477                 PMD_DRV_LOG(INFO, "No new protocol added");
12478                 return;
12479         }
12480
12481         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12482         proto = rte_zmalloc("new_proto", buff_size, 0);
12483         if (!proto) {
12484                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12485                 return;
12486         }
12487
12488         /* get information about protocol list */
12489         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12490                                         (uint8_t *)proto, buff_size,
12491                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12492         if (ret) {
12493                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12494                 rte_free(proto);
12495                 return;
12496         }
12497
12498         /* Check if GTP is supported. */
12499         for (i = 0; i < proto_num; i++) {
12500                 if (!strncmp(proto[i].name, "GTP", 3)) {
12501                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12502                                 pf->gtp_support = true;
12503                         else
12504                                 pf->gtp_support = false;
12505                         break;
12506                 }
12507         }
12508
12509         /* Update customized pctype info */
12510         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12511                                             proto_num, proto, op);
12512         if (ret)
12513                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12514
12515         /* Update customized ptype info */
12516         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12517                                            proto_num, proto, op);
12518         if (ret)
12519                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12520
12521         rte_free(proto);
12522 }
12523
12524 /* Create a QinQ cloud filter
12525  *
12526  * The Fortville NIC has limited resources for tunnel filters,
12527  * so we can only reuse existing filters.
12528  *
12529  * In step 1 we define which Field Vector fields can be used for
12530  * filter types.
12531  * As we do not have the inner tag defined as a field,
12532  * we have to define it first, by reusing one of L1 entries.
12533  *
12534  * In step 2 we are replacing one of existing filter types with
12535  * a new one for QinQ.
12536  * As we reusing L1 and replacing L2, some of the default filter
12537  * types will disappear,which depends on L1 and L2 entries we reuse.
12538  *
12539  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12540  *
12541  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12542  *              later when we define the cloud filter.
12543  *      a.      Valid_flags.replace_cloud = 0
12544  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12545  *      c.      New_filter = 0x10
12546  *      d.      TR bit = 0xff (optional, not used here)
12547  *      e.      Buffer – 2 entries:
12548  *              i.      Byte 0 = 8 (outer vlan FV index).
12549  *                      Byte 1 = 0 (rsv)
12550  *                      Byte 2-3 = 0x0fff
12551  *              ii.     Byte 0 = 37 (inner vlan FV index).
12552  *                      Byte 1 =0 (rsv)
12553  *                      Byte 2-3 = 0x0fff
12554  *
12555  * Step 2:
12556  * 2.   Create cloud filter using two L1 filters entries: stag and
12557  *              new filter(outer vlan+ inner vlan)
12558  *      a.      Valid_flags.replace_cloud = 1
12559  *      b.      Old_filter = 1 (instead of outer IP)
12560  *      c.      New_filter = 0x10
12561  *      d.      Buffer – 2 entries:
12562  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12563  *                      Byte 1-3 = 0 (rsv)
12564  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12565  *                      Byte 9-11 = 0 (rsv)
12566  */
12567 static int
12568 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12569 {
12570         int ret = -ENOTSUP;
12571         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12572         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12573         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12574         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12575
12576         if (pf->support_multi_driver) {
12577                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12578                 return ret;
12579         }
12580
12581         /* Init */
12582         memset(&filter_replace, 0,
12583                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12584         memset(&filter_replace_buf, 0,
12585                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12586
12587         /* create L1 filter */
12588         filter_replace.old_filter_type =
12589                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12590         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12591         filter_replace.tr_bit = 0;
12592
12593         /* Prepare the buffer, 2 entries */
12594         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12595         filter_replace_buf.data[0] |=
12596                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12597         /* Field Vector 12b mask */
12598         filter_replace_buf.data[2] = 0xff;
12599         filter_replace_buf.data[3] = 0x0f;
12600         filter_replace_buf.data[4] =
12601                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12602         filter_replace_buf.data[4] |=
12603                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12604         /* Field Vector 12b mask */
12605         filter_replace_buf.data[6] = 0xff;
12606         filter_replace_buf.data[7] = 0x0f;
12607         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12608                         &filter_replace_buf);
12609         if (ret != I40E_SUCCESS)
12610                 return ret;
12611
12612         if (filter_replace.old_filter_type !=
12613             filter_replace.new_filter_type)
12614                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12615                             " original: 0x%x, new: 0x%x",
12616                             dev->device->name,
12617                             filter_replace.old_filter_type,
12618                             filter_replace.new_filter_type);
12619
12620         /* Apply the second L2 cloud filter */
12621         memset(&filter_replace, 0,
12622                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12623         memset(&filter_replace_buf, 0,
12624                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12625
12626         /* create L2 filter, input for L2 filter will be L1 filter  */
12627         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12628         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12629         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12630
12631         /* Prepare the buffer, 2 entries */
12632         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12633         filter_replace_buf.data[0] |=
12634                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12635         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12636         filter_replace_buf.data[4] |=
12637                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12638         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12639                         &filter_replace_buf);
12640         if (!ret && (filter_replace.old_filter_type !=
12641                      filter_replace.new_filter_type))
12642                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12643                             " original: 0x%x, new: 0x%x",
12644                             dev->device->name,
12645                             filter_replace.old_filter_type,
12646                             filter_replace.new_filter_type);
12647
12648         return ret;
12649 }
12650
12651 int
12652 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12653                    const struct rte_flow_action_rss *in)
12654 {
12655         if (in->key_len > RTE_DIM(out->key) ||
12656             in->queue_num > RTE_DIM(out->queue))
12657                 return -EINVAL;
12658         if (!in->key && in->key_len)
12659                 return -EINVAL;
12660         out->conf = (struct rte_flow_action_rss){
12661                 .func = in->func,
12662                 .level = in->level,
12663                 .types = in->types,
12664                 .key_len = in->key_len,
12665                 .queue_num = in->queue_num,
12666                 .queue = memcpy(out->queue, in->queue,
12667                                 sizeof(*in->queue) * in->queue_num),
12668         };
12669         if (in->key)
12670                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12671         return 0;
12672 }
12673
12674 int
12675 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12676                      const struct rte_flow_action_rss *with)
12677 {
12678         return (comp->func == with->func &&
12679                 comp->level == with->level &&
12680                 comp->types == with->types &&
12681                 comp->key_len == with->key_len &&
12682                 comp->queue_num == with->queue_num &&
12683                 !memcmp(comp->key, with->key, with->key_len) &&
12684                 !memcmp(comp->queue, with->queue,
12685                         sizeof(*with->queue) * with->queue_num));
12686 }
12687
12688 int
12689 i40e_config_rss_filter(struct i40e_pf *pf,
12690                 struct i40e_rte_flow_rss_conf *conf, bool add)
12691 {
12692         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12693         uint32_t i, lut = 0;
12694         uint16_t j, num;
12695         struct rte_eth_rss_conf rss_conf = {
12696                 .rss_key = conf->conf.key_len ?
12697                         (void *)(uintptr_t)conf->conf.key : NULL,
12698                 .rss_key_len = conf->conf.key_len,
12699                 .rss_hf = conf->conf.types,
12700         };
12701         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12702
12703         if (!add) {
12704                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12705                         i40e_pf_disable_rss(pf);
12706                         memset(rss_info, 0,
12707                                 sizeof(struct i40e_rte_flow_rss_conf));
12708                         return 0;
12709                 }
12710                 return -EINVAL;
12711         }
12712
12713         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12714          * It's necessary to calculate the actual PF queues that are configured.
12715          */
12716         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12717                 num = i40e_pf_calc_configured_queues_num(pf);
12718         else
12719                 num = pf->dev_data->nb_rx_queues;
12720
12721         num = RTE_MIN(num, conf->conf.queue_num);
12722         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12723                         num);
12724
12725         if (num == 0) {
12726                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12727                 return -ENOTSUP;
12728         }
12729
12730         /* Fill in redirection table */
12731         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12732                 if (j == num)
12733                         j = 0;
12734                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12735                         hw->func_caps.rss_table_entry_width) - 1));
12736                 if ((i & 3) == 3)
12737                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12738         }
12739
12740         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12741                 i40e_pf_disable_rss(pf);
12742                 return 0;
12743         }
12744         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12745                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12746                 /* Random default keys */
12747                 static uint32_t rss_key_default[] = {0x6b793944,
12748                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12749                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12750                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12751
12752                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12753                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12754                                                         sizeof(uint32_t);
12755                 PMD_DRV_LOG(INFO,
12756                         "No valid RSS key config for i40e, using default\n");
12757         }
12758
12759         i40e_hw_rss_hash_set(pf, &rss_conf);
12760
12761         if (i40e_rss_conf_init(rss_info, &conf->conf))
12762                 return -EINVAL;
12763
12764         return 0;
12765 }
12766
12767 RTE_INIT(i40e_init_log)
12768 {
12769         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12770         if (i40e_logtype_init >= 0)
12771                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12772         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12773         if (i40e_logtype_driver >= 0)
12774                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12775 }
12776
12777 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12778                               ETH_I40E_FLOATING_VEB_ARG "=1"
12779                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12780                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12781                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12782                               ETH_I40E_USE_LATEST_VEC "=0|1");