4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memzone.h>
49 #include <rte_malloc.h>
50 #include <rte_memcpy.h>
51 #include <rte_alarm.h>
53 #include <rte_eth_ctrl.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
64 #include "i40e_regs.h"
66 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
67 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
69 #define I40E_CLEAR_PXE_WAIT_MS 200
71 /* Maximun number of capability elements */
72 #define I40E_MAX_CAP_ELE_NUM 128
74 /* Wait count and inteval */
75 #define I40E_CHK_Q_ENA_COUNT 1000
76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
78 /* Maximun number of VSI */
79 #define I40E_MAX_NUM_VSIS (384UL)
81 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
83 /* Flow control default timer */
84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
86 /* Flow control default high water */
87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
89 /* Flow control default low water */
90 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
92 /* Flow control enable fwd bit */
93 #define I40E_PRTMAC_FWD_CTRL 0x00000001
95 /* Receive Packet Buffer size */
96 #define I40E_RXPBSIZE (968 * 1024)
99 #define I40E_KILOSHIFT 10
101 /* Receive Average Packet Size in Byte*/
102 #define I40E_PACKET_AVERAGE_SIZE 128
104 /* Mask of PF interrupt causes */
105 #define I40E_PFINT_ICR0_ENA_MASK ( \
106 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
107 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
108 I40E_PFINT_ICR0_ENA_GRST_MASK | \
109 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
110 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
112 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
113 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
114 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
115 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
117 #define I40E_FLOW_TYPES ( \
118 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
123 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
128 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
130 /* Additional timesync values. */
131 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
132 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
133 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
134 #define I40E_PRTTSYN_TSYNENA 0x80000000
135 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
136 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
138 #define I40E_MAX_PERCENT 100
139 #define I40E_DEFAULT_DCB_APP_NUM 1
140 #define I40E_DEFAULT_DCB_APP_PRIO 3
142 #define I40E_INSET_NONE 0x00000000000000000ULL
145 #define I40E_INSET_DMAC 0x0000000000000001ULL
146 #define I40E_INSET_SMAC 0x0000000000000002ULL
147 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
148 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
149 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
152 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
153 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
154 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
155 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
156 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
157 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
158 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
160 /* bit 16 ~ bit 31 */
161 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
162 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
163 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
164 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
165 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
166 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
167 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
168 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
170 /* bit 32 ~ bit 47, tunnel fields */
171 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
172 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
173 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
174 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
175 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
176 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
178 /* bit 48 ~ bit 55 */
179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
181 /* bit 56 ~ bit 63, Flex Payload */
182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
190 #define I40E_INSET_FLEX_PAYLOAD \
191 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
192 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
193 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
194 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
197 * Below are values for writing un-exposed registers suggested
200 /* Destination MAC address */
201 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
202 /* Source MAC address */
203 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
205 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0200000000000000ULL
206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
207 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
208 /* Single VLAN tag in the inner L2 header */
209 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
210 /* Source IPv4 address */
211 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
212 /* Destination IPv4 address */
213 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
214 /* IPv4 Type of Service (TOS) */
215 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
217 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
218 /* IPv4 Time to Live */
219 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
220 /* Source IPv6 address */
221 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
222 /* Destination IPv6 address */
223 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
224 /* IPv6 Traffic Class (TC) */
225 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
226 /* IPv6 Next Header */
227 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
229 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
231 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
232 /* Destination L4 port */
233 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
234 /* SCTP verification tag */
235 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
236 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
237 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
238 /* Source port of tunneling UDP */
239 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
240 /* Destination port of tunneling UDP */
241 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
242 /* UDP Tunneling ID, NVGRE/GRE key */
243 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
244 /* Last ether type */
245 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
246 /* Tunneling outer destination IPv4 address */
247 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
248 /* Tunneling outer destination IPv6 address */
249 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
250 /* 1st word of flex payload */
251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
252 /* 2nd word of flex payload */
253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
254 /* 3rd word of flex payload */
255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
256 /* 4th word of flex payload */
257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
258 /* 5th word of flex payload */
259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
260 /* 6th word of flex payload */
261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
262 /* 7th word of flex payload */
263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
264 /* 8th word of flex payload */
265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
266 /* all 8 words flex payload */
267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
268 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
270 #define I40E_TRANSLATE_INSET 0
271 #define I40E_TRANSLATE_REG 1
273 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
274 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
275 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
276 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
277 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
278 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
280 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
281 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
282 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
283 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
285 /* PCI offset for querying capability */
286 #define PCI_DEV_CAP_REG 0xA4
287 /* PCI offset for enabling/disabling Extended Tag */
288 #define PCI_DEV_CTRL_REG 0xA8
289 /* Bit mask of Extended Tag capability */
290 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
291 /* Bit shift of Extended Tag enable/disable */
292 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
293 /* Bit mask of Extended Tag enable/disable */
294 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
296 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
297 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
298 static int i40e_dev_configure(struct rte_eth_dev *dev);
299 static int i40e_dev_start(struct rte_eth_dev *dev);
300 static void i40e_dev_stop(struct rte_eth_dev *dev);
301 static void i40e_dev_close(struct rte_eth_dev *dev);
302 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
303 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
304 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
305 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
306 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
307 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
308 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
309 struct rte_eth_stats *stats);
310 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
311 struct rte_eth_xstat *xstats, unsigned n);
312 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
313 struct rte_eth_xstat_name *xstats_names,
315 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
316 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
320 static void i40e_dev_info_get(struct rte_eth_dev *dev,
321 struct rte_eth_dev_info *dev_info);
322 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
325 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
326 enum rte_vlan_type vlan_type,
328 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
329 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
332 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
333 static int i40e_dev_led_on(struct rte_eth_dev *dev);
334 static int i40e_dev_led_off(struct rte_eth_dev *dev);
335 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
336 struct rte_eth_fc_conf *fc_conf);
337 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
338 struct rte_eth_fc_conf *fc_conf);
339 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
340 struct rte_eth_pfc_conf *pfc_conf);
341 static void i40e_macaddr_add(struct rte_eth_dev *dev,
342 struct ether_addr *mac_addr,
345 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
346 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
347 struct rte_eth_rss_reta_entry64 *reta_conf,
349 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
350 struct rte_eth_rss_reta_entry64 *reta_conf,
353 static int i40e_get_cap(struct i40e_hw *hw);
354 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
355 static int i40e_pf_setup(struct i40e_pf *pf);
356 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
357 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
358 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
359 static int i40e_dcb_setup(struct rte_eth_dev *dev);
360 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
361 bool offset_loaded, uint64_t *offset, uint64_t *stat);
362 static void i40e_stat_update_48(struct i40e_hw *hw,
368 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
369 static void i40e_dev_interrupt_handler(
370 __rte_unused struct rte_intr_handle *handle, void *param);
371 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
372 uint32_t base, uint32_t num);
373 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
374 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
376 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
378 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
379 static int i40e_veb_release(struct i40e_veb *veb);
380 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
381 struct i40e_vsi *vsi);
382 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
383 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
384 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
385 struct i40e_macvlan_filter *mv_f,
387 struct ether_addr *addr);
388 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
389 struct i40e_macvlan_filter *mv_f,
392 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
393 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
394 struct rte_eth_rss_conf *rss_conf);
395 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
396 struct rte_eth_rss_conf *rss_conf);
397 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
398 struct rte_eth_udp_tunnel *udp_tunnel);
399 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
400 struct rte_eth_udp_tunnel *udp_tunnel);
401 static void i40e_filter_input_set_init(struct i40e_pf *pf);
402 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
403 struct rte_eth_ethertype_filter *filter,
405 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
406 enum rte_filter_op filter_op,
408 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
409 enum rte_filter_type filter_type,
410 enum rte_filter_op filter_op,
412 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
413 struct rte_eth_dcb_info *dcb_info);
414 static void i40e_configure_registers(struct i40e_hw *hw);
415 static void i40e_hw_init(struct rte_eth_dev *dev);
416 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
417 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
418 struct rte_eth_mirror_conf *mirror_conf,
419 uint8_t sw_id, uint8_t on);
420 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
422 static int i40e_timesync_enable(struct rte_eth_dev *dev);
423 static int i40e_timesync_disable(struct rte_eth_dev *dev);
424 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
425 struct timespec *timestamp,
427 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
428 struct timespec *timestamp);
429 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
431 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
433 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
434 struct timespec *timestamp);
435 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
436 const struct timespec *timestamp);
438 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
440 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
443 static int i40e_get_regs(struct rte_eth_dev *dev,
444 struct rte_dev_reg_info *regs);
446 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
448 static int i40e_get_eeprom(struct rte_eth_dev *dev,
449 struct rte_dev_eeprom_info *eeprom);
451 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
452 struct ether_addr *mac_addr);
454 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
456 static const struct rte_pci_id pci_id_i40e_map[] = {
457 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
458 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
459 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
460 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
461 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
462 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
463 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
464 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
465 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
466 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
467 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
468 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
469 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
470 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
471 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
472 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
473 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
474 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
475 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
476 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
477 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_I_X722) },
478 { .vendor_id = 0, /* sentinel */ },
481 static const struct eth_dev_ops i40e_eth_dev_ops = {
482 .dev_configure = i40e_dev_configure,
483 .dev_start = i40e_dev_start,
484 .dev_stop = i40e_dev_stop,
485 .dev_close = i40e_dev_close,
486 .promiscuous_enable = i40e_dev_promiscuous_enable,
487 .promiscuous_disable = i40e_dev_promiscuous_disable,
488 .allmulticast_enable = i40e_dev_allmulticast_enable,
489 .allmulticast_disable = i40e_dev_allmulticast_disable,
490 .dev_set_link_up = i40e_dev_set_link_up,
491 .dev_set_link_down = i40e_dev_set_link_down,
492 .link_update = i40e_dev_link_update,
493 .stats_get = i40e_dev_stats_get,
494 .xstats_get = i40e_dev_xstats_get,
495 .xstats_get_names = i40e_dev_xstats_get_names,
496 .stats_reset = i40e_dev_stats_reset,
497 .xstats_reset = i40e_dev_stats_reset,
498 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
499 .dev_infos_get = i40e_dev_info_get,
500 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
501 .vlan_filter_set = i40e_vlan_filter_set,
502 .vlan_tpid_set = i40e_vlan_tpid_set,
503 .vlan_offload_set = i40e_vlan_offload_set,
504 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
505 .vlan_pvid_set = i40e_vlan_pvid_set,
506 .rx_queue_start = i40e_dev_rx_queue_start,
507 .rx_queue_stop = i40e_dev_rx_queue_stop,
508 .tx_queue_start = i40e_dev_tx_queue_start,
509 .tx_queue_stop = i40e_dev_tx_queue_stop,
510 .rx_queue_setup = i40e_dev_rx_queue_setup,
511 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
512 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
513 .rx_queue_release = i40e_dev_rx_queue_release,
514 .rx_queue_count = i40e_dev_rx_queue_count,
515 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
516 .tx_queue_setup = i40e_dev_tx_queue_setup,
517 .tx_queue_release = i40e_dev_tx_queue_release,
518 .dev_led_on = i40e_dev_led_on,
519 .dev_led_off = i40e_dev_led_off,
520 .flow_ctrl_get = i40e_flow_ctrl_get,
521 .flow_ctrl_set = i40e_flow_ctrl_set,
522 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
523 .mac_addr_add = i40e_macaddr_add,
524 .mac_addr_remove = i40e_macaddr_remove,
525 .reta_update = i40e_dev_rss_reta_update,
526 .reta_query = i40e_dev_rss_reta_query,
527 .rss_hash_update = i40e_dev_rss_hash_update,
528 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
529 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
530 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
531 .filter_ctrl = i40e_dev_filter_ctrl,
532 .rxq_info_get = i40e_rxq_info_get,
533 .txq_info_get = i40e_txq_info_get,
534 .mirror_rule_set = i40e_mirror_rule_set,
535 .mirror_rule_reset = i40e_mirror_rule_reset,
536 .timesync_enable = i40e_timesync_enable,
537 .timesync_disable = i40e_timesync_disable,
538 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
539 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
540 .get_dcb_info = i40e_dev_get_dcb_info,
541 .timesync_adjust_time = i40e_timesync_adjust_time,
542 .timesync_read_time = i40e_timesync_read_time,
543 .timesync_write_time = i40e_timesync_write_time,
544 .get_reg = i40e_get_regs,
545 .get_eeprom_length = i40e_get_eeprom_length,
546 .get_eeprom = i40e_get_eeprom,
547 .mac_addr_set = i40e_set_default_mac_addr,
548 .mtu_set = i40e_dev_mtu_set,
551 /* store statistics names and its offset in stats structure */
552 struct rte_i40e_xstats_name_off {
553 char name[RTE_ETH_XSTATS_NAME_SIZE];
557 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
558 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
559 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
560 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
561 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
562 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
563 rx_unknown_protocol)},
564 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
565 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
566 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
567 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
570 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
571 sizeof(rte_i40e_stats_strings[0]))
573 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
574 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
575 tx_dropped_link_down)},
576 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
577 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
579 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
580 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
582 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
584 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
586 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
587 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
588 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
589 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
590 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
591 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
593 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
595 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
597 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
599 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
601 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
603 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
605 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
607 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
608 mac_short_packet_dropped)},
609 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
611 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
612 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
613 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
615 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
617 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
619 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
621 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
623 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
625 {"rx_flow_director_atr_match_packets",
626 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
627 {"rx_flow_director_sb_match_packets",
628 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
629 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
631 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
633 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
635 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
639 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
640 sizeof(rte_i40e_hw_port_strings[0]))
642 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
643 {"xon_packets", offsetof(struct i40e_hw_port_stats,
645 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
649 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
650 sizeof(rte_i40e_rxq_prio_strings[0]))
652 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
653 {"xon_packets", offsetof(struct i40e_hw_port_stats,
655 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
657 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
658 priority_xon_2_xoff)},
661 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
662 sizeof(rte_i40e_txq_prio_strings[0]))
664 static struct eth_driver rte_i40e_pmd = {
666 .name = "rte_i40e_pmd",
667 .id_table = pci_id_i40e_map,
668 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
669 RTE_PCI_DRV_DETACHABLE,
671 .eth_dev_init = eth_i40e_dev_init,
672 .eth_dev_uninit = eth_i40e_dev_uninit,
673 .dev_private_size = sizeof(struct i40e_adapter),
677 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
678 struct rte_eth_link *link)
680 struct rte_eth_link *dst = link;
681 struct rte_eth_link *src = &(dev->data->dev_link);
683 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
684 *(uint64_t *)src) == 0)
691 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
692 struct rte_eth_link *link)
694 struct rte_eth_link *dst = &(dev->data->dev_link);
695 struct rte_eth_link *src = link;
697 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
698 *(uint64_t *)src) == 0)
705 * Driver initialization routine.
706 * Invoked once at EAL init time.
707 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
710 rte_i40e_pmd_init(const char *name __rte_unused,
711 const char *params __rte_unused)
713 PMD_INIT_FUNC_TRACE();
714 rte_eth_driver_register(&rte_i40e_pmd);
719 static struct rte_driver rte_i40e_driver = {
721 .init = rte_i40e_pmd_init,
724 PMD_REGISTER_DRIVER(rte_i40e_driver, i40e);
725 DRIVER_REGISTER_PCI_TABLE(i40e, pci_id_i40e_map);
728 * Initialize registers for flexible payload, which should be set by NVM.
729 * This should be removed from code once it is fixed in NVM.
731 #ifndef I40E_GLQF_ORT
732 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
734 #ifndef I40E_GLQF_PIT
735 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
738 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
740 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
741 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
742 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
743 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
744 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
745 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
746 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
747 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
748 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
749 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
751 /* GLQF_PIT Registers */
752 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
753 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
756 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
759 * Add a ethertype filter to drop all flow control frames transmitted
763 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
765 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
766 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
767 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
768 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
771 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
772 I40E_FLOW_CONTROL_ETHERTYPE, flags,
773 pf->main_vsi_seid, 0,
776 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
777 " frames from VSIs.");
781 floating_veb_list_handler(__rte_unused const char *key,
782 const char *floating_veb_value,
786 unsigned int count = 0;
789 bool *vf_floating_veb = opaque;
791 while (isblank(*floating_veb_value))
792 floating_veb_value++;
794 /* Reset floating VEB configuration for VFs */
795 for (idx = 0; idx < I40E_MAX_VF; idx++)
796 vf_floating_veb[idx] = false;
800 while (isblank(*floating_veb_value))
801 floating_veb_value++;
802 if (*floating_veb_value == '\0')
805 idx = strtoul(floating_veb_value, &end, 10);
806 if (errno || end == NULL)
808 while (isblank(*end))
812 } else if ((*end == ';') || (*end == '\0')) {
814 if (min == I40E_MAX_VF)
816 if (max >= I40E_MAX_VF)
817 max = I40E_MAX_VF - 1;
818 for (idx = min; idx <= max; idx++) {
819 vf_floating_veb[idx] = true;
826 floating_veb_value = end + 1;
827 } while (*end != '\0');
836 config_vf_floating_veb(struct rte_devargs *devargs,
837 uint16_t floating_veb,
838 bool *vf_floating_veb)
840 struct rte_kvargs *kvlist;
842 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
846 /* All the VFs attach to the floating VEB by default
847 * when the floating VEB is enabled.
849 for (i = 0; i < I40E_MAX_VF; i++)
850 vf_floating_veb[i] = true;
855 kvlist = rte_kvargs_parse(devargs->args, NULL);
859 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
860 rte_kvargs_free(kvlist);
863 /* When the floating_veb_list parameter exists, all the VFs
864 * will attach to the legacy VEB firstly, then configure VFs
865 * to the floating VEB according to the floating_veb_list.
867 if (rte_kvargs_process(kvlist, floating_veb_list,
868 floating_veb_list_handler,
869 vf_floating_veb) < 0) {
870 rte_kvargs_free(kvlist);
873 rte_kvargs_free(kvlist);
877 i40e_check_floating_handler(__rte_unused const char *key,
879 __rte_unused void *opaque)
881 if (strcmp(value, "1"))
888 is_floating_veb_supported(struct rte_devargs *devargs)
890 struct rte_kvargs *kvlist;
891 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
896 kvlist = rte_kvargs_parse(devargs->args, NULL);
900 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
901 rte_kvargs_free(kvlist);
904 /* Floating VEB is enabled when there's key-value:
905 * enable_floating_veb=1
907 if (rte_kvargs_process(kvlist, floating_veb_key,
908 i40e_check_floating_handler, NULL) < 0) {
909 rte_kvargs_free(kvlist);
912 rte_kvargs_free(kvlist);
918 config_floating_veb(struct rte_eth_dev *dev)
920 struct rte_pci_device *pci_dev = dev->pci_dev;
921 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
922 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
924 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
926 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
927 pf->floating_veb = is_floating_veb_supported(pci_dev->devargs);
928 config_vf_floating_veb(pci_dev->devargs, pf->floating_veb,
929 pf->floating_veb_list);
931 pf->floating_veb = false;
936 eth_i40e_dev_init(struct rte_eth_dev *dev)
938 struct rte_pci_device *pci_dev;
939 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
940 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
941 struct i40e_vsi *vsi;
946 PMD_INIT_FUNC_TRACE();
948 dev->dev_ops = &i40e_eth_dev_ops;
949 dev->rx_pkt_burst = i40e_recv_pkts;
950 dev->tx_pkt_burst = i40e_xmit_pkts;
952 /* for secondary processes, we don't initialise any further as primary
953 * has already done this work. Only check we don't need a different
955 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
956 i40e_set_rx_function(dev);
957 i40e_set_tx_function(dev);
960 pci_dev = dev->pci_dev;
962 rte_eth_copy_pci_info(dev, pci_dev);
964 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
965 pf->adapter->eth_dev = dev;
966 pf->dev_data = dev->data;
968 hw->back = I40E_PF_TO_ADAPTER(pf);
969 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
971 PMD_INIT_LOG(ERR, "Hardware is not available, "
972 "as address is NULL");
976 hw->vendor_id = pci_dev->id.vendor_id;
977 hw->device_id = pci_dev->id.device_id;
978 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
979 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
980 hw->bus.device = pci_dev->addr.devid;
981 hw->bus.func = pci_dev->addr.function;
982 hw->adapter_stopped = 0;
984 /* Make sure all is clean before doing PF reset */
987 /* Initialize the hardware */
990 /* Reset here to make sure all is clean for each PF */
991 ret = i40e_pf_reset(hw);
993 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
997 /* Initialize the shared code (base driver) */
998 ret = i40e_init_shared_code(hw);
1000 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1005 * To work around the NVM issue,initialize registers
1006 * for flexible payload by software.
1007 * It should be removed once issues are fixed in NVM.
1009 i40e_flex_payload_reg_init(hw);
1011 /* Initialize the input set for filters (hash and fd) to default value */
1012 i40e_filter_input_set_init(pf);
1014 /* Initialize the parameters for adminq */
1015 i40e_init_adminq_parameter(hw);
1016 ret = i40e_init_adminq(hw);
1017 if (ret != I40E_SUCCESS) {
1018 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1021 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1022 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1023 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1024 ((hw->nvm.version >> 12) & 0xf),
1025 ((hw->nvm.version >> 4) & 0xff),
1026 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1028 /* Need the special FW version to support floating VEB */
1029 config_floating_veb(dev);
1030 /* Clear PXE mode */
1031 i40e_clear_pxe_mode(hw);
1034 * On X710, performance number is far from the expectation on recent
1035 * firmware versions. The fix for this issue may not be integrated in
1036 * the following firmware version. So the workaround in software driver
1037 * is needed. It needs to modify the initial values of 3 internal only
1038 * registers. Note that the workaround can be removed when it is fixed
1039 * in firmware in the future.
1041 i40e_configure_registers(hw);
1043 /* Get hw capabilities */
1044 ret = i40e_get_cap(hw);
1045 if (ret != I40E_SUCCESS) {
1046 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1047 goto err_get_capabilities;
1050 /* Initialize parameters for PF */
1051 ret = i40e_pf_parameter_init(dev);
1053 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1054 goto err_parameter_init;
1057 /* Initialize the queue management */
1058 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1060 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1061 goto err_qp_pool_init;
1063 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1064 hw->func_caps.num_msix_vectors - 1);
1066 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1067 goto err_msix_pool_init;
1070 /* Initialize lan hmc */
1071 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1072 hw->func_caps.num_rx_qp, 0, 0);
1073 if (ret != I40E_SUCCESS) {
1074 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1075 goto err_init_lan_hmc;
1078 /* Configure lan hmc */
1079 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1080 if (ret != I40E_SUCCESS) {
1081 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1082 goto err_configure_lan_hmc;
1085 /* Get and check the mac address */
1086 i40e_get_mac_addr(hw, hw->mac.addr);
1087 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1088 PMD_INIT_LOG(ERR, "mac address is not valid");
1090 goto err_get_mac_addr;
1092 /* Copy the permanent MAC address */
1093 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1094 (struct ether_addr *) hw->mac.perm_addr);
1096 /* Disable flow control */
1097 hw->fc.requested_mode = I40E_FC_NONE;
1098 i40e_set_fc(hw, &aq_fail, TRUE);
1100 /* Set the global registers with default ether type value */
1101 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1102 if (ret != I40E_SUCCESS) {
1103 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1105 goto err_setup_pf_switch;
1108 /* PF setup, which includes VSI setup */
1109 ret = i40e_pf_setup(pf);
1111 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1112 goto err_setup_pf_switch;
1115 /* reset all stats of the device, including pf and main vsi */
1116 i40e_dev_stats_reset(dev);
1120 /* Disable double vlan by default */
1121 i40e_vsi_config_double_vlan(vsi, FALSE);
1123 if (!vsi->max_macaddrs)
1124 len = ETHER_ADDR_LEN;
1126 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1128 /* Should be after VSI initialized */
1129 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1130 if (!dev->data->mac_addrs) {
1131 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1132 "for storing mac address");
1135 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1136 &dev->data->mac_addrs[0]);
1138 /* initialize pf host driver to setup SRIOV resource if applicable */
1139 i40e_pf_host_init(dev);
1141 /* register callback func to eal lib */
1142 rte_intr_callback_register(&(pci_dev->intr_handle),
1143 i40e_dev_interrupt_handler, (void *)dev);
1145 /* configure and enable device interrupt */
1146 i40e_pf_config_irq0(hw, TRUE);
1147 i40e_pf_enable_irq0(hw);
1149 /* enable uio intr after callback register */
1150 rte_intr_enable(&(pci_dev->intr_handle));
1152 * Add an ethertype filter to drop all flow control frames transmitted
1153 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1156 i40e_add_tx_flow_control_drop_filter(pf);
1158 /* Set the max frame size to 0x2600 by default,
1159 * in case other drivers changed the default value.
1161 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1163 /* initialize mirror rule list */
1164 TAILQ_INIT(&pf->mirror_list);
1166 /* Init dcb to sw mode by default */
1167 ret = i40e_dcb_init_configure(dev, TRUE);
1168 if (ret != I40E_SUCCESS) {
1169 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1170 pf->flags &= ~I40E_FLAG_DCB;
1176 i40e_vsi_release(pf->main_vsi);
1177 err_setup_pf_switch:
1179 err_configure_lan_hmc:
1180 (void)i40e_shutdown_lan_hmc(hw);
1182 i40e_res_pool_destroy(&pf->msix_pool);
1184 i40e_res_pool_destroy(&pf->qp_pool);
1187 err_get_capabilities:
1188 (void)i40e_shutdown_adminq(hw);
1194 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1196 struct rte_pci_device *pci_dev;
1198 struct i40e_filter_control_settings settings;
1200 uint8_t aq_fail = 0;
1202 PMD_INIT_FUNC_TRACE();
1204 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1207 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1208 pci_dev = dev->pci_dev;
1210 if (hw->adapter_stopped == 0)
1211 i40e_dev_close(dev);
1213 dev->dev_ops = NULL;
1214 dev->rx_pkt_burst = NULL;
1215 dev->tx_pkt_burst = NULL;
1218 ret = i40e_aq_stop_lldp(hw, true, NULL);
1219 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1220 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1222 /* Clear PXE mode */
1223 i40e_clear_pxe_mode(hw);
1225 /* Unconfigure filter control */
1226 memset(&settings, 0, sizeof(settings));
1227 ret = i40e_set_filter_control(hw, &settings);
1229 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1232 /* Disable flow control */
1233 hw->fc.requested_mode = I40E_FC_NONE;
1234 i40e_set_fc(hw, &aq_fail, TRUE);
1236 /* uninitialize pf host driver */
1237 i40e_pf_host_uninit(dev);
1239 rte_free(dev->data->mac_addrs);
1240 dev->data->mac_addrs = NULL;
1242 /* disable uio intr before callback unregister */
1243 rte_intr_disable(&(pci_dev->intr_handle));
1245 /* register callback func to eal lib */
1246 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1247 i40e_dev_interrupt_handler, (void *)dev);
1253 i40e_dev_configure(struct rte_eth_dev *dev)
1255 struct i40e_adapter *ad =
1256 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1257 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1258 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1261 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1262 * bulk allocation or vector Rx preconditions we will reset it.
1264 ad->rx_bulk_alloc_allowed = true;
1265 ad->rx_vec_allowed = true;
1266 ad->tx_simple_allowed = true;
1267 ad->tx_vec_allowed = true;
1269 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1270 ret = i40e_fdir_setup(pf);
1271 if (ret != I40E_SUCCESS) {
1272 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1275 ret = i40e_fdir_configure(dev);
1277 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1281 i40e_fdir_teardown(pf);
1283 ret = i40e_dev_init_vlan(dev);
1288 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1289 * RSS setting have different requirements.
1290 * General PMD driver call sequence are NIC init, configure,
1291 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1292 * will try to lookup the VSI that specific queue belongs to if VMDQ
1293 * applicable. So, VMDQ setting has to be done before
1294 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1295 * For RSS setting, it will try to calculate actual configured RX queue
1296 * number, which will be available after rx_queue_setup(). dev_start()
1297 * function is good to place RSS setup.
1299 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1300 ret = i40e_vmdq_setup(dev);
1305 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1306 ret = i40e_dcb_setup(dev);
1308 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1316 /* need to release vmdq resource if exists */
1317 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1318 i40e_vsi_release(pf->vmdq[i].vsi);
1319 pf->vmdq[i].vsi = NULL;
1324 /* need to release fdir resource if exists */
1325 i40e_fdir_teardown(pf);
1330 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1332 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1333 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1334 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1335 uint16_t msix_vect = vsi->msix_intr;
1338 for (i = 0; i < vsi->nb_qps; i++) {
1339 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1340 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1344 if (vsi->type != I40E_VSI_SRIOV) {
1345 if (!rte_intr_allow_others(intr_handle)) {
1346 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1347 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1349 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1352 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1353 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1355 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1360 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1361 vsi->user_param + (msix_vect - 1);
1363 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1364 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1366 I40E_WRITE_FLUSH(hw);
1370 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1371 int base_queue, int nb_queue)
1375 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1377 /* Bind all RX queues to allocated MSIX interrupt */
1378 for (i = 0; i < nb_queue; i++) {
1379 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1380 I40E_QINT_RQCTL_ITR_INDX_MASK |
1381 ((base_queue + i + 1) <<
1382 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1383 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1384 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1386 if (i == nb_queue - 1)
1387 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1388 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1391 /* Write first RX queue to Link list register as the head element */
1392 if (vsi->type != I40E_VSI_SRIOV) {
1394 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1396 if (msix_vect == I40E_MISC_VEC_ID) {
1397 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1399 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1401 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1403 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1406 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1408 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1410 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1412 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1419 if (msix_vect == I40E_MISC_VEC_ID) {
1421 I40E_VPINT_LNKLST0(vsi->user_param),
1423 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1425 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1427 /* num_msix_vectors_vf needs to minus irq0 */
1428 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1429 vsi->user_param + (msix_vect - 1);
1431 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1433 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1435 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1439 I40E_WRITE_FLUSH(hw);
1443 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1445 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1446 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1447 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1448 uint16_t msix_vect = vsi->msix_intr;
1449 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1450 uint16_t queue_idx = 0;
1455 for (i = 0; i < vsi->nb_qps; i++) {
1456 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1457 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1460 /* INTENA flag is not auto-cleared for interrupt */
1461 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1462 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1463 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1464 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1465 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1467 /* VF bind interrupt */
1468 if (vsi->type == I40E_VSI_SRIOV) {
1469 __vsi_queues_bind_intr(vsi, msix_vect,
1470 vsi->base_queue, vsi->nb_qps);
1474 /* PF & VMDq bind interrupt */
1475 if (rte_intr_dp_is_en(intr_handle)) {
1476 if (vsi->type == I40E_VSI_MAIN) {
1479 } else if (vsi->type == I40E_VSI_VMDQ2) {
1480 struct i40e_vsi *main_vsi =
1481 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1482 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1487 for (i = 0; i < vsi->nb_used_qps; i++) {
1489 if (!rte_intr_allow_others(intr_handle))
1490 /* allow to share MISC_VEC_ID */
1491 msix_vect = I40E_MISC_VEC_ID;
1493 /* no enough msix_vect, map all to one */
1494 __vsi_queues_bind_intr(vsi, msix_vect,
1495 vsi->base_queue + i,
1496 vsi->nb_used_qps - i);
1497 for (; !!record && i < vsi->nb_used_qps; i++)
1498 intr_handle->intr_vec[queue_idx + i] =
1502 /* 1:1 queue/msix_vect mapping */
1503 __vsi_queues_bind_intr(vsi, msix_vect,
1504 vsi->base_queue + i, 1);
1506 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1514 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1516 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1517 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1518 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1519 uint16_t interval = i40e_calc_itr_interval(\
1520 RTE_LIBRTE_I40E_ITR_INTERVAL);
1521 uint16_t msix_intr, i;
1523 if (rte_intr_allow_others(intr_handle))
1524 for (i = 0; i < vsi->nb_msix; i++) {
1525 msix_intr = vsi->msix_intr + i;
1526 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1527 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1528 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1529 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1531 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1534 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1535 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1536 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1537 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1539 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1541 I40E_WRITE_FLUSH(hw);
1545 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1547 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1548 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1549 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1550 uint16_t msix_intr, i;
1552 if (rte_intr_allow_others(intr_handle))
1553 for (i = 0; i < vsi->nb_msix; i++) {
1554 msix_intr = vsi->msix_intr + i;
1555 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1559 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1561 I40E_WRITE_FLUSH(hw);
1564 static inline uint8_t
1565 i40e_parse_link_speeds(uint16_t link_speeds)
1567 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1569 if (link_speeds & ETH_LINK_SPEED_40G)
1570 link_speed |= I40E_LINK_SPEED_40GB;
1571 if (link_speeds & ETH_LINK_SPEED_20G)
1572 link_speed |= I40E_LINK_SPEED_20GB;
1573 if (link_speeds & ETH_LINK_SPEED_10G)
1574 link_speed |= I40E_LINK_SPEED_10GB;
1575 if (link_speeds & ETH_LINK_SPEED_1G)
1576 link_speed |= I40E_LINK_SPEED_1GB;
1577 if (link_speeds & ETH_LINK_SPEED_100M)
1578 link_speed |= I40E_LINK_SPEED_100MB;
1584 i40e_phy_conf_link(struct i40e_hw *hw,
1586 uint8_t force_speed)
1588 enum i40e_status_code status;
1589 struct i40e_aq_get_phy_abilities_resp phy_ab;
1590 struct i40e_aq_set_phy_config phy_conf;
1591 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1592 I40E_AQ_PHY_FLAG_PAUSE_RX |
1593 I40E_AQ_PHY_FLAG_PAUSE_RX |
1594 I40E_AQ_PHY_FLAG_LOW_POWER;
1595 const uint8_t advt = I40E_LINK_SPEED_40GB |
1596 I40E_LINK_SPEED_10GB |
1597 I40E_LINK_SPEED_1GB |
1598 I40E_LINK_SPEED_100MB;
1602 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1607 memset(&phy_conf, 0, sizeof(phy_conf));
1609 /* bits 0-2 use the values from get_phy_abilities_resp */
1611 abilities |= phy_ab.abilities & mask;
1613 /* update ablities and speed */
1614 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1615 phy_conf.link_speed = advt;
1617 phy_conf.link_speed = force_speed;
1619 phy_conf.abilities = abilities;
1621 /* use get_phy_abilities_resp value for the rest */
1622 phy_conf.phy_type = phy_ab.phy_type;
1623 phy_conf.eee_capability = phy_ab.eee_capability;
1624 phy_conf.eeer = phy_ab.eeer_val;
1625 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1627 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1628 phy_ab.abilities, phy_ab.link_speed);
1629 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1630 phy_conf.abilities, phy_conf.link_speed);
1632 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1636 return I40E_SUCCESS;
1640 i40e_apply_link_speed(struct rte_eth_dev *dev)
1643 uint8_t abilities = 0;
1644 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1645 struct rte_eth_conf *conf = &dev->data->dev_conf;
1647 speed = i40e_parse_link_speeds(conf->link_speeds);
1648 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1649 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1650 abilities |= I40E_AQ_PHY_AN_ENABLED;
1651 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1653 /* Skip changing speed on 40G interfaces, FW does not support */
1654 if (i40e_is_40G_device(hw->device_id)) {
1655 speed = I40E_LINK_SPEED_UNKNOWN;
1656 abilities |= I40E_AQ_PHY_AN_ENABLED;
1659 return i40e_phy_conf_link(hw, abilities, speed);
1663 i40e_dev_start(struct rte_eth_dev *dev)
1665 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1666 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1667 struct i40e_vsi *main_vsi = pf->main_vsi;
1669 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1670 uint32_t intr_vector = 0;
1672 hw->adapter_stopped = 0;
1674 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1675 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1676 dev->data->port_id);
1680 rte_intr_disable(intr_handle);
1682 if ((rte_intr_cap_multiple(intr_handle) ||
1683 !RTE_ETH_DEV_SRIOV(dev).active) &&
1684 dev->data->dev_conf.intr_conf.rxq != 0) {
1685 intr_vector = dev->data->nb_rx_queues;
1686 if (rte_intr_efd_enable(intr_handle, intr_vector))
1690 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1691 intr_handle->intr_vec =
1692 rte_zmalloc("intr_vec",
1693 dev->data->nb_rx_queues * sizeof(int),
1695 if (!intr_handle->intr_vec) {
1696 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1697 " intr_vec\n", dev->data->nb_rx_queues);
1702 /* Initialize VSI */
1703 ret = i40e_dev_rxtx_init(pf);
1704 if (ret != I40E_SUCCESS) {
1705 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1709 /* Map queues with MSIX interrupt */
1710 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1711 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1712 i40e_vsi_queues_bind_intr(main_vsi);
1713 i40e_vsi_enable_queues_intr(main_vsi);
1715 /* Map VMDQ VSI queues with MSIX interrupt */
1716 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1717 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1718 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1719 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1722 /* enable FDIR MSIX interrupt */
1723 if (pf->fdir.fdir_vsi) {
1724 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1725 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1728 /* Enable all queues which have been configured */
1729 ret = i40e_dev_switch_queues(pf, TRUE);
1730 if (ret != I40E_SUCCESS) {
1731 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1735 /* Enable receiving broadcast packets */
1736 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1737 if (ret != I40E_SUCCESS)
1738 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1740 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1741 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1743 if (ret != I40E_SUCCESS)
1744 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1747 /* Apply link configure */
1748 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1749 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1750 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1751 PMD_DRV_LOG(ERR, "Invalid link setting");
1754 ret = i40e_apply_link_speed(dev);
1755 if (I40E_SUCCESS != ret) {
1756 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1760 if (!rte_intr_allow_others(intr_handle)) {
1761 rte_intr_callback_unregister(intr_handle,
1762 i40e_dev_interrupt_handler,
1764 /* configure and enable device interrupt */
1765 i40e_pf_config_irq0(hw, FALSE);
1766 i40e_pf_enable_irq0(hw);
1768 if (dev->data->dev_conf.intr_conf.lsc != 0)
1769 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1770 " no intr multiplex\n");
1773 /* enable uio intr after callback register */
1774 rte_intr_enable(intr_handle);
1776 return I40E_SUCCESS;
1779 i40e_dev_switch_queues(pf, FALSE);
1780 i40e_dev_clear_queues(dev);
1786 i40e_dev_stop(struct rte_eth_dev *dev)
1788 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1789 struct i40e_vsi *main_vsi = pf->main_vsi;
1790 struct i40e_mirror_rule *p_mirror;
1791 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1794 /* Disable all queues */
1795 i40e_dev_switch_queues(pf, FALSE);
1797 /* un-map queues with interrupt registers */
1798 i40e_vsi_disable_queues_intr(main_vsi);
1799 i40e_vsi_queues_unbind_intr(main_vsi);
1801 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1802 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1803 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1806 if (pf->fdir.fdir_vsi) {
1807 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1808 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1810 /* Clear all queues and release memory */
1811 i40e_dev_clear_queues(dev);
1814 i40e_dev_set_link_down(dev);
1816 /* Remove all mirror rules */
1817 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1818 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1821 pf->nb_mirror_rule = 0;
1823 if (!rte_intr_allow_others(intr_handle))
1824 /* resume to the default handler */
1825 rte_intr_callback_register(intr_handle,
1826 i40e_dev_interrupt_handler,
1829 /* Clean datapath event and queue/vec mapping */
1830 rte_intr_efd_disable(intr_handle);
1831 if (intr_handle->intr_vec) {
1832 rte_free(intr_handle->intr_vec);
1833 intr_handle->intr_vec = NULL;
1838 i40e_dev_close(struct rte_eth_dev *dev)
1840 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1841 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845 PMD_INIT_FUNC_TRACE();
1848 hw->adapter_stopped = 1;
1849 i40e_dev_free_queues(dev);
1851 /* Disable interrupt */
1852 i40e_pf_disable_irq0(hw);
1853 rte_intr_disable(&(dev->pci_dev->intr_handle));
1855 /* shutdown and destroy the HMC */
1856 i40e_shutdown_lan_hmc(hw);
1858 /* release all the existing VSIs and VEBs */
1859 i40e_fdir_teardown(pf);
1860 i40e_vsi_release(pf->main_vsi);
1862 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1863 i40e_vsi_release(pf->vmdq[i].vsi);
1864 pf->vmdq[i].vsi = NULL;
1870 /* shutdown the adminq */
1871 i40e_aq_queue_shutdown(hw, true);
1872 i40e_shutdown_adminq(hw);
1874 i40e_res_pool_destroy(&pf->qp_pool);
1875 i40e_res_pool_destroy(&pf->msix_pool);
1877 /* force a PF reset to clean anything leftover */
1878 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1879 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1880 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1881 I40E_WRITE_FLUSH(hw);
1885 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1887 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1888 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1889 struct i40e_vsi *vsi = pf->main_vsi;
1892 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1894 if (status != I40E_SUCCESS)
1895 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1897 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1899 if (status != I40E_SUCCESS)
1900 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1905 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1907 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1908 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1909 struct i40e_vsi *vsi = pf->main_vsi;
1912 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1914 if (status != I40E_SUCCESS)
1915 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1917 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1919 if (status != I40E_SUCCESS)
1920 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1924 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1926 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1927 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928 struct i40e_vsi *vsi = pf->main_vsi;
1931 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1932 if (ret != I40E_SUCCESS)
1933 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1937 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1939 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1940 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941 struct i40e_vsi *vsi = pf->main_vsi;
1944 if (dev->data->promiscuous == 1)
1945 return; /* must remain in all_multicast mode */
1947 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1948 vsi->seid, FALSE, NULL);
1949 if (ret != I40E_SUCCESS)
1950 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1954 * Set device link up.
1957 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1959 /* re-apply link speed setting */
1960 return i40e_apply_link_speed(dev);
1964 * Set device link down.
1967 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1969 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1970 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1971 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1973 return i40e_phy_conf_link(hw, abilities, speed);
1977 i40e_dev_link_update(struct rte_eth_dev *dev,
1978 int wait_to_complete)
1980 #define CHECK_INTERVAL 100 /* 100ms */
1981 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1982 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983 struct i40e_link_status link_status;
1984 struct rte_eth_link link, old;
1986 unsigned rep_cnt = MAX_REPEAT_TIME;
1988 memset(&link, 0, sizeof(link));
1989 memset(&old, 0, sizeof(old));
1990 memset(&link_status, 0, sizeof(link_status));
1991 rte_i40e_dev_atomic_read_link_status(dev, &old);
1994 /* Get link status information from hardware */
1995 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1996 if (status != I40E_SUCCESS) {
1997 link.link_speed = ETH_SPEED_NUM_100M;
1998 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1999 PMD_DRV_LOG(ERR, "Failed to get link info");
2003 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2004 if (!wait_to_complete)
2007 rte_delay_ms(CHECK_INTERVAL);
2008 } while (!link.link_status && rep_cnt--);
2010 if (!link.link_status)
2013 /* i40e uses full duplex only */
2014 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2016 /* Parse the link status */
2017 switch (link_status.link_speed) {
2018 case I40E_LINK_SPEED_100MB:
2019 link.link_speed = ETH_SPEED_NUM_100M;
2021 case I40E_LINK_SPEED_1GB:
2022 link.link_speed = ETH_SPEED_NUM_1G;
2024 case I40E_LINK_SPEED_10GB:
2025 link.link_speed = ETH_SPEED_NUM_10G;
2027 case I40E_LINK_SPEED_20GB:
2028 link.link_speed = ETH_SPEED_NUM_20G;
2030 case I40E_LINK_SPEED_40GB:
2031 link.link_speed = ETH_SPEED_NUM_40G;
2034 link.link_speed = ETH_SPEED_NUM_100M;
2038 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2039 ETH_LINK_SPEED_FIXED);
2042 rte_i40e_dev_atomic_write_link_status(dev, &link);
2043 if (link.link_status == old.link_status)
2049 /* Get all the statistics of a VSI */
2051 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2053 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2054 struct i40e_eth_stats *nes = &vsi->eth_stats;
2055 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2056 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2058 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2059 vsi->offset_loaded, &oes->rx_bytes,
2061 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2062 vsi->offset_loaded, &oes->rx_unicast,
2064 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2065 vsi->offset_loaded, &oes->rx_multicast,
2066 &nes->rx_multicast);
2067 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2068 vsi->offset_loaded, &oes->rx_broadcast,
2069 &nes->rx_broadcast);
2070 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2071 &oes->rx_discards, &nes->rx_discards);
2072 /* GLV_REPC not supported */
2073 /* GLV_RMPC not supported */
2074 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2075 &oes->rx_unknown_protocol,
2076 &nes->rx_unknown_protocol);
2077 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2078 vsi->offset_loaded, &oes->tx_bytes,
2080 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2081 vsi->offset_loaded, &oes->tx_unicast,
2083 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2084 vsi->offset_loaded, &oes->tx_multicast,
2085 &nes->tx_multicast);
2086 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2087 vsi->offset_loaded, &oes->tx_broadcast,
2088 &nes->tx_broadcast);
2089 /* GLV_TDPC not supported */
2090 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2091 &oes->tx_errors, &nes->tx_errors);
2092 vsi->offset_loaded = true;
2094 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2096 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2097 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2098 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2099 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2100 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2101 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2102 nes->rx_unknown_protocol);
2103 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2104 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2105 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2106 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2107 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2108 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2109 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2114 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2117 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2118 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2120 /* Get statistics of struct i40e_eth_stats */
2121 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2122 I40E_GLPRT_GORCL(hw->port),
2123 pf->offset_loaded, &os->eth.rx_bytes,
2125 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2126 I40E_GLPRT_UPRCL(hw->port),
2127 pf->offset_loaded, &os->eth.rx_unicast,
2128 &ns->eth.rx_unicast);
2129 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2130 I40E_GLPRT_MPRCL(hw->port),
2131 pf->offset_loaded, &os->eth.rx_multicast,
2132 &ns->eth.rx_multicast);
2133 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2134 I40E_GLPRT_BPRCL(hw->port),
2135 pf->offset_loaded, &os->eth.rx_broadcast,
2136 &ns->eth.rx_broadcast);
2137 /* Workaround: CRC size should not be included in byte statistics,
2138 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2140 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2141 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2143 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2144 pf->offset_loaded, &os->eth.rx_discards,
2145 &ns->eth.rx_discards);
2146 /* GLPRT_REPC not supported */
2147 /* GLPRT_RMPC not supported */
2148 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2150 &os->eth.rx_unknown_protocol,
2151 &ns->eth.rx_unknown_protocol);
2152 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2153 I40E_GLPRT_GOTCL(hw->port),
2154 pf->offset_loaded, &os->eth.tx_bytes,
2156 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2157 I40E_GLPRT_UPTCL(hw->port),
2158 pf->offset_loaded, &os->eth.tx_unicast,
2159 &ns->eth.tx_unicast);
2160 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2161 I40E_GLPRT_MPTCL(hw->port),
2162 pf->offset_loaded, &os->eth.tx_multicast,
2163 &ns->eth.tx_multicast);
2164 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2165 I40E_GLPRT_BPTCL(hw->port),
2166 pf->offset_loaded, &os->eth.tx_broadcast,
2167 &ns->eth.tx_broadcast);
2168 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2169 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2170 /* GLPRT_TEPC not supported */
2172 /* additional port specific stats */
2173 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2174 pf->offset_loaded, &os->tx_dropped_link_down,
2175 &ns->tx_dropped_link_down);
2176 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2177 pf->offset_loaded, &os->crc_errors,
2179 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2180 pf->offset_loaded, &os->illegal_bytes,
2181 &ns->illegal_bytes);
2182 /* GLPRT_ERRBC not supported */
2183 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2184 pf->offset_loaded, &os->mac_local_faults,
2185 &ns->mac_local_faults);
2186 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2187 pf->offset_loaded, &os->mac_remote_faults,
2188 &ns->mac_remote_faults);
2189 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2190 pf->offset_loaded, &os->rx_length_errors,
2191 &ns->rx_length_errors);
2192 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2193 pf->offset_loaded, &os->link_xon_rx,
2195 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2196 pf->offset_loaded, &os->link_xoff_rx,
2198 for (i = 0; i < 8; i++) {
2199 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2201 &os->priority_xon_rx[i],
2202 &ns->priority_xon_rx[i]);
2203 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2205 &os->priority_xoff_rx[i],
2206 &ns->priority_xoff_rx[i]);
2208 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2209 pf->offset_loaded, &os->link_xon_tx,
2211 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2212 pf->offset_loaded, &os->link_xoff_tx,
2214 for (i = 0; i < 8; i++) {
2215 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2217 &os->priority_xon_tx[i],
2218 &ns->priority_xon_tx[i]);
2219 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2221 &os->priority_xoff_tx[i],
2222 &ns->priority_xoff_tx[i]);
2223 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2225 &os->priority_xon_2_xoff[i],
2226 &ns->priority_xon_2_xoff[i]);
2228 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2229 I40E_GLPRT_PRC64L(hw->port),
2230 pf->offset_loaded, &os->rx_size_64,
2232 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2233 I40E_GLPRT_PRC127L(hw->port),
2234 pf->offset_loaded, &os->rx_size_127,
2236 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2237 I40E_GLPRT_PRC255L(hw->port),
2238 pf->offset_loaded, &os->rx_size_255,
2240 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2241 I40E_GLPRT_PRC511L(hw->port),
2242 pf->offset_loaded, &os->rx_size_511,
2244 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2245 I40E_GLPRT_PRC1023L(hw->port),
2246 pf->offset_loaded, &os->rx_size_1023,
2248 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2249 I40E_GLPRT_PRC1522L(hw->port),
2250 pf->offset_loaded, &os->rx_size_1522,
2252 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2253 I40E_GLPRT_PRC9522L(hw->port),
2254 pf->offset_loaded, &os->rx_size_big,
2256 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2257 pf->offset_loaded, &os->rx_undersize,
2259 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2260 pf->offset_loaded, &os->rx_fragments,
2262 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2263 pf->offset_loaded, &os->rx_oversize,
2265 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2266 pf->offset_loaded, &os->rx_jabber,
2268 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2269 I40E_GLPRT_PTC64L(hw->port),
2270 pf->offset_loaded, &os->tx_size_64,
2272 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2273 I40E_GLPRT_PTC127L(hw->port),
2274 pf->offset_loaded, &os->tx_size_127,
2276 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2277 I40E_GLPRT_PTC255L(hw->port),
2278 pf->offset_loaded, &os->tx_size_255,
2280 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2281 I40E_GLPRT_PTC511L(hw->port),
2282 pf->offset_loaded, &os->tx_size_511,
2284 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2285 I40E_GLPRT_PTC1023L(hw->port),
2286 pf->offset_loaded, &os->tx_size_1023,
2288 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2289 I40E_GLPRT_PTC1522L(hw->port),
2290 pf->offset_loaded, &os->tx_size_1522,
2292 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2293 I40E_GLPRT_PTC9522L(hw->port),
2294 pf->offset_loaded, &os->tx_size_big,
2296 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2298 &os->fd_sb_match, &ns->fd_sb_match);
2299 /* GLPRT_MSPDC not supported */
2300 /* GLPRT_XEC not supported */
2302 pf->offset_loaded = true;
2305 i40e_update_vsi_stats(pf->main_vsi);
2308 /* Get all statistics of a port */
2310 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2312 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2313 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2314 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2317 /* call read registers - updates values, now write them to struct */
2318 i40e_read_stats_registers(pf, hw);
2320 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2321 pf->main_vsi->eth_stats.rx_multicast +
2322 pf->main_vsi->eth_stats.rx_broadcast -
2323 pf->main_vsi->eth_stats.rx_discards;
2324 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2325 pf->main_vsi->eth_stats.tx_multicast +
2326 pf->main_vsi->eth_stats.tx_broadcast;
2327 stats->ibytes = ns->eth.rx_bytes;
2328 stats->obytes = ns->eth.tx_bytes;
2329 stats->oerrors = ns->eth.tx_errors +
2330 pf->main_vsi->eth_stats.tx_errors;
2333 stats->imissed = ns->eth.rx_discards +
2334 pf->main_vsi->eth_stats.rx_discards;
2335 stats->ierrors = ns->crc_errors +
2336 ns->rx_length_errors + ns->rx_undersize +
2337 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2339 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2340 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2341 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2342 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2343 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2344 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2345 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2346 ns->eth.rx_unknown_protocol);
2347 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2348 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2349 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2350 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2351 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2352 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2354 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2355 ns->tx_dropped_link_down);
2356 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2357 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2359 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2360 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2361 ns->mac_local_faults);
2362 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2363 ns->mac_remote_faults);
2364 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2365 ns->rx_length_errors);
2366 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2367 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2368 for (i = 0; i < 8; i++) {
2369 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2370 i, ns->priority_xon_rx[i]);
2371 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2372 i, ns->priority_xoff_rx[i]);
2374 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2375 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2376 for (i = 0; i < 8; i++) {
2377 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2378 i, ns->priority_xon_tx[i]);
2379 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2380 i, ns->priority_xoff_tx[i]);
2381 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2382 i, ns->priority_xon_2_xoff[i]);
2384 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2385 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2386 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2387 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2388 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2389 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2390 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2391 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2392 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2393 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2394 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2395 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2396 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2397 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2398 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2399 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2400 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2401 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2402 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2403 ns->mac_short_packet_dropped);
2404 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2405 ns->checksum_error);
2406 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2407 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2410 /* Reset the statistics */
2412 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2414 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2415 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2417 /* Mark PF and VSI stats to update the offset, aka "reset" */
2418 pf->offset_loaded = false;
2420 pf->main_vsi->offset_loaded = false;
2422 /* read the stats, reading current register values into offset */
2423 i40e_read_stats_registers(pf, hw);
2427 i40e_xstats_calc_num(void)
2429 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2430 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2431 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2434 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2435 struct rte_eth_xstat_name *xstats_names,
2436 __rte_unused unsigned limit)
2441 if (xstats_names == NULL)
2442 return i40e_xstats_calc_num();
2444 /* Note: limit checked in rte_eth_xstats_names() */
2446 /* Get stats from i40e_eth_stats struct */
2447 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2448 snprintf(xstats_names[count].name,
2449 sizeof(xstats_names[count].name),
2450 "%s", rte_i40e_stats_strings[i].name);
2454 /* Get individiual stats from i40e_hw_port struct */
2455 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2456 snprintf(xstats_names[count].name,
2457 sizeof(xstats_names[count].name),
2458 "%s", rte_i40e_hw_port_strings[i].name);
2462 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2463 for (prio = 0; prio < 8; prio++) {
2464 snprintf(xstats_names[count].name,
2465 sizeof(xstats_names[count].name),
2466 "rx_priority%u_%s", prio,
2467 rte_i40e_rxq_prio_strings[i].name);
2472 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2473 for (prio = 0; prio < 8; prio++) {
2474 snprintf(xstats_names[count].name,
2475 sizeof(xstats_names[count].name),
2476 "tx_priority%u_%s", prio,
2477 rte_i40e_txq_prio_strings[i].name);
2485 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2488 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2489 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2490 unsigned i, count, prio;
2491 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2493 count = i40e_xstats_calc_num();
2497 i40e_read_stats_registers(pf, hw);
2504 /* Get stats from i40e_eth_stats struct */
2505 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2506 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2507 rte_i40e_stats_strings[i].offset);
2511 /* Get individiual stats from i40e_hw_port struct */
2512 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2513 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2514 rte_i40e_hw_port_strings[i].offset);
2518 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2519 for (prio = 0; prio < 8; prio++) {
2520 xstats[count].value =
2521 *(uint64_t *)(((char *)hw_stats) +
2522 rte_i40e_rxq_prio_strings[i].offset +
2523 (sizeof(uint64_t) * prio));
2528 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2529 for (prio = 0; prio < 8; prio++) {
2530 xstats[count].value =
2531 *(uint64_t *)(((char *)hw_stats) +
2532 rte_i40e_txq_prio_strings[i].offset +
2533 (sizeof(uint64_t) * prio));
2542 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2543 __rte_unused uint16_t queue_id,
2544 __rte_unused uint8_t stat_idx,
2545 __rte_unused uint8_t is_rx)
2547 PMD_INIT_FUNC_TRACE();
2553 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2555 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2556 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2557 struct i40e_vsi *vsi = pf->main_vsi;
2559 dev_info->max_rx_queues = vsi->nb_qps;
2560 dev_info->max_tx_queues = vsi->nb_qps;
2561 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2562 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2563 dev_info->max_mac_addrs = vsi->max_macaddrs;
2564 dev_info->max_vfs = dev->pci_dev->max_vfs;
2565 dev_info->rx_offload_capa =
2566 DEV_RX_OFFLOAD_VLAN_STRIP |
2567 DEV_RX_OFFLOAD_QINQ_STRIP |
2568 DEV_RX_OFFLOAD_IPV4_CKSUM |
2569 DEV_RX_OFFLOAD_UDP_CKSUM |
2570 DEV_RX_OFFLOAD_TCP_CKSUM;
2571 dev_info->tx_offload_capa =
2572 DEV_TX_OFFLOAD_VLAN_INSERT |
2573 DEV_TX_OFFLOAD_QINQ_INSERT |
2574 DEV_TX_OFFLOAD_IPV4_CKSUM |
2575 DEV_TX_OFFLOAD_UDP_CKSUM |
2576 DEV_TX_OFFLOAD_TCP_CKSUM |
2577 DEV_TX_OFFLOAD_SCTP_CKSUM |
2578 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2579 DEV_TX_OFFLOAD_TCP_TSO;
2580 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2582 dev_info->reta_size = pf->hash_lut_size;
2583 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2585 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2587 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2588 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2589 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2591 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2595 dev_info->default_txconf = (struct rte_eth_txconf) {
2597 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2598 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2599 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2601 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2602 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2603 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2604 ETH_TXQ_FLAGS_NOOFFLOADS,
2607 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2608 .nb_max = I40E_MAX_RING_DESC,
2609 .nb_min = I40E_MIN_RING_DESC,
2610 .nb_align = I40E_ALIGN_RING_DESC,
2613 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2614 .nb_max = I40E_MAX_RING_DESC,
2615 .nb_min = I40E_MIN_RING_DESC,
2616 .nb_align = I40E_ALIGN_RING_DESC,
2619 if (pf->flags & I40E_FLAG_VMDQ) {
2620 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2621 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2622 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2623 pf->max_nb_vmdq_vsi;
2624 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2625 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2626 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2629 if (i40e_is_40G_device(hw->device_id))
2631 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2634 dev_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
2638 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2640 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2641 struct i40e_vsi *vsi = pf->main_vsi;
2642 PMD_INIT_FUNC_TRACE();
2645 return i40e_vsi_add_vlan(vsi, vlan_id);
2647 return i40e_vsi_delete_vlan(vsi, vlan_id);
2651 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2652 enum rte_vlan_type vlan_type,
2655 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2656 uint64_t reg_r = 0, reg_w = 0;
2657 uint16_t reg_id = 0;
2659 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2661 switch (vlan_type) {
2662 case ETH_VLAN_TYPE_OUTER:
2668 case ETH_VLAN_TYPE_INNER:
2674 "Unsupported vlan type in single vlan.\n");
2680 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2683 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2685 if (ret != I40E_SUCCESS) {
2686 PMD_DRV_LOG(ERR, "Fail to debug read from "
2687 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2691 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2692 "0x%08"PRIx64"", reg_id, reg_r);
2694 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2695 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2696 if (reg_r == reg_w) {
2698 PMD_DRV_LOG(DEBUG, "No need to write");
2702 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2704 if (ret != I40E_SUCCESS) {
2706 PMD_DRV_LOG(ERR, "Fail to debug write to "
2707 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2710 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2711 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2717 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2719 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2720 struct i40e_vsi *vsi = pf->main_vsi;
2722 if (mask & ETH_VLAN_FILTER_MASK) {
2723 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2724 i40e_vsi_config_vlan_filter(vsi, TRUE);
2726 i40e_vsi_config_vlan_filter(vsi, FALSE);
2729 if (mask & ETH_VLAN_STRIP_MASK) {
2730 /* Enable or disable VLAN stripping */
2731 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2732 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2734 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2737 if (mask & ETH_VLAN_EXTEND_MASK) {
2738 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2739 i40e_vsi_config_double_vlan(vsi, TRUE);
2740 /* Set global registers with default ether type value */
2741 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2743 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2747 i40e_vsi_config_double_vlan(vsi, FALSE);
2752 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2753 __rte_unused uint16_t queue,
2754 __rte_unused int on)
2756 PMD_INIT_FUNC_TRACE();
2760 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2762 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2763 struct i40e_vsi *vsi = pf->main_vsi;
2764 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2765 struct i40e_vsi_vlan_pvid_info info;
2767 memset(&info, 0, sizeof(info));
2770 info.config.pvid = pvid;
2772 info.config.reject.tagged =
2773 data->dev_conf.txmode.hw_vlan_reject_tagged;
2774 info.config.reject.untagged =
2775 data->dev_conf.txmode.hw_vlan_reject_untagged;
2778 return i40e_vsi_vlan_pvid_set(vsi, &info);
2782 i40e_dev_led_on(struct rte_eth_dev *dev)
2784 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2785 uint32_t mode = i40e_led_get(hw);
2788 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2794 i40e_dev_led_off(struct rte_eth_dev *dev)
2796 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2797 uint32_t mode = i40e_led_get(hw);
2800 i40e_led_set(hw, 0, false);
2806 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2808 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2809 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2811 fc_conf->pause_time = pf->fc_conf.pause_time;
2812 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2813 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2815 /* Return current mode according to actual setting*/
2816 switch (hw->fc.current_mode) {
2818 fc_conf->mode = RTE_FC_FULL;
2820 case I40E_FC_TX_PAUSE:
2821 fc_conf->mode = RTE_FC_TX_PAUSE;
2823 case I40E_FC_RX_PAUSE:
2824 fc_conf->mode = RTE_FC_RX_PAUSE;
2828 fc_conf->mode = RTE_FC_NONE;
2835 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2837 uint32_t mflcn_reg, fctrl_reg, reg;
2838 uint32_t max_high_water;
2839 uint8_t i, aq_failure;
2843 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2844 [RTE_FC_NONE] = I40E_FC_NONE,
2845 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2846 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2847 [RTE_FC_FULL] = I40E_FC_FULL
2850 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2852 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2853 if ((fc_conf->high_water > max_high_water) ||
2854 (fc_conf->high_water < fc_conf->low_water)) {
2855 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2856 "High_water must <= %d.", max_high_water);
2860 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2861 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2862 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2864 pf->fc_conf.pause_time = fc_conf->pause_time;
2865 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2866 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2868 PMD_INIT_FUNC_TRACE();
2870 /* All the link flow control related enable/disable register
2871 * configuration is handle by the F/W
2873 err = i40e_set_fc(hw, &aq_failure, true);
2877 if (i40e_is_40G_device(hw->device_id)) {
2878 /* Configure flow control refresh threshold,
2879 * the value for stat_tx_pause_refresh_timer[8]
2880 * is used for global pause operation.
2884 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2885 pf->fc_conf.pause_time);
2887 /* configure the timer value included in transmitted pause
2889 * the value for stat_tx_pause_quanta[8] is used for global
2892 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2893 pf->fc_conf.pause_time);
2895 fctrl_reg = I40E_READ_REG(hw,
2896 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2898 if (fc_conf->mac_ctrl_frame_fwd != 0)
2899 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2901 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2903 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2906 /* Configure pause time (2 TCs per register) */
2907 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2908 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2909 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2911 /* Configure flow control refresh threshold value */
2912 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2913 pf->fc_conf.pause_time / 2);
2915 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2917 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2918 *depending on configuration
2920 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2921 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2922 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2924 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2925 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2928 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2931 /* config the water marker both based on the packets and bytes */
2932 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2933 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2934 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2935 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2936 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2937 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2938 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2939 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2941 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2942 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2945 I40E_WRITE_FLUSH(hw);
2951 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2952 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2954 PMD_INIT_FUNC_TRACE();
2959 /* Add a MAC address, and update filters */
2961 i40e_macaddr_add(struct rte_eth_dev *dev,
2962 struct ether_addr *mac_addr,
2963 __rte_unused uint32_t index,
2966 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2967 struct i40e_mac_filter_info mac_filter;
2968 struct i40e_vsi *vsi;
2971 /* If VMDQ not enabled or configured, return */
2972 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
2973 !pf->nb_cfg_vmdq_vsi)) {
2974 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2975 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
2980 if (pool > pf->nb_cfg_vmdq_vsi) {
2981 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2982 pool, pf->nb_cfg_vmdq_vsi);
2986 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2987 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2988 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2990 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2995 vsi = pf->vmdq[pool - 1].vsi;
2997 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2998 if (ret != I40E_SUCCESS) {
2999 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3004 /* Remove a MAC address, and update filters */
3006 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3008 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3009 struct i40e_vsi *vsi;
3010 struct rte_eth_dev_data *data = dev->data;
3011 struct ether_addr *macaddr;
3016 macaddr = &(data->mac_addrs[index]);
3018 pool_sel = dev->data->mac_pool_sel[index];
3020 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3021 if (pool_sel & (1ULL << i)) {
3025 /* No VMDQ pool enabled or configured */
3026 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3027 (i > pf->nb_cfg_vmdq_vsi)) {
3028 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3032 vsi = pf->vmdq[i - 1].vsi;
3034 ret = i40e_vsi_delete_mac(vsi, macaddr);
3037 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3044 /* Set perfect match or hash match of MAC and VLAN for a VF */
3046 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3047 struct rte_eth_mac_filter *filter,
3051 struct i40e_mac_filter_info mac_filter;
3052 struct ether_addr old_mac;
3053 struct ether_addr *new_mac;
3054 struct i40e_pf_vf *vf = NULL;
3059 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3062 hw = I40E_PF_TO_HW(pf);
3064 if (filter == NULL) {
3065 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3069 new_mac = &filter->mac_addr;
3071 if (is_zero_ether_addr(new_mac)) {
3072 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3076 vf_id = filter->dst_id;
3078 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3079 PMD_DRV_LOG(ERR, "Invalid argument.");
3082 vf = &pf->vfs[vf_id];
3084 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3085 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3090 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3091 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3093 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3096 mac_filter.filter_type = filter->filter_type;
3097 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3098 if (ret != I40E_SUCCESS) {
3099 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3102 ether_addr_copy(new_mac, &pf->dev_addr);
3104 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3106 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3107 if (ret != I40E_SUCCESS) {
3108 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3112 /* Clear device address as it has been removed */
3113 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3114 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3120 /* MAC filter handle */
3122 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3125 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3126 struct rte_eth_mac_filter *filter;
3127 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3128 int ret = I40E_NOT_SUPPORTED;
3130 filter = (struct rte_eth_mac_filter *)(arg);
3132 switch (filter_op) {
3133 case RTE_ETH_FILTER_NOP:
3136 case RTE_ETH_FILTER_ADD:
3137 i40e_pf_disable_irq0(hw);
3139 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3140 i40e_pf_enable_irq0(hw);
3142 case RTE_ETH_FILTER_DELETE:
3143 i40e_pf_disable_irq0(hw);
3145 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3146 i40e_pf_enable_irq0(hw);
3149 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3150 ret = I40E_ERR_PARAM;
3158 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3160 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3161 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3167 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3168 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3171 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3175 uint32_t *lut_dw = (uint32_t *)lut;
3176 uint16_t i, lut_size_dw = lut_size / 4;
3178 for (i = 0; i < lut_size_dw; i++)
3179 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3186 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3195 pf = I40E_VSI_TO_PF(vsi);
3196 hw = I40E_VSI_TO_HW(vsi);
3198 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3199 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3202 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3206 uint32_t *lut_dw = (uint32_t *)lut;
3207 uint16_t i, lut_size_dw = lut_size / 4;
3209 for (i = 0; i < lut_size_dw; i++)
3210 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3211 I40E_WRITE_FLUSH(hw);
3218 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3219 struct rte_eth_rss_reta_entry64 *reta_conf,
3222 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3223 uint16_t i, lut_size = pf->hash_lut_size;
3224 uint16_t idx, shift;
3228 if (reta_size != lut_size ||
3229 reta_size > ETH_RSS_RETA_SIZE_512) {
3230 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3231 "(%d) doesn't match the number hardware can supported "
3232 "(%d)\n", reta_size, lut_size);
3236 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3238 PMD_DRV_LOG(ERR, "No memory can be allocated");
3241 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3244 for (i = 0; i < reta_size; i++) {
3245 idx = i / RTE_RETA_GROUP_SIZE;
3246 shift = i % RTE_RETA_GROUP_SIZE;
3247 if (reta_conf[idx].mask & (1ULL << shift))
3248 lut[i] = reta_conf[idx].reta[shift];
3250 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3259 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3260 struct rte_eth_rss_reta_entry64 *reta_conf,
3263 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3264 uint16_t i, lut_size = pf->hash_lut_size;
3265 uint16_t idx, shift;
3269 if (reta_size != lut_size ||
3270 reta_size > ETH_RSS_RETA_SIZE_512) {
3271 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3272 "(%d) doesn't match the number hardware can supported "
3273 "(%d)\n", reta_size, lut_size);
3277 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3279 PMD_DRV_LOG(ERR, "No memory can be allocated");
3283 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3286 for (i = 0; i < reta_size; i++) {
3287 idx = i / RTE_RETA_GROUP_SIZE;
3288 shift = i % RTE_RETA_GROUP_SIZE;
3289 if (reta_conf[idx].mask & (1ULL << shift))
3290 reta_conf[idx].reta[shift] = lut[i];
3300 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3301 * @hw: pointer to the HW structure
3302 * @mem: pointer to mem struct to fill out
3303 * @size: size of memory requested
3304 * @alignment: what to align the allocation to
3306 enum i40e_status_code
3307 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3308 struct i40e_dma_mem *mem,
3312 const struct rte_memzone *mz = NULL;
3313 char z_name[RTE_MEMZONE_NAMESIZE];
3316 return I40E_ERR_PARAM;
3318 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3319 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3320 alignment, RTE_PGSIZE_2M);
3322 return I40E_ERR_NO_MEMORY;
3326 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3327 mem->zone = (const void *)mz;
3328 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3329 "%"PRIu64, mz->name, mem->pa);
3331 return I40E_SUCCESS;
3335 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3336 * @hw: pointer to the HW structure
3337 * @mem: ptr to mem struct to free
3339 enum i40e_status_code
3340 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3341 struct i40e_dma_mem *mem)
3344 return I40E_ERR_PARAM;
3346 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3347 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3349 rte_memzone_free((const struct rte_memzone *)mem->zone);
3354 return I40E_SUCCESS;
3358 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3359 * @hw: pointer to the HW structure
3360 * @mem: pointer to mem struct to fill out
3361 * @size: size of memory requested
3363 enum i40e_status_code
3364 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3365 struct i40e_virt_mem *mem,
3369 return I40E_ERR_PARAM;
3372 mem->va = rte_zmalloc("i40e", size, 0);
3375 return I40E_SUCCESS;
3377 return I40E_ERR_NO_MEMORY;
3381 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3382 * @hw: pointer to the HW structure
3383 * @mem: pointer to mem struct to free
3385 enum i40e_status_code
3386 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3387 struct i40e_virt_mem *mem)
3390 return I40E_ERR_PARAM;
3395 return I40E_SUCCESS;
3399 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3401 rte_spinlock_init(&sp->spinlock);
3405 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3407 rte_spinlock_lock(&sp->spinlock);
3411 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3413 rte_spinlock_unlock(&sp->spinlock);
3417 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3423 * Get the hardware capabilities, which will be parsed
3424 * and saved into struct i40e_hw.
3427 i40e_get_cap(struct i40e_hw *hw)
3429 struct i40e_aqc_list_capabilities_element_resp *buf;
3430 uint16_t len, size = 0;
3433 /* Calculate a huge enough buff for saving response data temporarily */
3434 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3435 I40E_MAX_CAP_ELE_NUM;
3436 buf = rte_zmalloc("i40e", len, 0);
3438 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3439 return I40E_ERR_NO_MEMORY;
3442 /* Get, parse the capabilities and save it to hw */
3443 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3444 i40e_aqc_opc_list_func_capabilities, NULL);
3445 if (ret != I40E_SUCCESS)
3446 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3448 /* Free the temporary buffer after being used */
3455 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3457 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3458 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3459 uint16_t qp_count = 0, vsi_count = 0;
3461 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3462 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3465 /* Add the parameter init for LFC */
3466 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3467 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3468 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3470 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3471 pf->max_num_vsi = hw->func_caps.num_vsis;
3472 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3473 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3474 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3476 /* FDir queue/VSI allocation */
3477 pf->fdir_qp_offset = 0;
3478 if (hw->func_caps.fd) {
3479 pf->flags |= I40E_FLAG_FDIR;
3480 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3482 pf->fdir_nb_qps = 0;
3484 qp_count += pf->fdir_nb_qps;
3487 /* LAN queue/VSI allocation */
3488 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3489 if (!hw->func_caps.rss) {
3492 pf->flags |= I40E_FLAG_RSS;
3493 if (hw->mac.type == I40E_MAC_X722)
3494 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3495 pf->lan_nb_qps = pf->lan_nb_qp_max;
3497 qp_count += pf->lan_nb_qps;
3500 /* VF queue/VSI allocation */
3501 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3502 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3503 pf->flags |= I40E_FLAG_SRIOV;
3504 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3505 pf->vf_num = dev->pci_dev->max_vfs;
3506 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3507 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3508 pf->vf_nb_qps * pf->vf_num);
3513 qp_count += pf->vf_nb_qps * pf->vf_num;
3514 vsi_count += pf->vf_num;
3516 /* VMDq queue/VSI allocation */
3517 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3518 pf->vmdq_nb_qps = 0;
3519 pf->max_nb_vmdq_vsi = 0;
3520 if (hw->func_caps.vmdq) {
3521 if (qp_count < hw->func_caps.num_tx_qp &&
3522 vsi_count < hw->func_caps.num_vsis) {
3523 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3524 qp_count) / pf->vmdq_nb_qp_max;
3526 /* Limit the maximum number of VMDq vsi to the maximum
3527 * ethdev can support
3529 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3530 hw->func_caps.num_vsis - vsi_count);
3531 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3533 if (pf->max_nb_vmdq_vsi) {
3534 pf->flags |= I40E_FLAG_VMDQ;
3535 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3536 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3537 "per VMDQ VSI, in total %u queues",
3538 pf->max_nb_vmdq_vsi,
3539 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3540 pf->max_nb_vmdq_vsi);
3542 PMD_DRV_LOG(INFO, "No enough queues left for "
3546 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3549 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3550 vsi_count += pf->max_nb_vmdq_vsi;
3552 if (hw->func_caps.dcb)
3553 pf->flags |= I40E_FLAG_DCB;
3555 if (qp_count > hw->func_caps.num_tx_qp) {
3556 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3557 "the hardware maximum %u", qp_count,
3558 hw->func_caps.num_tx_qp);
3561 if (vsi_count > hw->func_caps.num_vsis) {
3562 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3563 "the hardware maximum %u", vsi_count,
3564 hw->func_caps.num_vsis);
3572 i40e_pf_get_switch_config(struct i40e_pf *pf)
3574 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3575 struct i40e_aqc_get_switch_config_resp *switch_config;
3576 struct i40e_aqc_switch_config_element_resp *element;
3577 uint16_t start_seid = 0, num_reported;
3580 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3581 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3582 if (!switch_config) {
3583 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3587 /* Get the switch configurations */
3588 ret = i40e_aq_get_switch_config(hw, switch_config,
3589 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3590 if (ret != I40E_SUCCESS) {
3591 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3594 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3595 if (num_reported != 1) { /* The number should be 1 */
3596 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3600 /* Parse the switch configuration elements */
3601 element = &(switch_config->element[0]);
3602 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3603 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3604 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3606 PMD_DRV_LOG(INFO, "Unknown element type");
3609 rte_free(switch_config);
3615 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3618 struct pool_entry *entry;
3620 if (pool == NULL || num == 0)
3623 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3624 if (entry == NULL) {
3625 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3629 /* queue heap initialize */
3630 pool->num_free = num;
3631 pool->num_alloc = 0;
3633 LIST_INIT(&pool->alloc_list);
3634 LIST_INIT(&pool->free_list);
3636 /* Initialize element */
3640 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3645 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3647 struct pool_entry *entry, *next_entry;
3652 for (entry = LIST_FIRST(&pool->alloc_list);
3653 entry && (next_entry = LIST_NEXT(entry, next), 1);
3654 entry = next_entry) {
3655 LIST_REMOVE(entry, next);
3659 for (entry = LIST_FIRST(&pool->free_list);
3660 entry && (next_entry = LIST_NEXT(entry, next), 1);
3661 entry = next_entry) {
3662 LIST_REMOVE(entry, next);
3667 pool->num_alloc = 0;
3669 LIST_INIT(&pool->alloc_list);
3670 LIST_INIT(&pool->free_list);
3674 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3677 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3678 uint32_t pool_offset;
3682 PMD_DRV_LOG(ERR, "Invalid parameter");
3686 pool_offset = base - pool->base;
3687 /* Lookup in alloc list */
3688 LIST_FOREACH(entry, &pool->alloc_list, next) {
3689 if (entry->base == pool_offset) {
3690 valid_entry = entry;
3691 LIST_REMOVE(entry, next);
3696 /* Not find, return */
3697 if (valid_entry == NULL) {
3698 PMD_DRV_LOG(ERR, "Failed to find entry");
3703 * Found it, move it to free list and try to merge.
3704 * In order to make merge easier, always sort it by qbase.
3705 * Find adjacent prev and last entries.
3708 LIST_FOREACH(entry, &pool->free_list, next) {
3709 if (entry->base > valid_entry->base) {
3717 /* Try to merge with next one*/
3719 /* Merge with next one */
3720 if (valid_entry->base + valid_entry->len == next->base) {
3721 next->base = valid_entry->base;
3722 next->len += valid_entry->len;
3723 rte_free(valid_entry);
3730 /* Merge with previous one */
3731 if (prev->base + prev->len == valid_entry->base) {
3732 prev->len += valid_entry->len;
3733 /* If it merge with next one, remove next node */
3735 LIST_REMOVE(valid_entry, next);
3736 rte_free(valid_entry);
3738 rte_free(valid_entry);
3744 /* Not find any entry to merge, insert */
3747 LIST_INSERT_AFTER(prev, valid_entry, next);
3748 else if (next != NULL)
3749 LIST_INSERT_BEFORE(next, valid_entry, next);
3750 else /* It's empty list, insert to head */
3751 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3754 pool->num_free += valid_entry->len;
3755 pool->num_alloc -= valid_entry->len;
3761 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3764 struct pool_entry *entry, *valid_entry;
3766 if (pool == NULL || num == 0) {
3767 PMD_DRV_LOG(ERR, "Invalid parameter");
3771 if (pool->num_free < num) {
3772 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3773 num, pool->num_free);
3778 /* Lookup in free list and find most fit one */
3779 LIST_FOREACH(entry, &pool->free_list, next) {
3780 if (entry->len >= num) {
3782 if (entry->len == num) {
3783 valid_entry = entry;
3786 if (valid_entry == NULL || valid_entry->len > entry->len)
3787 valid_entry = entry;
3791 /* Not find one to satisfy the request, return */
3792 if (valid_entry == NULL) {
3793 PMD_DRV_LOG(ERR, "No valid entry found");
3797 * The entry have equal queue number as requested,
3798 * remove it from alloc_list.
3800 if (valid_entry->len == num) {
3801 LIST_REMOVE(valid_entry, next);
3804 * The entry have more numbers than requested,
3805 * create a new entry for alloc_list and minus its
3806 * queue base and number in free_list.
3808 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3809 if (entry == NULL) {
3810 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3814 entry->base = valid_entry->base;
3816 valid_entry->base += num;
3817 valid_entry->len -= num;
3818 valid_entry = entry;
3821 /* Insert it into alloc list, not sorted */
3822 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3824 pool->num_free -= valid_entry->len;
3825 pool->num_alloc += valid_entry->len;
3827 return valid_entry->base + pool->base;
3831 * bitmap_is_subset - Check whether src2 is subset of src1
3834 bitmap_is_subset(uint8_t src1, uint8_t src2)
3836 return !((src1 ^ src2) & src2);
3839 static enum i40e_status_code
3840 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3842 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3844 /* If DCB is not supported, only default TC is supported */
3845 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3846 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3847 return I40E_NOT_SUPPORTED;
3850 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3851 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3852 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3854 return I40E_NOT_SUPPORTED;
3856 return I40E_SUCCESS;
3860 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3861 struct i40e_vsi_vlan_pvid_info *info)
3864 struct i40e_vsi_context ctxt;
3865 uint8_t vlan_flags = 0;
3868 if (vsi == NULL || info == NULL) {
3869 PMD_DRV_LOG(ERR, "invalid parameters");
3870 return I40E_ERR_PARAM;
3874 vsi->info.pvid = info->config.pvid;
3876 * If insert pvid is enabled, only tagged pkts are
3877 * allowed to be sent out.
3879 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3880 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3883 if (info->config.reject.tagged == 0)
3884 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3886 if (info->config.reject.untagged == 0)
3887 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3889 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3890 I40E_AQ_VSI_PVLAN_MODE_MASK);
3891 vsi->info.port_vlan_flags |= vlan_flags;
3892 vsi->info.valid_sections =
3893 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3894 memset(&ctxt, 0, sizeof(ctxt));
3895 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3896 ctxt.seid = vsi->seid;
3898 hw = I40E_VSI_TO_HW(vsi);
3899 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3900 if (ret != I40E_SUCCESS)
3901 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3907 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3909 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3911 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3913 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3914 if (ret != I40E_SUCCESS)
3918 PMD_DRV_LOG(ERR, "seid not valid");
3922 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3923 tc_bw_data.tc_valid_bits = enabled_tcmap;
3924 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3925 tc_bw_data.tc_bw_credits[i] =
3926 (enabled_tcmap & (1 << i)) ? 1 : 0;
3928 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3929 if (ret != I40E_SUCCESS) {
3930 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3934 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3935 sizeof(vsi->info.qs_handle));
3936 return I40E_SUCCESS;
3939 static enum i40e_status_code
3940 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3941 struct i40e_aqc_vsi_properties_data *info,
3942 uint8_t enabled_tcmap)
3944 enum i40e_status_code ret;
3945 int i, total_tc = 0;
3946 uint16_t qpnum_per_tc, bsf, qp_idx;
3948 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3949 if (ret != I40E_SUCCESS)
3952 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3953 if (enabled_tcmap & (1 << i))
3955 vsi->enabled_tc = enabled_tcmap;
3957 /* Number of queues per enabled TC */
3958 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3959 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3960 bsf = rte_bsf32(qpnum_per_tc);
3962 /* Adjust the queue number to actual queues that can be applied */
3963 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3964 vsi->nb_qps = qpnum_per_tc * total_tc;
3967 * Configure TC and queue mapping parameters, for enabled TC,
3968 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3969 * default queue will serve it.
3972 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3973 if (vsi->enabled_tc & (1 << i)) {
3974 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3975 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3976 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3977 qp_idx += qpnum_per_tc;
3979 info->tc_mapping[i] = 0;
3982 /* Associate queue number with VSI */
3983 if (vsi->type == I40E_VSI_SRIOV) {
3984 info->mapping_flags |=
3985 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3986 for (i = 0; i < vsi->nb_qps; i++)
3987 info->queue_mapping[i] =
3988 rte_cpu_to_le_16(vsi->base_queue + i);
3990 info->mapping_flags |=
3991 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3992 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3994 info->valid_sections |=
3995 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3997 return I40E_SUCCESS;
4001 i40e_veb_release(struct i40e_veb *veb)
4003 struct i40e_vsi *vsi;
4009 if (!TAILQ_EMPTY(&veb->head)) {
4010 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4013 /* associate_vsi field is NULL for floating VEB */
4014 if (veb->associate_vsi != NULL) {
4015 vsi = veb->associate_vsi;
4016 hw = I40E_VSI_TO_HW(vsi);
4018 vsi->uplink_seid = veb->uplink_seid;
4021 veb->associate_pf->main_vsi->floating_veb = NULL;
4022 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4025 i40e_aq_delete_element(hw, veb->seid, NULL);
4027 return I40E_SUCCESS;
4031 static struct i40e_veb *
4032 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4034 struct i40e_veb *veb;
4040 "veb setup failed, associated PF shouldn't null");
4043 hw = I40E_PF_TO_HW(pf);
4045 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4047 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4051 veb->associate_vsi = vsi;
4052 veb->associate_pf = pf;
4053 TAILQ_INIT(&veb->head);
4054 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4056 /* create floating veb if vsi is NULL */
4058 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4059 I40E_DEFAULT_TCMAP, false,
4060 &veb->seid, false, NULL);
4062 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4063 true, &veb->seid, false, NULL);
4066 if (ret != I40E_SUCCESS) {
4067 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4068 hw->aq.asq_last_status);
4072 /* get statistics index */
4073 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4074 &veb->stats_idx, NULL, NULL, NULL);
4075 if (ret != I40E_SUCCESS) {
4076 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4077 hw->aq.asq_last_status);
4080 /* Get VEB bandwidth, to be implemented */
4081 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4083 vsi->uplink_seid = veb->seid;
4092 i40e_vsi_release(struct i40e_vsi *vsi)
4096 struct i40e_vsi_list *vsi_list;
4098 struct i40e_mac_filter *f;
4099 uint16_t user_param = vsi->user_param;
4102 return I40E_SUCCESS;
4104 pf = I40E_VSI_TO_PF(vsi);
4105 hw = I40E_VSI_TO_HW(vsi);
4107 /* VSI has child to attach, release child first */
4109 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
4110 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4112 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
4114 i40e_veb_release(vsi->veb);
4117 if (vsi->floating_veb) {
4118 TAILQ_FOREACH(vsi_list, &vsi->floating_veb->head, list) {
4119 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4121 TAILQ_REMOVE(&vsi->floating_veb->head, vsi_list, list);
4125 /* Remove all macvlan filters of the VSI */
4126 i40e_vsi_remove_all_macvlan_filter(vsi);
4127 TAILQ_FOREACH(f, &vsi->mac_list, next)
4130 if (vsi->type != I40E_VSI_MAIN &&
4131 ((vsi->type != I40E_VSI_SRIOV) ||
4132 !pf->floating_veb_list[user_param])) {
4133 /* Remove vsi from parent's sibling list */
4134 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4135 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4136 return I40E_ERR_PARAM;
4138 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4139 &vsi->sib_vsi_list, list);
4141 /* Remove all switch element of the VSI */
4142 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4143 if (ret != I40E_SUCCESS)
4144 PMD_DRV_LOG(ERR, "Failed to delete element");
4147 if ((vsi->type == I40E_VSI_SRIOV) &&
4148 pf->floating_veb_list[user_param]) {
4149 /* Remove vsi from parent's sibling list */
4150 if (vsi->parent_vsi == NULL ||
4151 vsi->parent_vsi->floating_veb == NULL) {
4152 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4153 return I40E_ERR_PARAM;
4155 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4156 &vsi->sib_vsi_list, list);
4158 /* Remove all switch element of the VSI */
4159 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4160 if (ret != I40E_SUCCESS)
4161 PMD_DRV_LOG(ERR, "Failed to delete element");
4164 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4166 if (vsi->type != I40E_VSI_SRIOV)
4167 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4170 return I40E_SUCCESS;
4174 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4176 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4177 struct i40e_aqc_remove_macvlan_element_data def_filter;
4178 struct i40e_mac_filter_info filter;
4181 if (vsi->type != I40E_VSI_MAIN)
4182 return I40E_ERR_CONFIG;
4183 memset(&def_filter, 0, sizeof(def_filter));
4184 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4186 def_filter.vlan_tag = 0;
4187 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4188 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4189 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4190 if (ret != I40E_SUCCESS) {
4191 struct i40e_mac_filter *f;
4192 struct ether_addr *mac;
4194 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4196 /* It needs to add the permanent mac into mac list */
4197 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4199 PMD_DRV_LOG(ERR, "failed to allocate memory");
4200 return I40E_ERR_NO_MEMORY;
4202 mac = &f->mac_info.mac_addr;
4203 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4205 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4206 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4211 (void)rte_memcpy(&filter.mac_addr,
4212 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4213 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4214 return i40e_vsi_add_mac(vsi, &filter);
4218 * i40e_vsi_get_bw_config - Query VSI BW Information
4219 * @vsi: the VSI to be queried
4221 * Returns 0 on success, negative value on failure
4223 static enum i40e_status_code
4224 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4226 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4227 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4228 struct i40e_hw *hw = &vsi->adapter->hw;
4233 memset(&bw_config, 0, sizeof(bw_config));
4234 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4235 if (ret != I40E_SUCCESS) {
4236 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4237 hw->aq.asq_last_status);
4241 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4242 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4243 &ets_sla_config, NULL);
4244 if (ret != I40E_SUCCESS) {
4245 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4246 "configuration %u", hw->aq.asq_last_status);
4250 /* store and print out BW info */
4251 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4252 vsi->bw_info.bw_max = bw_config.max_bw;
4253 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4254 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4255 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4256 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4258 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4259 vsi->bw_info.bw_ets_share_credits[i] =
4260 ets_sla_config.share_credits[i];
4261 vsi->bw_info.bw_ets_credits[i] =
4262 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4263 /* 4 bits per TC, 4th bit is reserved */
4264 vsi->bw_info.bw_ets_max[i] =
4265 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4266 RTE_LEN2MASK(3, uint8_t));
4267 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4268 vsi->bw_info.bw_ets_share_credits[i]);
4269 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4270 vsi->bw_info.bw_ets_credits[i]);
4271 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4272 vsi->bw_info.bw_ets_max[i]);
4275 return I40E_SUCCESS;
4278 /* i40e_enable_pf_lb
4279 * @pf: pointer to the pf structure
4281 * allow loopback on pf
4284 i40e_enable_pf_lb(struct i40e_pf *pf)
4286 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4287 struct i40e_vsi_context ctxt;
4290 /* Use the FW API if FW >= v5.0 */
4291 if (hw->aq.fw_maj_ver < 5) {
4292 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4296 memset(&ctxt, 0, sizeof(ctxt));
4297 ctxt.seid = pf->main_vsi_seid;
4298 ctxt.pf_num = hw->pf_id;
4299 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4301 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4302 ret, hw->aq.asq_last_status);
4305 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4306 ctxt.info.valid_sections =
4307 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4308 ctxt.info.switch_id |=
4309 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4311 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4313 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4314 hw->aq.asq_last_status);
4319 i40e_vsi_setup(struct i40e_pf *pf,
4320 enum i40e_vsi_type type,
4321 struct i40e_vsi *uplink_vsi,
4322 uint16_t user_param)
4324 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4325 struct i40e_vsi *vsi;
4326 struct i40e_mac_filter_info filter;
4328 struct i40e_vsi_context ctxt;
4329 struct ether_addr broadcast =
4330 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4332 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4333 uplink_vsi == NULL) {
4334 PMD_DRV_LOG(ERR, "VSI setup failed, "
4335 "VSI link shouldn't be NULL");
4339 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4340 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4341 "uplink VSI should be NULL");
4346 * 1.type is not MAIN and uplink vsi is not NULL
4347 * If uplink vsi didn't setup VEB, create one first under veb field
4348 * 2.type is SRIOV and the uplink is NULL
4349 * If floating VEB is NULL, create one veb under floating veb field
4352 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4353 uplink_vsi->veb == NULL) {
4354 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4356 if (uplink_vsi->veb == NULL) {
4357 PMD_DRV_LOG(ERR, "VEB setup failed");
4360 /* set ALLOWLOOPBACk on pf, when veb is created */
4361 i40e_enable_pf_lb(pf);
4364 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4365 pf->main_vsi->floating_veb == NULL) {
4366 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4368 if (pf->main_vsi->floating_veb == NULL) {
4369 PMD_DRV_LOG(ERR, "VEB setup failed");
4374 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4376 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4379 TAILQ_INIT(&vsi->mac_list);
4381 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4382 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4383 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4384 vsi->user_param = user_param;
4385 /* Allocate queues */
4386 switch (vsi->type) {
4387 case I40E_VSI_MAIN :
4388 vsi->nb_qps = pf->lan_nb_qps;
4390 case I40E_VSI_SRIOV :
4391 vsi->nb_qps = pf->vf_nb_qps;
4393 case I40E_VSI_VMDQ2:
4394 vsi->nb_qps = pf->vmdq_nb_qps;
4397 vsi->nb_qps = pf->fdir_nb_qps;
4403 * The filter status descriptor is reported in rx queue 0,
4404 * while the tx queue for fdir filter programming has no
4405 * such constraints, can be non-zero queues.
4406 * To simplify it, choose FDIR vsi use queue 0 pair.
4407 * To make sure it will use queue 0 pair, queue allocation
4408 * need be done before this function is called
4410 if (type != I40E_VSI_FDIR) {
4411 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4413 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4417 vsi->base_queue = ret;
4419 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4421 /* VF has MSIX interrupt in VF range, don't allocate here */
4422 if (type == I40E_VSI_MAIN) {
4423 ret = i40e_res_pool_alloc(&pf->msix_pool,
4424 RTE_MIN(vsi->nb_qps,
4425 RTE_MAX_RXTX_INTR_VEC_ID));
4427 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4429 goto fail_queue_alloc;
4431 vsi->msix_intr = ret;
4432 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4433 } else if (type != I40E_VSI_SRIOV) {
4434 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4436 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4437 goto fail_queue_alloc;
4439 vsi->msix_intr = ret;
4447 if (type == I40E_VSI_MAIN) {
4448 /* For main VSI, no need to add since it's default one */
4449 vsi->uplink_seid = pf->mac_seid;
4450 vsi->seid = pf->main_vsi_seid;
4451 /* Bind queues with specific MSIX interrupt */
4453 * Needs 2 interrupt at least, one for misc cause which will
4454 * enabled from OS side, Another for queues binding the
4455 * interrupt from device side only.
4458 /* Get default VSI parameters from hardware */
4459 memset(&ctxt, 0, sizeof(ctxt));
4460 ctxt.seid = vsi->seid;
4461 ctxt.pf_num = hw->pf_id;
4462 ctxt.uplink_seid = vsi->uplink_seid;
4464 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4465 if (ret != I40E_SUCCESS) {
4466 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4467 goto fail_msix_alloc;
4469 (void)rte_memcpy(&vsi->info, &ctxt.info,
4470 sizeof(struct i40e_aqc_vsi_properties_data));
4471 vsi->vsi_id = ctxt.vsi_number;
4472 vsi->info.valid_sections = 0;
4474 /* Configure tc, enabled TC0 only */
4475 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4477 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4478 goto fail_msix_alloc;
4481 /* TC, queue mapping */
4482 memset(&ctxt, 0, sizeof(ctxt));
4483 vsi->info.valid_sections |=
4484 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4485 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4486 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4487 (void)rte_memcpy(&ctxt.info, &vsi->info,
4488 sizeof(struct i40e_aqc_vsi_properties_data));
4489 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4490 I40E_DEFAULT_TCMAP);
4491 if (ret != I40E_SUCCESS) {
4492 PMD_DRV_LOG(ERR, "Failed to configure "
4493 "TC queue mapping");
4494 goto fail_msix_alloc;
4496 ctxt.seid = vsi->seid;
4497 ctxt.pf_num = hw->pf_id;
4498 ctxt.uplink_seid = vsi->uplink_seid;
4501 /* Update VSI parameters */
4502 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4503 if (ret != I40E_SUCCESS) {
4504 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4505 goto fail_msix_alloc;
4508 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4509 sizeof(vsi->info.tc_mapping));
4510 (void)rte_memcpy(&vsi->info.queue_mapping,
4511 &ctxt.info.queue_mapping,
4512 sizeof(vsi->info.queue_mapping));
4513 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4514 vsi->info.valid_sections = 0;
4516 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4520 * Updating default filter settings are necessary to prevent
4521 * reception of tagged packets.
4522 * Some old firmware configurations load a default macvlan
4523 * filter which accepts both tagged and untagged packets.
4524 * The updating is to use a normal filter instead if needed.
4525 * For NVM 4.2.2 or after, the updating is not needed anymore.
4526 * The firmware with correct configurations load the default
4527 * macvlan filter which is expected and cannot be removed.
4529 i40e_update_default_filter_setting(vsi);
4530 i40e_config_qinq(hw, vsi);
4531 } else if (type == I40E_VSI_SRIOV) {
4532 memset(&ctxt, 0, sizeof(ctxt));
4534 * For other VSI, the uplink_seid equals to uplink VSI's
4535 * uplink_seid since they share same VEB
4537 if (uplink_vsi == NULL)
4538 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4540 vsi->uplink_seid = uplink_vsi->uplink_seid;
4541 ctxt.pf_num = hw->pf_id;
4542 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4543 ctxt.uplink_seid = vsi->uplink_seid;
4544 ctxt.connection_type = 0x1;
4545 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4547 /* Use the VEB configuration if FW >= v5.0 */
4548 if (hw->aq.fw_maj_ver >= 5) {
4549 /* Configure switch ID */
4550 ctxt.info.valid_sections |=
4551 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4552 ctxt.info.switch_id =
4553 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4556 /* Configure port/vlan */
4557 ctxt.info.valid_sections |=
4558 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4559 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4560 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4561 I40E_DEFAULT_TCMAP);
4562 if (ret != I40E_SUCCESS) {
4563 PMD_DRV_LOG(ERR, "Failed to configure "
4564 "TC queue mapping");
4565 goto fail_msix_alloc;
4567 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4568 ctxt.info.valid_sections |=
4569 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4571 * Since VSI is not created yet, only configure parameter,
4572 * will add vsi below.
4575 i40e_config_qinq(hw, vsi);
4576 } else if (type == I40E_VSI_VMDQ2) {
4577 memset(&ctxt, 0, sizeof(ctxt));
4579 * For other VSI, the uplink_seid equals to uplink VSI's
4580 * uplink_seid since they share same VEB
4582 vsi->uplink_seid = uplink_vsi->uplink_seid;
4583 ctxt.pf_num = hw->pf_id;
4585 ctxt.uplink_seid = vsi->uplink_seid;
4586 ctxt.connection_type = 0x1;
4587 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4589 ctxt.info.valid_sections |=
4590 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4591 /* user_param carries flag to enable loop back */
4593 ctxt.info.switch_id =
4594 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4595 ctxt.info.switch_id |=
4596 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4599 /* Configure port/vlan */
4600 ctxt.info.valid_sections |=
4601 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4602 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4603 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4604 I40E_DEFAULT_TCMAP);
4605 if (ret != I40E_SUCCESS) {
4606 PMD_DRV_LOG(ERR, "Failed to configure "
4607 "TC queue mapping");
4608 goto fail_msix_alloc;
4610 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4611 ctxt.info.valid_sections |=
4612 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4613 } else if (type == I40E_VSI_FDIR) {
4614 memset(&ctxt, 0, sizeof(ctxt));
4615 vsi->uplink_seid = uplink_vsi->uplink_seid;
4616 ctxt.pf_num = hw->pf_id;
4618 ctxt.uplink_seid = vsi->uplink_seid;
4619 ctxt.connection_type = 0x1; /* regular data port */
4620 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4621 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4622 I40E_DEFAULT_TCMAP);
4623 if (ret != I40E_SUCCESS) {
4624 PMD_DRV_LOG(ERR, "Failed to configure "
4625 "TC queue mapping.");
4626 goto fail_msix_alloc;
4628 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4629 ctxt.info.valid_sections |=
4630 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4632 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4633 goto fail_msix_alloc;
4636 if (vsi->type != I40E_VSI_MAIN) {
4637 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4638 if (ret != I40E_SUCCESS) {
4639 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4640 hw->aq.asq_last_status);
4641 goto fail_msix_alloc;
4643 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4644 vsi->info.valid_sections = 0;
4645 vsi->seid = ctxt.seid;
4646 vsi->vsi_id = ctxt.vsi_number;
4647 vsi->sib_vsi_list.vsi = vsi;
4648 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4649 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4650 &vsi->sib_vsi_list, list);
4652 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4653 &vsi->sib_vsi_list, list);
4657 /* MAC/VLAN configuration */
4658 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4659 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4661 ret = i40e_vsi_add_mac(vsi, &filter);
4662 if (ret != I40E_SUCCESS) {
4663 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4664 goto fail_msix_alloc;
4667 /* Get VSI BW information */
4668 i40e_vsi_get_bw_config(vsi);
4671 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4673 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4679 /* Configure vlan filter on or off */
4681 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4684 struct i40e_mac_filter *f;
4685 struct i40e_mac_filter_info *mac_filter;
4686 enum rte_mac_filter_type desired_filter;
4687 int ret = I40E_SUCCESS;
4690 /* Filter to match MAC and VLAN */
4691 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4693 /* Filter to match only MAC */
4694 desired_filter = RTE_MAC_PERFECT_MATCH;
4699 mac_filter = rte_zmalloc("mac_filter_info_data",
4700 num * sizeof(*mac_filter), 0);
4701 if (mac_filter == NULL) {
4702 PMD_DRV_LOG(ERR, "failed to allocate memory");
4703 return I40E_ERR_NO_MEMORY;
4708 /* Remove all existing mac */
4709 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4710 mac_filter[i] = f->mac_info;
4711 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4713 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4714 on ? "enable" : "disable");
4720 /* Override with new filter */
4721 for (i = 0; i < num; i++) {
4722 mac_filter[i].filter_type = desired_filter;
4723 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4725 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4726 on ? "enable" : "disable");
4732 rte_free(mac_filter);
4736 /* Configure vlan stripping on or off */
4738 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4740 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4741 struct i40e_vsi_context ctxt;
4743 int ret = I40E_SUCCESS;
4745 /* Check if it has been already on or off */
4746 if (vsi->info.valid_sections &
4747 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4749 if ((vsi->info.port_vlan_flags &
4750 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4751 return 0; /* already on */
4753 if ((vsi->info.port_vlan_flags &
4754 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4755 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4756 return 0; /* already off */
4761 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4763 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4764 vsi->info.valid_sections =
4765 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4766 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4767 vsi->info.port_vlan_flags |= vlan_flags;
4768 ctxt.seid = vsi->seid;
4769 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4770 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4772 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4773 on ? "enable" : "disable");
4779 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4781 struct rte_eth_dev_data *data = dev->data;
4785 /* Apply vlan offload setting */
4786 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4787 i40e_vlan_offload_set(dev, mask);
4789 /* Apply double-vlan setting, not implemented yet */
4791 /* Apply pvid setting */
4792 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4793 data->dev_conf.txmode.hw_vlan_insert_pvid);
4795 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4801 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4803 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4805 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4809 i40e_update_flow_control(struct i40e_hw *hw)
4811 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4812 struct i40e_link_status link_status;
4813 uint32_t rxfc = 0, txfc = 0, reg;
4817 memset(&link_status, 0, sizeof(link_status));
4818 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4819 if (ret != I40E_SUCCESS) {
4820 PMD_DRV_LOG(ERR, "Failed to get link status information");
4821 goto write_reg; /* Disable flow control */
4824 an_info = hw->phy.link_info.an_info;
4825 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4826 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4827 ret = I40E_ERR_NOT_READY;
4828 goto write_reg; /* Disable flow control */
4831 * If link auto negotiation is enabled, flow control needs to
4832 * be configured according to it
4834 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4835 case I40E_LINK_PAUSE_RXTX:
4838 hw->fc.current_mode = I40E_FC_FULL;
4840 case I40E_AQ_LINK_PAUSE_RX:
4842 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4844 case I40E_AQ_LINK_PAUSE_TX:
4846 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4849 hw->fc.current_mode = I40E_FC_NONE;
4854 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4855 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4856 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4857 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4858 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4859 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4866 i40e_pf_setup(struct i40e_pf *pf)
4868 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4869 struct i40e_filter_control_settings settings;
4870 struct i40e_vsi *vsi;
4873 /* Clear all stats counters */
4874 pf->offset_loaded = FALSE;
4875 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4876 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4878 ret = i40e_pf_get_switch_config(pf);
4879 if (ret != I40E_SUCCESS) {
4880 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4883 if (pf->flags & I40E_FLAG_FDIR) {
4884 /* make queue allocated first, let FDIR use queue pair 0*/
4885 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4886 if (ret != I40E_FDIR_QUEUE_ID) {
4887 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4889 pf->flags &= ~I40E_FLAG_FDIR;
4892 /* main VSI setup */
4893 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4895 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4896 return I40E_ERR_NOT_READY;
4900 /* Configure filter control */
4901 memset(&settings, 0, sizeof(settings));
4902 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4903 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4904 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4905 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4907 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4908 hw->func_caps.rss_table_size);
4909 return I40E_ERR_PARAM;
4911 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4912 "size: %u\n", hw->func_caps.rss_table_size);
4913 pf->hash_lut_size = hw->func_caps.rss_table_size;
4915 /* Enable ethtype and macvlan filters */
4916 settings.enable_ethtype = TRUE;
4917 settings.enable_macvlan = TRUE;
4918 ret = i40e_set_filter_control(hw, &settings);
4920 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4923 /* Update flow control according to the auto negotiation */
4924 i40e_update_flow_control(hw);
4926 return I40E_SUCCESS;
4930 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4936 * Set or clear TX Queue Disable flags,
4937 * which is required by hardware.
4939 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4940 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4942 /* Wait until the request is finished */
4943 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4944 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4945 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4946 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4947 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4953 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4954 return I40E_SUCCESS; /* already on, skip next steps */
4956 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4957 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4959 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4960 return I40E_SUCCESS; /* already off, skip next steps */
4961 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4963 /* Write the register */
4964 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4965 /* Check the result */
4966 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4967 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4968 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4970 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4971 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4974 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4975 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4979 /* Check if it is timeout */
4980 if (j >= I40E_CHK_Q_ENA_COUNT) {
4981 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4982 (on ? "enable" : "disable"), q_idx);
4983 return I40E_ERR_TIMEOUT;
4986 return I40E_SUCCESS;
4989 /* Swith on or off the tx queues */
4991 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4993 struct rte_eth_dev_data *dev_data = pf->dev_data;
4994 struct i40e_tx_queue *txq;
4995 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4999 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5000 txq = dev_data->tx_queues[i];
5001 /* Don't operate the queue if not configured or
5002 * if starting only per queue */
5003 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5006 ret = i40e_dev_tx_queue_start(dev, i);
5008 ret = i40e_dev_tx_queue_stop(dev, i);
5009 if ( ret != I40E_SUCCESS)
5013 return I40E_SUCCESS;
5017 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5022 /* Wait until the request is finished */
5023 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5024 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5025 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5026 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5027 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5032 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5033 return I40E_SUCCESS; /* Already on, skip next steps */
5034 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5036 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5037 return I40E_SUCCESS; /* Already off, skip next steps */
5038 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5041 /* Write the register */
5042 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5043 /* Check the result */
5044 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5045 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5046 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5048 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5049 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5052 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5053 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5058 /* Check if it is timeout */
5059 if (j >= I40E_CHK_Q_ENA_COUNT) {
5060 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5061 (on ? "enable" : "disable"), q_idx);
5062 return I40E_ERR_TIMEOUT;
5065 return I40E_SUCCESS;
5067 /* Switch on or off the rx queues */
5069 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5071 struct rte_eth_dev_data *dev_data = pf->dev_data;
5072 struct i40e_rx_queue *rxq;
5073 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5077 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5078 rxq = dev_data->rx_queues[i];
5079 /* Don't operate the queue if not configured or
5080 * if starting only per queue */
5081 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5084 ret = i40e_dev_rx_queue_start(dev, i);
5086 ret = i40e_dev_rx_queue_stop(dev, i);
5087 if (ret != I40E_SUCCESS)
5091 return I40E_SUCCESS;
5094 /* Switch on or off all the rx/tx queues */
5096 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5101 /* enable rx queues before enabling tx queues */
5102 ret = i40e_dev_switch_rx_queues(pf, on);
5104 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5107 ret = i40e_dev_switch_tx_queues(pf, on);
5109 /* Stop tx queues before stopping rx queues */
5110 ret = i40e_dev_switch_tx_queues(pf, on);
5112 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5115 ret = i40e_dev_switch_rx_queues(pf, on);
5121 /* Initialize VSI for TX */
5123 i40e_dev_tx_init(struct i40e_pf *pf)
5125 struct rte_eth_dev_data *data = pf->dev_data;
5127 uint32_t ret = I40E_SUCCESS;
5128 struct i40e_tx_queue *txq;
5130 for (i = 0; i < data->nb_tx_queues; i++) {
5131 txq = data->tx_queues[i];
5132 if (!txq || !txq->q_set)
5134 ret = i40e_tx_queue_init(txq);
5135 if (ret != I40E_SUCCESS)
5138 if (ret == I40E_SUCCESS)
5139 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5145 /* Initialize VSI for RX */
5147 i40e_dev_rx_init(struct i40e_pf *pf)
5149 struct rte_eth_dev_data *data = pf->dev_data;
5150 int ret = I40E_SUCCESS;
5152 struct i40e_rx_queue *rxq;
5154 i40e_pf_config_mq_rx(pf);
5155 for (i = 0; i < data->nb_rx_queues; i++) {
5156 rxq = data->rx_queues[i];
5157 if (!rxq || !rxq->q_set)
5160 ret = i40e_rx_queue_init(rxq);
5161 if (ret != I40E_SUCCESS) {
5162 PMD_DRV_LOG(ERR, "Failed to do RX queue "
5167 if (ret == I40E_SUCCESS)
5168 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5175 i40e_dev_rxtx_init(struct i40e_pf *pf)
5179 err = i40e_dev_tx_init(pf);
5181 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5184 err = i40e_dev_rx_init(pf);
5186 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5194 i40e_vmdq_setup(struct rte_eth_dev *dev)
5196 struct rte_eth_conf *conf = &dev->data->dev_conf;
5197 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5198 int i, err, conf_vsis, j, loop;
5199 struct i40e_vsi *vsi;
5200 struct i40e_vmdq_info *vmdq_info;
5201 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5202 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5205 * Disable interrupt to avoid message from VF. Furthermore, it will
5206 * avoid race condition in VSI creation/destroy.
5208 i40e_pf_disable_irq0(hw);
5210 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5211 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5215 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5216 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5217 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5218 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5219 pf->max_nb_vmdq_vsi);
5223 if (pf->vmdq != NULL) {
5224 PMD_INIT_LOG(INFO, "VMDQ already configured");
5228 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5229 sizeof(*vmdq_info) * conf_vsis, 0);
5231 if (pf->vmdq == NULL) {
5232 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5236 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5238 /* Create VMDQ VSI */
5239 for (i = 0; i < conf_vsis; i++) {
5240 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5241 vmdq_conf->enable_loop_back);
5243 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5247 vmdq_info = &pf->vmdq[i];
5249 vmdq_info->vsi = vsi;
5251 pf->nb_cfg_vmdq_vsi = conf_vsis;
5253 /* Configure Vlan */
5254 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5255 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5256 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5257 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5258 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5259 vmdq_conf->pool_map[i].vlan_id, j);
5261 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5262 vmdq_conf->pool_map[i].vlan_id);
5264 PMD_INIT_LOG(ERR, "Failed to add vlan");
5272 i40e_pf_enable_irq0(hw);
5277 for (i = 0; i < conf_vsis; i++)
5278 if (pf->vmdq[i].vsi == NULL)
5281 i40e_vsi_release(pf->vmdq[i].vsi);
5285 i40e_pf_enable_irq0(hw);
5290 i40e_stat_update_32(struct i40e_hw *hw,
5298 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5302 if (new_data >= *offset)
5303 *stat = (uint64_t)(new_data - *offset);
5305 *stat = (uint64_t)((new_data +
5306 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5310 i40e_stat_update_48(struct i40e_hw *hw,
5319 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5320 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5321 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5326 if (new_data >= *offset)
5327 *stat = new_data - *offset;
5329 *stat = (uint64_t)((new_data +
5330 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5332 *stat &= I40E_48_BIT_MASK;
5337 i40e_pf_disable_irq0(struct i40e_hw *hw)
5339 /* Disable all interrupt types */
5340 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5341 I40E_WRITE_FLUSH(hw);
5346 i40e_pf_enable_irq0(struct i40e_hw *hw)
5348 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5349 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5350 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5351 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5352 I40E_WRITE_FLUSH(hw);
5356 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5358 /* read pending request and disable first */
5359 i40e_pf_disable_irq0(hw);
5360 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5361 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5362 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5365 /* Link no queues with irq0 */
5366 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5367 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5371 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5373 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5374 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5377 uint32_t index, offset, val;
5382 * Try to find which VF trigger a reset, use absolute VF id to access
5383 * since the reg is global register.
5385 for (i = 0; i < pf->vf_num; i++) {
5386 abs_vf_id = hw->func_caps.vf_base_id + i;
5387 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5388 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5389 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5390 /* VFR event occured */
5391 if (val & (0x1 << offset)) {
5394 /* Clear the event first */
5395 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5397 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5399 * Only notify a VF reset event occured,
5400 * don't trigger another SW reset
5402 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5403 if (ret != I40E_SUCCESS)
5404 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5410 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5412 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5413 struct i40e_arq_event_info info;
5414 uint16_t pending, opcode;
5417 info.buf_len = I40E_AQ_BUF_SZ;
5418 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5419 if (!info.msg_buf) {
5420 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5426 ret = i40e_clean_arq_element(hw, &info, &pending);
5428 if (ret != I40E_SUCCESS) {
5429 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5430 "aq_err: %u", hw->aq.asq_last_status);
5433 opcode = rte_le_to_cpu_16(info.desc.opcode);
5436 case i40e_aqc_opc_send_msg_to_pf:
5437 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5438 i40e_pf_host_handle_vf_msg(dev,
5439 rte_le_to_cpu_16(info.desc.retval),
5440 rte_le_to_cpu_32(info.desc.cookie_high),
5441 rte_le_to_cpu_32(info.desc.cookie_low),
5446 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5451 rte_free(info.msg_buf);
5455 * Interrupt handler is registered as the alarm callback for handling LSC
5456 * interrupt in a definite of time, in order to wait the NIC into a stable
5457 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5458 * no need for link down interrupt.
5461 i40e_dev_interrupt_delayed_handler(void *param)
5463 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5464 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5467 /* read interrupt causes again */
5468 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5470 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5471 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5472 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5473 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5474 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5475 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5476 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5477 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5478 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5479 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5480 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5482 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5483 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5484 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5485 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5486 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5488 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5489 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5490 i40e_dev_handle_vfr_event(dev);
5492 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5493 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5494 i40e_dev_handle_aq_msg(dev);
5497 /* handle the link up interrupt in an alarm callback */
5498 i40e_dev_link_update(dev, 0);
5499 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5501 i40e_pf_enable_irq0(hw);
5502 rte_intr_enable(&(dev->pci_dev->intr_handle));
5506 * Interrupt handler triggered by NIC for handling
5507 * specific interrupt.
5510 * Pointer to interrupt handle.
5512 * The address of parameter (struct rte_eth_dev *) regsitered before.
5518 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5521 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5522 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5525 /* Disable interrupt */
5526 i40e_pf_disable_irq0(hw);
5528 /* read out interrupt causes */
5529 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5531 /* No interrupt event indicated */
5532 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5533 PMD_DRV_LOG(INFO, "No interrupt event");
5536 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5537 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5538 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5539 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5540 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5541 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5542 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5543 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5544 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5545 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5546 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5547 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5548 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5549 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5550 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5551 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5553 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5554 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5555 i40e_dev_handle_vfr_event(dev);
5557 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5558 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5559 i40e_dev_handle_aq_msg(dev);
5562 /* Link Status Change interrupt */
5563 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5564 #define I40E_US_PER_SECOND 1000000
5565 struct rte_eth_link link;
5567 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5568 memset(&link, 0, sizeof(link));
5569 rte_i40e_dev_atomic_read_link_status(dev, &link);
5570 i40e_dev_link_update(dev, 0);
5573 * For link up interrupt, it needs to wait 1 second to let the
5574 * hardware be a stable state. Otherwise several consecutive
5575 * interrupts can be observed.
5576 * For link down interrupt, no need to wait.
5578 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5579 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5582 _rte_eth_dev_callback_process(dev,
5583 RTE_ETH_EVENT_INTR_LSC);
5587 /* Enable interrupt */
5588 i40e_pf_enable_irq0(hw);
5589 rte_intr_enable(&(dev->pci_dev->intr_handle));
5593 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5594 struct i40e_macvlan_filter *filter,
5597 int ele_num, ele_buff_size;
5598 int num, actual_num, i;
5600 int ret = I40E_SUCCESS;
5601 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5602 struct i40e_aqc_add_macvlan_element_data *req_list;
5604 if (filter == NULL || total == 0)
5605 return I40E_ERR_PARAM;
5606 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5607 ele_buff_size = hw->aq.asq_buf_size;
5609 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5610 if (req_list == NULL) {
5611 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5612 return I40E_ERR_NO_MEMORY;
5617 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5618 memset(req_list, 0, ele_buff_size);
5620 for (i = 0; i < actual_num; i++) {
5621 (void)rte_memcpy(req_list[i].mac_addr,
5622 &filter[num + i].macaddr, ETH_ADDR_LEN);
5623 req_list[i].vlan_tag =
5624 rte_cpu_to_le_16(filter[num + i].vlan_id);
5626 switch (filter[num + i].filter_type) {
5627 case RTE_MAC_PERFECT_MATCH:
5628 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5629 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5631 case RTE_MACVLAN_PERFECT_MATCH:
5632 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5634 case RTE_MAC_HASH_MATCH:
5635 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5636 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5638 case RTE_MACVLAN_HASH_MATCH:
5639 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5642 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5643 ret = I40E_ERR_PARAM;
5647 req_list[i].queue_number = 0;
5649 req_list[i].flags = rte_cpu_to_le_16(flags);
5652 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5654 if (ret != I40E_SUCCESS) {
5655 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5659 } while (num < total);
5667 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5668 struct i40e_macvlan_filter *filter,
5671 int ele_num, ele_buff_size;
5672 int num, actual_num, i;
5674 int ret = I40E_SUCCESS;
5675 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5676 struct i40e_aqc_remove_macvlan_element_data *req_list;
5678 if (filter == NULL || total == 0)
5679 return I40E_ERR_PARAM;
5681 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5682 ele_buff_size = hw->aq.asq_buf_size;
5684 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5685 if (req_list == NULL) {
5686 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5687 return I40E_ERR_NO_MEMORY;
5692 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5693 memset(req_list, 0, ele_buff_size);
5695 for (i = 0; i < actual_num; i++) {
5696 (void)rte_memcpy(req_list[i].mac_addr,
5697 &filter[num + i].macaddr, ETH_ADDR_LEN);
5698 req_list[i].vlan_tag =
5699 rte_cpu_to_le_16(filter[num + i].vlan_id);
5701 switch (filter[num + i].filter_type) {
5702 case RTE_MAC_PERFECT_MATCH:
5703 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5704 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5706 case RTE_MACVLAN_PERFECT_MATCH:
5707 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5709 case RTE_MAC_HASH_MATCH:
5710 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5711 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5713 case RTE_MACVLAN_HASH_MATCH:
5714 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5717 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5718 ret = I40E_ERR_PARAM;
5721 req_list[i].flags = rte_cpu_to_le_16(flags);
5724 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5726 if (ret != I40E_SUCCESS) {
5727 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5731 } while (num < total);
5738 /* Find out specific MAC filter */
5739 static struct i40e_mac_filter *
5740 i40e_find_mac_filter(struct i40e_vsi *vsi,
5741 struct ether_addr *macaddr)
5743 struct i40e_mac_filter *f;
5745 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5746 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5754 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5757 uint32_t vid_idx, vid_bit;
5759 if (vlan_id > ETH_VLAN_ID_MAX)
5762 vid_idx = I40E_VFTA_IDX(vlan_id);
5763 vid_bit = I40E_VFTA_BIT(vlan_id);
5765 if (vsi->vfta[vid_idx] & vid_bit)
5772 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5773 uint16_t vlan_id, bool on)
5775 uint32_t vid_idx, vid_bit;
5777 if (vlan_id > ETH_VLAN_ID_MAX)
5780 vid_idx = I40E_VFTA_IDX(vlan_id);
5781 vid_bit = I40E_VFTA_BIT(vlan_id);
5784 vsi->vfta[vid_idx] |= vid_bit;
5786 vsi->vfta[vid_idx] &= ~vid_bit;
5790 * Find all vlan options for specific mac addr,
5791 * return with actual vlan found.
5794 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5795 struct i40e_macvlan_filter *mv_f,
5796 int num, struct ether_addr *addr)
5802 * Not to use i40e_find_vlan_filter to decrease the loop time,
5803 * although the code looks complex.
5805 if (num < vsi->vlan_num)
5806 return I40E_ERR_PARAM;
5809 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5811 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5812 if (vsi->vfta[j] & (1 << k)) {
5814 PMD_DRV_LOG(ERR, "vlan number "
5816 return I40E_ERR_PARAM;
5818 (void)rte_memcpy(&mv_f[i].macaddr,
5819 addr, ETH_ADDR_LEN);
5821 j * I40E_UINT32_BIT_SIZE + k;
5827 return I40E_SUCCESS;
5831 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5832 struct i40e_macvlan_filter *mv_f,
5837 struct i40e_mac_filter *f;
5839 if (num < vsi->mac_num)
5840 return I40E_ERR_PARAM;
5842 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5844 PMD_DRV_LOG(ERR, "buffer number not match");
5845 return I40E_ERR_PARAM;
5847 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5849 mv_f[i].vlan_id = vlan;
5850 mv_f[i].filter_type = f->mac_info.filter_type;
5854 return I40E_SUCCESS;
5858 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5861 struct i40e_mac_filter *f;
5862 struct i40e_macvlan_filter *mv_f;
5863 int ret = I40E_SUCCESS;
5865 if (vsi == NULL || vsi->mac_num == 0)
5866 return I40E_ERR_PARAM;
5868 /* Case that no vlan is set */
5869 if (vsi->vlan_num == 0)
5872 num = vsi->mac_num * vsi->vlan_num;
5874 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5876 PMD_DRV_LOG(ERR, "failed to allocate memory");
5877 return I40E_ERR_NO_MEMORY;
5881 if (vsi->vlan_num == 0) {
5882 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5883 (void)rte_memcpy(&mv_f[i].macaddr,
5884 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5885 mv_f[i].vlan_id = 0;
5889 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5890 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5891 vsi->vlan_num, &f->mac_info.mac_addr);
5892 if (ret != I40E_SUCCESS)
5898 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5906 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5908 struct i40e_macvlan_filter *mv_f;
5910 int ret = I40E_SUCCESS;
5912 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5913 return I40E_ERR_PARAM;
5915 /* If it's already set, just return */
5916 if (i40e_find_vlan_filter(vsi,vlan))
5917 return I40E_SUCCESS;
5919 mac_num = vsi->mac_num;
5922 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5923 return I40E_ERR_PARAM;
5926 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5929 PMD_DRV_LOG(ERR, "failed to allocate memory");
5930 return I40E_ERR_NO_MEMORY;
5933 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5935 if (ret != I40E_SUCCESS)
5938 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5940 if (ret != I40E_SUCCESS)
5943 i40e_set_vlan_filter(vsi, vlan, 1);
5953 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5955 struct i40e_macvlan_filter *mv_f;
5957 int ret = I40E_SUCCESS;
5960 * Vlan 0 is the generic filter for untagged packets
5961 * and can't be removed.
5963 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5964 return I40E_ERR_PARAM;
5966 /* If can't find it, just return */
5967 if (!i40e_find_vlan_filter(vsi, vlan))
5968 return I40E_ERR_PARAM;
5970 mac_num = vsi->mac_num;
5973 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5974 return I40E_ERR_PARAM;
5977 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5980 PMD_DRV_LOG(ERR, "failed to allocate memory");
5981 return I40E_ERR_NO_MEMORY;
5984 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5986 if (ret != I40E_SUCCESS)
5989 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5991 if (ret != I40E_SUCCESS)
5994 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5995 if (vsi->vlan_num == 1) {
5996 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5997 if (ret != I40E_SUCCESS)
6000 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6001 if (ret != I40E_SUCCESS)
6005 i40e_set_vlan_filter(vsi, vlan, 0);
6015 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6017 struct i40e_mac_filter *f;
6018 struct i40e_macvlan_filter *mv_f;
6019 int i, vlan_num = 0;
6020 int ret = I40E_SUCCESS;
6022 /* If it's add and we've config it, return */
6023 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6025 return I40E_SUCCESS;
6026 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6027 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6030 * If vlan_num is 0, that's the first time to add mac,
6031 * set mask for vlan_id 0.
6033 if (vsi->vlan_num == 0) {
6034 i40e_set_vlan_filter(vsi, 0, 1);
6037 vlan_num = vsi->vlan_num;
6038 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6039 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6042 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6044 PMD_DRV_LOG(ERR, "failed to allocate memory");
6045 return I40E_ERR_NO_MEMORY;
6048 for (i = 0; i < vlan_num; i++) {
6049 mv_f[i].filter_type = mac_filter->filter_type;
6050 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6054 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6055 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6056 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6057 &mac_filter->mac_addr);
6058 if (ret != I40E_SUCCESS)
6062 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6063 if (ret != I40E_SUCCESS)
6066 /* Add the mac addr into mac list */
6067 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6069 PMD_DRV_LOG(ERR, "failed to allocate memory");
6070 ret = I40E_ERR_NO_MEMORY;
6073 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6075 f->mac_info.filter_type = mac_filter->filter_type;
6076 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6087 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6089 struct i40e_mac_filter *f;
6090 struct i40e_macvlan_filter *mv_f;
6092 enum rte_mac_filter_type filter_type;
6093 int ret = I40E_SUCCESS;
6095 /* Can't find it, return an error */
6096 f = i40e_find_mac_filter(vsi, addr);
6098 return I40E_ERR_PARAM;
6100 vlan_num = vsi->vlan_num;
6101 filter_type = f->mac_info.filter_type;
6102 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6103 filter_type == RTE_MACVLAN_HASH_MATCH) {
6104 if (vlan_num == 0) {
6105 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6106 return I40E_ERR_PARAM;
6108 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6109 filter_type == RTE_MAC_HASH_MATCH)
6112 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6114 PMD_DRV_LOG(ERR, "failed to allocate memory");
6115 return I40E_ERR_NO_MEMORY;
6118 for (i = 0; i < vlan_num; i++) {
6119 mv_f[i].filter_type = filter_type;
6120 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6123 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6124 filter_type == RTE_MACVLAN_HASH_MATCH) {
6125 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6126 if (ret != I40E_SUCCESS)
6130 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6131 if (ret != I40E_SUCCESS)
6134 /* Remove the mac addr into mac list */
6135 TAILQ_REMOVE(&vsi->mac_list, f, next);
6145 /* Configure hash enable flags for RSS */
6147 i40e_config_hena(uint64_t flags)
6154 if (flags & ETH_RSS_FRAG_IPV4)
6155 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6156 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6157 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6158 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6159 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6160 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6161 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6162 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6163 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6164 if (flags & ETH_RSS_FRAG_IPV6)
6165 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6166 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6167 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6168 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6169 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6170 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6171 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6172 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6173 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6174 if (flags & ETH_RSS_L2_PAYLOAD)
6175 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6180 /* Parse the hash enable flags */
6182 i40e_parse_hena(uint64_t flags)
6184 uint64_t rss_hf = 0;
6188 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6189 rss_hf |= ETH_RSS_FRAG_IPV4;
6190 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6191 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6192 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6193 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6194 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6195 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6196 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6197 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6198 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6199 rss_hf |= ETH_RSS_FRAG_IPV6;
6200 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6201 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6202 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6203 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6204 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6205 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6206 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6207 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6208 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6209 rss_hf |= ETH_RSS_L2_PAYLOAD;
6216 i40e_pf_disable_rss(struct i40e_pf *pf)
6218 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6221 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6222 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6223 hena &= ~I40E_RSS_HENA_ALL;
6224 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6225 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6226 I40E_WRITE_FLUSH(hw);
6230 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6232 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6233 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6236 if (!key || key_len == 0) {
6237 PMD_DRV_LOG(DEBUG, "No key to be configured");
6239 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6241 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6245 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6246 struct i40e_aqc_get_set_rss_key_data *key_dw =
6247 (struct i40e_aqc_get_set_rss_key_data *)key;
6249 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6251 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6254 uint32_t *hash_key = (uint32_t *)key;
6257 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6258 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6259 I40E_WRITE_FLUSH(hw);
6266 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6268 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6269 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6272 if (!key || !key_len)
6275 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6276 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6277 (struct i40e_aqc_get_set_rss_key_data *)key);
6279 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6283 uint32_t *key_dw = (uint32_t *)key;
6286 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6287 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6289 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6295 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6297 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6302 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6303 rss_conf->rss_key_len);
6307 rss_hf = rss_conf->rss_hf;
6308 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6309 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6310 hena &= ~I40E_RSS_HENA_ALL;
6311 hena |= i40e_config_hena(rss_hf);
6312 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6313 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6314 I40E_WRITE_FLUSH(hw);
6320 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6321 struct rte_eth_rss_conf *rss_conf)
6323 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6324 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6325 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6328 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6329 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6330 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6331 if (rss_hf != 0) /* Enable RSS */
6333 return 0; /* Nothing to do */
6336 if (rss_hf == 0) /* Disable RSS */
6339 return i40e_hw_rss_hash_set(pf, rss_conf);
6343 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6344 struct rte_eth_rss_conf *rss_conf)
6346 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6347 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6350 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6351 &rss_conf->rss_key_len);
6353 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6354 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6355 rss_conf->rss_hf = i40e_parse_hena(hena);
6361 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6363 switch (filter_type) {
6364 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6365 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6367 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6368 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6370 case RTE_TUNNEL_FILTER_IMAC_TENID:
6371 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6373 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6374 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6376 case ETH_TUNNEL_FILTER_IMAC:
6377 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6379 case ETH_TUNNEL_FILTER_OIP:
6380 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6382 case ETH_TUNNEL_FILTER_IIP:
6383 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6386 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6394 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6395 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6400 uint8_t i, tun_type = 0;
6401 /* internal varialbe to convert ipv6 byte order */
6402 uint32_t convert_ipv6[4];
6404 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6405 struct i40e_vsi *vsi = pf->main_vsi;
6406 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6407 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6409 cld_filter = rte_zmalloc("tunnel_filter",
6410 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6413 if (NULL == cld_filter) {
6414 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6417 pfilter = cld_filter;
6419 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6420 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6422 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6423 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6424 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6425 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6426 rte_memcpy(&pfilter->ipaddr.v4.data,
6427 &rte_cpu_to_le_32(ipv4_addr),
6428 sizeof(pfilter->ipaddr.v4.data));
6430 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6431 for (i = 0; i < 4; i++) {
6433 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6435 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6436 sizeof(pfilter->ipaddr.v6.data));
6439 /* check tunneled type */
6440 switch (tunnel_filter->tunnel_type) {
6441 case RTE_TUNNEL_TYPE_VXLAN:
6442 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6444 case RTE_TUNNEL_TYPE_NVGRE:
6445 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6447 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6448 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6451 /* Other tunnel types is not supported. */
6452 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6453 rte_free(cld_filter);
6457 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6460 rte_free(cld_filter);
6464 pfilter->flags |= rte_cpu_to_le_16(
6465 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6466 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6467 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6468 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6471 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6473 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6476 rte_free(cld_filter);
6481 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6485 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6486 if (pf->vxlan_ports[i] == port)
6494 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6498 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6500 idx = i40e_get_vxlan_port_idx(pf, port);
6502 /* Check if port already exists */
6504 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6508 /* Now check if there is space to add the new port */
6509 idx = i40e_get_vxlan_port_idx(pf, 0);
6511 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6512 "not adding port %d", port);
6516 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6519 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6523 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6526 /* New port: add it and mark its index in the bitmap */
6527 pf->vxlan_ports[idx] = port;
6528 pf->vxlan_bitmap |= (1 << idx);
6530 if (!(pf->flags & I40E_FLAG_VXLAN))
6531 pf->flags |= I40E_FLAG_VXLAN;
6537 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6540 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6542 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6543 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6547 idx = i40e_get_vxlan_port_idx(pf, port);
6550 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6554 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6555 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6559 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6562 pf->vxlan_ports[idx] = 0;
6563 pf->vxlan_bitmap &= ~(1 << idx);
6565 if (!pf->vxlan_bitmap)
6566 pf->flags &= ~I40E_FLAG_VXLAN;
6571 /* Add UDP tunneling port */
6573 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6574 struct rte_eth_udp_tunnel *udp_tunnel)
6577 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6579 if (udp_tunnel == NULL)
6582 switch (udp_tunnel->prot_type) {
6583 case RTE_TUNNEL_TYPE_VXLAN:
6584 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6587 case RTE_TUNNEL_TYPE_GENEVE:
6588 case RTE_TUNNEL_TYPE_TEREDO:
6589 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6594 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6602 /* Remove UDP tunneling port */
6604 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6605 struct rte_eth_udp_tunnel *udp_tunnel)
6608 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6610 if (udp_tunnel == NULL)
6613 switch (udp_tunnel->prot_type) {
6614 case RTE_TUNNEL_TYPE_VXLAN:
6615 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6617 case RTE_TUNNEL_TYPE_GENEVE:
6618 case RTE_TUNNEL_TYPE_TEREDO:
6619 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6623 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6631 /* Calculate the maximum number of contiguous PF queues that are configured */
6633 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6635 struct rte_eth_dev_data *data = pf->dev_data;
6637 struct i40e_rx_queue *rxq;
6640 for (i = 0; i < pf->lan_nb_qps; i++) {
6641 rxq = data->rx_queues[i];
6642 if (rxq && rxq->q_set)
6653 i40e_pf_config_rss(struct i40e_pf *pf)
6655 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6656 struct rte_eth_rss_conf rss_conf;
6657 uint32_t i, lut = 0;
6661 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6662 * It's necessary to calulate the actual PF queues that are configured.
6664 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6665 num = i40e_pf_calc_configured_queues_num(pf);
6667 num = pf->dev_data->nb_rx_queues;
6669 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6670 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6674 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6678 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6681 lut = (lut << 8) | (j & ((0x1 <<
6682 hw->func_caps.rss_table_entry_width) - 1));
6684 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6687 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6688 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6689 i40e_pf_disable_rss(pf);
6692 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6693 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6694 /* Random default keys */
6695 static uint32_t rss_key_default[] = {0x6b793944,
6696 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6697 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6698 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6700 rss_conf.rss_key = (uint8_t *)rss_key_default;
6701 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6705 return i40e_hw_rss_hash_set(pf, &rss_conf);
6709 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6710 struct rte_eth_tunnel_filter_conf *filter)
6712 if (pf == NULL || filter == NULL) {
6713 PMD_DRV_LOG(ERR, "Invalid parameter");
6717 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6718 PMD_DRV_LOG(ERR, "Invalid queue ID");
6722 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6723 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6727 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6728 (is_zero_ether_addr(&filter->outer_mac))) {
6729 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6733 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6734 (is_zero_ether_addr(&filter->inner_mac))) {
6735 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6742 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6743 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6745 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6750 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6751 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6754 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6755 } else if (len == 4) {
6756 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6758 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6763 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6770 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6771 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6777 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6784 switch (cfg->cfg_type) {
6785 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6786 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6789 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6797 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6798 enum rte_filter_op filter_op,
6801 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6802 int ret = I40E_ERR_PARAM;
6804 switch (filter_op) {
6805 case RTE_ETH_FILTER_SET:
6806 ret = i40e_dev_global_config_set(hw,
6807 (struct rte_eth_global_cfg *)arg);
6810 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6818 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6819 enum rte_filter_op filter_op,
6822 struct rte_eth_tunnel_filter_conf *filter;
6823 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6824 int ret = I40E_SUCCESS;
6826 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6828 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6829 return I40E_ERR_PARAM;
6831 switch (filter_op) {
6832 case RTE_ETH_FILTER_NOP:
6833 if (!(pf->flags & I40E_FLAG_VXLAN))
6834 ret = I40E_NOT_SUPPORTED;
6836 case RTE_ETH_FILTER_ADD:
6837 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6839 case RTE_ETH_FILTER_DELETE:
6840 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6843 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6844 ret = I40E_ERR_PARAM;
6852 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6855 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6858 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6859 ret = i40e_pf_config_rss(pf);
6861 i40e_pf_disable_rss(pf);
6866 /* Get the symmetric hash enable configurations per port */
6868 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6870 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6872 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6875 /* Set the symmetric hash enable configurations per port */
6877 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6879 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6882 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6883 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6887 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6889 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6890 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6894 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6896 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6897 I40E_WRITE_FLUSH(hw);
6901 * Get global configurations of hash function type and symmetric hash enable
6902 * per flow type (pctype). Note that global configuration means it affects all
6903 * the ports on the same NIC.
6906 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6907 struct rte_eth_hash_global_conf *g_cfg)
6909 uint32_t reg, mask = I40E_FLOW_TYPES;
6911 enum i40e_filter_pctype pctype;
6913 memset(g_cfg, 0, sizeof(*g_cfg));
6914 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6915 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6916 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6918 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6919 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6920 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6922 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6923 if (!(mask & (1UL << i)))
6925 mask &= ~(1UL << i);
6926 /* Bit set indicats the coresponding flow type is supported */
6927 g_cfg->valid_bit_mask[0] |= (1UL << i);
6928 /* if flowtype is invalid, continue */
6929 if (!I40E_VALID_FLOW(i))
6931 pctype = i40e_flowtype_to_pctype(i);
6932 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6933 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6934 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6941 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6944 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6946 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6947 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6948 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6949 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6955 * As i40e supports less than 32 flow types, only first 32 bits need to
6958 mask0 = g_cfg->valid_bit_mask[0];
6959 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6961 /* Check if any unsupported flow type configured */
6962 if ((mask0 | i40e_mask) ^ i40e_mask)
6965 if (g_cfg->valid_bit_mask[i])
6973 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6979 * Set global configurations of hash function type and symmetric hash enable
6980 * per flow type (pctype). Note any modifying global configuration will affect
6981 * all the ports on the same NIC.
6984 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6985 struct rte_eth_hash_global_conf *g_cfg)
6990 uint32_t mask0 = g_cfg->valid_bit_mask[0];
6991 enum i40e_filter_pctype pctype;
6993 /* Check the input parameters */
6994 ret = i40e_hash_global_config_check(g_cfg);
6998 for (i = 0; mask0 && i < UINT32_BIT; i++) {
6999 if (!(mask0 & (1UL << i)))
7001 mask0 &= ~(1UL << i);
7002 /* if flowtype is invalid, continue */
7003 if (!I40E_VALID_FLOW(i))
7005 pctype = i40e_flowtype_to_pctype(i);
7006 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7007 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7008 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7011 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7012 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7014 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7015 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7019 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7020 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7022 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7023 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7027 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7029 /* Use the default, and keep it as it is */
7032 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7035 I40E_WRITE_FLUSH(hw);
7041 * Valid input sets for hash and flow director filters per PCTYPE
7044 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7045 enum rte_filter_type filter)
7049 static const uint64_t valid_hash_inset_table[] = {
7050 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7051 I40E_INSET_DMAC | I40E_INSET_SMAC |
7052 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7053 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7054 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7055 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7056 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7057 I40E_INSET_FLEX_PAYLOAD,
7058 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7059 I40E_INSET_DMAC | I40E_INSET_SMAC |
7060 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7061 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7062 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7063 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7064 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7065 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7066 I40E_INSET_FLEX_PAYLOAD,
7067 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7068 I40E_INSET_DMAC | I40E_INSET_SMAC |
7069 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7070 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7071 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7072 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7073 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7074 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7075 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7076 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7077 I40E_INSET_DMAC | I40E_INSET_SMAC |
7078 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7079 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7080 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7081 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7082 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7083 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7084 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7085 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7086 I40E_INSET_DMAC | I40E_INSET_SMAC |
7087 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7088 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7089 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7090 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7091 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7092 I40E_INSET_FLEX_PAYLOAD,
7093 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7094 I40E_INSET_DMAC | I40E_INSET_SMAC |
7095 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7096 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7097 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7098 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7099 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7100 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7101 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7102 I40E_INSET_DMAC | I40E_INSET_SMAC |
7103 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7104 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7105 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7106 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7107 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7108 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7109 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7110 I40E_INSET_DMAC | I40E_INSET_SMAC |
7111 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7112 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7113 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7114 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7115 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7116 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7117 I40E_INSET_FLEX_PAYLOAD,
7118 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7119 I40E_INSET_DMAC | I40E_INSET_SMAC |
7120 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7121 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7122 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7123 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7124 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7125 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7126 I40E_INSET_FLEX_PAYLOAD,
7127 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7128 I40E_INSET_DMAC | I40E_INSET_SMAC |
7129 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7130 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7131 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7132 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7133 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7134 I40E_INSET_FLEX_PAYLOAD,
7135 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7136 I40E_INSET_DMAC | I40E_INSET_SMAC |
7137 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7138 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7139 I40E_INSET_FLEX_PAYLOAD,
7143 * Flow director supports only fields defined in
7144 * union rte_eth_fdir_flow.
7146 static const uint64_t valid_fdir_inset_table[] = {
7147 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7148 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7149 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7150 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7151 I40E_INSET_IPV4_TTL,
7152 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7153 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7154 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7155 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7156 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7157 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7158 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7159 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7160 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7161 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7162 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7163 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7164 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7165 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7166 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7168 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7169 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7170 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7171 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7172 I40E_INSET_IPV4_TTL,
7173 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7174 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7175 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7176 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7177 I40E_INSET_IPV6_HOP_LIMIT,
7178 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7179 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7180 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7181 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7182 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7183 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7184 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7185 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7186 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7187 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7188 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7189 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7190 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7191 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7192 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7194 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7195 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7196 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7197 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7198 I40E_INSET_IPV6_HOP_LIMIT,
7199 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7200 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7201 I40E_INSET_LAST_ETHER_TYPE,
7204 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7206 if (filter == RTE_ETH_FILTER_HASH)
7207 valid = valid_hash_inset_table[pctype];
7209 valid = valid_fdir_inset_table[pctype];
7215 * Validate if the input set is allowed for a specific PCTYPE
7218 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7219 enum rte_filter_type filter, uint64_t inset)
7223 valid = i40e_get_valid_input_set(pctype, filter);
7224 if (inset & (~valid))
7230 /* default input set fields combination per pctype */
7232 i40e_get_default_input_set(uint16_t pctype)
7234 static const uint64_t default_inset_table[] = {
7235 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7236 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7237 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7238 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7239 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7240 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7241 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7242 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7243 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7244 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7245 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7247 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7248 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7249 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7250 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7251 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7252 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7253 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7254 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7255 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7256 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7257 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7258 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7259 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7261 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7262 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7263 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7264 I40E_INSET_LAST_ETHER_TYPE,
7267 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7270 return default_inset_table[pctype];
7274 * Parse the input set from index to logical bit masks
7277 i40e_parse_input_set(uint64_t *inset,
7278 enum i40e_filter_pctype pctype,
7279 enum rte_eth_input_set_field *field,
7285 static const struct {
7286 enum rte_eth_input_set_field field;
7288 } inset_convert_table[] = {
7289 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7290 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7291 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7292 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7293 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7294 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7295 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7296 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7297 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7298 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7299 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7300 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7301 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7302 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7303 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7304 I40E_INSET_IPV6_NEXT_HDR},
7305 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7306 I40E_INSET_IPV6_HOP_LIMIT},
7307 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7308 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7309 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7310 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7311 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7312 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7313 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7314 I40E_INSET_SCTP_VT},
7315 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7316 I40E_INSET_TUNNEL_DMAC},
7317 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7318 I40E_INSET_VLAN_TUNNEL},
7319 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7320 I40E_INSET_TUNNEL_ID},
7321 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7322 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7323 I40E_INSET_FLEX_PAYLOAD_W1},
7324 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7325 I40E_INSET_FLEX_PAYLOAD_W2},
7326 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7327 I40E_INSET_FLEX_PAYLOAD_W3},
7328 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7329 I40E_INSET_FLEX_PAYLOAD_W4},
7330 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7331 I40E_INSET_FLEX_PAYLOAD_W5},
7332 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7333 I40E_INSET_FLEX_PAYLOAD_W6},
7334 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7335 I40E_INSET_FLEX_PAYLOAD_W7},
7336 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7337 I40E_INSET_FLEX_PAYLOAD_W8},
7340 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7343 /* Only one item allowed for default or all */
7345 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7346 *inset = i40e_get_default_input_set(pctype);
7348 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7349 *inset = I40E_INSET_NONE;
7354 for (i = 0, *inset = 0; i < size; i++) {
7355 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7356 if (field[i] == inset_convert_table[j].field) {
7357 *inset |= inset_convert_table[j].inset;
7362 /* It contains unsupported input set, return immediately */
7363 if (j == RTE_DIM(inset_convert_table))
7371 * Translate the input set from bit masks to register aware bit masks
7375 i40e_translate_input_set_reg(uint64_t input)
7380 static const struct {
7384 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7385 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7386 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7387 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7388 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7389 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7390 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7391 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7392 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7393 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7394 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7395 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7396 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7397 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7398 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7399 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7400 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7401 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7402 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7403 {I40E_INSET_TUNNEL_DMAC,
7404 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7405 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7406 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7407 {I40E_INSET_TUNNEL_SRC_PORT,
7408 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7409 {I40E_INSET_TUNNEL_DST_PORT,
7410 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7411 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7412 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7413 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7414 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7415 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7416 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7417 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7418 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7419 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7425 /* Translate input set to register aware inset */
7426 for (i = 0; i < RTE_DIM(inset_map); i++) {
7427 if (input & inset_map[i].inset)
7428 val |= inset_map[i].inset_reg;
7435 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7438 uint64_t inset_need_mask = inset;
7440 static const struct {
7443 } inset_mask_map[] = {
7444 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7445 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7446 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7447 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7448 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7449 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7450 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7451 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7454 if (!inset || !mask || !nb_elem)
7457 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7458 /* Clear the inset bit, if no MASK is required,
7459 * for example proto + ttl
7461 if ((inset & inset_mask_map[i].inset) ==
7462 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7463 inset_need_mask &= ~inset_mask_map[i].inset;
7464 if (!inset_need_mask)
7467 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7468 if ((inset_need_mask & inset_mask_map[i].inset) ==
7469 inset_mask_map[i].inset) {
7470 if (idx >= nb_elem) {
7471 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7474 mask[idx] = inset_mask_map[i].mask;
7483 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7485 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7487 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7489 i40e_write_rx_ctl(hw, addr, val);
7490 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7491 (uint32_t)i40e_read_rx_ctl(hw, addr));
7495 i40e_filter_input_set_init(struct i40e_pf *pf)
7497 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7498 enum i40e_filter_pctype pctype;
7499 uint64_t input_set, inset_reg;
7500 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7503 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7504 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7505 if (!I40E_VALID_PCTYPE(pctype))
7507 input_set = i40e_get_default_input_set(pctype);
7509 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7510 I40E_INSET_MASK_NUM_REG);
7513 inset_reg = i40e_translate_input_set_reg(input_set);
7515 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7516 (uint32_t)(inset_reg & UINT32_MAX));
7517 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7518 (uint32_t)((inset_reg >>
7519 I40E_32_BIT_WIDTH) & UINT32_MAX));
7520 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7521 (uint32_t)(inset_reg & UINT32_MAX));
7522 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7523 (uint32_t)((inset_reg >>
7524 I40E_32_BIT_WIDTH) & UINT32_MAX));
7526 for (i = 0; i < num; i++) {
7527 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7529 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7532 /*clear unused mask registers of the pctype */
7533 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7534 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7536 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7539 I40E_WRITE_FLUSH(hw);
7541 /* store the default input set */
7542 pf->hash_input_set[pctype] = input_set;
7543 pf->fdir.input_set[pctype] = input_set;
7548 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7549 struct rte_eth_input_set_conf *conf)
7551 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7552 enum i40e_filter_pctype pctype;
7553 uint64_t input_set, inset_reg = 0;
7554 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7558 PMD_DRV_LOG(ERR, "Invalid pointer");
7561 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7562 conf->op != RTE_ETH_INPUT_SET_ADD) {
7563 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7567 if (!I40E_VALID_FLOW(conf->flow_type)) {
7568 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7571 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7572 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7575 PMD_DRV_LOG(ERR, "Failed to parse input set");
7578 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7580 PMD_DRV_LOG(ERR, "Invalid input set");
7583 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7584 /* get inset value in register */
7585 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7586 inset_reg <<= I40E_32_BIT_WIDTH;
7587 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7588 input_set |= pf->hash_input_set[pctype];
7590 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7591 I40E_INSET_MASK_NUM_REG);
7595 inset_reg |= i40e_translate_input_set_reg(input_set);
7597 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7598 (uint32_t)(inset_reg & UINT32_MAX));
7599 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7600 (uint32_t)((inset_reg >>
7601 I40E_32_BIT_WIDTH) & UINT32_MAX));
7603 for (i = 0; i < num; i++)
7604 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7606 /*clear unused mask registers of the pctype */
7607 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7608 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7610 I40E_WRITE_FLUSH(hw);
7612 pf->hash_input_set[pctype] = input_set;
7617 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7618 struct rte_eth_input_set_conf *conf)
7620 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7621 enum i40e_filter_pctype pctype;
7622 uint64_t input_set, inset_reg = 0;
7623 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7627 PMD_DRV_LOG(ERR, "Invalid pointer");
7630 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7631 conf->op != RTE_ETH_INPUT_SET_ADD) {
7632 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7636 if (!I40E_VALID_FLOW(conf->flow_type)) {
7637 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7640 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7641 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7644 PMD_DRV_LOG(ERR, "Failed to parse input set");
7647 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7649 PMD_DRV_LOG(ERR, "Invalid input set");
7653 /* get inset value in register */
7654 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7655 inset_reg <<= I40E_32_BIT_WIDTH;
7656 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7658 /* Can not change the inset reg for flex payload for fdir,
7659 * it is done by writing I40E_PRTQF_FD_FLXINSET
7660 * in i40e_set_flex_mask_on_pctype.
7662 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7663 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7665 input_set |= pf->fdir.input_set[pctype];
7666 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7667 I40E_INSET_MASK_NUM_REG);
7671 inset_reg |= i40e_translate_input_set_reg(input_set);
7673 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7674 (uint32_t)(inset_reg & UINT32_MAX));
7675 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7676 (uint32_t)((inset_reg >>
7677 I40E_32_BIT_WIDTH) & UINT32_MAX));
7679 for (i = 0; i < num; i++)
7680 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7682 /*clear unused mask registers of the pctype */
7683 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7684 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7686 I40E_WRITE_FLUSH(hw);
7688 pf->fdir.input_set[pctype] = input_set;
7693 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7698 PMD_DRV_LOG(ERR, "Invalid pointer");
7702 switch (info->info_type) {
7703 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7704 i40e_get_symmetric_hash_enable_per_port(hw,
7705 &(info->info.enable));
7707 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7708 ret = i40e_get_hash_filter_global_config(hw,
7709 &(info->info.global_conf));
7712 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7722 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7727 PMD_DRV_LOG(ERR, "Invalid pointer");
7731 switch (info->info_type) {
7732 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7733 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7735 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7736 ret = i40e_set_hash_filter_global_config(hw,
7737 &(info->info.global_conf));
7739 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7740 ret = i40e_hash_filter_inset_select(hw,
7741 &(info->info.input_set_conf));
7745 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7754 /* Operations for hash function */
7756 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7757 enum rte_filter_op filter_op,
7760 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7763 switch (filter_op) {
7764 case RTE_ETH_FILTER_NOP:
7766 case RTE_ETH_FILTER_GET:
7767 ret = i40e_hash_filter_get(hw,
7768 (struct rte_eth_hash_filter_info *)arg);
7770 case RTE_ETH_FILTER_SET:
7771 ret = i40e_hash_filter_set(hw,
7772 (struct rte_eth_hash_filter_info *)arg);
7775 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7785 * Configure ethertype filter, which can director packet by filtering
7786 * with mac address and ether_type or only ether_type
7789 i40e_ethertype_filter_set(struct i40e_pf *pf,
7790 struct rte_eth_ethertype_filter *filter,
7793 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7794 struct i40e_control_filter_stats stats;
7798 if (filter->queue >= pf->dev_data->nb_rx_queues) {
7799 PMD_DRV_LOG(ERR, "Invalid queue ID");
7802 if (filter->ether_type == ETHER_TYPE_IPv4 ||
7803 filter->ether_type == ETHER_TYPE_IPv6) {
7804 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7805 " control packet filter.", filter->ether_type);
7808 if (filter->ether_type == ETHER_TYPE_VLAN)
7809 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7812 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7813 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7814 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7815 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7816 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7818 memset(&stats, 0, sizeof(stats));
7819 ret = i40e_aq_add_rem_control_packet_filter(hw,
7820 filter->mac_addr.addr_bytes,
7821 filter->ether_type, flags,
7823 filter->queue, add, &stats, NULL);
7825 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7826 " mac_etype_used = %u, etype_used = %u,"
7827 " mac_etype_free = %u, etype_free = %u\n",
7828 ret, stats.mac_etype_used, stats.etype_used,
7829 stats.mac_etype_free, stats.etype_free);
7836 * Handle operations for ethertype filter.
7839 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7840 enum rte_filter_op filter_op,
7843 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7846 if (filter_op == RTE_ETH_FILTER_NOP)
7850 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7855 switch (filter_op) {
7856 case RTE_ETH_FILTER_ADD:
7857 ret = i40e_ethertype_filter_set(pf,
7858 (struct rte_eth_ethertype_filter *)arg,
7861 case RTE_ETH_FILTER_DELETE:
7862 ret = i40e_ethertype_filter_set(pf,
7863 (struct rte_eth_ethertype_filter *)arg,
7867 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7875 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7876 enum rte_filter_type filter_type,
7877 enum rte_filter_op filter_op,
7885 switch (filter_type) {
7886 case RTE_ETH_FILTER_NONE:
7887 /* For global configuration */
7888 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7890 case RTE_ETH_FILTER_HASH:
7891 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7893 case RTE_ETH_FILTER_MACVLAN:
7894 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7896 case RTE_ETH_FILTER_ETHERTYPE:
7897 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7899 case RTE_ETH_FILTER_TUNNEL:
7900 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7902 case RTE_ETH_FILTER_FDIR:
7903 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7906 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7916 * Check and enable Extended Tag.
7917 * Enabling Extended Tag is important for 40G performance.
7920 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7925 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7928 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7932 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7933 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7938 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7941 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7945 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7946 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7949 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7950 ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7953 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7960 * As some registers wouldn't be reset unless a global hardware reset,
7961 * hardware initialization is needed to put those registers into an
7962 * expected initial state.
7965 i40e_hw_init(struct rte_eth_dev *dev)
7967 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7969 i40e_enable_extended_tag(dev);
7971 /* clear the PF Queue Filter control register */
7972 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7974 /* Disable symmetric hash per port */
7975 i40e_set_symmetric_hash_enable_per_port(hw, 0);
7978 enum i40e_filter_pctype
7979 i40e_flowtype_to_pctype(uint16_t flow_type)
7981 static const enum i40e_filter_pctype pctype_table[] = {
7982 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7983 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7984 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7985 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7986 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7987 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7988 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7989 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7990 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7991 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7992 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7993 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7994 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7995 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7996 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7997 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7998 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7999 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8000 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8003 return pctype_table[flow_type];
8007 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8009 static const uint16_t flowtype_table[] = {
8010 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8011 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8012 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8013 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8014 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8015 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8016 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8017 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8018 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8019 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8020 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8021 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8022 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8023 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8024 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8025 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8026 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8027 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8028 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8031 return flowtype_table[pctype];
8035 * On X710, performance number is far from the expectation on recent firmware
8036 * versions; on XL710, performance number is also far from the expectation on
8037 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8038 * mode is enabled and port MAC address is equal to the packet destination MAC
8039 * address. The fix for this issue may not be integrated in the following
8040 * firmware version. So the workaround in software driver is needed. It needs
8041 * to modify the initial values of 3 internal only registers for both X710 and
8042 * XL710. Note that the values for X710 or XL710 could be different, and the
8043 * workaround can be removed when it is fixed in firmware in the future.
8046 /* For both X710 and XL710 */
8047 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8048 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
8050 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8051 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
8054 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
8056 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
8057 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
8060 i40e_configure_registers(struct i40e_hw *hw)
8066 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8067 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8068 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8074 for (i = 0; i < RTE_DIM(reg_table); i++) {
8075 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8076 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
8078 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8081 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8084 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8087 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8091 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8092 reg_table[i].addr, reg);
8093 if (reg == reg_table[i].val)
8096 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8097 reg_table[i].val, NULL);
8099 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8100 "address of 0x%"PRIx32, reg_table[i].val,
8104 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8105 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8109 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
8110 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
8111 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
8112 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8114 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8119 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8120 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8124 /* Configure for double VLAN RX stripping */
8125 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8126 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8127 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8128 ret = i40e_aq_debug_write_register(hw,
8129 I40E_VSI_TSR(vsi->vsi_id),
8132 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8134 return I40E_ERR_CONFIG;
8138 /* Configure for double VLAN TX insertion */
8139 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8140 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8141 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8142 ret = i40e_aq_debug_write_register(hw,
8143 I40E_VSI_L2TAGSTXVALID(
8144 vsi->vsi_id), reg, NULL);
8146 PMD_DRV_LOG(ERR, "Failed to update "
8147 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8148 return I40E_ERR_CONFIG;
8156 * i40e_aq_add_mirror_rule
8157 * @hw: pointer to the hardware structure
8158 * @seid: VEB seid to add mirror rule to
8159 * @dst_id: destination vsi seid
8160 * @entries: Buffer which contains the entities to be mirrored
8161 * @count: number of entities contained in the buffer
8162 * @rule_id:the rule_id of the rule to be added
8164 * Add a mirror rule for a given veb.
8167 static enum i40e_status_code
8168 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8169 uint16_t seid, uint16_t dst_id,
8170 uint16_t rule_type, uint16_t *entries,
8171 uint16_t count, uint16_t *rule_id)
8173 struct i40e_aq_desc desc;
8174 struct i40e_aqc_add_delete_mirror_rule cmd;
8175 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8176 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8179 enum i40e_status_code status;
8181 i40e_fill_default_direct_cmd_desc(&desc,
8182 i40e_aqc_opc_add_mirror_rule);
8183 memset(&cmd, 0, sizeof(cmd));
8185 buff_len = sizeof(uint16_t) * count;
8186 desc.datalen = rte_cpu_to_le_16(buff_len);
8188 desc.flags |= rte_cpu_to_le_16(
8189 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8190 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8191 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8192 cmd.num_entries = rte_cpu_to_le_16(count);
8193 cmd.seid = rte_cpu_to_le_16(seid);
8194 cmd.destination = rte_cpu_to_le_16(dst_id);
8196 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8197 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8198 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8200 " mirror_rules_used = %u, mirror_rules_free = %u,",
8201 hw->aq.asq_last_status, resp->rule_id,
8202 resp->mirror_rules_used, resp->mirror_rules_free);
8203 *rule_id = rte_le_to_cpu_16(resp->rule_id);
8209 * i40e_aq_del_mirror_rule
8210 * @hw: pointer to the hardware structure
8211 * @seid: VEB seid to add mirror rule to
8212 * @entries: Buffer which contains the entities to be mirrored
8213 * @count: number of entities contained in the buffer
8214 * @rule_id:the rule_id of the rule to be delete
8216 * Delete a mirror rule for a given veb.
8219 static enum i40e_status_code
8220 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8221 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8222 uint16_t count, uint16_t rule_id)
8224 struct i40e_aq_desc desc;
8225 struct i40e_aqc_add_delete_mirror_rule cmd;
8226 uint16_t buff_len = 0;
8227 enum i40e_status_code status;
8230 i40e_fill_default_direct_cmd_desc(&desc,
8231 i40e_aqc_opc_delete_mirror_rule);
8232 memset(&cmd, 0, sizeof(cmd));
8233 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8234 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8236 cmd.num_entries = count;
8237 buff_len = sizeof(uint16_t) * count;
8238 desc.datalen = rte_cpu_to_le_16(buff_len);
8239 buff = (void *)entries;
8241 /* rule id is filled in destination field for deleting mirror rule */
8242 cmd.destination = rte_cpu_to_le_16(rule_id);
8244 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8245 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8246 cmd.seid = rte_cpu_to_le_16(seid);
8248 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8249 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8255 * i40e_mirror_rule_set
8256 * @dev: pointer to the hardware structure
8257 * @mirror_conf: mirror rule info
8258 * @sw_id: mirror rule's sw_id
8259 * @on: enable/disable
8261 * set a mirror rule.
8265 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8266 struct rte_eth_mirror_conf *mirror_conf,
8267 uint8_t sw_id, uint8_t on)
8269 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8270 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8271 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8272 struct i40e_mirror_rule *parent = NULL;
8273 uint16_t seid, dst_seid, rule_id;
8277 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8279 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8280 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8281 " without veb or vfs.");
8284 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8285 PMD_DRV_LOG(ERR, "mirror table is full.");
8288 if (mirror_conf->dst_pool > pf->vf_num) {
8289 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8290 mirror_conf->dst_pool);
8294 seid = pf->main_vsi->veb->seid;
8296 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8297 if (sw_id <= it->index) {
8303 if (mirr_rule && sw_id == mirr_rule->index) {
8305 PMD_DRV_LOG(ERR, "mirror rule exists.");
8308 ret = i40e_aq_del_mirror_rule(hw, seid,
8309 mirr_rule->rule_type,
8311 mirr_rule->num_entries, mirr_rule->id);
8313 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8314 " ret = %d, aq_err = %d.",
8315 ret, hw->aq.asq_last_status);
8318 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8319 rte_free(mirr_rule);
8320 pf->nb_mirror_rule--;
8324 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8328 mirr_rule = rte_zmalloc("i40e_mirror_rule",
8329 sizeof(struct i40e_mirror_rule) , 0);
8331 PMD_DRV_LOG(ERR, "failed to allocate memory");
8332 return I40E_ERR_NO_MEMORY;
8334 switch (mirror_conf->rule_type) {
8335 case ETH_MIRROR_VLAN:
8336 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8337 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8338 mirr_rule->entries[j] =
8339 mirror_conf->vlan.vlan_id[i];
8344 PMD_DRV_LOG(ERR, "vlan is not specified.");
8345 rte_free(mirr_rule);
8348 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8350 case ETH_MIRROR_VIRTUAL_POOL_UP:
8351 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8352 /* check if the specified pool bit is out of range */
8353 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8354 PMD_DRV_LOG(ERR, "pool mask is out of range.");
8355 rte_free(mirr_rule);
8358 for (i = 0, j = 0; i < pf->vf_num; i++) {
8359 if (mirror_conf->pool_mask & (1ULL << i)) {
8360 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8364 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8365 /* add pf vsi to entries */
8366 mirr_rule->entries[j] = pf->main_vsi_seid;
8370 PMD_DRV_LOG(ERR, "pool is not specified.");
8371 rte_free(mirr_rule);
8374 /* egress and ingress in aq commands means from switch but not port */
8375 mirr_rule->rule_type =
8376 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8377 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8378 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8380 case ETH_MIRROR_UPLINK_PORT:
8381 /* egress and ingress in aq commands means from switch but not port*/
8382 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8384 case ETH_MIRROR_DOWNLINK_PORT:
8385 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8388 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8389 mirror_conf->rule_type);
8390 rte_free(mirr_rule);
8394 /* If the dst_pool is equal to vf_num, consider it as PF */
8395 if (mirror_conf->dst_pool == pf->vf_num)
8396 dst_seid = pf->main_vsi_seid;
8398 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8400 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8401 mirr_rule->rule_type, mirr_rule->entries,
8404 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8405 " ret = %d, aq_err = %d.",
8406 ret, hw->aq.asq_last_status);
8407 rte_free(mirr_rule);
8411 mirr_rule->index = sw_id;
8412 mirr_rule->num_entries = j;
8413 mirr_rule->id = rule_id;
8414 mirr_rule->dst_vsi_seid = dst_seid;
8417 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8419 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8421 pf->nb_mirror_rule++;
8426 * i40e_mirror_rule_reset
8427 * @dev: pointer to the device
8428 * @sw_id: mirror rule's sw_id
8430 * reset a mirror rule.
8434 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8436 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8437 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8438 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8442 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8444 seid = pf->main_vsi->veb->seid;
8446 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8447 if (sw_id == it->index) {
8453 ret = i40e_aq_del_mirror_rule(hw, seid,
8454 mirr_rule->rule_type,
8456 mirr_rule->num_entries, mirr_rule->id);
8458 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8459 " status = %d, aq_err = %d.",
8460 ret, hw->aq.asq_last_status);
8463 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8464 rte_free(mirr_rule);
8465 pf->nb_mirror_rule--;
8467 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8474 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8476 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8477 uint64_t systim_cycles;
8479 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8480 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8483 return systim_cycles;
8487 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8489 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8492 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8493 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8500 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8502 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8505 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8506 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8513 i40e_start_timecounters(struct rte_eth_dev *dev)
8515 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8516 struct i40e_adapter *adapter =
8517 (struct i40e_adapter *)dev->data->dev_private;
8518 struct rte_eth_link link;
8519 uint32_t tsync_inc_l;
8520 uint32_t tsync_inc_h;
8522 /* Get current link speed. */
8523 memset(&link, 0, sizeof(link));
8524 i40e_dev_link_update(dev, 1);
8525 rte_i40e_dev_atomic_read_link_status(dev, &link);
8527 switch (link.link_speed) {
8528 case ETH_SPEED_NUM_40G:
8529 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8530 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8532 case ETH_SPEED_NUM_10G:
8533 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8534 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8536 case ETH_SPEED_NUM_1G:
8537 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8538 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8545 /* Set the timesync increment value. */
8546 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8547 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8549 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8550 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8551 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8553 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8554 adapter->systime_tc.cc_shift = 0;
8555 adapter->systime_tc.nsec_mask = 0;
8557 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8558 adapter->rx_tstamp_tc.cc_shift = 0;
8559 adapter->rx_tstamp_tc.nsec_mask = 0;
8561 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8562 adapter->tx_tstamp_tc.cc_shift = 0;
8563 adapter->tx_tstamp_tc.nsec_mask = 0;
8567 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8569 struct i40e_adapter *adapter =
8570 (struct i40e_adapter *)dev->data->dev_private;
8572 adapter->systime_tc.nsec += delta;
8573 adapter->rx_tstamp_tc.nsec += delta;
8574 adapter->tx_tstamp_tc.nsec += delta;
8580 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8583 struct i40e_adapter *adapter =
8584 (struct i40e_adapter *)dev->data->dev_private;
8586 ns = rte_timespec_to_ns(ts);
8588 /* Set the timecounters to a new value. */
8589 adapter->systime_tc.nsec = ns;
8590 adapter->rx_tstamp_tc.nsec = ns;
8591 adapter->tx_tstamp_tc.nsec = ns;
8597 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8599 uint64_t ns, systime_cycles;
8600 struct i40e_adapter *adapter =
8601 (struct i40e_adapter *)dev->data->dev_private;
8603 systime_cycles = i40e_read_systime_cyclecounter(dev);
8604 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8605 *ts = rte_ns_to_timespec(ns);
8611 i40e_timesync_enable(struct rte_eth_dev *dev)
8613 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8614 uint32_t tsync_ctl_l;
8615 uint32_t tsync_ctl_h;
8617 /* Stop the timesync system time. */
8618 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8619 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8620 /* Reset the timesync system time value. */
8621 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8622 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8624 i40e_start_timecounters(dev);
8626 /* Clear timesync registers. */
8627 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8628 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8629 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8630 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8631 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8632 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8634 /* Enable timestamping of PTP packets. */
8635 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8636 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8638 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8639 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8640 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8642 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8643 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8649 i40e_timesync_disable(struct rte_eth_dev *dev)
8651 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8652 uint32_t tsync_ctl_l;
8653 uint32_t tsync_ctl_h;
8655 /* Disable timestamping of transmitted PTP packets. */
8656 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8657 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8659 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8660 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8662 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8663 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8665 /* Reset the timesync increment value. */
8666 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8667 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8673 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8674 struct timespec *timestamp, uint32_t flags)
8676 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8677 struct i40e_adapter *adapter =
8678 (struct i40e_adapter *)dev->data->dev_private;
8680 uint32_t sync_status;
8681 uint32_t index = flags & 0x03;
8682 uint64_t rx_tstamp_cycles;
8685 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8686 if ((sync_status & (1 << index)) == 0)
8689 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8690 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8691 *timestamp = rte_ns_to_timespec(ns);
8697 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8698 struct timespec *timestamp)
8700 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8701 struct i40e_adapter *adapter =
8702 (struct i40e_adapter *)dev->data->dev_private;
8704 uint32_t sync_status;
8705 uint64_t tx_tstamp_cycles;
8708 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8709 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8712 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8713 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8714 *timestamp = rte_ns_to_timespec(ns);
8720 * i40e_parse_dcb_configure - parse dcb configure from user
8721 * @dev: the device being configured
8722 * @dcb_cfg: pointer of the result of parse
8723 * @*tc_map: bit map of enabled traffic classes
8725 * Returns 0 on success, negative value on failure
8728 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8729 struct i40e_dcbx_config *dcb_cfg,
8732 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8733 uint8_t i, tc_bw, bw_lf;
8735 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8737 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8738 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8739 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8743 /* assume each tc has the same bw */
8744 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8745 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8746 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8747 /* to ensure the sum of tcbw is equal to 100 */
8748 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8749 for (i = 0; i < bw_lf; i++)
8750 dcb_cfg->etscfg.tcbwtable[i]++;
8752 /* assume each tc has the same Transmission Selection Algorithm */
8753 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8754 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8756 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8757 dcb_cfg->etscfg.prioritytable[i] =
8758 dcb_rx_conf->dcb_tc[i];
8760 /* FW needs one App to configure HW */
8761 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8762 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8763 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8764 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8766 if (dcb_rx_conf->nb_tcs == 0)
8767 *tc_map = 1; /* tc0 only */
8769 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8771 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8772 dcb_cfg->pfc.willing = 0;
8773 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8774 dcb_cfg->pfc.pfcenable = *tc_map;
8780 static enum i40e_status_code
8781 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8782 struct i40e_aqc_vsi_properties_data *info,
8783 uint8_t enabled_tcmap)
8785 enum i40e_status_code ret;
8786 int i, total_tc = 0;
8787 uint16_t qpnum_per_tc, bsf, qp_idx;
8788 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8789 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8790 uint16_t used_queues;
8792 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8793 if (ret != I40E_SUCCESS)
8796 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8797 if (enabled_tcmap & (1 << i))
8802 vsi->enabled_tc = enabled_tcmap;
8804 /* different VSI has different queues assigned */
8805 if (vsi->type == I40E_VSI_MAIN)
8806 used_queues = dev_data->nb_rx_queues -
8807 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8808 else if (vsi->type == I40E_VSI_VMDQ2)
8809 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8811 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8812 return I40E_ERR_NO_AVAILABLE_VSI;
8815 qpnum_per_tc = used_queues / total_tc;
8816 /* Number of queues per enabled TC */
8817 if (qpnum_per_tc == 0) {
8818 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8819 return I40E_ERR_INVALID_QP_ID;
8821 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8823 bsf = rte_bsf32(qpnum_per_tc);
8826 * Configure TC and queue mapping parameters, for enabled TC,
8827 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8828 * default queue will serve it.
8831 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8832 if (vsi->enabled_tc & (1 << i)) {
8833 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8834 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8835 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8836 qp_idx += qpnum_per_tc;
8838 info->tc_mapping[i] = 0;
8841 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8842 if (vsi->type == I40E_VSI_SRIOV) {
8843 info->mapping_flags |=
8844 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8845 for (i = 0; i < vsi->nb_qps; i++)
8846 info->queue_mapping[i] =
8847 rte_cpu_to_le_16(vsi->base_queue + i);
8849 info->mapping_flags |=
8850 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8851 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8853 info->valid_sections |=
8854 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8856 return I40E_SUCCESS;
8860 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8861 * @veb: VEB to be configured
8862 * @tc_map: enabled TC bitmap
8864 * Returns 0 on success, negative value on failure
8866 static enum i40e_status_code
8867 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8869 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8870 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8871 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8872 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8873 enum i40e_status_code ret = I40E_SUCCESS;
8877 /* Check if enabled_tc is same as existing or new TCs */
8878 if (veb->enabled_tc == tc_map)
8881 /* configure tc bandwidth */
8882 memset(&veb_bw, 0, sizeof(veb_bw));
8883 veb_bw.tc_valid_bits = tc_map;
8884 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8885 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8886 if (tc_map & BIT_ULL(i))
8887 veb_bw.tc_bw_share_credits[i] = 1;
8889 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8892 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8893 " per TC failed = %d",
8894 hw->aq.asq_last_status);
8898 memset(&ets_query, 0, sizeof(ets_query));
8899 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8901 if (ret != I40E_SUCCESS) {
8902 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8903 " configuration %u", hw->aq.asq_last_status);
8906 memset(&bw_query, 0, sizeof(bw_query));
8907 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8909 if (ret != I40E_SUCCESS) {
8910 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8911 " configuration %u", hw->aq.asq_last_status);
8915 /* store and print out BW info */
8916 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8917 veb->bw_info.bw_max = ets_query.tc_bw_max;
8918 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8919 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8920 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8921 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8923 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8924 veb->bw_info.bw_ets_share_credits[i] =
8925 bw_query.tc_bw_share_credits[i];
8926 veb->bw_info.bw_ets_credits[i] =
8927 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8928 /* 4 bits per TC, 4th bit is reserved */
8929 veb->bw_info.bw_ets_max[i] =
8930 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8931 RTE_LEN2MASK(3, uint8_t));
8932 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8933 veb->bw_info.bw_ets_share_credits[i]);
8934 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8935 veb->bw_info.bw_ets_credits[i]);
8936 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8937 veb->bw_info.bw_ets_max[i]);
8940 veb->enabled_tc = tc_map;
8947 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8948 * @vsi: VSI to be configured
8949 * @tc_map: enabled TC bitmap
8951 * Returns 0 on success, negative value on failure
8953 static enum i40e_status_code
8954 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8956 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8957 struct i40e_vsi_context ctxt;
8958 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8959 enum i40e_status_code ret = I40E_SUCCESS;
8962 /* Check if enabled_tc is same as existing or new TCs */
8963 if (vsi->enabled_tc == tc_map)
8966 /* configure tc bandwidth */
8967 memset(&bw_data, 0, sizeof(bw_data));
8968 bw_data.tc_valid_bits = tc_map;
8969 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8970 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8971 if (tc_map & BIT_ULL(i))
8972 bw_data.tc_bw_credits[i] = 1;
8974 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8976 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8977 " per TC failed = %d",
8978 hw->aq.asq_last_status);
8981 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8982 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8984 /* Update Queue Pairs Mapping for currently enabled UPs */
8985 ctxt.seid = vsi->seid;
8986 ctxt.pf_num = hw->pf_id;
8988 ctxt.uplink_seid = vsi->uplink_seid;
8989 ctxt.info = vsi->info;
8991 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8995 /* Update the VSI after updating the VSI queue-mapping information */
8996 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8998 PMD_INIT_LOG(ERR, "Failed to configure "
8999 "TC queue mapping = %d",
9000 hw->aq.asq_last_status);
9003 /* update the local VSI info with updated queue map */
9004 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9005 sizeof(vsi->info.tc_mapping));
9006 (void)rte_memcpy(&vsi->info.queue_mapping,
9007 &ctxt.info.queue_mapping,
9008 sizeof(vsi->info.queue_mapping));
9009 vsi->info.mapping_flags = ctxt.info.mapping_flags;
9010 vsi->info.valid_sections = 0;
9012 /* query and update current VSI BW information */
9013 ret = i40e_vsi_get_bw_config(vsi);
9016 "Failed updating vsi bw info, err %s aq_err %s",
9017 i40e_stat_str(hw, ret),
9018 i40e_aq_str(hw, hw->aq.asq_last_status));
9022 vsi->enabled_tc = tc_map;
9029 * i40e_dcb_hw_configure - program the dcb setting to hw
9030 * @pf: pf the configuration is taken on
9031 * @new_cfg: new configuration
9032 * @tc_map: enabled TC bitmap
9034 * Returns 0 on success, negative value on failure
9036 static enum i40e_status_code
9037 i40e_dcb_hw_configure(struct i40e_pf *pf,
9038 struct i40e_dcbx_config *new_cfg,
9041 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9042 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9043 struct i40e_vsi *main_vsi = pf->main_vsi;
9044 struct i40e_vsi_list *vsi_list;
9045 enum i40e_status_code ret;
9049 /* Use the FW API if FW > v4.4*/
9050 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9051 (hw->aq.fw_maj_ver >= 5))) {
9052 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9053 " to configure DCB");
9054 return I40E_ERR_FIRMWARE_API_VERSION;
9057 /* Check if need reconfiguration */
9058 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9059 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9060 return I40E_SUCCESS;
9063 /* Copy the new config to the current config */
9064 *old_cfg = *new_cfg;
9065 old_cfg->etsrec = old_cfg->etscfg;
9066 ret = i40e_set_dcb_config(hw);
9069 "Set DCB Config failed, err %s aq_err %s\n",
9070 i40e_stat_str(hw, ret),
9071 i40e_aq_str(hw, hw->aq.asq_last_status));
9074 /* set receive Arbiter to RR mode and ETS scheme by default */
9075 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9076 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9077 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
9078 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9079 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9080 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9081 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9082 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9083 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9084 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9085 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9086 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9087 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9089 /* get local mib to check whether it is configured correctly */
9091 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9092 /* Get Local DCB Config */
9093 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9094 &hw->local_dcbx_config);
9096 /* if Veb is created, need to update TC of it at first */
9097 if (main_vsi->veb) {
9098 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9100 PMD_INIT_LOG(WARNING,
9101 "Failed configuring TC for VEB seid=%d\n",
9102 main_vsi->veb->seid);
9104 /* Update each VSI */
9105 i40e_vsi_config_tc(main_vsi, tc_map);
9106 if (main_vsi->veb) {
9107 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9108 /* Beside main VSI and VMDQ VSIs, only enable default
9111 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9112 ret = i40e_vsi_config_tc(vsi_list->vsi,
9115 ret = i40e_vsi_config_tc(vsi_list->vsi,
9116 I40E_DEFAULT_TCMAP);
9118 PMD_INIT_LOG(WARNING,
9119 "Failed configuring TC for VSI seid=%d\n",
9120 vsi_list->vsi->seid);
9124 return I40E_SUCCESS;
9128 * i40e_dcb_init_configure - initial dcb config
9129 * @dev: device being configured
9130 * @sw_dcb: indicate whether dcb is sw configured or hw offload
9132 * Returns 0 on success, negative value on failure
9135 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9137 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9138 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9141 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9142 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9146 /* DCB initialization:
9147 * Update DCB configuration from the Firmware and configure
9148 * LLDP MIB change event.
9150 if (sw_dcb == TRUE) {
9151 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9152 if (ret != I40E_SUCCESS)
9153 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9155 ret = i40e_init_dcb(hw);
9156 /* if sw_dcb, lldp agent is stopped, the return from
9157 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9160 if (ret != I40E_SUCCESS &&
9161 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9162 memset(&hw->local_dcbx_config, 0,
9163 sizeof(struct i40e_dcbx_config));
9164 /* set dcb default configuration */
9165 hw->local_dcbx_config.etscfg.willing = 0;
9166 hw->local_dcbx_config.etscfg.maxtcs = 0;
9167 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9168 hw->local_dcbx_config.etscfg.tsatable[0] =
9170 hw->local_dcbx_config.etsrec =
9171 hw->local_dcbx_config.etscfg;
9172 hw->local_dcbx_config.pfc.willing = 0;
9173 hw->local_dcbx_config.pfc.pfccap =
9174 I40E_MAX_TRAFFIC_CLASS;
9175 /* FW needs one App to configure HW */
9176 hw->local_dcbx_config.numapps = 1;
9177 hw->local_dcbx_config.app[0].selector =
9178 I40E_APP_SEL_ETHTYPE;
9179 hw->local_dcbx_config.app[0].priority = 3;
9180 hw->local_dcbx_config.app[0].protocolid =
9181 I40E_APP_PROTOID_FCOE;
9182 ret = i40e_set_dcb_config(hw);
9184 PMD_INIT_LOG(ERR, "default dcb config fails."
9185 " err = %d, aq_err = %d.", ret,
9186 hw->aq.asq_last_status);
9190 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9191 " aq_err = %d.", ret,
9192 hw->aq.asq_last_status);
9196 ret = i40e_aq_start_lldp(hw, NULL);
9197 if (ret != I40E_SUCCESS)
9198 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9200 ret = i40e_init_dcb(hw);
9202 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9203 PMD_INIT_LOG(ERR, "HW doesn't support"
9208 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9209 " aq_err = %d.", ret,
9210 hw->aq.asq_last_status);
9218 * i40e_dcb_setup - setup dcb related config
9219 * @dev: device being configured
9221 * Returns 0 on success, negative value on failure
9224 i40e_dcb_setup(struct rte_eth_dev *dev)
9226 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9227 struct i40e_dcbx_config dcb_cfg;
9231 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9232 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9236 if (pf->vf_num != 0)
9237 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9239 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9241 PMD_INIT_LOG(ERR, "invalid dcb config");
9244 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9246 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9254 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9255 struct rte_eth_dcb_info *dcb_info)
9257 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9258 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9259 struct i40e_vsi *vsi = pf->main_vsi;
9260 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9261 uint16_t bsf, tc_mapping;
9264 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9265 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9267 dcb_info->nb_tcs = 1;
9268 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9269 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9270 for (i = 0; i < dcb_info->nb_tcs; i++)
9271 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9273 /* get queue mapping if vmdq is disabled */
9274 if (!pf->nb_cfg_vmdq_vsi) {
9275 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9276 if (!(vsi->enabled_tc & (1 << i)))
9278 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9279 dcb_info->tc_queue.tc_rxq[j][i].base =
9280 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9281 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9282 dcb_info->tc_queue.tc_txq[j][i].base =
9283 dcb_info->tc_queue.tc_rxq[j][i].base;
9284 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9285 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9286 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9287 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9288 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9293 /* get queue mapping if vmdq is enabled */
9295 vsi = pf->vmdq[j].vsi;
9296 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9297 if (!(vsi->enabled_tc & (1 << i)))
9299 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9300 dcb_info->tc_queue.tc_rxq[j][i].base =
9301 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9302 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9303 dcb_info->tc_queue.tc_txq[j][i].base =
9304 dcb_info->tc_queue.tc_rxq[j][i].base;
9305 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9306 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9307 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9308 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9309 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9312 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9317 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9319 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9320 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9322 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9325 msix_intr = intr_handle->intr_vec[queue_id];
9326 if (msix_intr == I40E_MISC_VEC_ID)
9327 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9328 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9329 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9330 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9332 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9335 I40E_PFINT_DYN_CTLN(msix_intr -
9337 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9338 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9339 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9341 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9343 I40E_WRITE_FLUSH(hw);
9344 rte_intr_enable(&dev->pci_dev->intr_handle);
9350 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9352 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9353 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9356 msix_intr = intr_handle->intr_vec[queue_id];
9357 if (msix_intr == I40E_MISC_VEC_ID)
9358 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9361 I40E_PFINT_DYN_CTLN(msix_intr -
9364 I40E_WRITE_FLUSH(hw);
9369 static int i40e_get_regs(struct rte_eth_dev *dev,
9370 struct rte_dev_reg_info *regs)
9372 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9373 uint32_t *ptr_data = regs->data;
9374 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9375 const struct i40e_reg_info *reg_info;
9377 if (ptr_data == NULL) {
9378 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9379 regs->width = sizeof(uint32_t);
9383 /* The first few registers have to be read using AQ operations */
9385 while (i40e_regs_adminq[reg_idx].name) {
9386 reg_info = &i40e_regs_adminq[reg_idx++];
9387 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9389 arr_idx2 <= reg_info->count2;
9391 reg_offset = arr_idx * reg_info->stride1 +
9392 arr_idx2 * reg_info->stride2;
9393 reg_offset += reg_info->base_addr;
9394 ptr_data[reg_offset >> 2] =
9395 i40e_read_rx_ctl(hw, reg_offset);
9399 /* The remaining registers can be read using primitives */
9401 while (i40e_regs_others[reg_idx].name) {
9402 reg_info = &i40e_regs_others[reg_idx++];
9403 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9405 arr_idx2 <= reg_info->count2;
9407 reg_offset = arr_idx * reg_info->stride1 +
9408 arr_idx2 * reg_info->stride2;
9409 reg_offset += reg_info->base_addr;
9410 ptr_data[reg_offset >> 2] =
9411 I40E_READ_REG(hw, reg_offset);
9418 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9420 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9422 /* Convert word count to byte count */
9423 return hw->nvm.sr_size << 1;
9426 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9427 struct rte_dev_eeprom_info *eeprom)
9429 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9430 uint16_t *data = eeprom->data;
9431 uint16_t offset, length, cnt_words;
9434 offset = eeprom->offset >> 1;
9435 length = eeprom->length >> 1;
9438 if (offset > hw->nvm.sr_size ||
9439 offset + length > hw->nvm.sr_size) {
9440 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9444 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9446 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9447 if (ret_code != I40E_SUCCESS || cnt_words != length) {
9448 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9455 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9456 struct ether_addr *mac_addr)
9458 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9460 if (!is_valid_assigned_ether_addr(mac_addr)) {
9461 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9465 /* Flags: 0x3 updates port address */
9466 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9470 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9472 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9473 struct rte_eth_dev_data *dev_data = pf->dev_data;
9474 uint32_t frame_size = mtu + ETHER_HDR_LEN
9475 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9478 /* check if mtu is within the allowed range */
9479 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9482 /* mtu setting is forbidden if port is start */
9483 if (dev_data->dev_started) {
9485 "port %d must be stopped before configuration\n",
9490 if (frame_size > ETHER_MAX_LEN)
9491 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9493 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9495 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;