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34 #ifndef _I40E_ETHDEV_H_
35 #define _I40E_ETHDEV_H_
37 #include <rte_eth_ctrl.h>
39 #include <rte_kvargs.h>
41 #define I40E_VLAN_TAG_SIZE 4
43 #define I40E_AQ_LEN 32
44 #define I40E_AQ_BUF_SZ 4096
45 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
46 #define I40E_MAX_Q_PER_TC 64
47 #define I40E_NUM_DESC_DEFAULT 512
48 #define I40E_NUM_DESC_ALIGN 32
49 #define I40E_BUF_SIZE_MIN 1024
50 #define I40E_FRAME_SIZE_MAX 9728
51 #define I40E_QUEUE_BASE_ADDR_UNIT 128
52 /* number of VSIs and queue default setting */
53 #define I40E_MAX_QP_NUM_PER_VF 16
54 #define I40E_DEFAULT_QP_NUM_FDIR 1
55 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
56 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
57 /* Maximun number of MAC addresses */
58 #define I40E_NUM_MACADDR_MAX 64
59 /* Maximum number of VFs */
60 #define I40E_MAX_VF 128
63 * vlan_id is a 12 bit number.
64 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
65 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
66 * The higher 7 bit val specifies VFTA array index.
68 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
69 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
71 /* Default TC traffic in case DCB is not enabled */
72 #define I40E_DEFAULT_TCMAP 0x1
73 #define I40E_FDIR_QUEUE_ID 0
75 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
76 #define I40E_VMDQ_POOL_BASE 1
78 #define I40E_DEFAULT_RX_FREE_THRESH 32
79 #define I40E_DEFAULT_RX_PTHRESH 8
80 #define I40E_DEFAULT_RX_HTHRESH 8
81 #define I40E_DEFAULT_RX_WTHRESH 0
83 #define I40E_DEFAULT_TX_FREE_THRESH 32
84 #define I40E_DEFAULT_TX_PTHRESH 32
85 #define I40E_DEFAULT_TX_HTHRESH 0
86 #define I40E_DEFAULT_TX_WTHRESH 0
87 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
89 /* Bit shift and mask */
90 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
91 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
92 #define I40E_8_BIT_WIDTH CHAR_BIT
93 #define I40E_8_BIT_MASK UINT8_MAX
94 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
95 #define I40E_16_BIT_MASK UINT16_MAX
96 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
97 #define I40E_32_BIT_MASK UINT32_MAX
98 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
99 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
101 /* Linux PF host with virtchnl version 1.1 */
102 #define PF_IS_V11(vf) \
103 (((vf)->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && \
104 ((vf)->version_minor == 1))
107 I40E_WRITE_GLB_REG(struct i40e_hw *hw, uint32_t reg, uint32_t value) {
108 I40E_WRITE_REG(hw, reg, value);
109 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
114 /* index flex payload per layer */
115 enum i40e_flxpld_layer_idx {
116 I40E_FLXPLD_L2_IDX = 0,
117 I40E_FLXPLD_L3_IDX = 1,
118 I40E_FLXPLD_L4_IDX = 2,
119 I40E_MAX_FLXPLD_LAYER = 3,
121 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
122 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
123 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
124 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
125 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
128 #define I40E_FLAG_RSS (1ULL << 0)
129 #define I40E_FLAG_DCB (1ULL << 1)
130 #define I40E_FLAG_VMDQ (1ULL << 2)
131 #define I40E_FLAG_SRIOV (1ULL << 3)
132 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
133 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
134 #define I40E_FLAG_FDIR (1ULL << 6)
135 #define I40E_FLAG_VXLAN (1ULL << 7)
136 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
137 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
141 I40E_FLAG_HEADER_SPLIT_DISABLED | \
142 I40E_FLAG_HEADER_SPLIT_ENABLED | \
145 I40E_FLAG_RSS_AQ_CAPABLE)
147 #define I40E_RSS_OFFLOAD_ALL ( \
148 ETH_RSS_FRAG_IPV4 | \
149 ETH_RSS_NONFRAG_IPV4_TCP | \
150 ETH_RSS_NONFRAG_IPV4_UDP | \
151 ETH_RSS_NONFRAG_IPV4_SCTP | \
152 ETH_RSS_NONFRAG_IPV4_OTHER | \
153 ETH_RSS_FRAG_IPV6 | \
154 ETH_RSS_NONFRAG_IPV6_TCP | \
155 ETH_RSS_NONFRAG_IPV6_UDP | \
156 ETH_RSS_NONFRAG_IPV6_SCTP | \
157 ETH_RSS_NONFRAG_IPV6_OTHER | \
160 /* All bits of RSS hash enable for X722*/
161 #define I40E_RSS_HENA_ALL_X722 ( \
162 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
163 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
164 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
165 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
166 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
167 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
170 /* All bits of RSS hash enable */
171 #define I40E_RSS_HENA_ALL ( \
172 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
173 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
174 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
175 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
176 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
177 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
178 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
179 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
180 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
181 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
182 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
183 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
184 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
185 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
187 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
188 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
190 /* Default queue interrupt throttling time in microseconds */
191 #define I40E_ITR_INDEX_DEFAULT 0
192 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
193 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
195 /* Special FW support this floating VEB feature */
196 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
197 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
202 * MAC filter structure
204 struct i40e_mac_filter_info {
205 enum rte_mac_filter_type filter_type;
206 struct ether_addr mac_addr;
209 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
211 /* MAC filter list structure */
212 struct i40e_mac_filter {
213 TAILQ_ENTRY(i40e_mac_filter) next;
214 struct i40e_mac_filter_info mac_info;
217 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
221 /* VSI list structure */
222 struct i40e_vsi_list {
223 TAILQ_ENTRY(i40e_vsi_list) list;
224 struct i40e_vsi *vsi;
227 struct i40e_rx_queue;
228 struct i40e_tx_queue;
230 /* Bandwidth limit information */
231 struct i40e_bw_info {
232 uint16_t bw_limit; /* BW Limit (0 = disabled) */
233 uint8_t bw_max; /* Max BW limit if enabled */
235 /* Relative credits within same TC with respect to other VSIs or Comps */
236 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
237 /* Bandwidth limit per TC */
238 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
239 /* Max bandwidth limit per TC */
240 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
243 /* Structure that defines a VEB */
245 struct i40e_vsi_list_head head;
246 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
247 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
248 uint16_t seid; /* The seid of VEB itself */
249 uint16_t uplink_seid; /* The uplink seid of this VEB */
251 struct i40e_eth_stats stats;
252 uint8_t enabled_tc; /* The traffic class enabled */
253 struct i40e_bw_info bw_info; /* VEB bandwidth information */
256 /* i40e MACVLAN filter structure */
257 struct i40e_macvlan_filter {
258 struct ether_addr macaddr;
259 enum rte_mac_filter_type filter_type;
264 * Structure that defines a VSI, associated with a adapter.
267 struct i40e_adapter *adapter; /* Backreference to associated adapter */
268 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
270 struct i40e_eth_stats eth_stats_offset;
271 struct i40e_eth_stats eth_stats;
273 * When drivers loaded, only a default main VSI exists. In case new VSI
274 * needs to add, HW needs to know the layout that VSIs are organized.
275 * Besides that, VSI isan element and can't switch packets, which needs
276 * to add new component VEB to perform switching. So, a new VSI needs
277 * to specify the the uplink VSI (Parent VSI) before created. The
278 * uplink VSI will check whether it had a VEB to switch packets. If no,
279 * it will try to create one. Then, uplink VSI will move the new VSI
280 * into its' sib_vsi_list to manage all the downlink VSI.
281 * sib_vsi_list: the VSI list that shared the same uplink VSI.
282 * parent_vsi : the uplink VSI. It's NULL for main VSI.
283 * veb : the VEB associates with the VSI.
285 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
286 struct i40e_vsi *parent_vsi;
287 struct i40e_veb *veb; /* Associated veb, could be null */
288 struct i40e_veb *floating_veb; /* Associated floating veb */
290 enum i40e_vsi_type type; /* VSI types */
291 uint16_t vlan_num; /* Total VLAN number */
292 uint16_t mac_num; /* Total mac number */
293 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
294 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
295 /* specific VSI-defined parameters, SRIOV stored the vf_id */
297 uint16_t seid; /* The seid of VSI itself */
298 uint16_t uplink_seid; /* The uplink seid of this VSI */
299 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
300 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
301 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
302 uint16_t base_queue; /* The first queue index of this VSI */
304 * The offset to visit VSI related register, assigned by HW when
308 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
309 uint16_t nb_msix; /* The max number of msix vector */
310 uint8_t enabled_tc; /* The traffic class enabled */
311 struct i40e_bw_info bw_info; /* VSI bandwidth information */
315 LIST_ENTRY(pool_entry) next;
320 LIST_HEAD(res_list, pool_entry);
322 struct i40e_res_pool_info {
323 uint32_t base; /* Resource start index */
324 uint32_t num_alloc; /* Allocated resource number */
325 uint32_t num_free; /* Total available resource number */
326 struct res_list alloc_list; /* Allocated resource list */
327 struct res_list free_list; /* Available resource list */
331 I40E_VF_INACTIVE = 0,
338 * Structure to store private data for PF host.
342 struct i40e_vsi *vsi;
343 enum I40E_VF_STATE state; /* The number of queue pairs availiable */
344 uint16_t vf_idx; /* VF index in pf->vfs */
345 uint16_t lan_nb_qps; /* Actual queues allocated */
346 uint16_t reset_cnt; /* Total vf reset times */
347 struct ether_addr mac_addr; /* Default MAC address */
351 * Structure to store private data for flow control.
353 struct i40e_fc_conf {
354 uint16_t pause_time; /* Flow control pause timer */
355 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
356 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
357 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
358 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
362 * Structure to store private data for VMDQ instance
364 struct i40e_vmdq_info {
366 struct i40e_vsi *vsi;
370 * Structure to store flex pit for flow diretor.
372 struct i40e_fdir_flex_pit {
373 uint8_t src_offset; /* offset in words from the beginning of payload */
374 uint8_t size; /* size in words */
375 uint8_t dst_offset; /* offset in words of flexible payload */
378 struct i40e_fdir_flex_mask {
379 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
383 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
386 #define I40E_FILTER_PCTYPE_MAX 64
388 * A structure used to define fields of a FDIR related info.
390 struct i40e_fdir_info {
391 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
392 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
393 struct i40e_tx_queue *txq;
394 struct i40e_rx_queue *rxq;
395 void *prg_pkt; /* memory for fdir program packet */
396 uint64_t dma_addr; /* physic address of packet memory*/
397 /* input set bits for each pctype */
398 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
400 * the rule how bytes stream is extracted as flexible payload
401 * for each payload layer, the setting can up to three elements
403 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
404 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
407 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
408 #define I40E_MAX_MIRROR_RULES 64
410 * Mirror rule structure
412 struct i40e_mirror_rule {
413 TAILQ_ENTRY(i40e_mirror_rule) rules;
415 uint16_t index; /* the sw index of mirror rule */
416 uint16_t id; /* the rule id assigned by firmware */
417 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
418 uint16_t num_entries;
419 /* the info stores depend on the rule type.
420 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
421 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
423 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
426 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
429 * Structure to store private data specific for PF instance.
432 struct i40e_adapter *adapter; /* The adapter this PF associate to */
433 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
434 uint16_t mac_seid; /* The seid of the MAC of this PF */
435 uint16_t main_vsi_seid; /* The seid of the main VSI */
436 uint16_t max_num_vsi;
437 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
438 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
440 struct i40e_hw_port_stats stats_offset;
441 struct i40e_hw_port_stats stats;
442 /* internal packet byte count, it should be excluded from the total */
443 uint64_t internal_rx_bytes;
444 uint64_t internal_tx_bytes;
445 uint64_t internal_rx_bytes_offset;
446 uint64_t internal_tx_bytes_offset;
449 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
450 struct ether_addr dev_addr; /* PF device mac address */
451 uint64_t flags; /* PF feature flags */
452 /* All kinds of queue pair setting for different VSIs */
453 struct i40e_pf_vf *vfs;
455 /* Each of below queue pairs should be power of 2 since it's the
456 precondition after TC configuration applied */
457 uint16_t lan_nb_qp_max;
458 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
459 uint16_t lan_qp_offset;
460 uint16_t vmdq_nb_qp_max;
461 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
462 uint16_t vmdq_qp_offset;
463 uint16_t vf_nb_qp_max;
464 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
465 uint16_t vf_qp_offset;
466 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
467 uint16_t fdir_qp_offset;
469 uint16_t hash_lut_size; /* The size of hash lookup table */
470 /* input set bits for each pctype */
471 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
472 /* store VXLAN UDP ports */
473 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
474 uint16_t vxlan_bitmap; /* Vxlan bit mask */
476 /* VMDQ related info */
477 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
478 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
479 struct i40e_vmdq_info *vmdq;
481 struct i40e_fdir_info fdir; /* flow director info */
482 struct i40e_fc_conf fc_conf; /* Flow control conf */
483 struct i40e_mirror_rule_list mirror_list;
484 uint16_t nb_mirror_rule; /* The number of mirror rules */
485 bool floating_veb; /* The flag to use the floating VEB */
486 /* The floating enable flag for the specific VF */
487 bool floating_veb_list[I40E_MAX_VF];
489 bool support_multi_driver; /* 1 - support multiple driver */
493 PFMSG_LINK_CHANGE = 0x1,
494 PFMSG_RESET_IMPENDING = 0x2,
495 PFMSG_DRIVER_CLOSE = 0x4,
498 struct i40e_vsi_vlan_pvid_info {
499 uint16_t on; /* Enable or disable pvid */
501 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
503 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
504 * while 'untagged' will reject untagged packets.
512 struct i40e_vf_rx_queues {
513 uint64_t rx_dma_addr;
514 uint32_t rx_ring_len;
518 struct i40e_vf_tx_queues {
519 uint64_t tx_dma_addr;
520 uint32_t tx_ring_len;
524 * Structure to store private data specific for VF instance.
527 struct i40e_adapter *adapter; /* The adapter this VF associate to */
528 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
529 uint16_t num_queue_pairs;
530 uint16_t max_pkt_len; /* Maximum packet length */
531 bool promisc_unicast_enabled;
532 bool promisc_multicast_enabled;
534 uint32_t version_major; /* Major version number */
535 uint32_t version_minor; /* Minor version number */
536 uint16_t promisc_flags; /* Promiscuous setting */
537 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
542 enum i40e_aq_link_speed link_speed;
544 volatile uint32_t pend_cmd; /* pending command not finished yet */
545 int32_t cmd_retval; /* return value of the cmd response from PF */
546 u16 pend_msg; /* flags indicates events from pf not handled yet */
547 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
550 struct i40e_virtchnl_vf_resource *vf_res; /* All VSIs */
551 struct i40e_virtchnl_vsi_resource *vsi_res; /* LAN VSI */
557 * Structure to store private data for each PF/VF instance.
559 struct i40e_adapter {
560 /* Common for both PF and VF */
562 struct rte_eth_dev *eth_dev;
564 /* Specific for PF or VF */
571 bool rx_bulk_alloc_allowed;
573 bool tx_simple_allowed;
577 struct rte_timecounter systime_tc;
578 struct rte_timecounter rx_tstamp_tc;
579 struct rte_timecounter tx_tstamp_tc;
582 enum I40E_WARNING_IDX {
583 I40E_WARNING_DIS_FLX_PLD,
584 I40E_WARNING_ENA_FLX_PLD,
585 I40E_WARNING_QINQ_PARSER,
586 I40E_WARNING_QINQ_CLOUD_FILTER,
588 I40E_WARNING_FLOW_CTL,
589 I40E_WARNING_GRE_KEY_LEN,
591 I40E_WARNING_HASH_INSET,
593 I40E_WARNING_HASH_MSK,
595 I40E_WARNING_RPL_CLD_FILTER,
598 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
599 int i40e_vsi_release(struct i40e_vsi *vsi);
600 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
601 enum i40e_vsi_type type,
602 struct i40e_vsi *uplink_vsi,
603 uint16_t user_param);
604 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
605 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
606 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
607 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
608 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
609 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
610 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
611 void i40e_pf_disable_irq0(struct i40e_hw *hw);
612 void i40e_pf_enable_irq0(struct i40e_hw *hw);
613 int i40e_dev_link_update(struct rte_eth_dev *dev,
614 __rte_unused int wait_to_complete);
615 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi);
616 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
617 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
618 struct i40e_vsi_vlan_pvid_info *info);
619 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
620 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
621 uint64_t i40e_config_hena(uint64_t flags, enum i40e_mac_type type);
622 uint64_t i40e_parse_hena(uint64_t flags);
623 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
624 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
625 int i40e_fdir_setup(struct i40e_pf *pf);
626 const struct rte_memzone *i40e_memzone_reserve(const char *name,
629 int i40e_fdir_configure(struct rte_eth_dev *dev);
630 void i40e_fdir_teardown(struct i40e_pf *pf);
631 enum i40e_filter_pctype i40e_flowtype_to_pctype(uint16_t flow_type);
632 uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype);
633 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
634 enum rte_filter_op filter_op,
636 int i40e_select_filter_input_set(struct i40e_hw *hw,
637 struct rte_eth_input_set_conf *conf,
638 enum rte_filter_type filter);
639 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
640 struct rte_eth_input_set_conf *conf);
641 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
642 struct rte_eth_input_set_conf *conf);
643 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
644 uint32_t retval, uint8_t *msg,
646 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
647 struct rte_eth_rxq_info *qinfo);
648 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
649 struct rte_eth_txq_info *qinfo);
651 /* I40E_DEV_PRIVATE_TO */
652 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
653 (&((struct i40e_adapter *)adapter)->pf)
654 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
655 (&((struct i40e_adapter *)adapter)->hw)
656 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
657 ((struct i40e_adapter *)adapter)
659 /* I40EVF_DEV_PRIVATE_TO */
660 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
661 (&((struct i40e_adapter *)adapter)->vf)
663 static inline struct i40e_vsi *
664 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
671 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
672 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
673 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
676 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
680 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
681 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
684 #define I40E_VSI_TO_HW(vsi) \
685 (&(((struct i40e_vsi *)vsi)->adapter->hw))
686 #define I40E_VSI_TO_PF(vsi) \
687 (&(((struct i40e_vsi *)vsi)->adapter->pf))
688 #define I40E_VSI_TO_VF(vsi) \
689 (&(((struct i40e_vsi *)vsi)->adapter->vf))
690 #define I40E_VSI_TO_DEV_DATA(vsi) \
691 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
692 #define I40E_VSI_TO_ETH_DEV(vsi) \
693 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
696 #define I40E_PF_TO_HW(pf) \
697 (&(((struct i40e_pf *)pf)->adapter->hw))
698 #define I40E_PF_TO_ADAPTER(pf) \
699 ((struct i40e_adapter *)pf->adapter)
702 #define I40E_VF_TO_HW(vf) \
703 (&(((struct i40e_vf *)vf)->adapter->hw))
706 i40e_init_adminq_parameter(struct i40e_hw *hw)
708 hw->aq.num_arq_entries = I40E_AQ_LEN;
709 hw->aq.num_asq_entries = I40E_AQ_LEN;
710 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
711 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
715 i40e_align_floor(int n)
719 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
722 static inline uint16_t
723 i40e_calc_itr_interval(int16_t interval, bool is_multi_drv)
725 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX) {
727 interval = I40E_QUEUE_ITR_INTERVAL_MAX;
729 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
732 /* Convert to hardware count, as writing each 1 represents 2 us */
737 i40e_global_cfg_warning(enum I40E_WARNING_IDX idx)
740 static const char *const warning_list[] = {
741 [I40E_WARNING_DIS_FLX_PLD] = "disable FDIR flexible payload",
742 [I40E_WARNING_ENA_FLX_PLD] = "enable FDIR flexible payload",
743 [I40E_WARNING_QINQ_PARSER] = "support QinQ parser",
744 [I40E_WARNING_QINQ_CLOUD_FILTER] = "support QinQ cloud filter",
745 [I40E_WARNING_TPID] = "support TPID configuration",
746 [I40E_WARNING_FLOW_CTL] = "configure water marker",
747 [I40E_WARNING_GRE_KEY_LEN] = "support GRE key length setting",
748 [I40E_WARNING_QF_CTL] = "support hash function setting",
749 [I40E_WARNING_HASH_INSET] = "configure hash input set",
750 [I40E_WARNING_HSYM] = "set symmetric hash",
751 [I40E_WARNING_HASH_MSK] = "configure hash mask",
752 [I40E_WARNING_FD_MSK] = "configure fdir mask",
753 [I40E_WARNING_RPL_CLD_FILTER] = "replace cloud filter",
756 warning = warning_list[idx];
758 RTE_LOG(WARNING, PMD,
759 "Global register is changed during %s\n",
763 #define I40E_VALID_FLOW(flow_type) \
764 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
765 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
766 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
767 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
768 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
769 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
770 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
771 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
772 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
773 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
774 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
776 #define I40E_VALID_PCTYPE_X722(pctype) \
777 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
778 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
779 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
780 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
781 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
782 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
783 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
784 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
785 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
786 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
787 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
788 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
789 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
790 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
791 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
792 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
793 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
795 #define I40E_VALID_PCTYPE(pctype) \
796 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
797 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
798 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
799 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
800 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
801 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
802 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
803 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
804 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
805 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
806 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
808 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
809 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
810 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
811 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
812 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
813 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
814 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
816 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
817 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
818 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
819 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
820 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
822 #endif /* _I40E_ETHDEV_H_ */