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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
55 #include <rte_alarm.h>
56 #include <rte_ether.h>
57 #include <rte_ethdev.h>
58 #include <rte_atomic.h>
59 #include <rte_malloc.h>
62 #include "i40e_logs.h"
63 #include "base/i40e_prototype.h"
64 #include "base/i40e_adminq_cmd.h"
65 #include "base/i40e_type.h"
67 #include "i40e_rxtx.h"
68 #include "i40e_ethdev.h"
70 #define I40EVF_VSI_DEFAULT_MSIX_INTR 1
72 /* busy wait delay in msec */
73 #define I40EVF_BUSY_WAIT_DELAY 10
74 #define I40EVF_BUSY_WAIT_COUNT 50
75 #define MAX_RESET_WAIT_CNT 20
77 struct i40evf_arq_msg_info {
78 enum i40e_virtchnl_ops ops;
79 enum i40e_status_code result;
86 enum i40e_virtchnl_ops ops;
88 uint32_t in_args_size;
90 /* Input & output type. pass in buffer size and pass out
91 * actual return result
96 enum i40evf_aq_result {
97 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
98 I40EVF_MSG_NON, /* Read nothing from admin queue */
99 I40EVF_MSG_SYS, /* Read system msg from admin queue */
100 I40EVF_MSG_CMD, /* Read async command result */
103 static int i40evf_dev_configure(struct rte_eth_dev *dev);
104 static int i40evf_dev_start(struct rte_eth_dev *dev);
105 static void i40evf_dev_stop(struct rte_eth_dev *dev);
106 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
107 struct rte_eth_dev_info *dev_info);
108 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
109 __rte_unused int wait_to_complete);
110 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
111 struct rte_eth_stats *stats);
112 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
113 struct rte_eth_xstat *xstats, unsigned n);
114 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
115 struct rte_eth_xstat_name *xstats_names,
117 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
118 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
119 uint16_t vlan_id, int on);
120 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
121 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
123 static void i40evf_dev_close(struct rte_eth_dev *dev);
124 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
125 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
126 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
127 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
128 static int i40evf_init_vlan(struct rte_eth_dev *dev);
129 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
130 uint16_t rx_queue_id);
131 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
132 uint16_t rx_queue_id);
133 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
134 uint16_t tx_queue_id);
135 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
136 uint16_t tx_queue_id);
137 static void i40evf_add_mac_addr(struct rte_eth_dev *dev,
138 struct ether_addr *addr,
141 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
142 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
143 struct rte_eth_rss_reta_entry64 *reta_conf,
145 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
146 struct rte_eth_rss_reta_entry64 *reta_conf,
148 static int i40evf_config_rss(struct i40e_vf *vf);
149 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
150 struct rte_eth_rss_conf *rss_conf);
151 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
152 struct rte_eth_rss_conf *rss_conf);
154 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
156 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
157 static void i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
161 /* Default hash key buffer for RSS */
162 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
164 struct rte_i40evf_xstats_name_off {
165 char name[RTE_ETH_XSTATS_NAME_SIZE];
169 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
170 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
171 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
172 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
173 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
174 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
175 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
176 rx_unknown_protocol)},
177 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
178 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
179 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
180 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
181 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
182 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
185 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
186 sizeof(rte_i40evf_stats_strings[0]))
188 static const struct eth_dev_ops i40evf_eth_dev_ops = {
189 .dev_configure = i40evf_dev_configure,
190 .dev_start = i40evf_dev_start,
191 .dev_stop = i40evf_dev_stop,
192 .promiscuous_enable = i40evf_dev_promiscuous_enable,
193 .promiscuous_disable = i40evf_dev_promiscuous_disable,
194 .allmulticast_enable = i40evf_dev_allmulticast_enable,
195 .allmulticast_disable = i40evf_dev_allmulticast_disable,
196 .link_update = i40evf_dev_link_update,
197 .stats_get = i40evf_dev_stats_get,
198 .xstats_get = i40evf_dev_xstats_get,
199 .xstats_get_names = i40evf_dev_xstats_get_names,
200 .xstats_reset = i40evf_dev_xstats_reset,
201 .dev_close = i40evf_dev_close,
202 .dev_infos_get = i40evf_dev_info_get,
203 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
204 .vlan_filter_set = i40evf_vlan_filter_set,
205 .vlan_offload_set = i40evf_vlan_offload_set,
206 .vlan_pvid_set = i40evf_vlan_pvid_set,
207 .rx_queue_start = i40evf_dev_rx_queue_start,
208 .rx_queue_stop = i40evf_dev_rx_queue_stop,
209 .tx_queue_start = i40evf_dev_tx_queue_start,
210 .tx_queue_stop = i40evf_dev_tx_queue_stop,
211 .rx_queue_setup = i40e_dev_rx_queue_setup,
212 .rx_queue_release = i40e_dev_rx_queue_release,
213 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
214 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
215 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
216 .tx_queue_setup = i40e_dev_tx_queue_setup,
217 .tx_queue_release = i40e_dev_tx_queue_release,
218 .rx_queue_count = i40e_dev_rx_queue_count,
219 .rxq_info_get = i40e_rxq_info_get,
220 .txq_info_get = i40e_txq_info_get,
221 .mac_addr_add = i40evf_add_mac_addr,
222 .mac_addr_remove = i40evf_del_mac_addr,
223 .reta_update = i40evf_dev_rss_reta_update,
224 .reta_query = i40evf_dev_rss_reta_query,
225 .rss_hash_update = i40evf_dev_rss_hash_update,
226 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
230 * Read data in admin queue to get msg from pf driver
232 static enum i40evf_aq_result
233 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
235 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
236 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
237 struct i40e_arq_event_info event;
238 enum i40e_virtchnl_ops opcode;
239 enum i40e_status_code retval;
241 enum i40evf_aq_result result = I40EVF_MSG_NON;
243 event.buf_len = data->buf_len;
244 event.msg_buf = data->msg;
245 ret = i40e_clean_arq_element(hw, &event, NULL);
246 /* Can't read any msg from adminQ */
248 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
249 result = I40EVF_MSG_ERR;
253 opcode = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
254 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
256 if (opcode == I40E_VIRTCHNL_OP_EVENT) {
257 struct i40e_virtchnl_pf_event *vpe =
258 (struct i40e_virtchnl_pf_event *)event.msg_buf;
260 result = I40EVF_MSG_SYS;
261 switch (vpe->event) {
262 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
264 vpe->event_data.link_event.link_status;
266 vpe->event_data.link_event.link_speed;
267 vf->pend_msg |= PFMSG_LINK_CHANGE;
268 PMD_DRV_LOG(INFO, "Link status update:%s",
269 vf->link_up ? "up" : "down");
271 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
273 vf->pend_msg |= PFMSG_RESET_IMPENDING;
274 PMD_DRV_LOG(INFO, "vf is reseting");
276 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
277 vf->dev_closed = true;
278 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
279 PMD_DRV_LOG(INFO, "PF driver closed");
282 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
283 __func__, vpe->event);
286 /* async reply msg on command issued by vf previously */
287 result = I40EVF_MSG_CMD;
288 /* Actual data length read from PF */
289 data->msg_len = event.msg_len;
292 data->result = retval;
299 * clear current command. Only call in case execute
300 * _atomic_set_cmd successfully.
303 _clear_cmd(struct i40e_vf *vf)
306 vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
310 * Check there is pending cmd in execution. If none, set new command.
313 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
315 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
316 I40E_VIRTCHNL_OP_UNKNOWN, ops);
319 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
324 #define MAX_TRY_TIMES 200
325 #define ASQ_DELAY_MS 10
328 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
330 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
331 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
332 struct i40evf_arq_msg_info info;
333 enum i40evf_aq_result ret;
336 if (_atomic_set_cmd(vf, args->ops))
339 info.msg = args->out_buffer;
340 info.buf_len = args->out_size;
341 info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
342 info.result = I40E_SUCCESS;
344 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
345 args->in_args, args->in_args_size, NULL);
347 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
353 case I40E_VIRTCHNL_OP_RESET_VF:
354 /*no need to process in this function */
357 case I40E_VIRTCHNL_OP_VERSION:
358 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
359 /* for init adminq commands, need to poll the response */
362 ret = i40evf_read_pfmsg(dev, &info);
363 vf->cmd_retval = info.result;
364 if (ret == I40EVF_MSG_CMD) {
367 } else if (ret == I40EVF_MSG_ERR)
369 rte_delay_ms(ASQ_DELAY_MS);
370 /* If don't read msg or read sys event, continue */
371 } while (i++ < MAX_TRY_TIMES);
376 /* for other adminq in running time, waiting the cmd done flag */
379 if (vf->pend_cmd == I40E_VIRTCHNL_OP_UNKNOWN) {
383 rte_delay_ms(ASQ_DELAY_MS);
384 /* If don't read msg or read sys event, continue */
385 } while (i++ < MAX_TRY_TIMES);
389 return err | vf->cmd_retval;
393 * Check API version with sync wait until version read or fail from admin queue
396 i40evf_check_api_version(struct rte_eth_dev *dev)
398 struct i40e_virtchnl_version_info version, *pver;
400 struct vf_cmd_info args;
401 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
403 version.major = I40E_VIRTCHNL_VERSION_MAJOR;
404 version.minor = I40E_VIRTCHNL_VERSION_MINOR;
406 args.ops = I40E_VIRTCHNL_OP_VERSION;
407 args.in_args = (uint8_t *)&version;
408 args.in_args_size = sizeof(version);
409 args.out_buffer = vf->aq_resp;
410 args.out_size = I40E_AQ_BUF_SZ;
412 err = i40evf_execute_vf_cmd(dev, &args);
414 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
418 pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
419 vf->version_major = pver->major;
420 vf->version_minor = pver->minor;
421 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
422 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
423 else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
424 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR))
425 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
427 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
428 vf->version_major, vf->version_minor,
429 I40E_VIRTCHNL_VERSION_MAJOR,
430 I40E_VIRTCHNL_VERSION_MINOR);
438 i40evf_get_vf_resource(struct rte_eth_dev *dev)
440 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
441 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
443 struct vf_cmd_info args;
446 args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
447 args.out_buffer = vf->aq_resp;
448 args.out_size = I40E_AQ_BUF_SZ;
450 caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
451 I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
452 I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
453 I40E_VIRTCHNL_VF_OFFLOAD_VLAN |
454 I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
455 args.in_args = (uint8_t *)∩︀
456 args.in_args_size = sizeof(caps);
459 args.in_args_size = 0;
461 err = i40evf_execute_vf_cmd(dev, &args);
464 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
468 len = sizeof(struct i40e_virtchnl_vf_resource) +
469 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
471 (void)rte_memcpy(vf->vf_res, args.out_buffer,
472 RTE_MIN(args.out_size, len));
473 i40e_vf_parse_hw_config(hw, vf->vf_res);
479 i40evf_config_promisc(struct rte_eth_dev *dev,
481 bool enable_multicast)
483 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
485 struct vf_cmd_info args;
486 struct i40e_virtchnl_promisc_info promisc;
489 promisc.vsi_id = vf->vsi_res->vsi_id;
492 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
494 if (enable_multicast)
495 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
497 args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
498 args.in_args = (uint8_t *)&promisc;
499 args.in_args_size = sizeof(promisc);
500 args.out_buffer = vf->aq_resp;
501 args.out_size = I40E_AQ_BUF_SZ;
503 err = i40evf_execute_vf_cmd(dev, &args);
506 PMD_DRV_LOG(ERR, "fail to execute command "
507 "CONFIG_PROMISCUOUS_MODE");
511 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
513 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
514 bool enable_vlan_strip)
516 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
518 struct vf_cmd_info args;
519 struct i40e_virtchnl_vlan_offload_info offload;
521 offload.vsi_id = vf->vsi_res->vsi_id;
522 offload.enable_vlan_strip = enable_vlan_strip;
524 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
525 args.in_args = (uint8_t *)&offload;
526 args.in_args_size = sizeof(offload);
527 args.out_buffer = vf->aq_resp;
528 args.out_size = I40E_AQ_BUF_SZ;
530 err = i40evf_execute_vf_cmd(dev, &args);
532 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
538 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
539 struct i40e_vsi_vlan_pvid_info *info)
541 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
543 struct vf_cmd_info args;
544 struct i40e_virtchnl_pvid_info tpid_info;
547 PMD_DRV_LOG(ERR, "invalid parameters");
548 return I40E_ERR_PARAM;
551 memset(&tpid_info, 0, sizeof(tpid_info));
552 tpid_info.vsi_id = vf->vsi_res->vsi_id;
553 (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
555 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
556 args.in_args = (uint8_t *)&tpid_info;
557 args.in_args_size = sizeof(tpid_info);
558 args.out_buffer = vf->aq_resp;
559 args.out_size = I40E_AQ_BUF_SZ;
561 err = i40evf_execute_vf_cmd(dev, &args);
563 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
569 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
573 struct i40e_tx_queue *txq)
575 txq_info->vsi_id = vsi_id;
576 txq_info->queue_id = queue_id;
577 if (queue_id < nb_txq) {
578 txq_info->ring_len = txq->nb_tx_desc;
579 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
584 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
588 uint32_t max_pkt_size,
589 struct i40e_rx_queue *rxq)
591 rxq_info->vsi_id = vsi_id;
592 rxq_info->queue_id = queue_id;
593 rxq_info->max_pkt_size = max_pkt_size;
594 if (queue_id < nb_rxq) {
595 rxq_info->ring_len = rxq->nb_rx_desc;
596 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
597 rxq_info->databuffer_size =
598 (rte_pktmbuf_data_room_size(rxq->mp) -
599 RTE_PKTMBUF_HEADROOM);
603 /* It configures VSI queues to co-work with Linux PF host */
605 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
607 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
608 struct i40e_rx_queue **rxq =
609 (struct i40e_rx_queue **)dev->data->rx_queues;
610 struct i40e_tx_queue **txq =
611 (struct i40e_tx_queue **)dev->data->tx_queues;
612 struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
613 struct i40e_virtchnl_queue_pair_info *vc_qpi;
614 struct vf_cmd_info args;
615 uint16_t i, nb_qp = vf->num_queue_pairs;
616 const uint32_t size =
617 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
621 memset(buff, 0, sizeof(buff));
622 vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
623 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
624 vc_vqci->num_queue_pairs = nb_qp;
626 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
627 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
628 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
629 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
630 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
631 vf->max_pkt_len, rxq[i]);
633 memset(&args, 0, sizeof(args));
634 args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
635 args.in_args = (uint8_t *)vc_vqci;
636 args.in_args_size = size;
637 args.out_buffer = vf->aq_resp;
638 args.out_size = I40E_AQ_BUF_SZ;
639 ret = i40evf_execute_vf_cmd(dev, &args);
641 PMD_DRV_LOG(ERR, "Failed to execute command of "
642 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\n");
647 /* It configures VSI queues to co-work with DPDK PF host */
649 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
651 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
652 struct i40e_rx_queue **rxq =
653 (struct i40e_rx_queue **)dev->data->rx_queues;
654 struct i40e_tx_queue **txq =
655 (struct i40e_tx_queue **)dev->data->tx_queues;
656 struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
657 struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
658 struct vf_cmd_info args;
659 uint16_t i, nb_qp = vf->num_queue_pairs;
660 const uint32_t size =
661 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
665 memset(buff, 0, sizeof(buff));
666 vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
667 vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
668 vc_vqcei->num_queue_pairs = nb_qp;
669 vc_qpei = vc_vqcei->qpair;
670 for (i = 0; i < nb_qp; i++, vc_qpei++) {
671 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
672 vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
673 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
674 vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
675 vf->max_pkt_len, rxq[i]);
676 if (i < dev->data->nb_rx_queues)
678 * It adds extra info for configuring VSI queues, which
679 * is needed to enable the configurable crc stripping
682 vc_qpei->rxq_ext.crcstrip =
683 dev->data->dev_conf.rxmode.hw_strip_crc;
685 memset(&args, 0, sizeof(args));
687 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
688 args.in_args = (uint8_t *)vc_vqcei;
689 args.in_args_size = size;
690 args.out_buffer = vf->aq_resp;
691 args.out_size = I40E_AQ_BUF_SZ;
692 ret = i40evf_execute_vf_cmd(dev, &args);
694 PMD_DRV_LOG(ERR, "Failed to execute command of "
695 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT\n");
701 i40evf_configure_queues(struct rte_eth_dev *dev)
703 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
705 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
706 /* To support DPDK PF host */
707 return i40evf_configure_vsi_queues_ext(dev);
709 /* To support Linux PF host */
710 return i40evf_configure_vsi_queues(dev);
714 i40evf_config_irq_map(struct rte_eth_dev *dev)
716 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
717 struct vf_cmd_info args;
718 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
719 sizeof(struct i40e_virtchnl_vector_map)];
720 struct i40e_virtchnl_irq_map_info *map_info;
721 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
725 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
726 rte_intr_allow_others(intr_handle)) {
727 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
728 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
730 vector_id = I40E_RX_VEC_START;
732 vector_id = I40E_MISC_VEC_ID;
735 map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
736 map_info->num_vectors = 1;
737 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
738 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
739 /* Alway use default dynamic MSIX interrupt */
740 map_info->vecmap[0].vector_id = vector_id;
741 /* Don't map any tx queue */
742 map_info->vecmap[0].txq_map = 0;
743 map_info->vecmap[0].rxq_map = 0;
744 for (i = 0; i < dev->data->nb_rx_queues; i++) {
745 map_info->vecmap[0].rxq_map |= 1 << i;
746 if (rte_intr_dp_is_en(intr_handle))
747 intr_handle->intr_vec[i] = vector_id;
750 args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
751 args.in_args = (u8 *)cmd_buffer;
752 args.in_args_size = sizeof(cmd_buffer);
753 args.out_buffer = vf->aq_resp;
754 args.out_size = I40E_AQ_BUF_SZ;
755 err = i40evf_execute_vf_cmd(dev, &args);
757 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
763 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
766 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
767 struct i40e_virtchnl_queue_select queue_select;
769 struct vf_cmd_info args;
770 memset(&queue_select, 0, sizeof(queue_select));
771 queue_select.vsi_id = vf->vsi_res->vsi_id;
774 queue_select.rx_queues |= 1 << qid;
776 queue_select.tx_queues |= 1 << qid;
779 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
781 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
782 args.in_args = (u8 *)&queue_select;
783 args.in_args_size = sizeof(queue_select);
784 args.out_buffer = vf->aq_resp;
785 args.out_size = I40E_AQ_BUF_SZ;
786 err = i40evf_execute_vf_cmd(dev, &args);
788 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
789 isrx ? "RX" : "TX", qid, on ? "on" : "off");
795 i40evf_start_queues(struct rte_eth_dev *dev)
797 struct rte_eth_dev_data *dev_data = dev->data;
799 struct i40e_rx_queue *rxq;
800 struct i40e_tx_queue *txq;
802 for (i = 0; i < dev->data->nb_rx_queues; i++) {
803 rxq = dev_data->rx_queues[i];
804 if (rxq->rx_deferred_start)
806 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
807 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
812 for (i = 0; i < dev->data->nb_tx_queues; i++) {
813 txq = dev_data->tx_queues[i];
814 if (txq->tx_deferred_start)
816 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
817 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
826 i40evf_stop_queues(struct rte_eth_dev *dev)
830 /* Stop TX queues first */
831 for (i = 0; i < dev->data->nb_tx_queues; i++) {
832 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
833 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
838 /* Then stop RX queues */
839 for (i = 0; i < dev->data->nb_rx_queues; i++) {
840 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
841 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
850 i40evf_add_mac_addr(struct rte_eth_dev *dev,
851 struct ether_addr *addr,
852 __rte_unused uint32_t index,
853 __rte_unused uint32_t pool)
855 struct i40e_virtchnl_ether_addr_list *list;
856 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
857 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
858 sizeof(struct i40e_virtchnl_ether_addr)];
860 struct vf_cmd_info args;
862 if (is_zero_ether_addr(addr)) {
863 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
864 addr->addr_bytes[0], addr->addr_bytes[1],
865 addr->addr_bytes[2], addr->addr_bytes[3],
866 addr->addr_bytes[4], addr->addr_bytes[5]);
870 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
871 list->vsi_id = vf->vsi_res->vsi_id;
872 list->num_elements = 1;
873 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
874 sizeof(addr->addr_bytes));
876 args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
877 args.in_args = cmd_buffer;
878 args.in_args_size = sizeof(cmd_buffer);
879 args.out_buffer = vf->aq_resp;
880 args.out_size = I40E_AQ_BUF_SZ;
881 err = i40evf_execute_vf_cmd(dev, &args);
883 PMD_DRV_LOG(ERR, "fail to execute command "
884 "OP_ADD_ETHER_ADDRESS");
890 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
892 struct i40e_virtchnl_ether_addr_list *list;
893 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
894 struct rte_eth_dev_data *data = dev->data;
895 struct ether_addr *addr;
896 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
897 sizeof(struct i40e_virtchnl_ether_addr)];
899 struct vf_cmd_info args;
901 addr = &(data->mac_addrs[index]);
903 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
904 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
905 addr->addr_bytes[0], addr->addr_bytes[1],
906 addr->addr_bytes[2], addr->addr_bytes[3],
907 addr->addr_bytes[4], addr->addr_bytes[5]);
911 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
912 list->vsi_id = vf->vsi_res->vsi_id;
913 list->num_elements = 1;
914 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
915 sizeof(addr->addr_bytes));
917 args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
918 args.in_args = cmd_buffer;
919 args.in_args_size = sizeof(cmd_buffer);
920 args.out_buffer = vf->aq_resp;
921 args.out_size = I40E_AQ_BUF_SZ;
922 err = i40evf_execute_vf_cmd(dev, &args);
924 PMD_DRV_LOG(ERR, "fail to execute command "
925 "OP_DEL_ETHER_ADDRESS");
930 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
932 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
933 struct i40e_virtchnl_queue_select q_stats;
935 struct vf_cmd_info args;
937 memset(&q_stats, 0, sizeof(q_stats));
938 q_stats.vsi_id = vf->vsi_res->vsi_id;
939 args.ops = I40E_VIRTCHNL_OP_GET_STATS;
940 args.in_args = (u8 *)&q_stats;
941 args.in_args_size = sizeof(q_stats);
942 args.out_buffer = vf->aq_resp;
943 args.out_size = I40E_AQ_BUF_SZ;
945 err = i40evf_execute_vf_cmd(dev, &args);
947 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
951 *pstats = (struct i40e_eth_stats *)args.out_buffer;
956 i40evf_stat_update_48(uint64_t *offset,
959 if (*stat >= *offset)
960 *stat = *stat - *offset;
962 *stat = (uint64_t)((*stat +
963 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
965 *stat &= I40E_48_BIT_MASK;
969 i40evf_stat_update_32(uint64_t *offset,
972 if (*stat >= *offset)
973 *stat = (uint64_t)(*stat - *offset);
975 *stat = (uint64_t)((*stat +
976 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
980 i40evf_update_vsi_stats(struct i40e_vsi *vsi,
981 struct i40e_eth_stats *nes)
983 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
985 i40evf_stat_update_48(&oes->rx_bytes,
987 i40evf_stat_update_48(&oes->rx_unicast,
989 i40evf_stat_update_48(&oes->rx_multicast,
991 i40evf_stat_update_48(&oes->rx_broadcast,
993 i40evf_stat_update_32(&oes->rx_discards,
995 i40evf_stat_update_32(&oes->rx_unknown_protocol,
996 &nes->rx_unknown_protocol);
997 i40evf_stat_update_48(&oes->tx_bytes,
999 i40evf_stat_update_48(&oes->tx_unicast,
1001 i40evf_stat_update_48(&oes->tx_multicast,
1002 &nes->tx_multicast);
1003 i40evf_stat_update_48(&oes->tx_broadcast,
1004 &nes->tx_broadcast);
1005 i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
1006 i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
1010 i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1013 struct i40e_eth_stats *pstats = NULL;
1014 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1015 struct i40e_vsi *vsi = &vf->vsi;
1017 ret = i40evf_update_stats(dev, &pstats);
1021 i40evf_update_vsi_stats(vsi, pstats);
1023 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
1024 pstats->rx_broadcast;
1025 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
1027 stats->imissed = pstats->rx_discards;
1028 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
1029 stats->ibytes = pstats->rx_bytes;
1030 stats->obytes = pstats->tx_bytes;
1036 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
1039 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1040 struct i40e_eth_stats *pstats = NULL;
1042 /* read stat values to clear hardware registers */
1043 ret = i40evf_update_stats(dev, &pstats);
1045 /* set stats offset base on current values */
1047 vf->vsi.eth_stats_offset = *pstats;
1050 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1051 struct rte_eth_xstat_name *xstats_names,
1052 __rte_unused unsigned limit)
1056 if (xstats_names != NULL)
1057 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1058 snprintf(xstats_names[i].name,
1059 sizeof(xstats_names[i].name),
1060 "%s", rte_i40evf_stats_strings[i].name);
1062 return I40EVF_NB_XSTATS;
1065 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1066 struct rte_eth_xstat *xstats, unsigned n)
1070 struct i40e_eth_stats *pstats = NULL;
1071 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1072 struct i40e_vsi *vsi = &vf->vsi;
1074 if (n < I40EVF_NB_XSTATS)
1075 return I40EVF_NB_XSTATS;
1077 ret = i40evf_update_stats(dev, &pstats);
1084 i40evf_update_vsi_stats(vsi, pstats);
1086 /* loop over xstats array and values from pstats */
1087 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1089 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1090 rte_i40evf_stats_strings[i].offset);
1093 return I40EVF_NB_XSTATS;
1097 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1099 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1100 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1101 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1104 struct vf_cmd_info args;
1106 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1107 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1108 vlan_list->num_elements = 1;
1109 vlan_list->vlan_id[0] = vlanid;
1111 args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
1112 args.in_args = (u8 *)&cmd_buffer;
1113 args.in_args_size = sizeof(cmd_buffer);
1114 args.out_buffer = vf->aq_resp;
1115 args.out_size = I40E_AQ_BUF_SZ;
1116 err = i40evf_execute_vf_cmd(dev, &args);
1118 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1124 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1126 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1127 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1128 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1131 struct vf_cmd_info args;
1133 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1134 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1135 vlan_list->num_elements = 1;
1136 vlan_list->vlan_id[0] = vlanid;
1138 args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
1139 args.in_args = (u8 *)&cmd_buffer;
1140 args.in_args_size = sizeof(cmd_buffer);
1141 args.out_buffer = vf->aq_resp;
1142 args.out_size = I40E_AQ_BUF_SZ;
1143 err = i40evf_execute_vf_cmd(dev, &args);
1145 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1150 static const struct rte_pci_id pci_id_i40evf_map[] = {
1151 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1152 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1153 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1154 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1155 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF_HV) },
1156 { .vendor_id = 0, /* sentinel */ },
1160 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1161 struct rte_eth_link *link)
1163 struct rte_eth_link *dst = &(dev->data->dev_link);
1164 struct rte_eth_link *src = link;
1166 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1167 *(uint64_t *)src) == 0)
1175 i40evf_disable_irq0(struct i40e_hw *hw)
1177 /* Disable all interrupt types */
1178 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1179 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1180 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1181 I40EVF_WRITE_FLUSH(hw);
1186 i40evf_enable_irq0(struct i40e_hw *hw)
1188 /* Enable admin queue interrupt trigger */
1191 i40evf_disable_irq0(hw);
1192 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1193 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1194 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1195 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1197 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1198 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1199 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1200 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1202 I40EVF_WRITE_FLUSH(hw);
1206 i40evf_reset_vf(struct i40e_hw *hw)
1210 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1211 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1215 * After issuing vf reset command to pf, pf won't necessarily
1216 * reset vf, it depends on what state it exactly is. If it's not
1217 * initialized yet, it won't have vf reset since it's in a certain
1218 * state. If not, it will try to reset. Even vf is reset, pf will
1219 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1220 * it to ACTIVE. In this duration, vf may not catch the moment that
1221 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1225 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1226 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1227 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1228 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1229 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1235 if (i >= MAX_RESET_WAIT_CNT) {
1236 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1244 i40evf_init_vf(struct rte_eth_dev *dev)
1247 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1248 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1249 struct ether_addr *p_mac_addr;
1251 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX, 0);
1253 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1254 vf->dev_data = dev->data;
1255 err = i40e_set_mac_type(hw);
1257 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1261 i40e_init_adminq_parameter(hw);
1262 err = i40e_init_adminq(hw);
1264 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1268 /* Reset VF and wait until it's complete */
1269 if (i40evf_reset_vf(hw)) {
1270 PMD_INIT_LOG(ERR, "reset NIC failed");
1274 /* VF reset, shutdown admin queue and initialize again */
1275 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1276 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1280 i40e_init_adminq_parameter(hw);
1281 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1282 PMD_INIT_LOG(ERR, "init_adminq failed");
1285 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1287 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1290 if (i40evf_check_api_version(dev) != 0) {
1291 PMD_INIT_LOG(ERR, "check_api version failed");
1294 bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1295 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1296 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1298 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1302 if (i40evf_get_vf_resource(dev) != 0) {
1303 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1307 /* got VF config message back from PF, now we can parse it */
1308 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1309 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1310 vf->vsi_res = &vf->vf_res->vsi_res[i];
1314 PMD_INIT_LOG(ERR, "no LAN VSI found");
1318 if (hw->mac.type == I40E_MAC_X722_VF)
1319 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1320 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1321 vf->vsi.type = vf->vsi_res->vsi_type;
1322 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1323 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1325 /* Store the MAC address configured by host, or generate random one */
1326 p_mac_addr = (struct ether_addr *)(vf->vsi_res->default_mac_addr);
1327 if (is_valid_assigned_ether_addr(p_mac_addr)) /* Configured by host */
1328 ether_addr_copy(p_mac_addr, (struct ether_addr *)hw->mac.addr);
1330 eth_random_addr(hw->mac.addr); /* Generate a random one */
1332 /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1333 if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1334 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1335 (I40E_ITR_INDEX_DEFAULT <<
1336 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1338 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1339 I40EVF_WRITE_FLUSH(hw);
1345 rte_free(vf->vf_res);
1348 rte_free(vf->aq_resp);
1350 i40e_shutdown_adminq(hw); /* ignore error */
1356 i40evf_uninit_vf(struct rte_eth_dev *dev)
1358 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1359 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1361 PMD_INIT_FUNC_TRACE();
1363 if (hw->adapter_stopped == 0)
1364 i40evf_dev_close(dev);
1365 rte_free(vf->vf_res);
1367 rte_free(vf->aq_resp);
1374 i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
1376 __rte_unused uint16_t msglen)
1378 struct i40e_virtchnl_pf_event *pf_msg =
1379 (struct i40e_virtchnl_pf_event *)msg;
1380 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1382 switch (pf_msg->event) {
1383 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
1384 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event\n");
1385 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
1387 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
1388 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event\n");
1389 vf->link_up = pf_msg->event_data.link_event.link_status;
1390 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1392 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1393 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event\n");
1396 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1402 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1404 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1405 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1406 struct i40e_arq_event_info info;
1407 uint16_t pending, aq_opc;
1408 enum i40e_virtchnl_ops msg_opc;
1409 enum i40e_status_code msg_ret;
1412 info.buf_len = I40E_AQ_BUF_SZ;
1414 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1417 info.msg_buf = vf->aq_resp;
1421 ret = i40e_clean_arq_element(hw, &info, &pending);
1423 if (ret != I40E_SUCCESS) {
1424 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1428 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1429 /* For the message sent from pf to vf, opcode is stored in
1430 * cookie_high of struct i40e_aq_desc, while return error code
1431 * are stored in cookie_low, Which is done by
1432 * i40e_aq_send_msg_to_vf in PF driver.*/
1433 msg_opc = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(
1434 info.desc.cookie_high);
1435 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1436 info.desc.cookie_low);
1438 case i40e_aqc_opc_send_msg_to_vf:
1439 if (msg_opc == I40E_VIRTCHNL_OP_EVENT)
1441 i40evf_handle_pf_event(dev, info.msg_buf,
1444 /* read message and it's expected one */
1445 if (msg_opc == vf->pend_cmd) {
1446 vf->cmd_retval = msg_ret;
1447 /* prevent compiler reordering */
1448 rte_compiler_barrier();
1451 PMD_DRV_LOG(ERR, "command mismatch,"
1452 "expect %u, get %u",
1453 vf->pend_cmd, msg_opc);
1454 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1455 " opcode = %d\n", msg_opc);
1459 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1467 * Interrupt handler triggered by NIC for handling
1468 * specific interrupt. Only adminq interrupt is processed in VF.
1471 * Pointer to interrupt handle.
1473 * The address of parameter (struct rte_eth_dev *) regsitered before.
1479 i40evf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1482 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1483 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1486 i40evf_disable_irq0(hw);
1488 /* read out interrupt causes */
1489 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1491 /* No interrupt event indicated */
1492 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1493 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do\n");
1497 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1498 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported\n");
1499 i40evf_handle_aq_msg(dev);
1502 /* Link Status Change interrupt */
1503 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1504 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1508 i40evf_enable_irq0(hw);
1512 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1514 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(\
1515 eth_dev->data->dev_private);
1516 struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1518 PMD_INIT_FUNC_TRACE();
1520 /* assign ops func pointer */
1521 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1522 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1523 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1526 * For secondary processes, we don't initialise any further as primary
1527 * has already done this work.
1529 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1530 i40e_set_rx_function(eth_dev);
1531 i40e_set_tx_function(eth_dev);
1535 rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
1537 hw->vendor_id = eth_dev->pci_dev->id.vendor_id;
1538 hw->device_id = eth_dev->pci_dev->id.device_id;
1539 hw->subsystem_vendor_id = eth_dev->pci_dev->id.subsystem_vendor_id;
1540 hw->subsystem_device_id = eth_dev->pci_dev->id.subsystem_device_id;
1541 hw->bus.device = eth_dev->pci_dev->addr.devid;
1542 hw->bus.func = eth_dev->pci_dev->addr.function;
1543 hw->hw_addr = (void *)eth_dev->pci_dev->mem_resource[0].addr;
1544 hw->adapter_stopped = 0;
1546 if(i40evf_init_vf(eth_dev) != 0) {
1547 PMD_INIT_LOG(ERR, "Init vf failed");
1551 /* register callback func to eal lib */
1552 rte_intr_callback_register(&pci_dev->intr_handle,
1553 i40evf_dev_interrupt_handler, (void *)eth_dev);
1555 /* enable uio intr after callback register */
1556 rte_intr_enable(&pci_dev->intr_handle);
1558 /* configure and enable device interrupt */
1559 i40evf_enable_irq0(hw);
1562 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1563 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1565 if (eth_dev->data->mac_addrs == NULL) {
1566 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1567 " store MAC addresses",
1568 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1571 ether_addr_copy((struct ether_addr *)hw->mac.addr,
1572 ð_dev->data->mac_addrs[0]);
1578 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1580 PMD_INIT_FUNC_TRACE();
1582 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1585 eth_dev->dev_ops = NULL;
1586 eth_dev->rx_pkt_burst = NULL;
1587 eth_dev->tx_pkt_burst = NULL;
1589 if (i40evf_uninit_vf(eth_dev) != 0) {
1590 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1594 rte_free(eth_dev->data->mac_addrs);
1595 eth_dev->data->mac_addrs = NULL;
1600 * virtual function driver struct
1602 static struct eth_driver rte_i40evf_pmd = {
1604 .id_table = pci_id_i40evf_map,
1605 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1606 .probe = rte_eth_dev_pci_probe,
1607 .remove = rte_eth_dev_pci_remove,
1609 .eth_dev_init = i40evf_dev_init,
1610 .eth_dev_uninit = i40evf_dev_uninit,
1611 .dev_private_size = sizeof(struct i40e_adapter),
1614 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd.pci_drv);
1615 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1618 i40evf_dev_configure(struct rte_eth_dev *dev)
1620 struct i40e_adapter *ad =
1621 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1622 struct rte_eth_conf *conf = &dev->data->dev_conf;
1625 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1626 * allocation or vector Rx preconditions we will reset it.
1628 ad->rx_bulk_alloc_allowed = true;
1629 ad->rx_vec_allowed = true;
1630 ad->tx_simple_allowed = true;
1631 ad->tx_vec_allowed = true;
1633 /* For non-DPDK PF drivers, VF has no ability to disable HW
1634 * CRC strip, and is implicitly enabled by the PF.
1636 if (!conf->rxmode.hw_strip_crc) {
1637 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1638 if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
1639 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR)) {
1640 /* Peer is running non-DPDK PF driver. */
1641 PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1646 return i40evf_init_vlan(dev);
1650 i40evf_init_vlan(struct rte_eth_dev *dev)
1652 struct rte_eth_dev_data *data = dev->data;
1655 /* Apply vlan offload setting */
1656 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1658 /* Apply pvid setting */
1659 ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1660 data->dev_conf.txmode.hw_vlan_insert_pvid);
1665 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1667 bool enable_vlan_strip = 0;
1668 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1669 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1671 /* Linux pf host doesn't support vlan offload yet */
1672 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1673 /* Vlan stripping setting */
1674 if (mask & ETH_VLAN_STRIP_MASK) {
1675 /* Enable or disable VLAN stripping */
1676 if (dev_conf->rxmode.hw_vlan_strip)
1677 enable_vlan_strip = 1;
1679 enable_vlan_strip = 0;
1681 i40evf_config_vlan_offload(dev, enable_vlan_strip);
1687 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1689 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1690 struct i40e_vsi_vlan_pvid_info info;
1691 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1693 memset(&info, 0, sizeof(info));
1696 /* Linux pf host don't support vlan offload yet */
1697 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1699 info.config.pvid = pvid;
1701 info.config.reject.tagged =
1702 dev_conf->txmode.hw_vlan_reject_tagged;
1703 info.config.reject.untagged =
1704 dev_conf->txmode.hw_vlan_reject_untagged;
1706 return i40evf_config_vlan_pvid(dev, &info);
1713 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1715 struct i40e_rx_queue *rxq;
1717 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1719 PMD_INIT_FUNC_TRACE();
1721 if (rx_queue_id < dev->data->nb_rx_queues) {
1722 rxq = dev->data->rx_queues[rx_queue_id];
1724 err = i40e_alloc_rx_queue_mbufs(rxq);
1726 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1732 /* Init the RX tail register. */
1733 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1734 I40EVF_WRITE_FLUSH(hw);
1736 /* Ready to switch the queue on */
1737 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1740 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1743 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1750 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1752 struct i40e_rx_queue *rxq;
1755 if (rx_queue_id < dev->data->nb_rx_queues) {
1756 rxq = dev->data->rx_queues[rx_queue_id];
1758 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1761 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1766 i40e_rx_queue_release_mbufs(rxq);
1767 i40e_reset_rx_queue(rxq);
1768 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1775 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1779 PMD_INIT_FUNC_TRACE();
1781 if (tx_queue_id < dev->data->nb_tx_queues) {
1783 /* Ready to switch the queue on */
1784 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1787 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1790 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1797 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1799 struct i40e_tx_queue *txq;
1802 if (tx_queue_id < dev->data->nb_tx_queues) {
1803 txq = dev->data->tx_queues[tx_queue_id];
1805 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1808 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1813 i40e_tx_queue_release_mbufs(txq);
1814 i40e_reset_tx_queue(txq);
1815 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1822 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1827 ret = i40evf_add_vlan(dev, vlan_id);
1829 ret = i40evf_del_vlan(dev,vlan_id);
1835 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1837 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1838 struct rte_eth_dev_data *dev_data = dev->data;
1839 struct rte_pktmbuf_pool_private *mbp_priv;
1840 uint16_t buf_size, len;
1842 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1843 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1844 I40EVF_WRITE_FLUSH(hw);
1846 /* Calculate the maximum packet length allowed */
1847 mbp_priv = rte_mempool_get_priv(rxq->mp);
1848 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1849 RTE_PKTMBUF_HEADROOM);
1850 rxq->hs_mode = i40e_header_split_none;
1851 rxq->rx_hdr_len = 0;
1852 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1853 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1854 rxq->max_pkt_len = RTE_MIN(len,
1855 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1858 * Check if the jumbo frame and maximum packet length are set correctly
1860 if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1861 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1862 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1863 PMD_DRV_LOG(ERR, "maximum packet length must be "
1864 "larger than %u and smaller than %u, as jumbo "
1865 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1866 (uint32_t)I40E_FRAME_SIZE_MAX);
1867 return I40E_ERR_CONFIG;
1870 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1871 rxq->max_pkt_len > ETHER_MAX_LEN) {
1872 PMD_DRV_LOG(ERR, "maximum packet length must be "
1873 "larger than %u and smaller than %u, as jumbo "
1874 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1875 (uint32_t)ETHER_MAX_LEN);
1876 return I40E_ERR_CONFIG;
1880 if (dev_data->dev_conf.rxmode.enable_scatter ||
1881 (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1882 dev_data->scattered_rx = 1;
1889 i40evf_rx_init(struct rte_eth_dev *dev)
1891 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1893 int ret = I40E_SUCCESS;
1894 struct i40e_rx_queue **rxq =
1895 (struct i40e_rx_queue **)dev->data->rx_queues;
1897 i40evf_config_rss(vf);
1898 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1899 if (!rxq[i] || !rxq[i]->q_set)
1901 ret = i40evf_rxq_init(dev, rxq[i]);
1902 if (ret != I40E_SUCCESS)
1905 if (ret == I40E_SUCCESS)
1906 i40e_set_rx_function(dev);
1912 i40evf_tx_init(struct rte_eth_dev *dev)
1915 struct i40e_tx_queue **txq =
1916 (struct i40e_tx_queue **)dev->data->tx_queues;
1917 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1919 for (i = 0; i < dev->data->nb_tx_queues; i++)
1920 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1922 i40e_set_tx_function(dev);
1926 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1928 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1929 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1932 if (!rte_intr_allow_others(intr_handle)) {
1934 I40E_VFINT_DYN_CTL01,
1935 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1936 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1937 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1938 I40EVF_WRITE_FLUSH(hw);
1942 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1943 /* To support DPDK PF host */
1945 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1946 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1947 I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1948 /* If host driver is kernel driver, do nothing.
1949 * Interrupt 0 is used for rx packets, but don't set
1950 * I40E_VFINT_DYN_CTL01,
1951 * because it is already done in i40evf_enable_irq0.
1954 I40EVF_WRITE_FLUSH(hw);
1958 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1960 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1961 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1962 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1964 if (!rte_intr_allow_others(intr_handle)) {
1965 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1966 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1967 I40EVF_WRITE_FLUSH(hw);
1971 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1973 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1976 /* If host driver is kernel driver, do nothing.
1977 * Interrupt 0 is used for rx packets, but don't zero
1978 * I40E_VFINT_DYN_CTL01,
1979 * because interrupt 0 is also used for adminq processing.
1982 I40EVF_WRITE_FLUSH(hw);
1986 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1988 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1989 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 0);
1994 msix_intr = intr_handle->intr_vec[queue_id];
1995 if (msix_intr == I40E_MISC_VEC_ID)
1996 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1997 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1998 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1999 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
2001 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
2004 I40E_VFINT_DYN_CTLN1(msix_intr -
2006 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
2007 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
2008 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
2010 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
2012 I40EVF_WRITE_FLUSH(hw);
2014 rte_intr_enable(&dev->pci_dev->intr_handle);
2020 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2022 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2023 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2026 msix_intr = intr_handle->intr_vec[queue_id];
2027 if (msix_intr == I40E_MISC_VEC_ID)
2028 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
2031 I40E_VFINT_DYN_CTLN1(msix_intr -
2035 I40EVF_WRITE_FLUSH(hw);
2041 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
2043 struct i40e_virtchnl_ether_addr_list *list;
2044 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2049 struct ether_addr *addr;
2050 struct vf_cmd_info args;
2054 len = sizeof(struct i40e_virtchnl_ether_addr_list);
2055 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
2056 if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
2058 len += sizeof(struct i40e_virtchnl_ether_addr);
2059 if (len >= I40E_AQ_BUF_SZ) {
2065 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2067 PMD_DRV_LOG(ERR, "fail to allocate memory");
2071 for (i = begin; i < next_begin; i++) {
2072 addr = &dev->data->mac_addrs[i];
2073 if (is_zero_ether_addr(addr))
2075 (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
2076 sizeof(addr->addr_bytes));
2077 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2078 addr->addr_bytes[0], addr->addr_bytes[1],
2079 addr->addr_bytes[2], addr->addr_bytes[3],
2080 addr->addr_bytes[4], addr->addr_bytes[5]);
2083 list->vsi_id = vf->vsi_res->vsi_id;
2084 list->num_elements = j;
2085 args.ops = add ? I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS :
2086 I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
2087 args.in_args = (uint8_t *)list;
2088 args.in_args_size = len;
2089 args.out_buffer = vf->aq_resp;
2090 args.out_size = I40E_AQ_BUF_SZ;
2091 err = i40evf_execute_vf_cmd(dev, &args);
2093 PMD_DRV_LOG(ERR, "fail to execute command %s",
2094 add ? "OP_ADD_ETHER_ADDRESS" :
2095 "OP_DEL_ETHER_ADDRESS");
2098 } while (begin < I40E_NUM_MACADDR_MAX);
2102 i40evf_dev_start(struct rte_eth_dev *dev)
2104 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2105 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2107 uint32_t intr_vector = 0;
2109 PMD_INIT_FUNC_TRACE();
2111 hw->adapter_stopped = 0;
2113 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2114 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2115 dev->data->nb_tx_queues);
2117 /* check and configure queue intr-vector mapping */
2118 if (rte_intr_cap_multiple(intr_handle) &&
2119 dev->data->dev_conf.intr_conf.rxq) {
2120 intr_vector = dev->data->nb_rx_queues;
2121 if (rte_intr_efd_enable(intr_handle, intr_vector))
2125 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2126 intr_handle->intr_vec =
2127 rte_zmalloc("intr_vec",
2128 dev->data->nb_rx_queues * sizeof(int), 0);
2129 if (!intr_handle->intr_vec) {
2130 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2131 " intr_vec\n", dev->data->nb_rx_queues);
2136 if (i40evf_rx_init(dev) != 0){
2137 PMD_DRV_LOG(ERR, "failed to do RX init");
2141 i40evf_tx_init(dev);
2143 if (i40evf_configure_queues(dev) != 0) {
2144 PMD_DRV_LOG(ERR, "configure queues failed");
2147 if (i40evf_config_irq_map(dev)) {
2148 PMD_DRV_LOG(ERR, "config_irq_map failed");
2152 /* Set all mac addrs */
2153 i40evf_add_del_all_mac_addr(dev, TRUE);
2155 if (i40evf_start_queues(dev) != 0) {
2156 PMD_DRV_LOG(ERR, "enable queues failed");
2160 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
2161 * is mapped to VFIO vector 0 in i40evf_dev_init( ).
2162 * If previous VFIO interrupt mapping set in i40evf_dev_init( ) is
2163 * not cleared, it will fail when rte_intr_enable( ) tries to map Rx
2164 * queue interrupt to other VFIO vectors.
2165 * So clear uio/vfio intr/evevnfd first to avoid failure.
2167 if (dev->data->dev_conf.intr_conf.rxq != 0) {
2168 rte_intr_disable(intr_handle);
2169 rte_intr_enable(intr_handle);
2172 i40evf_enable_queues_intr(dev);
2177 i40evf_add_del_all_mac_addr(dev, FALSE);
2183 i40evf_dev_stop(struct rte_eth_dev *dev)
2185 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2187 PMD_INIT_FUNC_TRACE();
2189 i40evf_stop_queues(dev);
2190 i40evf_disable_queues_intr(dev);
2191 i40e_dev_clear_queues(dev);
2193 /* Clean datapath event and queue/vec mapping */
2194 rte_intr_efd_disable(intr_handle);
2195 if (intr_handle->intr_vec) {
2196 rte_free(intr_handle->intr_vec);
2197 intr_handle->intr_vec = NULL;
2199 /* remove all mac addrs */
2200 i40evf_add_del_all_mac_addr(dev, FALSE);
2205 i40evf_dev_link_update(struct rte_eth_dev *dev,
2206 __rte_unused int wait_to_complete)
2208 struct rte_eth_link new_link;
2209 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2211 * DPDK pf host provide interfacet to acquire link status
2212 * while Linux driver does not
2215 /* Linux driver PF host */
2216 switch (vf->link_speed) {
2217 case I40E_LINK_SPEED_100MB:
2218 new_link.link_speed = ETH_SPEED_NUM_100M;
2220 case I40E_LINK_SPEED_1GB:
2221 new_link.link_speed = ETH_SPEED_NUM_1G;
2223 case I40E_LINK_SPEED_10GB:
2224 new_link.link_speed = ETH_SPEED_NUM_10G;
2226 case I40E_LINK_SPEED_20GB:
2227 new_link.link_speed = ETH_SPEED_NUM_20G;
2229 case I40E_LINK_SPEED_25GB:
2230 new_link.link_speed = ETH_SPEED_NUM_25G;
2232 case I40E_LINK_SPEED_40GB:
2233 new_link.link_speed = ETH_SPEED_NUM_40G;
2236 new_link.link_speed = ETH_SPEED_NUM_100M;
2239 /* full duplex only */
2240 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2241 new_link.link_status = vf->link_up ? ETH_LINK_UP :
2243 new_link.link_autoneg =
2244 dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED;
2246 i40evf_dev_atomic_write_link_status(dev, &new_link);
2252 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2254 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2257 /* If enabled, just return */
2258 if (vf->promisc_unicast_enabled)
2261 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2263 vf->promisc_unicast_enabled = TRUE;
2267 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2269 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2272 /* If disabled, just return */
2273 if (!vf->promisc_unicast_enabled)
2276 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2278 vf->promisc_unicast_enabled = FALSE;
2282 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2284 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2287 /* If enabled, just return */
2288 if (vf->promisc_multicast_enabled)
2291 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2293 vf->promisc_multicast_enabled = TRUE;
2297 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2299 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2302 /* If enabled, just return */
2303 if (!vf->promisc_multicast_enabled)
2306 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2308 vf->promisc_multicast_enabled = FALSE;
2312 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2314 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2316 dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2317 dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2318 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2319 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2320 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2321 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2322 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2323 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2324 dev_info->rx_offload_capa =
2325 DEV_RX_OFFLOAD_VLAN_STRIP |
2326 DEV_RX_OFFLOAD_QINQ_STRIP |
2327 DEV_RX_OFFLOAD_IPV4_CKSUM |
2328 DEV_RX_OFFLOAD_UDP_CKSUM |
2329 DEV_RX_OFFLOAD_TCP_CKSUM;
2330 dev_info->tx_offload_capa =
2331 DEV_TX_OFFLOAD_VLAN_INSERT |
2332 DEV_TX_OFFLOAD_QINQ_INSERT |
2333 DEV_TX_OFFLOAD_IPV4_CKSUM |
2334 DEV_TX_OFFLOAD_UDP_CKSUM |
2335 DEV_TX_OFFLOAD_TCP_CKSUM |
2336 DEV_TX_OFFLOAD_SCTP_CKSUM;
2338 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2340 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2341 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2342 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2344 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2348 dev_info->default_txconf = (struct rte_eth_txconf) {
2350 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2351 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2352 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2354 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2355 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2356 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2357 ETH_TXQ_FLAGS_NOOFFLOADS,
2360 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2361 .nb_max = I40E_MAX_RING_DESC,
2362 .nb_min = I40E_MIN_RING_DESC,
2363 .nb_align = I40E_ALIGN_RING_DESC,
2366 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2367 .nb_max = I40E_MAX_RING_DESC,
2368 .nb_min = I40E_MIN_RING_DESC,
2369 .nb_align = I40E_ALIGN_RING_DESC,
2374 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2376 if (i40evf_get_statics(dev, stats))
2377 PMD_DRV_LOG(ERR, "Get statics failed");
2381 i40evf_dev_close(struct rte_eth_dev *dev)
2383 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2384 struct rte_pci_device *pci_dev = dev->pci_dev;
2386 i40evf_dev_stop(dev);
2387 hw->adapter_stopped = 1;
2388 i40e_dev_free_queues(dev);
2389 i40evf_reset_vf(hw);
2390 i40e_shutdown_adminq(hw);
2391 /* disable uio intr before callback unregister */
2392 rte_intr_disable(&pci_dev->intr_handle);
2394 /* unregister callback func from eal lib */
2395 rte_intr_callback_unregister(&pci_dev->intr_handle,
2396 i40evf_dev_interrupt_handler, (void *)dev);
2397 i40evf_disable_irq0(hw);
2401 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2403 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2404 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2410 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2411 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2414 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2418 uint32_t *lut_dw = (uint32_t *)lut;
2419 uint16_t i, lut_size_dw = lut_size / 4;
2421 for (i = 0; i < lut_size_dw; i++)
2422 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2429 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2438 vf = I40E_VSI_TO_VF(vsi);
2439 hw = I40E_VSI_TO_HW(vsi);
2441 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2442 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2445 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2449 uint32_t *lut_dw = (uint32_t *)lut;
2450 uint16_t i, lut_size_dw = lut_size / 4;
2452 for (i = 0; i < lut_size_dw; i++)
2453 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2454 I40EVF_WRITE_FLUSH(hw);
2461 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2462 struct rte_eth_rss_reta_entry64 *reta_conf,
2465 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2467 uint16_t i, idx, shift;
2470 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2471 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2472 "(%d) doesn't match the number of hardware can "
2473 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2477 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2479 PMD_DRV_LOG(ERR, "No memory can be allocated");
2482 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2485 for (i = 0; i < reta_size; i++) {
2486 idx = i / RTE_RETA_GROUP_SIZE;
2487 shift = i % RTE_RETA_GROUP_SIZE;
2488 if (reta_conf[idx].mask & (1ULL << shift))
2489 lut[i] = reta_conf[idx].reta[shift];
2491 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2500 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2501 struct rte_eth_rss_reta_entry64 *reta_conf,
2504 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2505 uint16_t i, idx, shift;
2509 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2510 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2511 "(%d) doesn't match the number of hardware can "
2512 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2516 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2518 PMD_DRV_LOG(ERR, "No memory can be allocated");
2522 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2525 for (i = 0; i < reta_size; i++) {
2526 idx = i / RTE_RETA_GROUP_SIZE;
2527 shift = i % RTE_RETA_GROUP_SIZE;
2528 if (reta_conf[idx].mask & (1ULL << shift))
2529 reta_conf[idx].reta[shift] = lut[i];
2539 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2541 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2542 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2545 if (!key || key_len == 0) {
2546 PMD_DRV_LOG(DEBUG, "No key to be configured");
2548 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2550 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2554 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2555 struct i40e_aqc_get_set_rss_key_data *key_dw =
2556 (struct i40e_aqc_get_set_rss_key_data *)key;
2558 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2560 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2563 uint32_t *hash_key = (uint32_t *)key;
2566 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2567 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2568 I40EVF_WRITE_FLUSH(hw);
2575 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2577 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2578 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2581 if (!key || !key_len)
2584 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2585 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2586 (struct i40e_aqc_get_set_rss_key_data *)key);
2588 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2592 uint32_t *key_dw = (uint32_t *)key;
2595 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2596 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2598 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2604 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2606 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2607 uint64_t rss_hf, hena;
2610 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2611 rss_conf->rss_key_len);
2615 rss_hf = rss_conf->rss_hf;
2616 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2617 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2618 if (hw->mac.type == I40E_MAC_X722)
2619 hena &= ~I40E_RSS_HENA_ALL_X722;
2621 hena &= ~I40E_RSS_HENA_ALL;
2622 hena |= i40e_config_hena(rss_hf, hw->mac.type);
2623 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2624 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2625 I40EVF_WRITE_FLUSH(hw);
2631 i40evf_disable_rss(struct i40e_vf *vf)
2633 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2636 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2637 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2638 if (hw->mac.type == I40E_MAC_X722)
2639 hena &= ~I40E_RSS_HENA_ALL_X722;
2641 hena &= ~I40E_RSS_HENA_ALL;
2642 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2643 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2644 I40EVF_WRITE_FLUSH(hw);
2648 i40evf_config_rss(struct i40e_vf *vf)
2650 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2651 struct rte_eth_rss_conf rss_conf;
2652 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2655 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2656 i40evf_disable_rss(vf);
2657 PMD_DRV_LOG(DEBUG, "RSS not configured\n");
2661 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2662 /* Fill out the look up table */
2663 for (i = 0, j = 0; i < nb_q; i++, j++) {
2666 lut = (lut << 8) | j;
2668 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2671 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2672 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2673 i40evf_disable_rss(vf);
2674 PMD_DRV_LOG(DEBUG, "No hash flag is set\n");
2678 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2679 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2680 /* Calculate the default hash key */
2681 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2682 rss_key_default[i] = (uint32_t)rte_rand();
2683 rss_conf.rss_key = (uint8_t *)rss_key_default;
2684 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2688 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2692 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2693 struct rte_eth_rss_conf *rss_conf)
2695 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2696 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2697 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2700 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2701 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2702 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
2703 ? I40E_RSS_HENA_ALL_X722
2704 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
2705 if (rss_hf != 0) /* Enable RSS */
2711 if (rss_hf == 0) /* Disable RSS */
2714 return i40evf_hw_rss_hash_set(vf, rss_conf);
2718 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2719 struct rte_eth_rss_conf *rss_conf)
2721 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2722 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2725 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2726 &rss_conf->rss_key_len);
2728 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2729 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2730 rss_conf->rss_hf = i40e_parse_hena(hena);