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34 #include <sys/queue.h>
42 #include <rte_ether.h>
43 #include <rte_ethdev.h>
45 #include <rte_memzone.h>
46 #include <rte_malloc.h>
53 #include "i40e_logs.h"
54 #include "base/i40e_type.h"
55 #include "base/i40e_prototype.h"
56 #include "i40e_ethdev.h"
57 #include "i40e_rxtx.h"
59 #define I40E_FDIR_MZ_NAME "FDIR_MEMZONE"
61 #define IPV6_ADDR_LEN 16
64 #define I40E_FDIR_PKT_LEN 512
65 #define I40E_FDIR_IP_DEFAULT_LEN 420
66 #define I40E_FDIR_IP_DEFAULT_TTL 0x40
67 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL 0x45
68 #define I40E_FDIR_TCP_DEFAULT_DATAOFF 0x50
69 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW 0x60000000
70 #define I40E_FDIR_IPv6_TC_OFFSET 20
72 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS 0xFF
73 #define I40E_FDIR_IPv6_PAYLOAD_LEN 380
74 #define I40E_FDIR_UDP_DEFAULT_LEN 400
76 /* Wait count and interval for fdir filter programming */
77 #define I40E_FDIR_WAIT_COUNT 10
78 #define I40E_FDIR_WAIT_INTERVAL_US 1000
80 /* Wait count and interval for fdir filter flush */
81 #define I40E_FDIR_FLUSH_RETRY 50
82 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
84 #define I40E_COUNTER_PF 2
85 /* Statistic counter index for one pf */
86 #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF)
87 #define I40E_MAX_FLX_SOURCE_OFF 480
88 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
90 #define NONUSE_FLX_PIT_DEST_OFF 63
91 #define NONUSE_FLX_PIT_FSIZE 1
92 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
93 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
94 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
95 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
96 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
97 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
98 NONUSE_FLX_PIT_DEST_OFF : \
99 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
100 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
101 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
103 #define I40E_FDIR_FLOWS ( \
104 (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
105 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
106 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
107 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
108 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
109 (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
110 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
111 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
112 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
113 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
114 (1 << RTE_ETH_FLOW_L2_PAYLOAD))
116 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
118 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
119 enum i40e_filter_pctype pctype,
120 const struct rte_eth_fdir_filter *filter,
122 static int i40e_fdir_flush(struct rte_eth_dev *dev);
125 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
127 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
128 struct i40e_hmc_obj_rxq rx_ctx;
129 int err = I40E_SUCCESS;
131 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
132 /* Init the RX queue in hardware */
133 rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
135 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
136 rx_ctx.qlen = rxq->nb_rx_desc;
137 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
140 rx_ctx.dtype = i40e_header_split_none;
141 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
142 rx_ctx.rxmax = ETHER_MAX_LEN;
143 rx_ctx.tphrdesc_ena = 1;
144 rx_ctx.tphwdesc_ena = 1;
145 rx_ctx.tphdata_ena = 1;
146 rx_ctx.tphhead_ena = 1;
147 rx_ctx.lrxqthresh = 2;
153 err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
154 if (err != I40E_SUCCESS) {
155 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
158 err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
159 if (err != I40E_SUCCESS) {
160 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
163 rxq->qrx_tail = hw->hw_addr +
164 I40E_QRX_TAIL(rxq->vsi->base_queue);
167 /* Init the RX tail regieter. */
168 I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
169 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
175 * i40e_fdir_setup - reserve and initialize the Flow Director resources
176 * @pf: board private structure
179 i40e_fdir_setup(struct i40e_pf *pf)
181 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
182 struct i40e_vsi *vsi;
183 int err = I40E_SUCCESS;
184 char z_name[RTE_MEMZONE_NAMESIZE];
185 const struct rte_memzone *mz = NULL;
186 struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
188 if ((pf->flags & I40E_FLAG_FDIR) == 0) {
189 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
190 return I40E_NOT_SUPPORTED;
193 PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
194 " num_filters_best_effort = %u.",
195 hw->func_caps.fd_filters_guaranteed,
196 hw->func_caps.fd_filters_best_effort);
198 vsi = pf->fdir.fdir_vsi;
200 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
203 /* make new FDIR VSI */
204 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
206 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
207 return I40E_ERR_NO_AVAILABLE_VSI;
209 pf->fdir.fdir_vsi = vsi;
211 /*Fdir tx queue setup*/
212 err = i40e_fdir_setup_tx_resources(pf);
214 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
218 /*Fdir rx queue setup*/
219 err = i40e_fdir_setup_rx_resources(pf);
221 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
225 err = i40e_tx_queue_init(pf->fdir.txq);
227 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
231 /* need switch on before dev start*/
232 err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
234 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
238 /* Init the rx queue in hardware */
239 err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
241 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
245 /* switch on rx queue */
246 err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
248 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
252 /* reserve memory for the fdir programming packet */
253 snprintf(z_name, sizeof(z_name), "%s_%s_%d",
254 eth_dev->driver->pci_drv.driver.name,
256 eth_dev->data->port_id);
257 mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
259 PMD_DRV_LOG(ERR, "Cannot init memzone for "
260 "flow director program packet.");
261 err = I40E_ERR_NO_MEMORY;
264 pf->fdir.prg_pkt = mz->addr;
265 pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
267 pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
268 PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
273 i40e_dev_rx_queue_release(pf->fdir.rxq);
276 i40e_dev_tx_queue_release(pf->fdir.txq);
279 i40e_vsi_release(vsi);
280 pf->fdir.fdir_vsi = NULL;
285 * i40e_fdir_teardown - release the Flow Director resources
286 * @pf: board private structure
289 i40e_fdir_teardown(struct i40e_pf *pf)
291 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
292 struct i40e_vsi *vsi;
294 vsi = pf->fdir.fdir_vsi;
297 int err = i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
299 PMD_DRV_LOG(DEBUG, "Failed to do FDIR TX switch off");
300 err = i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
302 PMD_DRV_LOG(DEBUG, "Failed to do FDIR RX switch off");
303 i40e_dev_rx_queue_release(pf->fdir.rxq);
305 i40e_dev_tx_queue_release(pf->fdir.txq);
307 i40e_vsi_release(vsi);
308 pf->fdir.fdir_vsi = NULL;
311 /* check whether the flow director table in empty */
313 i40e_fdir_empty(struct i40e_hw *hw)
315 uint32_t guarant_cnt, best_cnt;
317 guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
318 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
319 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
320 best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
321 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
322 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
323 if (best_cnt + guarant_cnt > 0)
330 * Initialize the configuration about bytes stream extracted as flexible payload
334 i40e_init_flx_pld(struct i40e_pf *pf)
336 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
341 * Define the bytes stream extracted as flexible payload in
342 * field vector. By default, select 8 words from the beginning
343 * of payload as flexible payload.
345 for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
346 index = i * I40E_MAX_FLXPLD_FIED;
347 pf->fdir.flex_set[index].src_offset = 0;
348 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
349 pf->fdir.flex_set[index].dst_offset = 0;
350 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
352 I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
354 I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
357 /* initialize the masks */
358 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
359 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
360 if (hw->mac.type == I40E_MAC_X722) {
361 if (!I40E_VALID_PCTYPE_X722(
362 (enum i40e_filter_pctype)pctype))
365 if (!I40E_VALID_PCTYPE(
366 (enum i40e_filter_pctype)pctype))
369 pf->fdir.flex_mask[pctype].word_mask = 0;
370 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
371 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
372 pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
373 pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
374 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
379 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
381 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
382 if ((flex_pit2).src_offset < \
383 (flex_pit1).src_offset + (flex_pit1).size) { \
384 PMD_DRV_LOG(ERR, "src_offset should be not" \
385 " less than than previous offset" \
386 " + previous FSIZE."); \
392 * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
393 * and the flex_pit will be sorted by it's src_offset value
395 static inline uint16_t
396 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
397 struct i40e_fdir_flex_pit *flex_pit)
399 uint16_t src_tmp, size, num = 0;
400 uint16_t i, k, j = 0;
402 while (j < I40E_FDIR_MAX_FLEX_LEN) {
404 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
405 if (src_offset[j + 1] == src_offset[j] + 1)
410 src_tmp = src_offset[j] + 1 - size;
411 /* the flex_pit need to be sort by src_offset */
412 for (i = 0; i < num; i++) {
413 if (src_tmp < flex_pit[i].src_offset)
416 /* if insert required, move backward */
417 for (k = num; k > i; k--)
418 flex_pit[k] = flex_pit[k - 1];
420 flex_pit[i].dst_offset = j + 1 - size;
421 flex_pit[i].src_offset = src_tmp;
422 flex_pit[i].size = size;
429 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
431 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
433 struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
436 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
437 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
438 PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
443 memset(flex_pit, 0, sizeof(flex_pit));
444 num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
445 if (num > I40E_MAX_FLXPLD_FIED) {
446 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
449 for (i = 0; i < num; i++) {
450 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
451 flex_pit[i].src_offset & 0x01) {
452 PMD_DRV_LOG(ERR, "flexpayload should be measured"
457 I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
463 * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
464 * arguments are valid
467 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
469 const struct rte_eth_flex_payload_cfg *flex_cfg;
470 const struct rte_eth_fdir_flex_mask *flex_mask;
477 PMD_DRV_LOG(INFO, "NULL pointer.");
480 /* check flexible payload setting configuration */
481 if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
482 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
485 for (i = 0; i < conf->nb_payloads; i++) {
486 flex_cfg = &conf->flex_set[i];
487 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
488 PMD_DRV_LOG(ERR, "invalid payload type.");
491 ret = i40e_check_fdir_flex_payload(flex_cfg);
493 PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
498 /* check flex mask setting configuration */
499 if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
500 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
503 for (i = 0; i < conf->nb_flexmasks; i++) {
504 flex_mask = &conf->flex_mask[i];
505 if (!I40E_VALID_FLOW(flex_mask->flow_type)) {
506 PMD_DRV_LOG(WARNING, "invalid flow type.");
510 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
511 mask_tmp = I40E_WORD(flex_mask->mask[j],
512 flex_mask->mask[j + 1]);
513 if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
515 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
516 PMD_DRV_LOG(ERR, " exceed maximal"
517 " number of bitmasks.");
527 * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
528 * @pf: board private structure
529 * @cfg: the rule how bytes stream is extracted as flexible payload
532 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
533 const struct rte_eth_flex_payload_cfg *cfg)
535 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
536 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
538 uint16_t num, min_next_off; /* in words */
539 uint8_t field_idx = 0;
540 uint8_t layer_idx = 0;
543 if (cfg->type == RTE_ETH_L2_PAYLOAD)
544 layer_idx = I40E_FLXPLD_L2_IDX;
545 else if (cfg->type == RTE_ETH_L3_PAYLOAD)
546 layer_idx = I40E_FLXPLD_L3_IDX;
547 else if (cfg->type == RTE_ETH_L4_PAYLOAD)
548 layer_idx = I40E_FLXPLD_L4_IDX;
550 memset(flex_pit, 0, sizeof(flex_pit));
551 num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
553 for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
554 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
555 /* record the info in fdir structure */
556 pf->fdir.flex_set[field_idx].src_offset =
557 flex_pit[i].src_offset / sizeof(uint16_t);
558 pf->fdir.flex_set[field_idx].size =
559 flex_pit[i].size / sizeof(uint16_t);
560 pf->fdir.flex_set[field_idx].dst_offset =
561 flex_pit[i].dst_offset / sizeof(uint16_t);
562 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
563 pf->fdir.flex_set[field_idx].size,
564 pf->fdir.flex_set[field_idx].dst_offset);
566 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
568 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
569 pf->fdir.flex_set[field_idx].size;
571 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
572 /* set the non-used register obeying register's constrain */
573 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
574 NONUSE_FLX_PIT_DEST_OFF);
576 I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
583 * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
584 * @pf: board private structure
585 * @pctype: packet classify type
586 * @flex_masks: mask for flexible payload
589 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
590 enum i40e_filter_pctype pctype,
591 const struct rte_eth_fdir_flex_mask *mask_cfg)
593 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
594 struct i40e_fdir_flex_mask *flex_mask;
595 uint32_t flxinset, fd_mask;
597 uint8_t i, nb_bitmask = 0;
599 flex_mask = &pf->fdir.flex_mask[pctype];
600 memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
601 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
602 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
603 if (mask_tmp != 0x0) {
604 flex_mask->word_mask |=
605 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
606 if (mask_tmp != UINT16_MAX) {
608 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
609 flex_mask->bitmask[nb_bitmask].offset =
610 i / sizeof(uint16_t);
615 /* write mask to hw */
616 flxinset = (flex_mask->word_mask <<
617 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
618 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
619 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
621 for (i = 0; i < nb_bitmask; i++) {
622 fd_mask = (flex_mask->bitmask[i].mask <<
623 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
624 I40E_PRTQF_FD_MSK_MASK_MASK;
625 fd_mask |= ((flex_mask->bitmask[i].offset +
626 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
627 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
628 I40E_PRTQF_FD_MSK_OFFSET_MASK;
629 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
634 * Configure flow director related setting
637 i40e_fdir_configure(struct rte_eth_dev *dev)
639 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
640 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
641 struct rte_eth_fdir_flex_conf *conf;
642 enum i40e_filter_pctype pctype;
648 * configuration need to be done before
649 * flow director filters are added
650 * If filters exist, flush them.
652 if (i40e_fdir_empty(hw) < 0) {
653 ret = i40e_fdir_flush(dev);
655 PMD_DRV_LOG(ERR, "failed to flush fdir table.");
660 /* enable FDIR filter */
661 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
662 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
663 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
665 i40e_init_flx_pld(pf); /* set flex config to default value */
667 conf = &dev->data->dev_conf.fdir_conf.flex_conf;
668 ret = i40e_check_fdir_flex_conf(conf);
670 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
673 /* configure flex payload */
674 for (i = 0; i < conf->nb_payloads; i++)
675 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
676 /* configure flex mask*/
677 for (i = 0; i < conf->nb_flexmasks; i++) {
678 if (hw->mac.type == I40E_MAC_X722) {
679 /* get translated pctype value in fd pctype register */
680 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
681 hw, I40E_GLQF_FD_PCTYPES(
682 (int)i40e_flowtype_to_pctype(
683 conf->flex_mask[i].flow_type)));
685 pctype = i40e_flowtype_to_pctype(
686 conf->flex_mask[i].flow_type);
688 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
695 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
696 unsigned char *raw_pkt,
699 static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
700 uint16_t *ether_type;
701 uint8_t len = 2 * sizeof(struct ether_addr);
703 struct ipv6_hdr *ip6;
704 static const uint8_t next_proto[] = {
705 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
706 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
707 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
708 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
709 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
710 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
711 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
712 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
713 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
714 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
717 raw_pkt += 2 * sizeof(struct ether_addr);
718 if (vlan && fdir_input->flow_ext.vlan_tci) {
719 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
720 rte_memcpy(raw_pkt + sizeof(uint16_t),
721 &fdir_input->flow_ext.vlan_tci,
723 raw_pkt += sizeof(vlan_frame);
724 len += sizeof(vlan_frame);
726 ether_type = (uint16_t *)raw_pkt;
727 raw_pkt += sizeof(uint16_t);
728 len += sizeof(uint16_t);
730 switch (fdir_input->flow_type) {
731 case RTE_ETH_FLOW_L2_PAYLOAD:
732 *ether_type = fdir_input->flow.l2_flow.ether_type;
734 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
735 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
736 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
737 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
738 case RTE_ETH_FLOW_FRAG_IPV4:
739 ip = (struct ipv4_hdr *)raw_pkt;
741 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
742 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
743 /* set len to by default */
744 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
745 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
746 fdir_input->flow.ip4_flow.proto :
747 next_proto[fdir_input->flow_type];
748 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
749 fdir_input->flow.ip4_flow.ttl :
750 I40E_FDIR_IP_DEFAULT_TTL;
751 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
753 * The source and destination fields in the transmitted packet
754 * need to be presented in a reversed order with respect
755 * to the expected received packets.
757 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
758 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
759 len += sizeof(struct ipv4_hdr);
761 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
762 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
763 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
764 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
765 case RTE_ETH_FLOW_FRAG_IPV6:
766 ip6 = (struct ipv6_hdr *)raw_pkt;
768 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
770 rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
771 (fdir_input->flow.ipv6_flow.tc <<
772 I40E_FDIR_IPv6_TC_OFFSET));
774 rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
775 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
776 fdir_input->flow.ipv6_flow.proto :
777 next_proto[fdir_input->flow_type];
778 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
779 fdir_input->flow.ipv6_flow.hop_limits :
780 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
782 * The source and destination fields in the transmitted packet
783 * need to be presented in a reversed order with respect
784 * to the expected received packets.
786 rte_memcpy(&(ip6->src_addr),
787 &(fdir_input->flow.ipv6_flow.dst_ip),
789 rte_memcpy(&(ip6->dst_addr),
790 &(fdir_input->flow.ipv6_flow.src_ip),
792 len += sizeof(struct ipv6_hdr);
795 PMD_DRV_LOG(ERR, "unknown flow type %u.",
796 fdir_input->flow_type);
804 * i40e_fdir_construct_pkt - construct packet based on fields in input
805 * @pf: board private structure
806 * @fdir_input: input set of the flow director entry
807 * @raw_pkt: a packet to be constructed
810 i40e_fdir_construct_pkt(struct i40e_pf *pf,
811 const struct rte_eth_fdir_input *fdir_input,
812 unsigned char *raw_pkt)
814 unsigned char *payload, *ptr;
817 struct sctp_hdr *sctp;
818 uint8_t size, dst = 0;
819 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
822 /* fill the ethernet and IP head */
823 len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
824 !!fdir_input->flow_ext.vlan_tci);
828 /* fill the L4 head */
829 switch (fdir_input->flow_type) {
830 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
831 udp = (struct udp_hdr *)(raw_pkt + len);
832 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
834 * The source and destination fields in the transmitted packet
835 * need to be presented in a reversed order with respect
836 * to the expected received packets.
838 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
839 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
840 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
843 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
844 tcp = (struct tcp_hdr *)(raw_pkt + len);
845 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
847 * The source and destination fields in the transmitted packet
848 * need to be presented in a reversed order with respect
849 * to the expected received packets.
851 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
852 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
853 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
856 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
857 sctp = (struct sctp_hdr *)(raw_pkt + len);
858 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
860 * The source and destination fields in the transmitted packet
861 * need to be presented in a reversed order with respect
862 * to the expected received packets.
864 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
865 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
866 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
869 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
870 case RTE_ETH_FLOW_FRAG_IPV4:
871 payload = raw_pkt + len;
872 set_idx = I40E_FLXPLD_L3_IDX;
875 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
876 udp = (struct udp_hdr *)(raw_pkt + len);
877 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
879 * The source and destination fields in the transmitted packet
880 * need to be presented in a reversed order with respect
881 * to the expected received packets.
883 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
884 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
885 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
888 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
889 tcp = (struct tcp_hdr *)(raw_pkt + len);
890 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
892 * The source and destination fields in the transmitted packet
893 * need to be presented in a reversed order with respect
894 * to the expected received packets.
896 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
897 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
898 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
901 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
902 sctp = (struct sctp_hdr *)(raw_pkt + len);
903 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
905 * The source and destination fields in the transmitted packet
906 * need to be presented in a reversed order with respect
907 * to the expected received packets.
909 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
910 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
911 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
914 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
915 case RTE_ETH_FLOW_FRAG_IPV6:
916 payload = raw_pkt + len;
917 set_idx = I40E_FLXPLD_L3_IDX;
919 case RTE_ETH_FLOW_L2_PAYLOAD:
920 payload = raw_pkt + len;
922 * ARP packet is a special case on which the payload
923 * starts after the whole ARP header
925 if (fdir_input->flow.l2_flow.ether_type ==
926 rte_cpu_to_be_16(ETHER_TYPE_ARP))
927 payload += sizeof(struct arp_hdr);
928 set_idx = I40E_FLXPLD_L2_IDX;
931 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
935 /* fill the flexbytes to payload */
936 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
937 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
938 size = pf->fdir.flex_set[pit_idx].size;
941 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
943 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
944 (void)rte_memcpy(ptr,
945 &fdir_input->flow_ext.flexbytes[dst],
946 size * sizeof(uint16_t));
952 /* Construct the tx flags */
953 static inline uint64_t
954 i40e_build_ctob(uint32_t td_cmd,
959 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
960 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
961 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
962 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
963 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
967 * check the programming status descriptor in rx queue.
968 * done after Programming Flow Director is programmed on
972 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
974 volatile union i40e_rx_desc *rxdp;
981 rxdp = &rxq->rx_ring[rxq->rx_tail];
982 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
983 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
984 >> I40E_RXD_QW1_STATUS_SHIFT;
986 if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
987 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
988 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
989 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
991 if (len == I40E_RX_PROG_STATUS_DESC_LENGTH &&
992 id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
994 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
995 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
997 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
998 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
999 " (FD_ID %u): programming status"
1001 rxdp->wb.qword0.hi_dword.fd_id);
1003 } else if (error == (0x1 <<
1004 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
1005 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
1006 " (FD_ID %u): programming status"
1008 rxdp->wb.qword0.hi_dword.fd_id);
1011 PMD_DRV_LOG(ERR, "invalid programming status"
1012 " reported, error = %u.", error);
1014 PMD_DRV_LOG(ERR, "unknown programming status"
1015 " reported, len = %d, id = %u.", len, id);
1016 rxdp->wb.qword1.status_error_len = 0;
1018 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1025 * i40e_add_del_fdir_filter - add or remove a flow director filter.
1026 * @pf: board private structure
1027 * @filter: fdir filter entry
1028 * @add: 0 - delete, 1 - add
1031 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1032 const struct rte_eth_fdir_filter *filter,
1035 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1037 unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1038 enum i40e_filter_pctype pctype;
1041 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1042 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1043 " check the mode in fdir_conf.");
1047 if (!I40E_VALID_FLOW(filter->input.flow_type)) {
1048 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1051 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1052 PMD_DRV_LOG(ERR, "Invalid queue ID");
1055 if (filter->input.flow_ext.is_vf &&
1056 filter->input.flow_ext.dst_id >= pf->vf_num) {
1057 PMD_DRV_LOG(ERR, "Invalid VF ID");
1061 memset(pkt, 0, I40E_FDIR_PKT_LEN);
1063 ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1065 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1069 if (hw->mac.type == I40E_MAC_X722) {
1070 /* get translated pctype value in fd pctype register */
1071 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1072 hw, I40E_GLQF_FD_PCTYPES(
1073 (int)i40e_flowtype_to_pctype(
1074 filter->input.flow_type)));
1076 pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1078 ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1080 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1088 * i40e_fdir_filter_programming - Program a flow director filter rule.
1089 * Is done by Flow Director Programming Descriptor followed by packet
1090 * structure that contains the filter fields need to match.
1091 * @pf: board private structure
1093 * @filter: fdir filter entry
1094 * @add: 0 - delete, 1 - add
1097 i40e_fdir_filter_programming(struct i40e_pf *pf,
1098 enum i40e_filter_pctype pctype,
1099 const struct rte_eth_fdir_filter *filter,
1102 struct i40e_tx_queue *txq = pf->fdir.txq;
1103 struct i40e_rx_queue *rxq = pf->fdir.rxq;
1104 const struct rte_eth_fdir_action *fdir_action = &filter->action;
1105 volatile struct i40e_tx_desc *txdp;
1106 volatile struct i40e_filter_program_desc *fdirdp;
1111 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1112 fdirdp = (volatile struct i40e_filter_program_desc *)
1113 (&(txq->tx_ring[txq->tx_tail]));
1115 fdirdp->qindex_flex_ptype_vsi =
1116 rte_cpu_to_le_32((fdir_action->rx_queue <<
1117 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1118 I40E_TXD_FLTR_QW0_QINDEX_MASK);
1120 fdirdp->qindex_flex_ptype_vsi |=
1121 rte_cpu_to_le_32((fdir_action->flex_off <<
1122 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1123 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1125 fdirdp->qindex_flex_ptype_vsi |=
1126 rte_cpu_to_le_32((pctype <<
1127 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1128 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1130 if (filter->input.flow_ext.is_vf)
1131 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1133 /* Use LAN VSI Id by default */
1134 vsi_id = pf->main_vsi->vsi_id;
1135 fdirdp->qindex_flex_ptype_vsi |=
1136 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1137 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1138 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1140 fdirdp->dtype_cmd_cntindex =
1141 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1144 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1145 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1146 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1148 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1149 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1150 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1152 if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1153 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1154 else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1155 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1156 else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1157 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1159 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1160 " unsupported fdir behavior.");
1164 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1165 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1166 I40E_TXD_FLTR_QW1_DEST_MASK);
1168 fdirdp->dtype_cmd_cntindex |=
1169 rte_cpu_to_le_32((fdir_action->report_status<<
1170 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1171 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1173 fdirdp->dtype_cmd_cntindex |=
1174 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1175 fdirdp->dtype_cmd_cntindex |=
1177 ((uint32_t)pf->fdir.match_counter_index <<
1178 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1179 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1181 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1183 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1184 txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1185 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1186 td_cmd = I40E_TX_DESC_CMD_EOP |
1187 I40E_TX_DESC_CMD_RS |
1188 I40E_TX_DESC_CMD_DUMMY;
1190 txdp->cmd_type_offset_bsz =
1191 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1193 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1194 if (txq->tx_tail >= txq->nb_tx_desc)
1196 /* Update the tx tail register */
1198 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1200 for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
1201 rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
1202 if ((txdp->cmd_type_offset_bsz &
1203 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1204 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1207 if (i >= I40E_FDIR_WAIT_COUNT) {
1208 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1209 " time out to get DD on tx queue.");
1212 /* totally delay 10 ms to check programming status*/
1213 rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
1214 if (i40e_check_fdir_programming_status(rxq) < 0) {
1215 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1216 " programming status reported.");
1224 * i40e_fdir_flush - clear all filters of Flow Director table
1225 * @pf: board private structure
1228 i40e_fdir_flush(struct rte_eth_dev *dev)
1230 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1231 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1233 uint16_t guarant_cnt, best_cnt;
1236 I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1237 I40E_WRITE_FLUSH(hw);
1239 for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1240 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1241 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1242 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1245 if (i >= I40E_FDIR_FLUSH_RETRY) {
1246 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1249 guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1250 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1251 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1252 best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1253 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1254 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1255 if (guarant_cnt != 0 || best_cnt != 0) {
1256 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1259 PMD_DRV_LOG(INFO, "FD table Flush success.");
1264 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1265 struct rte_eth_flex_payload_cfg *flex_set,
1268 struct i40e_fdir_flex_pit *flex_pit;
1269 struct rte_eth_flex_payload_cfg *ptr = flex_set;
1270 uint16_t src, dst, size, j, k;
1271 uint8_t i, layer_idx;
1273 for (layer_idx = I40E_FLXPLD_L2_IDX;
1274 layer_idx <= I40E_FLXPLD_L4_IDX;
1276 if (layer_idx == I40E_FLXPLD_L2_IDX)
1277 ptr->type = RTE_ETH_L2_PAYLOAD;
1278 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1279 ptr->type = RTE_ETH_L3_PAYLOAD;
1280 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1281 ptr->type = RTE_ETH_L4_PAYLOAD;
1283 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1284 flex_pit = &pf->fdir.flex_set[layer_idx *
1285 I40E_MAX_FLXPLD_FIED + i];
1286 if (flex_pit->size == 0)
1288 src = flex_pit->src_offset * sizeof(uint16_t);
1289 dst = flex_pit->dst_offset * sizeof(uint16_t);
1290 size = flex_pit->size * sizeof(uint16_t);
1291 for (j = src, k = dst; j < src + size; j++, k++)
1292 ptr->src_offset[k] = j;
1300 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1301 struct rte_eth_fdir_flex_mask *flex_mask,
1304 struct i40e_fdir_flex_mask *mask;
1305 struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1306 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1309 uint16_t off_bytes, mask_tmp;
1311 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1312 i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1314 mask = &pf->fdir.flex_mask[i];
1315 if (hw->mac.type == I40E_MAC_X722) {
1316 if (!I40E_VALID_PCTYPE_X722((enum i40e_filter_pctype)i))
1319 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1322 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1323 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1324 if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1325 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1326 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1328 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1329 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1332 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1333 off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1334 mask_tmp = ~mask->bitmask[j].mask;
1335 ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1336 ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1338 ptr->flow_type = flow_type;
1345 * i40e_fdir_info_get - get information of Flow Director
1346 * @pf: ethernet device to get info from
1347 * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1348 * the flow director information.
1351 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1353 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1354 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1355 uint16_t num_flex_set = 0;
1356 uint16_t num_flex_mask = 0;
1358 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1359 fdir->mode = RTE_FDIR_MODE_PERFECT;
1361 fdir->mode = RTE_FDIR_MODE_NONE;
1364 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1366 (uint32_t)hw->func_caps.fd_filters_best_effort;
1367 fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1368 fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1369 fdir->flex_payload_unit = sizeof(uint16_t);
1370 fdir->flex_bitmask_unit = sizeof(uint16_t);
1371 fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1372 fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1373 fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1375 i40e_fdir_info_get_flex_set(pf,
1376 fdir->flex_conf.flex_set,
1378 i40e_fdir_info_get_flex_mask(pf,
1379 fdir->flex_conf.flex_mask,
1382 fdir->flex_conf.nb_payloads = num_flex_set;
1383 fdir->flex_conf.nb_flexmasks = num_flex_mask;
1387 * i40e_fdir_stat_get - get statistics of Flow Director
1388 * @pf: ethernet device to get info from
1389 * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1390 * the flow director statistics.
1393 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1395 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1396 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1399 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1401 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1402 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1404 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1405 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1409 i40e_fdir_filter_set(struct rte_eth_dev *dev,
1410 struct rte_eth_fdir_filter_info *info)
1412 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1416 PMD_DRV_LOG(ERR, "Invalid pointer");
1420 switch (info->info_type) {
1421 case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
1422 ret = i40e_fdir_filter_inset_select(pf,
1423 &(info->info.input_set_conf));
1426 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
1435 * i40e_fdir_ctrl_func - deal with all operations on flow director.
1436 * @pf: board private structure
1437 * @filter_op:operation will be taken.
1438 * @arg: a pointer to specific structure corresponding to the filter_op
1441 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1442 enum rte_filter_op filter_op,
1445 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1448 if ((pf->flags & I40E_FLAG_FDIR) == 0)
1451 if (filter_op == RTE_ETH_FILTER_NOP)
1454 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1457 switch (filter_op) {
1458 case RTE_ETH_FILTER_ADD:
1459 ret = i40e_add_del_fdir_filter(dev,
1460 (struct rte_eth_fdir_filter *)arg,
1463 case RTE_ETH_FILTER_DELETE:
1464 ret = i40e_add_del_fdir_filter(dev,
1465 (struct rte_eth_fdir_filter *)arg,
1468 case RTE_ETH_FILTER_FLUSH:
1469 ret = i40e_fdir_flush(dev);
1471 case RTE_ETH_FILTER_INFO:
1472 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1474 case RTE_ETH_FILTER_SET:
1475 ret = i40e_fdir_filter_set(dev,
1476 (struct rte_eth_fdir_filter_info *)arg);
1478 case RTE_ETH_FILTER_STATS:
1479 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1482 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);