4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
54 #include "i40e_logs.h"
55 #include "base/i40e_prototype.h"
56 #include "base/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
60 #define DEFAULT_TX_RS_THRESH 32
61 #define DEFAULT_TX_FREE_THRESH 32
62 #define I40E_MAX_PKT_TYPE 256
64 #define I40E_TX_MAX_BURST 32
66 #define I40E_DMA_MEM_ALIGN 4096
68 /* Base address of the HW descriptor ring should be 128B aligned. */
69 #define I40E_RING_BASE_ALIGN 128
71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
72 ETH_TXQ_FLAGS_NOOFFLOADS)
74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
76 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
80 PKT_TX_OUTER_IP_CKSUM)
82 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
83 struct rte_mbuf **tx_pkts,
87 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
89 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
90 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
91 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
93 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
94 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
95 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
99 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
100 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
101 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
102 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
103 mb->vlan_tci_outer = mb->vlan_tci;
104 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
105 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
106 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
107 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
109 mb->vlan_tci_outer = 0;
112 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
113 mb->vlan_tci, mb->vlan_tci_outer);
116 /* Translate the rx descriptor status to pkt flags */
117 static inline uint64_t
118 i40e_rxd_status_to_pkt_flags(uint64_t qword)
122 /* Check if RSS_HASH */
123 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
124 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
125 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
127 /* Check if FDIR Match */
128 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
134 static inline uint64_t
135 i40e_rxd_error_to_pkt_flags(uint64_t qword)
138 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
140 #define I40E_RX_ERR_BITS 0x3f
141 if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
142 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
146 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
147 flags |= PKT_RX_IP_CKSUM_BAD;
149 flags |= PKT_RX_IP_CKSUM_GOOD;
151 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
152 flags |= PKT_RX_L4_CKSUM_BAD;
154 flags |= PKT_RX_L4_CKSUM_GOOD;
156 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
157 flags |= PKT_RX_EIP_CKSUM_BAD;
162 /* Function to check and set the ieee1588 timesync index and get the
165 #ifdef RTE_LIBRTE_IEEE1588
166 static inline uint64_t
167 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
169 uint64_t pkt_flags = 0;
170 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
171 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
172 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
174 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
175 == RTE_PTYPE_L2_ETHER_TIMESYNC)
176 pkt_flags = PKT_RX_IEEE1588_PTP;
178 pkt_flags |= PKT_RX_IEEE1588_TMST;
179 mb->timesync = tsyn & 0x03;
186 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
187 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
188 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
189 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
190 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
192 static inline uint64_t
193 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
196 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
197 uint16_t flexbh, flexbl;
199 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
200 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
201 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
202 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
203 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
204 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
207 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
209 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
210 flags |= PKT_RX_FDIR_ID;
211 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
213 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
214 flags |= PKT_RX_FDIR_FLX;
216 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
218 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
219 flags |= PKT_RX_FDIR_FLX;
223 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
224 flags |= PKT_RX_FDIR_ID;
230 i40e_parse_tunneling_params(uint64_t ol_flags,
231 union i40e_tx_offload tx_offload,
232 uint32_t *cd_tunneling)
234 /* EIPT: External (outer) IP header type */
235 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
236 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
237 else if (ol_flags & PKT_TX_OUTER_IPV4)
238 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
239 else if (ol_flags & PKT_TX_OUTER_IPV6)
240 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
242 /* EIPLEN: External (outer) IP header length, in DWords */
243 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
244 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
246 /* L4TUNT: L4 Tunneling Type */
247 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
248 case PKT_TX_TUNNEL_IPIP:
249 /* for non UDP / GRE tunneling, set to 00b */
251 case PKT_TX_TUNNEL_VXLAN:
252 case PKT_TX_TUNNEL_GENEVE:
253 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
255 case PKT_TX_TUNNEL_GRE:
256 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
259 PMD_TX_LOG(ERR, "Tunnel type not supported\n");
263 /* L4TUNLEN: L4 Tunneling Length, in Words
265 * We depend on app to set rte_mbuf.l2_len correctly.
266 * For IP in GRE it should be set to the length of the GRE
268 * for MAC in GRE or MAC in UDP it should be set to the length
269 * of the GRE or UDP headers plus the inner MAC up to including
270 * its last Ethertype.
272 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
273 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
277 i40e_txd_enable_checksum(uint64_t ol_flags,
280 union i40e_tx_offload tx_offload)
283 if (ol_flags & PKT_TX_TUNNEL_MASK)
284 *td_offset |= (tx_offload.outer_l2_len >> 1)
285 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
287 *td_offset |= (tx_offload.l2_len >> 1)
288 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
290 /* Enable L3 checksum offloads */
291 if (ol_flags & PKT_TX_IP_CKSUM) {
292 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
293 *td_offset |= (tx_offload.l3_len >> 2)
294 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
295 } else if (ol_flags & PKT_TX_IPV4) {
296 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
297 *td_offset |= (tx_offload.l3_len >> 2)
298 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
299 } else if (ol_flags & PKT_TX_IPV6) {
300 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
301 *td_offset |= (tx_offload.l3_len >> 2)
302 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
305 if (ol_flags & PKT_TX_TCP_SEG) {
306 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
307 *td_offset |= (tx_offload.l4_len >> 2)
308 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
312 /* Enable L4 checksum offloads */
313 switch (ol_flags & PKT_TX_L4_MASK) {
314 case PKT_TX_TCP_CKSUM:
315 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
316 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
317 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
319 case PKT_TX_SCTP_CKSUM:
320 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
321 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
322 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
324 case PKT_TX_UDP_CKSUM:
325 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
326 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
327 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
334 /* Construct the tx flags */
335 static inline uint64_t
336 i40e_build_ctob(uint32_t td_cmd,
341 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
342 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
343 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
344 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
345 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
349 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
351 struct i40e_tx_entry *sw_ring = txq->sw_ring;
352 volatile struct i40e_tx_desc *txd = txq->tx_ring;
353 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
354 uint16_t nb_tx_desc = txq->nb_tx_desc;
355 uint16_t desc_to_clean_to;
356 uint16_t nb_tx_to_clean;
358 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
359 if (desc_to_clean_to >= nb_tx_desc)
360 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
362 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
363 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
364 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
365 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
366 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
367 "(port=%d queue=%d)", desc_to_clean_to,
368 txq->port_id, txq->queue_id);
372 if (last_desc_cleaned > desc_to_clean_to)
373 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
376 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
379 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
381 txq->last_desc_cleaned = desc_to_clean_to;
382 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
388 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
389 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
391 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
396 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
397 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
398 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
399 "rxq->rx_free_thresh=%d, "
400 "RTE_PMD_I40E_RX_MAX_BURST=%d",
401 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
403 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
404 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
405 "rxq->rx_free_thresh=%d, "
406 "rxq->nb_rx_desc=%d",
407 rxq->rx_free_thresh, rxq->nb_rx_desc);
409 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
410 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
411 "rxq->nb_rx_desc=%d, "
412 "rxq->rx_free_thresh=%d",
413 rxq->nb_rx_desc, rxq->rx_free_thresh);
415 } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
416 RTE_PMD_I40E_RX_MAX_BURST))) {
417 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
418 "rxq->nb_rx_desc=%d, "
419 "I40E_MAX_RING_DESC=%d, "
420 "RTE_PMD_I40E_RX_MAX_BURST=%d",
421 rxq->nb_rx_desc, I40E_MAX_RING_DESC,
422 RTE_PMD_I40E_RX_MAX_BURST);
432 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
433 #define I40E_LOOK_AHEAD 8
434 #if (I40E_LOOK_AHEAD != 8)
435 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
438 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
440 volatile union i40e_rx_desc *rxdp;
441 struct i40e_rx_entry *rxep;
446 int32_t s[I40E_LOOK_AHEAD], nb_dd;
447 int32_t i, j, nb_rx = 0;
450 rxdp = &rxq->rx_ring[rxq->rx_tail];
451 rxep = &rxq->sw_ring[rxq->rx_tail];
453 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
454 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
455 I40E_RXD_QW1_STATUS_SHIFT;
457 /* Make sure there is at least 1 packet to receive */
458 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
462 * Scan LOOK_AHEAD descriptors at a time to determine which
463 * descriptors reference packets that are ready to be received.
465 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
466 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
467 /* Read desc statuses backwards to avoid race condition */
468 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
469 qword1 = rte_le_to_cpu_64(\
470 rxdp[j].wb.qword1.status_error_len);
471 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
472 I40E_RXD_QW1_STATUS_SHIFT;
477 /* Compute how many status bits were set */
478 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
479 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
483 /* Translate descriptor info to mbuf parameters */
484 for (j = 0; j < nb_dd; j++) {
486 qword1 = rte_le_to_cpu_64(\
487 rxdp[j].wb.qword1.status_error_len);
488 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
489 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
490 mb->data_len = pkt_len;
491 mb->pkt_len = pkt_len;
493 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
494 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
495 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
497 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
498 I40E_RXD_QW1_PTYPE_MASK) >>
499 I40E_RXD_QW1_PTYPE_SHIFT));
500 if (pkt_flags & PKT_RX_RSS_HASH)
501 mb->hash.rss = rte_le_to_cpu_32(\
502 rxdp[j].wb.qword0.hi_dword.rss);
503 if (pkt_flags & PKT_RX_FDIR)
504 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
506 #ifdef RTE_LIBRTE_IEEE1588
507 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
509 mb->ol_flags |= pkt_flags;
513 for (j = 0; j < I40E_LOOK_AHEAD; j++)
514 rxq->rx_stage[i + j] = rxep[j].mbuf;
516 if (nb_dd != I40E_LOOK_AHEAD)
520 /* Clear software ring entries */
521 for (i = 0; i < nb_rx; i++)
522 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
527 static inline uint16_t
528 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
529 struct rte_mbuf **rx_pkts,
533 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
535 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
537 for (i = 0; i < nb_pkts; i++)
538 rx_pkts[i] = stage[i];
540 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
541 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
547 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
549 volatile union i40e_rx_desc *rxdp;
550 struct i40e_rx_entry *rxep;
552 uint16_t alloc_idx, i;
556 /* Allocate buffers in bulk */
557 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
558 (rxq->rx_free_thresh - 1));
559 rxep = &(rxq->sw_ring[alloc_idx]);
560 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
561 rxq->rx_free_thresh);
562 if (unlikely(diag != 0)) {
563 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
567 rxdp = &rxq->rx_ring[alloc_idx];
568 for (i = 0; i < rxq->rx_free_thresh; i++) {
569 if (likely(i < (rxq->rx_free_thresh - 1)))
570 /* Prefetch next mbuf */
571 rte_prefetch0(rxep[i + 1].mbuf);
574 rte_mbuf_refcnt_set(mb, 1);
576 mb->data_off = RTE_PKTMBUF_HEADROOM;
578 mb->port = rxq->port_id;
579 dma_addr = rte_cpu_to_le_64(\
580 rte_mbuf_data_dma_addr_default(mb));
581 rxdp[i].read.hdr_addr = 0;
582 rxdp[i].read.pkt_addr = dma_addr;
585 /* Update rx tail regsiter */
587 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
589 rxq->rx_free_trigger =
590 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
591 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
592 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
597 static inline uint16_t
598 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
600 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
601 struct rte_eth_dev *dev;
607 if (rxq->rx_nb_avail)
608 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
610 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
611 rxq->rx_next_avail = 0;
612 rxq->rx_nb_avail = nb_rx;
613 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
615 if (rxq->rx_tail > rxq->rx_free_trigger) {
616 if (i40e_rx_alloc_bufs(rxq) != 0) {
619 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
620 dev->data->rx_mbuf_alloc_failed +=
623 rxq->rx_nb_avail = 0;
624 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
625 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
626 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
632 if (rxq->rx_tail >= rxq->nb_rx_desc)
635 if (rxq->rx_nb_avail)
636 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
642 i40e_recv_pkts_bulk_alloc(void *rx_queue,
643 struct rte_mbuf **rx_pkts,
646 uint16_t nb_rx = 0, n, count;
648 if (unlikely(nb_pkts == 0))
651 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
652 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
655 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
656 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
657 nb_rx = (uint16_t)(nb_rx + count);
658 nb_pkts = (uint16_t)(nb_pkts - count);
667 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
668 struct rte_mbuf __rte_unused **rx_pkts,
669 uint16_t __rte_unused nb_pkts)
673 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
676 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
678 struct i40e_rx_queue *rxq;
679 volatile union i40e_rx_desc *rx_ring;
680 volatile union i40e_rx_desc *rxdp;
681 union i40e_rx_desc rxd;
682 struct i40e_rx_entry *sw_ring;
683 struct i40e_rx_entry *rxe;
684 struct rte_eth_dev *dev;
685 struct rte_mbuf *rxm;
686 struct rte_mbuf *nmb;
690 uint16_t rx_packet_len;
691 uint16_t rx_id, nb_hold;
698 rx_id = rxq->rx_tail;
699 rx_ring = rxq->rx_ring;
700 sw_ring = rxq->sw_ring;
702 while (nb_rx < nb_pkts) {
703 rxdp = &rx_ring[rx_id];
704 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
705 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
706 >> I40E_RXD_QW1_STATUS_SHIFT;
708 /* Check the DD bit first */
709 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
712 nmb = rte_mbuf_raw_alloc(rxq->mp);
713 if (unlikely(!nmb)) {
714 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
715 dev->data->rx_mbuf_alloc_failed++;
721 rxe = &sw_ring[rx_id];
723 if (unlikely(rx_id == rxq->nb_rx_desc))
726 /* Prefetch next mbuf */
727 rte_prefetch0(sw_ring[rx_id].mbuf);
730 * When next RX descriptor is on a cache line boundary,
731 * prefetch the next 4 RX descriptors and next 8 pointers
734 if ((rx_id & 0x3) == 0) {
735 rte_prefetch0(&rx_ring[rx_id]);
736 rte_prefetch0(&sw_ring[rx_id]);
741 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
742 rxdp->read.hdr_addr = 0;
743 rxdp->read.pkt_addr = dma_addr;
745 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
746 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
748 rxm->data_off = RTE_PKTMBUF_HEADROOM;
749 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
752 rxm->pkt_len = rx_packet_len;
753 rxm->data_len = rx_packet_len;
754 rxm->port = rxq->port_id;
756 i40e_rxd_to_vlan_tci(rxm, &rxd);
757 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
758 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
760 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
761 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
762 if (pkt_flags & PKT_RX_RSS_HASH)
764 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
765 if (pkt_flags & PKT_RX_FDIR)
766 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
768 #ifdef RTE_LIBRTE_IEEE1588
769 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
771 rxm->ol_flags |= pkt_flags;
773 rx_pkts[nb_rx++] = rxm;
775 rxq->rx_tail = rx_id;
778 * If the number of free RX descriptors is greater than the RX free
779 * threshold of the queue, advance the receive tail register of queue.
780 * Update that register with the value of the last processed RX
781 * descriptor minus 1.
783 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
784 if (nb_hold > rxq->rx_free_thresh) {
785 rx_id = (uint16_t) ((rx_id == 0) ?
786 (rxq->nb_rx_desc - 1) : (rx_id - 1));
787 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
790 rxq->nb_rx_hold = nb_hold;
796 i40e_recv_scattered_pkts(void *rx_queue,
797 struct rte_mbuf **rx_pkts,
800 struct i40e_rx_queue *rxq = rx_queue;
801 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
802 volatile union i40e_rx_desc *rxdp;
803 union i40e_rx_desc rxd;
804 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
805 struct i40e_rx_entry *rxe;
806 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
807 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
808 struct rte_mbuf *nmb, *rxm;
809 uint16_t rx_id = rxq->rx_tail;
810 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
811 struct rte_eth_dev *dev;
817 while (nb_rx < nb_pkts) {
818 rxdp = &rx_ring[rx_id];
819 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
820 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
821 I40E_RXD_QW1_STATUS_SHIFT;
823 /* Check the DD bit */
824 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
827 nmb = rte_mbuf_raw_alloc(rxq->mp);
828 if (unlikely(!nmb)) {
829 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
830 dev->data->rx_mbuf_alloc_failed++;
836 rxe = &sw_ring[rx_id];
838 if (rx_id == rxq->nb_rx_desc)
841 /* Prefetch next mbuf */
842 rte_prefetch0(sw_ring[rx_id].mbuf);
845 * When next RX descriptor is on a cache line boundary,
846 * prefetch the next 4 RX descriptors and next 8 pointers
849 if ((rx_id & 0x3) == 0) {
850 rte_prefetch0(&rx_ring[rx_id]);
851 rte_prefetch0(&sw_ring[rx_id]);
857 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
859 /* Set data buffer address and data length of the mbuf */
860 rxdp->read.hdr_addr = 0;
861 rxdp->read.pkt_addr = dma_addr;
862 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
863 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
864 rxm->data_len = rx_packet_len;
865 rxm->data_off = RTE_PKTMBUF_HEADROOM;
868 * If this is the first buffer of the received packet, set the
869 * pointer to the first mbuf of the packet and initialize its
870 * context. Otherwise, update the total length and the number
871 * of segments of the current scattered packet, and update the
872 * pointer to the last mbuf of the current packet.
876 first_seg->nb_segs = 1;
877 first_seg->pkt_len = rx_packet_len;
880 (uint16_t)(first_seg->pkt_len +
882 first_seg->nb_segs++;
883 last_seg->next = rxm;
887 * If this is not the last buffer of the received packet,
888 * update the pointer to the last mbuf of the current scattered
889 * packet and continue to parse the RX ring.
891 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
897 * This is the last buffer of the received packet. If the CRC
898 * is not stripped by the hardware:
899 * - Subtract the CRC length from the total packet length.
900 * - If the last buffer only contains the whole CRC or a part
901 * of it, free the mbuf associated to the last buffer. If part
902 * of the CRC is also contained in the previous mbuf, subtract
903 * the length of that CRC part from the data length of the
907 if (unlikely(rxq->crc_len > 0)) {
908 first_seg->pkt_len -= ETHER_CRC_LEN;
909 if (rx_packet_len <= ETHER_CRC_LEN) {
910 rte_pktmbuf_free_seg(rxm);
911 first_seg->nb_segs--;
913 (uint16_t)(last_seg->data_len -
914 (ETHER_CRC_LEN - rx_packet_len));
915 last_seg->next = NULL;
917 rxm->data_len = (uint16_t)(rx_packet_len -
921 first_seg->port = rxq->port_id;
922 first_seg->ol_flags = 0;
923 i40e_rxd_to_vlan_tci(first_seg, &rxd);
924 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
925 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
926 first_seg->packet_type =
927 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
928 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
929 if (pkt_flags & PKT_RX_RSS_HASH)
930 first_seg->hash.rss =
931 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
932 if (pkt_flags & PKT_RX_FDIR)
933 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
935 #ifdef RTE_LIBRTE_IEEE1588
936 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
938 first_seg->ol_flags |= pkt_flags;
940 /* Prefetch data of first segment, if configured to do so. */
941 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
942 first_seg->data_off));
943 rx_pkts[nb_rx++] = first_seg;
947 /* Record index of the next RX descriptor to probe. */
948 rxq->rx_tail = rx_id;
949 rxq->pkt_first_seg = first_seg;
950 rxq->pkt_last_seg = last_seg;
953 * If the number of free RX descriptors is greater than the RX free
954 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
955 * register. Update the RDT with the value of the last processed RX
956 * descriptor minus 1, to guarantee that the RDT register is never
957 * equal to the RDH register, which creates a "full" ring situtation
958 * from the hardware point of view.
960 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
961 if (nb_hold > rxq->rx_free_thresh) {
962 rx_id = (uint16_t)(rx_id == 0 ?
963 (rxq->nb_rx_desc - 1) : (rx_id - 1));
964 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
967 rxq->nb_rx_hold = nb_hold;
972 /* Check if the context descriptor is needed for TX offloading */
973 static inline uint16_t
974 i40e_calc_context_desc(uint64_t flags)
976 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
981 #ifdef RTE_LIBRTE_IEEE1588
982 mask |= PKT_TX_IEEE1588_TMST;
985 return (flags & mask) ? 1 : 0;
988 /* set i40e TSO context descriptor */
989 static inline uint64_t
990 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
992 uint64_t ctx_desc = 0;
993 uint32_t cd_cmd, hdr_len, cd_tso_len;
995 if (!tx_offload.l4_len) {
996 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1001 * in case of non tunneling packet, the outer_l2_len and
1002 * outer_l3_len must be 0.
1004 hdr_len = tx_offload.outer_l2_len +
1005 tx_offload.outer_l3_len +
1010 cd_cmd = I40E_TX_CTX_DESC_TSO;
1011 cd_tso_len = mbuf->pkt_len - hdr_len;
1012 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1013 ((uint64_t)cd_tso_len <<
1014 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1015 ((uint64_t)mbuf->tso_segsz <<
1016 I40E_TXD_CTX_QW1_MSS_SHIFT);
1022 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1024 struct i40e_tx_queue *txq;
1025 struct i40e_tx_entry *sw_ring;
1026 struct i40e_tx_entry *txe, *txn;
1027 volatile struct i40e_tx_desc *txd;
1028 volatile struct i40e_tx_desc *txr;
1029 struct rte_mbuf *tx_pkt;
1030 struct rte_mbuf *m_seg;
1031 uint32_t cd_tunneling_params;
1043 uint64_t buf_dma_addr;
1044 union i40e_tx_offload tx_offload = {0};
1047 sw_ring = txq->sw_ring;
1049 tx_id = txq->tx_tail;
1050 txe = &sw_ring[tx_id];
1052 /* Check if the descriptor ring needs to be cleaned. */
1053 if (txq->nb_tx_free < txq->tx_free_thresh)
1054 i40e_xmit_cleanup(txq);
1056 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1062 tx_pkt = *tx_pkts++;
1063 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1065 ol_flags = tx_pkt->ol_flags;
1066 tx_offload.l2_len = tx_pkt->l2_len;
1067 tx_offload.l3_len = tx_pkt->l3_len;
1068 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1069 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1070 tx_offload.l4_len = tx_pkt->l4_len;
1071 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1073 /* Calculate the number of context descriptors needed. */
1074 nb_ctx = i40e_calc_context_desc(ol_flags);
1077 * The number of descriptors that must be allocated for
1078 * a packet equals to the number of the segments of that
1079 * packet plus 1 context descriptor if needed.
1081 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1082 tx_last = (uint16_t)(tx_id + nb_used - 1);
1085 if (tx_last >= txq->nb_tx_desc)
1086 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1088 if (nb_used > txq->nb_tx_free) {
1089 if (i40e_xmit_cleanup(txq) != 0) {
1094 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1095 while (nb_used > txq->nb_tx_free) {
1096 if (i40e_xmit_cleanup(txq) != 0) {
1105 /* Descriptor based VLAN insertion */
1106 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1107 tx_flags |= tx_pkt->vlan_tci <<
1108 I40E_TX_FLAG_L2TAG1_SHIFT;
1109 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1110 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1111 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1112 I40E_TX_FLAG_L2TAG1_SHIFT;
1115 /* Always enable CRC offload insertion */
1116 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1118 /* Fill in tunneling parameters if necessary */
1119 cd_tunneling_params = 0;
1120 if (ol_flags & PKT_TX_TUNNEL_MASK)
1121 i40e_parse_tunneling_params(ol_flags, tx_offload,
1122 &cd_tunneling_params);
1123 /* Enable checksum offloading */
1124 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1125 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1126 &td_offset, tx_offload);
1129 /* Setup TX context descriptor if required */
1130 volatile struct i40e_tx_context_desc *ctx_txd =
1131 (volatile struct i40e_tx_context_desc *)\
1133 uint16_t cd_l2tag2 = 0;
1134 uint64_t cd_type_cmd_tso_mss =
1135 I40E_TX_DESC_DTYPE_CONTEXT;
1137 txn = &sw_ring[txe->next_id];
1138 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1139 if (txe->mbuf != NULL) {
1140 rte_pktmbuf_free_seg(txe->mbuf);
1144 /* TSO enabled means no timestamp */
1145 if (ol_flags & PKT_TX_TCP_SEG)
1146 cd_type_cmd_tso_mss |=
1147 i40e_set_tso_ctx(tx_pkt, tx_offload);
1149 #ifdef RTE_LIBRTE_IEEE1588
1150 if (ol_flags & PKT_TX_IEEE1588_TMST)
1151 cd_type_cmd_tso_mss |=
1152 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1153 I40E_TXD_CTX_QW1_CMD_SHIFT);
1157 ctx_txd->tunneling_params =
1158 rte_cpu_to_le_32(cd_tunneling_params);
1159 if (ol_flags & PKT_TX_QINQ_PKT) {
1160 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1161 cd_type_cmd_tso_mss |=
1162 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1163 I40E_TXD_CTX_QW1_CMD_SHIFT);
1165 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1166 ctx_txd->type_cmd_tso_mss =
1167 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1169 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1170 "tunneling_params: %#x;\n"
1173 "type_cmd_tso_mss: %#"PRIx64";\n",
1175 ctx_txd->tunneling_params,
1178 ctx_txd->type_cmd_tso_mss);
1180 txe->last_id = tx_last;
1181 tx_id = txe->next_id;
1188 txn = &sw_ring[txe->next_id];
1191 rte_pktmbuf_free_seg(txe->mbuf);
1194 /* Setup TX Descriptor */
1195 slen = m_seg->data_len;
1196 buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1198 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1199 "buf_dma_addr: %#"PRIx64";\n"
1204 tx_pkt, tx_id, buf_dma_addr,
1205 td_cmd, td_offset, slen, td_tag);
1207 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1208 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1209 td_offset, slen, td_tag);
1210 txe->last_id = tx_last;
1211 tx_id = txe->next_id;
1213 m_seg = m_seg->next;
1214 } while (m_seg != NULL);
1216 /* The last packet data descriptor needs End Of Packet (EOP) */
1217 td_cmd |= I40E_TX_DESC_CMD_EOP;
1218 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1219 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1221 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1222 PMD_TX_FREE_LOG(DEBUG,
1223 "Setting RS bit on TXD id="
1224 "%4u (port=%d queue=%d)",
1225 tx_last, txq->port_id, txq->queue_id);
1227 td_cmd |= I40E_TX_DESC_CMD_RS;
1229 /* Update txq RS bit counters */
1230 txq->nb_tx_used = 0;
1233 txd->cmd_type_offset_bsz |=
1234 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1235 I40E_TXD_QW1_CMD_SHIFT);
1241 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1242 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1243 (unsigned) tx_id, (unsigned) nb_tx);
1245 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1246 txq->tx_tail = tx_id;
1251 static inline int __attribute__((always_inline))
1252 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1254 struct i40e_tx_entry *txep;
1257 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1258 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1259 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1262 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1264 for (i = 0; i < txq->tx_rs_thresh; i++)
1265 rte_prefetch0((txep + i)->mbuf);
1267 if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1268 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1269 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1273 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1274 rte_pktmbuf_free_seg(txep->mbuf);
1279 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1280 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1281 if (txq->tx_next_dd >= txq->nb_tx_desc)
1282 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1284 return txq->tx_rs_thresh;
1287 /* Populate 4 descriptors with data from 4 mbufs */
1289 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1294 for (i = 0; i < 4; i++, txdp++, pkts++) {
1295 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1296 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1297 txdp->cmd_type_offset_bsz =
1298 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1299 (*pkts)->data_len, 0);
1303 /* Populate 1 descriptor with data from 1 mbuf */
1305 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1309 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1310 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1311 txdp->cmd_type_offset_bsz =
1312 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1313 (*pkts)->data_len, 0);
1316 /* Fill hardware descriptor ring with mbuf data */
1318 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1319 struct rte_mbuf **pkts,
1322 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1323 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1324 const int N_PER_LOOP = 4;
1325 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1326 int mainpart, leftover;
1329 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1330 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1331 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1332 for (j = 0; j < N_PER_LOOP; ++j) {
1333 (txep + i + j)->mbuf = *(pkts + i + j);
1335 tx4(txdp + i, pkts + i);
1337 if (unlikely(leftover > 0)) {
1338 for (i = 0; i < leftover; ++i) {
1339 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1340 tx1(txdp + mainpart + i, pkts + mainpart + i);
1345 static inline uint16_t
1346 tx_xmit_pkts(struct i40e_tx_queue *txq,
1347 struct rte_mbuf **tx_pkts,
1350 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1354 * Begin scanning the H/W ring for done descriptors when the number
1355 * of available descriptors drops below tx_free_thresh. For each done
1356 * descriptor, free the associated buffer.
1358 if (txq->nb_tx_free < txq->tx_free_thresh)
1359 i40e_tx_free_bufs(txq);
1361 /* Use available descriptor only */
1362 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1363 if (unlikely(!nb_pkts))
1366 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1367 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1368 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1369 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1370 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1371 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1372 I40E_TXD_QW1_CMD_SHIFT);
1373 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1377 /* Fill hardware descriptor ring with mbuf data */
1378 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1379 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1381 /* Determin if RS bit needs to be set */
1382 if (txq->tx_tail > txq->tx_next_rs) {
1383 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1384 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1385 I40E_TXD_QW1_CMD_SHIFT);
1387 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1388 if (txq->tx_next_rs >= txq->nb_tx_desc)
1389 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1392 if (txq->tx_tail >= txq->nb_tx_desc)
1395 /* Update the tx tail register */
1397 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1403 i40e_xmit_pkts_simple(void *tx_queue,
1404 struct rte_mbuf **tx_pkts,
1409 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1410 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1414 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1417 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1418 &tx_pkts[nb_tx], num);
1419 nb_tx = (uint16_t)(nb_tx + ret);
1420 nb_pkts = (uint16_t)(nb_pkts - ret);
1429 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1430 * application used, which assume having sequential ones. But from driver's
1431 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1432 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1433 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1434 * use queue_idx from 0 to 95 to access queues, while real queue would be
1435 * different. This function will do a queue mapping to find VSI the queue
1438 static struct i40e_vsi*
1439 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1441 /* the queue in MAIN VSI range */
1442 if (queue_idx < pf->main_vsi->nb_qps)
1443 return pf->main_vsi;
1445 queue_idx -= pf->main_vsi->nb_qps;
1447 /* queue_idx is greater than VMDQ VSIs range */
1448 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1449 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1453 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1457 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1459 /* the queue in MAIN VSI range */
1460 if (queue_idx < pf->main_vsi->nb_qps)
1463 /* It's VMDQ queues */
1464 queue_idx -= pf->main_vsi->nb_qps;
1466 if (pf->nb_cfg_vmdq_vsi)
1467 return queue_idx % pf->vmdq_nb_qps;
1469 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1470 return (uint16_t)(-1);
1475 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1477 struct i40e_rx_queue *rxq;
1479 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1481 PMD_INIT_FUNC_TRACE();
1483 if (rx_queue_id < dev->data->nb_rx_queues) {
1484 rxq = dev->data->rx_queues[rx_queue_id];
1486 err = i40e_alloc_rx_queue_mbufs(rxq);
1488 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1494 /* Init the RX tail regieter. */
1495 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1497 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1500 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1503 i40e_rx_queue_release_mbufs(rxq);
1504 i40e_reset_rx_queue(rxq);
1506 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1513 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1515 struct i40e_rx_queue *rxq;
1517 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1519 if (rx_queue_id < dev->data->nb_rx_queues) {
1520 rxq = dev->data->rx_queues[rx_queue_id];
1523 * rx_queue_id is queue id aplication refers to, while
1524 * rxq->reg_idx is the real queue index.
1526 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1529 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1533 i40e_rx_queue_release_mbufs(rxq);
1534 i40e_reset_rx_queue(rxq);
1535 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1542 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1545 struct i40e_tx_queue *txq;
1546 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1548 PMD_INIT_FUNC_TRACE();
1550 if (tx_queue_id < dev->data->nb_tx_queues) {
1551 txq = dev->data->tx_queues[tx_queue_id];
1554 * tx_queue_id is queue id aplication refers to, while
1555 * rxq->reg_idx is the real queue index.
1557 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1559 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1562 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1569 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1571 struct i40e_tx_queue *txq;
1573 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1575 if (tx_queue_id < dev->data->nb_tx_queues) {
1576 txq = dev->data->tx_queues[tx_queue_id];
1579 * tx_queue_id is queue id aplication refers to, while
1580 * txq->reg_idx is the real queue index.
1582 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1585 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1590 i40e_tx_queue_release_mbufs(txq);
1591 i40e_reset_tx_queue(txq);
1592 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1599 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1601 static const uint32_t ptypes[] = {
1602 /* refers to i40e_rxd_pkt_type_mapping() */
1604 RTE_PTYPE_L2_ETHER_TIMESYNC,
1605 RTE_PTYPE_L2_ETHER_LLDP,
1606 RTE_PTYPE_L2_ETHER_ARP,
1607 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1608 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1611 RTE_PTYPE_L4_NONFRAG,
1615 RTE_PTYPE_TUNNEL_GRENAT,
1616 RTE_PTYPE_TUNNEL_IP,
1617 RTE_PTYPE_INNER_L2_ETHER,
1618 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1619 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1620 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1621 RTE_PTYPE_INNER_L4_FRAG,
1622 RTE_PTYPE_INNER_L4_ICMP,
1623 RTE_PTYPE_INNER_L4_NONFRAG,
1624 RTE_PTYPE_INNER_L4_SCTP,
1625 RTE_PTYPE_INNER_L4_TCP,
1626 RTE_PTYPE_INNER_L4_UDP,
1630 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1631 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1632 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1634 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1635 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1636 dev->rx_pkt_burst == i40e_recv_pkts_vec)
1642 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1645 unsigned int socket_id,
1646 const struct rte_eth_rxconf *rx_conf,
1647 struct rte_mempool *mp)
1649 struct i40e_vsi *vsi;
1650 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1651 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1652 struct i40e_adapter *ad =
1653 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1654 struct i40e_rx_queue *rxq;
1655 const struct rte_memzone *rz;
1658 uint16_t base, bsf, tc_mapping;
1659 int use_def_burst_func = 1;
1661 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1662 struct i40e_vf *vf =
1663 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1666 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1669 PMD_DRV_LOG(ERR, "VSI not available or queue "
1670 "index exceeds the maximum");
1671 return I40E_ERR_PARAM;
1673 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1674 (nb_desc > I40E_MAX_RING_DESC) ||
1675 (nb_desc < I40E_MIN_RING_DESC)) {
1676 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1677 "invalid", nb_desc);
1678 return I40E_ERR_PARAM;
1681 /* Free memory if needed */
1682 if (dev->data->rx_queues[queue_idx]) {
1683 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1684 dev->data->rx_queues[queue_idx] = NULL;
1687 /* Allocate the rx queue data structure */
1688 rxq = rte_zmalloc_socket("i40e rx queue",
1689 sizeof(struct i40e_rx_queue),
1690 RTE_CACHE_LINE_SIZE,
1693 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1694 "rx queue data structure");
1698 rxq->nb_rx_desc = nb_desc;
1699 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1700 rxq->queue_id = queue_idx;
1701 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
1702 rxq->reg_idx = queue_idx;
1703 else /* PF device */
1704 rxq->reg_idx = vsi->base_queue +
1705 i40e_get_queue_offset_by_qindex(pf, queue_idx);
1707 rxq->port_id = dev->data->port_id;
1708 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1710 rxq->drop_en = rx_conf->rx_drop_en;
1712 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1714 /* Allocate the maximun number of RX ring hardware descriptor. */
1715 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1716 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1717 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1718 ring_size, I40E_RING_BASE_ALIGN, socket_id);
1720 i40e_dev_rx_queue_release(rxq);
1721 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1725 /* Zero all the descriptors in the ring. */
1726 memset(rz->addr, 0, ring_size);
1728 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1729 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1731 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1733 /* Allocate the software ring. */
1735 rte_zmalloc_socket("i40e rx sw ring",
1736 sizeof(struct i40e_rx_entry) * len,
1737 RTE_CACHE_LINE_SIZE,
1739 if (!rxq->sw_ring) {
1740 i40e_dev_rx_queue_release(rxq);
1741 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1745 i40e_reset_rx_queue(rxq);
1747 dev->data->rx_queues[queue_idx] = rxq;
1749 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1751 if (!use_def_burst_func) {
1752 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1753 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1754 "satisfied. Rx Burst Bulk Alloc function will be "
1755 "used on port=%d, queue=%d.",
1756 rxq->port_id, rxq->queue_id);
1757 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1759 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1760 "not satisfied, Scattered Rx is requested, "
1761 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1762 "not enabled on port=%d, queue=%d.",
1763 rxq->port_id, rxq->queue_id);
1764 ad->rx_bulk_alloc_allowed = false;
1767 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1768 if (!(vsi->enabled_tc & (1 << i)))
1770 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1771 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1772 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1773 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1774 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1776 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1784 i40e_dev_rx_queue_release(void *rxq)
1786 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1789 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1793 i40e_rx_queue_release_mbufs(q);
1794 rte_free(q->sw_ring);
1799 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1801 #define I40E_RXQ_SCAN_INTERVAL 4
1802 volatile union i40e_rx_desc *rxdp;
1803 struct i40e_rx_queue *rxq;
1806 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1807 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1811 rxq = dev->data->rx_queues[rx_queue_id];
1812 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1813 while ((desc < rxq->nb_rx_desc) &&
1814 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1815 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1816 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1818 * Check the DD bit of a rx descriptor of each 4 in a group,
1819 * to avoid checking too frequently and downgrading performance
1822 desc += I40E_RXQ_SCAN_INTERVAL;
1823 rxdp += I40E_RXQ_SCAN_INTERVAL;
1824 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1825 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1826 desc - rxq->nb_rx_desc]);
1833 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1835 volatile union i40e_rx_desc *rxdp;
1836 struct i40e_rx_queue *rxq = rx_queue;
1840 if (unlikely(offset >= rxq->nb_rx_desc)) {
1841 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1845 desc = rxq->rx_tail + offset;
1846 if (desc >= rxq->nb_rx_desc)
1847 desc -= rxq->nb_rx_desc;
1849 rxdp = &(rxq->rx_ring[desc]);
1851 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1852 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1853 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1859 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1862 unsigned int socket_id,
1863 const struct rte_eth_txconf *tx_conf)
1865 struct i40e_vsi *vsi;
1866 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1867 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1868 struct i40e_tx_queue *txq;
1869 const struct rte_memzone *tz;
1871 uint16_t tx_rs_thresh, tx_free_thresh;
1872 uint16_t i, base, bsf, tc_mapping;
1874 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1875 struct i40e_vf *vf =
1876 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1879 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1882 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1883 "exceeds the maximum", queue_idx);
1884 return I40E_ERR_PARAM;
1887 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1888 (nb_desc > I40E_MAX_RING_DESC) ||
1889 (nb_desc < I40E_MIN_RING_DESC)) {
1890 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1891 "invalid", nb_desc);
1892 return I40E_ERR_PARAM;
1896 * The following two parameters control the setting of the RS bit on
1897 * transmit descriptors. TX descriptors will have their RS bit set
1898 * after txq->tx_rs_thresh descriptors have been used. The TX
1899 * descriptor ring will be cleaned after txq->tx_free_thresh
1900 * descriptors are used or if the number of descriptors required to
1901 * transmit a packet is greater than the number of free TX descriptors.
1903 * The following constraints must be satisfied:
1904 * - tx_rs_thresh must be greater than 0.
1905 * - tx_rs_thresh must be less than the size of the ring minus 2.
1906 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1907 * - tx_rs_thresh must be a divisor of the ring size.
1908 * - tx_free_thresh must be greater than 0.
1909 * - tx_free_thresh must be less than the size of the ring minus 3.
1911 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1912 * race condition, hence the maximum threshold constraints. When set
1913 * to zero use default values.
1915 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1916 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1917 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1918 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1919 if (tx_rs_thresh >= (nb_desc - 2)) {
1920 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1921 "number of TX descriptors minus 2. "
1922 "(tx_rs_thresh=%u port=%d queue=%d)",
1923 (unsigned int)tx_rs_thresh,
1924 (int)dev->data->port_id,
1926 return I40E_ERR_PARAM;
1928 if (tx_free_thresh >= (nb_desc - 3)) {
1929 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
1930 "number of TX descriptors minus 3. "
1931 "(tx_free_thresh=%u port=%d queue=%d)",
1932 (unsigned int)tx_free_thresh,
1933 (int)dev->data->port_id,
1935 return I40E_ERR_PARAM;
1937 if (tx_rs_thresh > tx_free_thresh) {
1938 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1939 "equal to tx_free_thresh. (tx_free_thresh=%u"
1940 " tx_rs_thresh=%u port=%d queue=%d)",
1941 (unsigned int)tx_free_thresh,
1942 (unsigned int)tx_rs_thresh,
1943 (int)dev->data->port_id,
1945 return I40E_ERR_PARAM;
1947 if ((nb_desc % tx_rs_thresh) != 0) {
1948 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1949 "number of TX descriptors. (tx_rs_thresh=%u"
1950 " port=%d queue=%d)",
1951 (unsigned int)tx_rs_thresh,
1952 (int)dev->data->port_id,
1954 return I40E_ERR_PARAM;
1956 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1957 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1958 "tx_rs_thresh is greater than 1. "
1959 "(tx_rs_thresh=%u port=%d queue=%d)",
1960 (unsigned int)tx_rs_thresh,
1961 (int)dev->data->port_id,
1963 return I40E_ERR_PARAM;
1966 /* Free memory if needed. */
1967 if (dev->data->tx_queues[queue_idx]) {
1968 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
1969 dev->data->tx_queues[queue_idx] = NULL;
1972 /* Allocate the TX queue data structure. */
1973 txq = rte_zmalloc_socket("i40e tx queue",
1974 sizeof(struct i40e_tx_queue),
1975 RTE_CACHE_LINE_SIZE,
1978 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1979 "tx queue structure");
1983 /* Allocate TX hardware ring descriptors. */
1984 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
1985 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1986 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1987 ring_size, I40E_RING_BASE_ALIGN, socket_id);
1989 i40e_dev_tx_queue_release(txq);
1990 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
1994 txq->nb_tx_desc = nb_desc;
1995 txq->tx_rs_thresh = tx_rs_thresh;
1996 txq->tx_free_thresh = tx_free_thresh;
1997 txq->pthresh = tx_conf->tx_thresh.pthresh;
1998 txq->hthresh = tx_conf->tx_thresh.hthresh;
1999 txq->wthresh = tx_conf->tx_thresh.wthresh;
2000 txq->queue_id = queue_idx;
2001 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2002 txq->reg_idx = queue_idx;
2003 else /* PF device */
2004 txq->reg_idx = vsi->base_queue +
2005 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2007 txq->port_id = dev->data->port_id;
2008 txq->txq_flags = tx_conf->txq_flags;
2010 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2012 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2013 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2015 /* Allocate software ring */
2017 rte_zmalloc_socket("i40e tx sw ring",
2018 sizeof(struct i40e_tx_entry) * nb_desc,
2019 RTE_CACHE_LINE_SIZE,
2021 if (!txq->sw_ring) {
2022 i40e_dev_tx_queue_release(txq);
2023 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2027 i40e_reset_tx_queue(txq);
2029 dev->data->tx_queues[queue_idx] = txq;
2031 /* Use a simple TX queue without offloads or multi segs if possible */
2032 i40e_set_tx_function_flag(dev, txq);
2034 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2035 if (!(vsi->enabled_tc & (1 << i)))
2037 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2038 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2039 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2040 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2041 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2043 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2051 i40e_dev_tx_queue_release(void *txq)
2053 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2056 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2060 i40e_tx_queue_release_mbufs(q);
2061 rte_free(q->sw_ring);
2065 const struct rte_memzone *
2066 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2068 const struct rte_memzone *mz;
2070 mz = rte_memzone_lookup(name);
2074 if (rte_xen_dom0_supported())
2075 mz = rte_memzone_reserve_bounded(name, len,
2076 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2078 mz = rte_memzone_reserve_aligned(name, len,
2079 socket_id, 0, I40E_RING_BASE_ALIGN);
2084 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2088 /* SSE Vector driver has a different way of releasing mbufs. */
2089 if (rxq->rx_using_sse) {
2090 i40e_rx_queue_release_mbufs_vec(rxq);
2094 if (!rxq->sw_ring) {
2095 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2099 for (i = 0; i < rxq->nb_rx_desc; i++) {
2100 if (rxq->sw_ring[i].mbuf) {
2101 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2102 rxq->sw_ring[i].mbuf = NULL;
2105 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2106 if (rxq->rx_nb_avail == 0)
2108 for (i = 0; i < rxq->rx_nb_avail; i++) {
2109 struct rte_mbuf *mbuf;
2111 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2112 rte_pktmbuf_free_seg(mbuf);
2114 rxq->rx_nb_avail = 0;
2115 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2119 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2125 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2129 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2130 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2131 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2133 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2134 len = rxq->nb_rx_desc;
2136 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2137 ((volatile char *)rxq->rx_ring)[i] = 0;
2139 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2140 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2141 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2143 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2144 rxq->rx_nb_avail = 0;
2145 rxq->rx_next_avail = 0;
2146 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2147 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2149 rxq->nb_rx_hold = 0;
2150 rxq->pkt_first_seg = NULL;
2151 rxq->pkt_last_seg = NULL;
2153 rxq->rxrearm_start = 0;
2154 rxq->rxrearm_nb = 0;
2158 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2162 if (!txq || !txq->sw_ring) {
2163 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2167 for (i = 0; i < txq->nb_tx_desc; i++) {
2168 if (txq->sw_ring[i].mbuf) {
2169 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2170 txq->sw_ring[i].mbuf = NULL;
2176 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2178 struct i40e_tx_entry *txe;
2179 uint16_t i, prev, size;
2182 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2187 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2188 for (i = 0; i < size; i++)
2189 ((volatile char *)txq->tx_ring)[i] = 0;
2191 prev = (uint16_t)(txq->nb_tx_desc - 1);
2192 for (i = 0; i < txq->nb_tx_desc; i++) {
2193 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2195 txd->cmd_type_offset_bsz =
2196 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2199 txe[prev].next_id = i;
2203 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2204 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2207 txq->nb_tx_used = 0;
2209 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2210 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2213 /* Init the TX queue in hardware */
2215 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2217 enum i40e_status_code err = I40E_SUCCESS;
2218 struct i40e_vsi *vsi = txq->vsi;
2219 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2220 uint16_t pf_q = txq->reg_idx;
2221 struct i40e_hmc_obj_txq tx_ctx;
2224 /* clear the context structure first */
2225 memset(&tx_ctx, 0, sizeof(tx_ctx));
2226 tx_ctx.new_context = 1;
2227 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2228 tx_ctx.qlen = txq->nb_tx_desc;
2230 #ifdef RTE_LIBRTE_IEEE1588
2231 tx_ctx.timesync_ena = 1;
2233 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2234 if (vsi->type == I40E_VSI_FDIR)
2235 tx_ctx.fd_ena = TRUE;
2237 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2238 if (err != I40E_SUCCESS) {
2239 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2243 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2244 if (err != I40E_SUCCESS) {
2245 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2249 /* Now associate this queue with this PCI function */
2250 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2251 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2252 I40E_QTX_CTL_PF_INDX_MASK);
2253 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2254 I40E_WRITE_FLUSH(hw);
2256 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2262 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2264 struct i40e_rx_entry *rxe = rxq->sw_ring;
2268 for (i = 0; i < rxq->nb_rx_desc; i++) {
2269 volatile union i40e_rx_desc *rxd;
2270 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2272 if (unlikely(!mbuf)) {
2273 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2277 rte_mbuf_refcnt_set(mbuf, 1);
2279 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2281 mbuf->port = rxq->port_id;
2284 rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2286 rxd = &rxq->rx_ring[i];
2287 rxd->read.pkt_addr = dma_addr;
2288 rxd->read.hdr_addr = 0;
2289 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2290 rxd->read.rsvd1 = 0;
2291 rxd->read.rsvd2 = 0;
2292 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2301 * Calculate the buffer length, and check the jumbo frame
2302 * and maximum packet length.
2305 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2307 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2308 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2309 struct rte_eth_dev_data *data = pf->dev_data;
2310 uint16_t buf_size, len;
2312 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2313 RTE_PKTMBUF_HEADROOM);
2315 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2316 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2317 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2318 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2319 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2320 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2321 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2322 rxq->hs_mode = i40e_header_split_enabled;
2324 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2326 rxq->rx_hdr_len = 0;
2327 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2328 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2329 rxq->hs_mode = i40e_header_split_none;
2333 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2334 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2335 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2336 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2337 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2338 PMD_DRV_LOG(ERR, "maximum packet length must "
2339 "be larger than %u and smaller than %u,"
2340 "as jumbo frame is enabled",
2341 (uint32_t)ETHER_MAX_LEN,
2342 (uint32_t)I40E_FRAME_SIZE_MAX);
2343 return I40E_ERR_CONFIG;
2346 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2347 rxq->max_pkt_len > ETHER_MAX_LEN) {
2348 PMD_DRV_LOG(ERR, "maximum packet length must be "
2349 "larger than %u and smaller than %u, "
2350 "as jumbo frame is disabled",
2351 (uint32_t)ETHER_MIN_LEN,
2352 (uint32_t)ETHER_MAX_LEN);
2353 return I40E_ERR_CONFIG;
2360 /* Init the RX queue in hardware */
2362 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2364 int err = I40E_SUCCESS;
2365 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2366 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2367 uint16_t pf_q = rxq->reg_idx;
2369 struct i40e_hmc_obj_rxq rx_ctx;
2371 err = i40e_rx_queue_config(rxq);
2373 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2377 /* Clear the context structure first */
2378 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2379 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2380 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2382 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2383 rx_ctx.qlen = rxq->nb_rx_desc;
2384 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2387 rx_ctx.dtype = rxq->hs_mode;
2389 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2391 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2392 rx_ctx.rxmax = rxq->max_pkt_len;
2393 rx_ctx.tphrdesc_ena = 1;
2394 rx_ctx.tphwdesc_ena = 1;
2395 rx_ctx.tphdata_ena = 1;
2396 rx_ctx.tphhead_ena = 1;
2397 rx_ctx.lrxqthresh = 2;
2398 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2400 /* showiv indicates if inner VLAN is stripped inside of tunnel
2401 * packet. When set it to 1, vlan information is stripped from
2402 * the inner header, but the hardware does not put it in the
2403 * descriptor. So set it zero by default.
2408 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2409 if (err != I40E_SUCCESS) {
2410 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2413 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2414 if (err != I40E_SUCCESS) {
2415 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2419 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2421 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2422 RTE_PKTMBUF_HEADROOM);
2424 /* Check if scattered RX needs to be used. */
2425 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2426 dev_data->scattered_rx = 1;
2429 /* Init the RX tail regieter. */
2430 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2436 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2440 PMD_INIT_FUNC_TRACE();
2442 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2443 if (!dev->data->tx_queues[i])
2445 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2446 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2449 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2450 if (!dev->data->rx_queues[i])
2452 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2453 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2458 i40e_dev_free_queues(struct rte_eth_dev *dev)
2462 PMD_INIT_FUNC_TRACE();
2464 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2465 if (!dev->data->rx_queues[i])
2467 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2468 dev->data->rx_queues[i] = NULL;
2470 dev->data->nb_rx_queues = 0;
2472 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2473 if (!dev->data->tx_queues[i])
2475 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2476 dev->data->tx_queues[i] = NULL;
2478 dev->data->nb_tx_queues = 0;
2481 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2482 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2484 enum i40e_status_code
2485 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2487 struct i40e_tx_queue *txq;
2488 const struct rte_memzone *tz = NULL;
2490 struct rte_eth_dev *dev;
2493 PMD_DRV_LOG(ERR, "PF is not available");
2494 return I40E_ERR_BAD_PTR;
2497 dev = pf->adapter->eth_dev;
2499 /* Allocate the TX queue data structure. */
2500 txq = rte_zmalloc_socket("i40e fdir tx queue",
2501 sizeof(struct i40e_tx_queue),
2502 RTE_CACHE_LINE_SIZE,
2505 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2506 "tx queue structure.");
2507 return I40E_ERR_NO_MEMORY;
2510 /* Allocate TX hardware ring descriptors. */
2511 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2512 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2514 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2515 I40E_FDIR_QUEUE_ID, ring_size,
2516 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2518 i40e_dev_tx_queue_release(txq);
2519 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2520 return I40E_ERR_NO_MEMORY;
2523 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2524 txq->queue_id = I40E_FDIR_QUEUE_ID;
2525 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2526 txq->vsi = pf->fdir.fdir_vsi;
2528 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2529 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2531 * don't need to allocate software ring and reset for the fdir
2532 * program queue just set the queue has been configured.
2537 return I40E_SUCCESS;
2540 enum i40e_status_code
2541 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2543 struct i40e_rx_queue *rxq;
2544 const struct rte_memzone *rz = NULL;
2546 struct rte_eth_dev *dev;
2549 PMD_DRV_LOG(ERR, "PF is not available");
2550 return I40E_ERR_BAD_PTR;
2553 dev = pf->adapter->eth_dev;
2555 /* Allocate the RX queue data structure. */
2556 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2557 sizeof(struct i40e_rx_queue),
2558 RTE_CACHE_LINE_SIZE,
2561 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2562 "rx queue structure.");
2563 return I40E_ERR_NO_MEMORY;
2566 /* Allocate RX hardware ring descriptors. */
2567 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2568 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2570 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2571 I40E_FDIR_QUEUE_ID, ring_size,
2572 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2574 i40e_dev_rx_queue_release(rxq);
2575 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2576 return I40E_ERR_NO_MEMORY;
2579 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2580 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2581 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2582 rxq->vsi = pf->fdir.fdir_vsi;
2584 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2585 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2588 * Don't need to allocate software ring and reset for the fdir
2589 * rx queue, just set the queue has been configured.
2594 return I40E_SUCCESS;
2598 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2599 struct rte_eth_rxq_info *qinfo)
2601 struct i40e_rx_queue *rxq;
2603 rxq = dev->data->rx_queues[queue_id];
2605 qinfo->mp = rxq->mp;
2606 qinfo->scattered_rx = dev->data->scattered_rx;
2607 qinfo->nb_desc = rxq->nb_rx_desc;
2609 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2610 qinfo->conf.rx_drop_en = rxq->drop_en;
2611 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2615 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2616 struct rte_eth_txq_info *qinfo)
2618 struct i40e_tx_queue *txq;
2620 txq = dev->data->tx_queues[queue_id];
2622 qinfo->nb_desc = txq->nb_tx_desc;
2624 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2625 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2626 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2628 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2629 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2630 qinfo->conf.txq_flags = txq->txq_flags;
2631 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2634 void __attribute__((cold))
2635 i40e_set_rx_function(struct rte_eth_dev *dev)
2637 struct i40e_adapter *ad =
2638 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2639 uint16_t rx_using_sse, i;
2640 /* In order to allow Vector Rx there are a few configuration
2641 * conditions to be met and Rx Bulk Allocation should be allowed.
2643 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2644 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2645 !ad->rx_bulk_alloc_allowed) {
2646 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2647 " Vector Rx preconditions",
2648 dev->data->port_id);
2650 ad->rx_vec_allowed = false;
2652 if (ad->rx_vec_allowed) {
2653 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2654 struct i40e_rx_queue *rxq =
2655 dev->data->rx_queues[i];
2657 if (rxq && i40e_rxq_vec_setup(rxq)) {
2658 ad->rx_vec_allowed = false;
2665 if (dev->data->scattered_rx) {
2666 /* Set the non-LRO scattered callback: there are Vector and
2667 * single allocation versions.
2669 if (ad->rx_vec_allowed) {
2670 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2671 "callback (port=%d).",
2672 dev->data->port_id);
2674 dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2676 PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2677 "allocation callback (port=%d).",
2678 dev->data->port_id);
2679 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2681 /* If parameters allow we are going to choose between the following
2685 * - Single buffer allocation (the simplest one)
2687 } else if (ad->rx_vec_allowed) {
2688 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2689 "burst size no less than %d (port=%d).",
2690 RTE_I40E_DESCS_PER_LOOP,
2691 dev->data->port_id);
2693 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2694 } else if (ad->rx_bulk_alloc_allowed) {
2695 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2696 "satisfied. Rx Burst Bulk Alloc function "
2697 "will be used on port=%d.",
2698 dev->data->port_id);
2700 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2702 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2703 "satisfied, or Scattered Rx is requested "
2705 dev->data->port_id);
2707 dev->rx_pkt_burst = i40e_recv_pkts;
2710 /* Propagate information about RX function choice through all queues. */
2711 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2713 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2714 dev->rx_pkt_burst == i40e_recv_pkts_vec);
2716 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2717 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2720 rxq->rx_using_sse = rx_using_sse;
2725 void __attribute__((cold))
2726 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2728 struct i40e_adapter *ad =
2729 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2731 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2732 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2733 && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2734 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2735 PMD_INIT_LOG(DEBUG, "Vector tx"
2736 " can be enabled on this txq.");
2739 ad->tx_vec_allowed = false;
2742 ad->tx_simple_allowed = false;
2746 void __attribute__((cold))
2747 i40e_set_tx_function(struct rte_eth_dev *dev)
2749 struct i40e_adapter *ad =
2750 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2753 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2754 if (ad->tx_vec_allowed) {
2755 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2756 struct i40e_tx_queue *txq =
2757 dev->data->tx_queues[i];
2759 if (txq && i40e_txq_vec_setup(txq)) {
2760 ad->tx_vec_allowed = false;
2767 if (ad->tx_simple_allowed) {
2768 if (ad->tx_vec_allowed) {
2769 PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2770 dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2772 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2773 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2776 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
2777 dev->tx_pkt_burst = i40e_xmit_pkts;
2781 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
2782 int __attribute__((weak))
2783 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
2788 uint16_t __attribute__((weak))
2790 void __rte_unused *rx_queue,
2791 struct rte_mbuf __rte_unused **rx_pkts,
2792 uint16_t __rte_unused nb_pkts)
2797 uint16_t __attribute__((weak))
2798 i40e_recv_scattered_pkts_vec(
2799 void __rte_unused *rx_queue,
2800 struct rte_mbuf __rte_unused **rx_pkts,
2801 uint16_t __rte_unused nb_pkts)
2806 int __attribute__((weak))
2807 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
2812 int __attribute__((weak))
2813 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
2818 void __attribute__((weak))
2819 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
2824 uint16_t __attribute__((weak))
2825 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
2826 struct rte_mbuf __rte_unused **tx_pkts,
2827 uint16_t __rte_unused nb_pkts)