1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
40 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
41 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
42 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
44 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
47 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
48 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
53 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
55 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
57 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
58 u16 words, u16 *data);
59 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
63 * ixgbe_init_ops_generic - Inits function ptrs
64 * @hw: pointer to the hardware structure
66 * Initialize the function pointers.
68 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
70 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
71 struct ixgbe_mac_info *mac = &hw->mac;
72 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
74 DEBUGFUNC("ixgbe_init_ops_generic");
77 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
78 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
79 if (eec & IXGBE_EEC_PRES) {
80 eeprom->ops.read = ixgbe_read_eerd_generic;
81 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
83 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
84 eeprom->ops.read_buffer =
85 ixgbe_read_eeprom_buffer_bit_bang_generic;
87 eeprom->ops.write = ixgbe_write_eeprom_generic;
88 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
89 eeprom->ops.validate_checksum =
90 ixgbe_validate_eeprom_checksum_generic;
91 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
92 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
95 mac->ops.init_hw = ixgbe_init_hw_generic;
96 mac->ops.reset_hw = NULL;
97 mac->ops.start_hw = ixgbe_start_hw_generic;
98 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
99 mac->ops.get_media_type = NULL;
100 mac->ops.get_supported_physical_layer = NULL;
101 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
102 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
103 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
104 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
105 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
106 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
107 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
108 mac->ops.prot_autoc_read = prot_autoc_read_generic;
109 mac->ops.prot_autoc_write = prot_autoc_write_generic;
112 mac->ops.led_on = ixgbe_led_on_generic;
113 mac->ops.led_off = ixgbe_led_off_generic;
114 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
115 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
117 /* RAR, Multicast, VLAN */
118 mac->ops.set_rar = ixgbe_set_rar_generic;
119 mac->ops.clear_rar = ixgbe_clear_rar_generic;
120 mac->ops.insert_mac_addr = NULL;
121 mac->ops.set_vmdq = NULL;
122 mac->ops.clear_vmdq = NULL;
123 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
124 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
125 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
126 mac->ops.enable_mc = ixgbe_enable_mc_generic;
127 mac->ops.disable_mc = ixgbe_disable_mc_generic;
128 mac->ops.clear_vfta = NULL;
129 mac->ops.set_vfta = NULL;
130 mac->ops.set_vlvf = NULL;
131 mac->ops.init_uta_tables = NULL;
132 mac->ops.enable_rx = ixgbe_enable_rx_generic;
133 mac->ops.disable_rx = ixgbe_disable_rx_generic;
136 mac->ops.fc_enable = ixgbe_fc_enable_generic;
137 mac->ops.setup_fc = ixgbe_setup_fc_generic;
138 mac->ops.fc_autoneg = ixgbe_fc_autoneg;
141 mac->ops.get_link_capabilities = NULL;
142 mac->ops.setup_link = NULL;
143 mac->ops.check_link = NULL;
144 mac->ops.dmac_config = NULL;
145 mac->ops.dmac_update_tcs = NULL;
146 mac->ops.dmac_config_tcs = NULL;
148 return IXGBE_SUCCESS;
152 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
154 * @hw: pointer to hardware structure
156 * This function returns true if the device supports flow control
157 * autonegotiation, and false if it does not.
160 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
162 bool supported = false;
163 ixgbe_link_speed speed;
166 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
168 switch (hw->phy.media_type) {
169 case ixgbe_media_type_fiber_fixed:
170 case ixgbe_media_type_fiber_qsfp:
171 case ixgbe_media_type_fiber:
172 /* flow control autoneg black list */
173 switch (hw->device_id) {
174 case IXGBE_DEV_ID_X550EM_A_SFP:
175 case IXGBE_DEV_ID_X550EM_A_SFP_N:
176 case IXGBE_DEV_ID_X550EM_A_QSFP:
177 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
181 hw->mac.ops.check_link(hw, &speed, &link_up, false);
182 /* if link is down, assume supported */
184 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
191 case ixgbe_media_type_backplane:
194 case ixgbe_media_type_copper:
195 /* only some copper devices support flow control autoneg */
196 switch (hw->device_id) {
197 case IXGBE_DEV_ID_82599_T3_LOM:
198 case IXGBE_DEV_ID_X540T:
199 case IXGBE_DEV_ID_X540T1:
200 case IXGBE_DEV_ID_X540_BYPASS:
201 case IXGBE_DEV_ID_X550T:
202 case IXGBE_DEV_ID_X550T1:
203 case IXGBE_DEV_ID_X550EM_X_10G_T:
204 case IXGBE_DEV_ID_X550EM_A_10G_T:
205 case IXGBE_DEV_ID_X550EM_A_1G_T:
206 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
217 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
218 "Device %x does not support flow control autoneg",
224 * ixgbe_setup_fc_generic - Set up flow control
225 * @hw: pointer to hardware structure
227 * Called at init time to set up flow control.
229 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
231 s32 ret_val = IXGBE_SUCCESS;
232 u32 reg = 0, reg_bp = 0;
236 DEBUGFUNC("ixgbe_setup_fc_generic");
238 /* Validate the requested mode */
239 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
240 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
241 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
242 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
247 * 10gig parts do not have a word in the EEPROM to determine the
248 * default flow control setting, so we explicitly set it to full.
250 if (hw->fc.requested_mode == ixgbe_fc_default)
251 hw->fc.requested_mode = ixgbe_fc_full;
254 * Set up the 1G and 10G flow control advertisement registers so the
255 * HW will be able to do fc autoneg once the cable is plugged in. If
256 * we link at 10G, the 1G advertisement is harmless and vice versa.
258 switch (hw->phy.media_type) {
259 case ixgbe_media_type_backplane:
260 /* some MAC's need RMW protection on AUTOC */
261 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
262 if (ret_val != IXGBE_SUCCESS)
265 /* only backplane uses autoc so fall though */
266 case ixgbe_media_type_fiber_fixed:
267 case ixgbe_media_type_fiber_qsfp:
268 case ixgbe_media_type_fiber:
269 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
272 case ixgbe_media_type_copper:
273 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
274 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
281 * The possible values of fc.requested_mode are:
282 * 0: Flow control is completely disabled
283 * 1: Rx flow control is enabled (we can receive pause frames,
284 * but not send pause frames).
285 * 2: Tx flow control is enabled (we can send pause frames but
286 * we do not support receiving pause frames).
287 * 3: Both Rx and Tx flow control (symmetric) are enabled.
290 switch (hw->fc.requested_mode) {
292 /* Flow control completely disabled by software override. */
293 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
294 if (hw->phy.media_type == ixgbe_media_type_backplane)
295 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
296 IXGBE_AUTOC_ASM_PAUSE);
297 else if (hw->phy.media_type == ixgbe_media_type_copper)
298 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
300 case ixgbe_fc_tx_pause:
302 * Tx Flow control is enabled, and Rx Flow control is
303 * disabled by software override.
305 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
306 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
307 if (hw->phy.media_type == ixgbe_media_type_backplane) {
308 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
309 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
310 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
311 reg_cu |= IXGBE_TAF_ASM_PAUSE;
312 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
315 case ixgbe_fc_rx_pause:
317 * Rx Flow control is enabled and Tx Flow control is
318 * disabled by software override. Since there really
319 * isn't a way to advertise that we are capable of RX
320 * Pause ONLY, we will advertise that we support both
321 * symmetric and asymmetric Rx PAUSE, as such we fall
322 * through to the fc_full statement. Later, we will
323 * disable the adapter's ability to send PAUSE frames.
326 /* Flow control (both Rx and Tx) is enabled by SW override. */
327 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
328 if (hw->phy.media_type == ixgbe_media_type_backplane)
329 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
330 IXGBE_AUTOC_ASM_PAUSE;
331 else if (hw->phy.media_type == ixgbe_media_type_copper)
332 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
335 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
336 "Flow control param set incorrectly\n");
337 ret_val = IXGBE_ERR_CONFIG;
342 if (hw->mac.type < ixgbe_mac_X540) {
344 * Enable auto-negotiation between the MAC & PHY;
345 * the MAC will advertise clause 37 flow control.
347 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
348 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
350 /* Disable AN timeout */
351 if (hw->fc.strict_ieee)
352 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
354 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
355 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
359 * AUTOC restart handles negotiation of 1G and 10G on backplane
360 * and copper. There is no need to set the PCS1GCTL register.
363 if (hw->phy.media_type == ixgbe_media_type_backplane) {
364 reg_bp |= IXGBE_AUTOC_AN_RESTART;
365 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
368 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
369 (ixgbe_device_supports_autoneg_fc(hw))) {
370 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
371 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
374 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
380 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
381 * @hw: pointer to hardware structure
383 * Starts the hardware by filling the bus info structure and media type, clears
384 * all on chip counters, initializes receive address registers, multicast
385 * table, VLAN filter table, calls routine to set up link and flow control
386 * settings, and leaves transmit and receive units disabled and uninitialized
388 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
394 DEBUGFUNC("ixgbe_start_hw_generic");
396 /* Set the media type */
397 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
399 /* PHY ops initialization must be done in reset_hw() */
401 /* Clear the VLAN filter table */
402 hw->mac.ops.clear_vfta(hw);
404 /* Clear statistics registers */
405 hw->mac.ops.clear_hw_cntrs(hw);
407 /* Set No Snoop Disable */
408 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
409 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
410 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
411 IXGBE_WRITE_FLUSH(hw);
413 /* Setup flow control */
414 ret_val = ixgbe_setup_fc(hw);
415 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED)
418 /* Cache bit indicating need for crosstalk fix */
419 switch (hw->mac.type) {
420 case ixgbe_mac_82599EB:
421 case ixgbe_mac_X550EM_x:
422 case ixgbe_mac_X550EM_a:
423 hw->mac.ops.get_device_caps(hw, &device_caps);
424 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
425 hw->need_crosstalk_fix = false;
427 hw->need_crosstalk_fix = true;
430 hw->need_crosstalk_fix = false;
434 /* Clear adapter stopped flag */
435 hw->adapter_stopped = false;
437 return IXGBE_SUCCESS;
441 * ixgbe_start_hw_gen2 - Init sequence for common device family
442 * @hw: pointer to hw structure
444 * Performs the init sequence common to the second generation
446 * Devices in the second generation:
450 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
455 /* Clear the rate limiters */
456 for (i = 0; i < hw->mac.max_tx_queues; i++) {
457 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
458 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
460 IXGBE_WRITE_FLUSH(hw);
462 /* Disable relaxed ordering */
463 for (i = 0; i < hw->mac.max_tx_queues; i++) {
464 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
465 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
466 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
469 for (i = 0; i < hw->mac.max_rx_queues; i++) {
470 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
471 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
472 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
473 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
476 return IXGBE_SUCCESS;
480 * ixgbe_init_hw_generic - Generic hardware initialization
481 * @hw: pointer to hardware structure
483 * Initialize the hardware by resetting the hardware, filling the bus info
484 * structure and media type, clears all on chip counters, initializes receive
485 * address registers, multicast table, VLAN filter table, calls routine to set
486 * up link and flow control settings, and leaves transmit and receive units
487 * disabled and uninitialized
489 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
493 DEBUGFUNC("ixgbe_init_hw_generic");
495 /* Reset the hardware */
496 status = hw->mac.ops.reset_hw(hw);
498 if (status == IXGBE_SUCCESS) {
500 status = hw->mac.ops.start_hw(hw);
507 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
508 * @hw: pointer to hardware structure
510 * Clears all hardware statistics counters by reading them from the hardware
511 * Statistics counters are clear on read.
513 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
517 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
519 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
520 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
521 IXGBE_READ_REG(hw, IXGBE_ERRBC);
522 IXGBE_READ_REG(hw, IXGBE_MSPDC);
523 for (i = 0; i < 8; i++)
524 IXGBE_READ_REG(hw, IXGBE_MPC(i));
526 IXGBE_READ_REG(hw, IXGBE_MLFC);
527 IXGBE_READ_REG(hw, IXGBE_MRFC);
528 IXGBE_READ_REG(hw, IXGBE_RLEC);
529 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
530 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
531 if (hw->mac.type >= ixgbe_mac_82599EB) {
532 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
533 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
535 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
536 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
539 for (i = 0; i < 8; i++) {
540 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
541 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
542 if (hw->mac.type >= ixgbe_mac_82599EB) {
543 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
544 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
546 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
547 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
550 if (hw->mac.type >= ixgbe_mac_82599EB)
551 for (i = 0; i < 8; i++)
552 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
553 IXGBE_READ_REG(hw, IXGBE_PRC64);
554 IXGBE_READ_REG(hw, IXGBE_PRC127);
555 IXGBE_READ_REG(hw, IXGBE_PRC255);
556 IXGBE_READ_REG(hw, IXGBE_PRC511);
557 IXGBE_READ_REG(hw, IXGBE_PRC1023);
558 IXGBE_READ_REG(hw, IXGBE_PRC1522);
559 IXGBE_READ_REG(hw, IXGBE_GPRC);
560 IXGBE_READ_REG(hw, IXGBE_BPRC);
561 IXGBE_READ_REG(hw, IXGBE_MPRC);
562 IXGBE_READ_REG(hw, IXGBE_GPTC);
563 IXGBE_READ_REG(hw, IXGBE_GORCL);
564 IXGBE_READ_REG(hw, IXGBE_GORCH);
565 IXGBE_READ_REG(hw, IXGBE_GOTCL);
566 IXGBE_READ_REG(hw, IXGBE_GOTCH);
567 if (hw->mac.type == ixgbe_mac_82598EB)
568 for (i = 0; i < 8; i++)
569 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
570 IXGBE_READ_REG(hw, IXGBE_RUC);
571 IXGBE_READ_REG(hw, IXGBE_RFC);
572 IXGBE_READ_REG(hw, IXGBE_ROC);
573 IXGBE_READ_REG(hw, IXGBE_RJC);
574 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
575 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
576 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
577 IXGBE_READ_REG(hw, IXGBE_TORL);
578 IXGBE_READ_REG(hw, IXGBE_TORH);
579 IXGBE_READ_REG(hw, IXGBE_TPR);
580 IXGBE_READ_REG(hw, IXGBE_TPT);
581 IXGBE_READ_REG(hw, IXGBE_PTC64);
582 IXGBE_READ_REG(hw, IXGBE_PTC127);
583 IXGBE_READ_REG(hw, IXGBE_PTC255);
584 IXGBE_READ_REG(hw, IXGBE_PTC511);
585 IXGBE_READ_REG(hw, IXGBE_PTC1023);
586 IXGBE_READ_REG(hw, IXGBE_PTC1522);
587 IXGBE_READ_REG(hw, IXGBE_MPTC);
588 IXGBE_READ_REG(hw, IXGBE_BPTC);
589 for (i = 0; i < 16; i++) {
590 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
591 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
592 if (hw->mac.type >= ixgbe_mac_82599EB) {
593 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
594 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
595 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
596 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
597 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
599 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
600 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
604 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
606 ixgbe_identify_phy(hw);
607 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
608 IXGBE_MDIO_PCS_DEV_TYPE, &i);
609 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
610 IXGBE_MDIO_PCS_DEV_TYPE, &i);
611 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
612 IXGBE_MDIO_PCS_DEV_TYPE, &i);
613 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
614 IXGBE_MDIO_PCS_DEV_TYPE, &i);
617 return IXGBE_SUCCESS;
621 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
622 * @hw: pointer to hardware structure
623 * @pba_num: stores the part number string from the EEPROM
624 * @pba_num_size: part number string buffer length
626 * Reads the part number string from the EEPROM.
628 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
637 DEBUGFUNC("ixgbe_read_pba_string_generic");
639 if (pba_num == NULL) {
640 DEBUGOUT("PBA string buffer was null\n");
641 return IXGBE_ERR_INVALID_ARGUMENT;
644 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
646 DEBUGOUT("NVM Read Error\n");
650 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
652 DEBUGOUT("NVM Read Error\n");
657 * if data is not ptr guard the PBA must be in legacy format which
658 * means pba_ptr is actually our second data word for the PBA number
659 * and we can decode it into an ascii string
661 if (data != IXGBE_PBANUM_PTR_GUARD) {
662 DEBUGOUT("NVM PBA number is not stored as string\n");
664 /* we will need 11 characters to store the PBA */
665 if (pba_num_size < 11) {
666 DEBUGOUT("PBA string buffer too small\n");
667 return IXGBE_ERR_NO_SPACE;
670 /* extract hex string from data and pba_ptr */
671 pba_num[0] = (data >> 12) & 0xF;
672 pba_num[1] = (data >> 8) & 0xF;
673 pba_num[2] = (data >> 4) & 0xF;
674 pba_num[3] = data & 0xF;
675 pba_num[4] = (pba_ptr >> 12) & 0xF;
676 pba_num[5] = (pba_ptr >> 8) & 0xF;
679 pba_num[8] = (pba_ptr >> 4) & 0xF;
680 pba_num[9] = pba_ptr & 0xF;
682 /* put a null character on the end of our string */
685 /* switch all the data but the '-' to hex char */
686 for (offset = 0; offset < 10; offset++) {
687 if (pba_num[offset] < 0xA)
688 pba_num[offset] += '0';
689 else if (pba_num[offset] < 0x10)
690 pba_num[offset] += 'A' - 0xA;
693 return IXGBE_SUCCESS;
696 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
698 DEBUGOUT("NVM Read Error\n");
702 if (length == 0xFFFF || length == 0) {
703 DEBUGOUT("NVM PBA number section invalid length\n");
704 return IXGBE_ERR_PBA_SECTION;
707 /* check if pba_num buffer is big enough */
708 if (pba_num_size < (((u32)length * 2) - 1)) {
709 DEBUGOUT("PBA string buffer too small\n");
710 return IXGBE_ERR_NO_SPACE;
713 /* trim pba length from start of string */
717 for (offset = 0; offset < length; offset++) {
718 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
720 DEBUGOUT("NVM Read Error\n");
723 pba_num[offset * 2] = (u8)(data >> 8);
724 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
726 pba_num[offset * 2] = '\0';
728 return IXGBE_SUCCESS;
732 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
733 * @hw: pointer to hardware structure
734 * @pba_num: stores the part number from the EEPROM
736 * Reads the part number from the EEPROM.
738 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
743 DEBUGFUNC("ixgbe_read_pba_num_generic");
745 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
747 DEBUGOUT("NVM Read Error\n");
749 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
750 DEBUGOUT("NVM Not supported\n");
751 return IXGBE_NOT_IMPLEMENTED;
753 *pba_num = (u32)(data << 16);
755 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
757 DEBUGOUT("NVM Read Error\n");
762 return IXGBE_SUCCESS;
767 * @hw: pointer to the HW structure
768 * @eeprom_buf: optional pointer to EEPROM image
769 * @eeprom_buf_size: size of EEPROM image in words
770 * @max_pba_block_size: PBA block size limit
771 * @pba: pointer to output PBA structure
773 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
774 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
777 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
778 u32 eeprom_buf_size, u16 max_pba_block_size,
779 struct ixgbe_pba *pba)
785 return IXGBE_ERR_PARAM;
787 if (eeprom_buf == NULL) {
788 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
793 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
794 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
795 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
797 return IXGBE_ERR_PARAM;
801 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
802 if (pba->pba_block == NULL)
803 return IXGBE_ERR_PARAM;
805 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
811 if (pba_block_size > max_pba_block_size)
812 return IXGBE_ERR_PARAM;
814 if (eeprom_buf == NULL) {
815 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
821 if (eeprom_buf_size > (u32)(pba->word[1] +
823 memcpy(pba->pba_block,
824 &eeprom_buf[pba->word[1]],
825 pba_block_size * sizeof(u16));
827 return IXGBE_ERR_PARAM;
832 return IXGBE_SUCCESS;
836 * ixgbe_write_pba_raw
837 * @hw: pointer to the HW structure
838 * @eeprom_buf: optional pointer to EEPROM image
839 * @eeprom_buf_size: size of EEPROM image in words
840 * @pba: pointer to PBA structure
842 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
843 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
846 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
847 u32 eeprom_buf_size, struct ixgbe_pba *pba)
852 return IXGBE_ERR_PARAM;
854 if (eeprom_buf == NULL) {
855 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
860 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
861 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
862 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
864 return IXGBE_ERR_PARAM;
868 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
869 if (pba->pba_block == NULL)
870 return IXGBE_ERR_PARAM;
872 if (eeprom_buf == NULL) {
873 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
879 if (eeprom_buf_size > (u32)(pba->word[1] +
880 pba->pba_block[0])) {
881 memcpy(&eeprom_buf[pba->word[1]],
883 pba->pba_block[0] * sizeof(u16));
885 return IXGBE_ERR_PARAM;
890 return IXGBE_SUCCESS;
894 * ixgbe_get_pba_block_size
895 * @hw: pointer to the HW structure
896 * @eeprom_buf: optional pointer to EEPROM image
897 * @eeprom_buf_size: size of EEPROM image in words
898 * @pba_data_size: pointer to output variable
900 * Returns the size of the PBA block in words. Function operates on EEPROM
901 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
905 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
906 u32 eeprom_buf_size, u16 *pba_block_size)
912 DEBUGFUNC("ixgbe_get_pba_block_size");
914 if (eeprom_buf == NULL) {
915 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
920 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
921 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
922 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
924 return IXGBE_ERR_PARAM;
928 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
929 if (eeprom_buf == NULL) {
930 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
935 if (eeprom_buf_size > pba_word[1])
936 length = eeprom_buf[pba_word[1] + 0];
938 return IXGBE_ERR_PARAM;
941 if (length == 0xFFFF || length == 0)
942 return IXGBE_ERR_PBA_SECTION;
944 /* PBA number in legacy format, there is no PBA Block. */
948 if (pba_block_size != NULL)
949 *pba_block_size = length;
951 return IXGBE_SUCCESS;
955 * ixgbe_get_mac_addr_generic - Generic get MAC address
956 * @hw: pointer to hardware structure
957 * @mac_addr: Adapter MAC address
959 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
960 * A reset of the adapter must be performed prior to calling this function
961 * in order for the MAC address to have been loaded from the EEPROM into RAR0
963 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
969 DEBUGFUNC("ixgbe_get_mac_addr_generic");
971 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
972 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
974 for (i = 0; i < 4; i++)
975 mac_addr[i] = (u8)(rar_low >> (i*8));
977 for (i = 0; i < 2; i++)
978 mac_addr[i+4] = (u8)(rar_high >> (i*8));
980 return IXGBE_SUCCESS;
984 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
985 * @hw: pointer to hardware structure
986 * @link_status: the link status returned by the PCI config space
988 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
990 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
992 struct ixgbe_mac_info *mac = &hw->mac;
994 if (hw->bus.type == ixgbe_bus_type_unknown)
995 hw->bus.type = ixgbe_bus_type_pci_express;
997 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
998 case IXGBE_PCI_LINK_WIDTH_1:
999 hw->bus.width = ixgbe_bus_width_pcie_x1;
1001 case IXGBE_PCI_LINK_WIDTH_2:
1002 hw->bus.width = ixgbe_bus_width_pcie_x2;
1004 case IXGBE_PCI_LINK_WIDTH_4:
1005 hw->bus.width = ixgbe_bus_width_pcie_x4;
1007 case IXGBE_PCI_LINK_WIDTH_8:
1008 hw->bus.width = ixgbe_bus_width_pcie_x8;
1011 hw->bus.width = ixgbe_bus_width_unknown;
1015 switch (link_status & IXGBE_PCI_LINK_SPEED) {
1016 case IXGBE_PCI_LINK_SPEED_2500:
1017 hw->bus.speed = ixgbe_bus_speed_2500;
1019 case IXGBE_PCI_LINK_SPEED_5000:
1020 hw->bus.speed = ixgbe_bus_speed_5000;
1022 case IXGBE_PCI_LINK_SPEED_8000:
1023 hw->bus.speed = ixgbe_bus_speed_8000;
1026 hw->bus.speed = ixgbe_bus_speed_unknown;
1030 mac->ops.set_lan_id(hw);
1034 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1035 * @hw: pointer to hardware structure
1037 * Gets the PCI bus info (speed, width, type) then calls helper function to
1038 * store this data within the ixgbe_hw structure.
1040 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1044 DEBUGFUNC("ixgbe_get_bus_info_generic");
1046 /* Get the negotiated link width and speed from PCI config space */
1047 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1049 ixgbe_set_pci_config_data_generic(hw, link_status);
1051 return IXGBE_SUCCESS;
1055 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1056 * @hw: pointer to the HW structure
1058 * Determines the LAN function id by reading memory-mapped registers and swaps
1059 * the port value if requested, and set MAC instance for devices that share
1062 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1064 struct ixgbe_bus_info *bus = &hw->bus;
1068 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1070 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1071 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1072 bus->lan_id = (u8)bus->func;
1074 /* check for a port swap */
1075 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1076 if (reg & IXGBE_FACTPS_LFS)
1079 /* Get MAC instance from EEPROM for configuring CS4227 */
1080 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1081 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1082 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
1083 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
1088 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1089 * @hw: pointer to hardware structure
1091 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1092 * disables transmit and receive units. The adapter_stopped flag is used by
1093 * the shared code and drivers to determine if the adapter is in a stopped
1094 * state and should not touch the hardware.
1096 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1101 DEBUGFUNC("ixgbe_stop_adapter_generic");
1104 * Set the adapter_stopped flag so other driver functions stop touching
1107 hw->adapter_stopped = true;
1109 /* Disable the receive unit */
1110 ixgbe_disable_rx(hw);
1112 /* Clear interrupt mask to stop interrupts from being generated */
1113 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1115 /* Clear any pending interrupts, flush previous writes */
1116 IXGBE_READ_REG(hw, IXGBE_EICR);
1118 /* Disable the transmit unit. Each queue must be disabled. */
1119 for (i = 0; i < hw->mac.max_tx_queues; i++)
1120 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1122 /* Disable the receive unit by stopping each queue */
1123 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1124 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1125 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1126 reg_val |= IXGBE_RXDCTL_SWFLSH;
1127 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1130 /* flush all queues disables */
1131 IXGBE_WRITE_FLUSH(hw);
1135 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1136 * access and verify no pending requests
1138 return ixgbe_disable_pcie_master(hw);
1142 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1143 * @hw: pointer to hardware structure
1144 * @index: led number to turn on
1146 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1148 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1150 DEBUGFUNC("ixgbe_led_on_generic");
1153 return IXGBE_ERR_PARAM;
1155 /* To turn on the LED, set mode to ON. */
1156 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1157 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1158 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1159 IXGBE_WRITE_FLUSH(hw);
1161 return IXGBE_SUCCESS;
1165 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1166 * @hw: pointer to hardware structure
1167 * @index: led number to turn off
1169 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1171 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1173 DEBUGFUNC("ixgbe_led_off_generic");
1176 return IXGBE_ERR_PARAM;
1178 /* To turn off the LED, set mode to OFF. */
1179 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1180 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1181 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1182 IXGBE_WRITE_FLUSH(hw);
1184 return IXGBE_SUCCESS;
1188 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1189 * @hw: pointer to hardware structure
1191 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1192 * ixgbe_hw struct in order to set up EEPROM access.
1194 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1196 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1200 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1202 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1203 eeprom->type = ixgbe_eeprom_none;
1204 /* Set default semaphore delay to 10ms which is a well
1206 eeprom->semaphore_delay = 10;
1207 /* Clear EEPROM page size, it will be initialized as needed */
1208 eeprom->word_page_size = 0;
1211 * Check for EEPROM present first.
1212 * If not present leave as none
1214 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1215 if (eec & IXGBE_EEC_PRES) {
1216 eeprom->type = ixgbe_eeprom_spi;
1219 * SPI EEPROM is assumed here. This code would need to
1220 * change if a future EEPROM is not SPI.
1222 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1223 IXGBE_EEC_SIZE_SHIFT);
1224 eeprom->word_size = 1 << (eeprom_size +
1225 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1228 if (eec & IXGBE_EEC_ADDR_SIZE)
1229 eeprom->address_bits = 16;
1231 eeprom->address_bits = 8;
1232 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1233 "%d\n", eeprom->type, eeprom->word_size,
1234 eeprom->address_bits);
1237 return IXGBE_SUCCESS;
1241 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1242 * @hw: pointer to hardware structure
1243 * @offset: offset within the EEPROM to write
1244 * @words: number of word(s)
1245 * @data: 16 bit word(s) to write to EEPROM
1247 * Reads 16 bit word(s) from EEPROM through bit-bang method
1249 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1250 u16 words, u16 *data)
1252 s32 status = IXGBE_SUCCESS;
1255 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1257 hw->eeprom.ops.init_params(hw);
1260 status = IXGBE_ERR_INVALID_ARGUMENT;
1264 if (offset + words > hw->eeprom.word_size) {
1265 status = IXGBE_ERR_EEPROM;
1270 * The EEPROM page size cannot be queried from the chip. We do lazy
1271 * initialization. It is worth to do that when we write large buffer.
1273 if ((hw->eeprom.word_page_size == 0) &&
1274 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1275 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1278 * We cannot hold synchronization semaphores for too long
1279 * to avoid other entity starvation. However it is more efficient
1280 * to read in bursts than synchronizing access for each word.
1282 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1283 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1284 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1285 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1288 if (status != IXGBE_SUCCESS)
1297 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1298 * @hw: pointer to hardware structure
1299 * @offset: offset within the EEPROM to be written to
1300 * @words: number of word(s)
1301 * @data: 16 bit word(s) to be written to the EEPROM
1303 * If ixgbe_eeprom_update_checksum is not called after this function, the
1304 * EEPROM will most likely contain an invalid checksum.
1306 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1307 u16 words, u16 *data)
1313 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1315 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1317 /* Prepare the EEPROM for writing */
1318 status = ixgbe_acquire_eeprom(hw);
1320 if (status == IXGBE_SUCCESS) {
1321 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1322 ixgbe_release_eeprom(hw);
1323 status = IXGBE_ERR_EEPROM;
1327 if (status == IXGBE_SUCCESS) {
1328 for (i = 0; i < words; i++) {
1329 ixgbe_standby_eeprom(hw);
1331 /* Send the WRITE ENABLE command (8 bit opcode ) */
1332 ixgbe_shift_out_eeprom_bits(hw,
1333 IXGBE_EEPROM_WREN_OPCODE_SPI,
1334 IXGBE_EEPROM_OPCODE_BITS);
1336 ixgbe_standby_eeprom(hw);
1339 * Some SPI eeproms use the 8th address bit embedded
1342 if ((hw->eeprom.address_bits == 8) &&
1343 ((offset + i) >= 128))
1344 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1346 /* Send the Write command (8-bit opcode + addr) */
1347 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1348 IXGBE_EEPROM_OPCODE_BITS);
1349 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1350 hw->eeprom.address_bits);
1352 page_size = hw->eeprom.word_page_size;
1354 /* Send the data in burst via SPI*/
1357 word = (word >> 8) | (word << 8);
1358 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1363 /* do not wrap around page */
1364 if (((offset + i) & (page_size - 1)) ==
1367 } while (++i < words);
1369 ixgbe_standby_eeprom(hw);
1372 /* Done with writing - release the EEPROM */
1373 ixgbe_release_eeprom(hw);
1380 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1381 * @hw: pointer to hardware structure
1382 * @offset: offset within the EEPROM to be written to
1383 * @data: 16 bit word to be written to the EEPROM
1385 * If ixgbe_eeprom_update_checksum is not called after this function, the
1386 * EEPROM will most likely contain an invalid checksum.
1388 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1392 DEBUGFUNC("ixgbe_write_eeprom_generic");
1394 hw->eeprom.ops.init_params(hw);
1396 if (offset >= hw->eeprom.word_size) {
1397 status = IXGBE_ERR_EEPROM;
1401 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1408 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1409 * @hw: pointer to hardware structure
1410 * @offset: offset within the EEPROM to be read
1411 * @data: read 16 bit words(s) from EEPROM
1412 * @words: number of word(s)
1414 * Reads 16 bit word(s) from EEPROM through bit-bang method
1416 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1417 u16 words, u16 *data)
1419 s32 status = IXGBE_SUCCESS;
1422 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1424 hw->eeprom.ops.init_params(hw);
1427 status = IXGBE_ERR_INVALID_ARGUMENT;
1431 if (offset + words > hw->eeprom.word_size) {
1432 status = IXGBE_ERR_EEPROM;
1437 * We cannot hold synchronization semaphores for too long
1438 * to avoid other entity starvation. However it is more efficient
1439 * to read in bursts than synchronizing access for each word.
1441 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1442 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1443 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1445 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1448 if (status != IXGBE_SUCCESS)
1457 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1458 * @hw: pointer to hardware structure
1459 * @offset: offset within the EEPROM to be read
1460 * @words: number of word(s)
1461 * @data: read 16 bit word(s) from EEPROM
1463 * Reads 16 bit word(s) from EEPROM through bit-bang method
1465 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1466 u16 words, u16 *data)
1470 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1473 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1475 /* Prepare the EEPROM for reading */
1476 status = ixgbe_acquire_eeprom(hw);
1478 if (status == IXGBE_SUCCESS) {
1479 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1480 ixgbe_release_eeprom(hw);
1481 status = IXGBE_ERR_EEPROM;
1485 if (status == IXGBE_SUCCESS) {
1486 for (i = 0; i < words; i++) {
1487 ixgbe_standby_eeprom(hw);
1489 * Some SPI eeproms use the 8th address bit embedded
1492 if ((hw->eeprom.address_bits == 8) &&
1493 ((offset + i) >= 128))
1494 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1496 /* Send the READ command (opcode + addr) */
1497 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1498 IXGBE_EEPROM_OPCODE_BITS);
1499 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1500 hw->eeprom.address_bits);
1502 /* Read the data. */
1503 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1504 data[i] = (word_in >> 8) | (word_in << 8);
1507 /* End this read operation */
1508 ixgbe_release_eeprom(hw);
1515 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1516 * @hw: pointer to hardware structure
1517 * @offset: offset within the EEPROM to be read
1518 * @data: read 16 bit value from EEPROM
1520 * Reads 16 bit value from EEPROM through bit-bang method
1522 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1527 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1529 hw->eeprom.ops.init_params(hw);
1531 if (offset >= hw->eeprom.word_size) {
1532 status = IXGBE_ERR_EEPROM;
1536 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1543 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1544 * @hw: pointer to hardware structure
1545 * @offset: offset of word in the EEPROM to read
1546 * @words: number of word(s)
1547 * @data: 16 bit word(s) from the EEPROM
1549 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1551 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1552 u16 words, u16 *data)
1555 s32 status = IXGBE_SUCCESS;
1558 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1560 hw->eeprom.ops.init_params(hw);
1563 status = IXGBE_ERR_INVALID_ARGUMENT;
1564 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1568 if (offset >= hw->eeprom.word_size) {
1569 status = IXGBE_ERR_EEPROM;
1570 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1574 for (i = 0; i < words; i++) {
1575 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1576 IXGBE_EEPROM_RW_REG_START;
1578 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1579 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1581 if (status == IXGBE_SUCCESS) {
1582 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1583 IXGBE_EEPROM_RW_REG_DATA);
1585 DEBUGOUT("Eeprom read timed out\n");
1594 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1595 * @hw: pointer to hardware structure
1596 * @offset: offset within the EEPROM to be used as a scratch pad
1598 * Discover EEPROM page size by writing marching data at given offset.
1599 * This function is called only when we are writing a new large buffer
1600 * at given offset so the data would be overwritten anyway.
1602 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1605 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1606 s32 status = IXGBE_SUCCESS;
1609 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1611 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1614 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1615 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1616 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1617 hw->eeprom.word_page_size = 0;
1618 if (status != IXGBE_SUCCESS)
1621 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1622 if (status != IXGBE_SUCCESS)
1626 * When writing in burst more than the actual page size
1627 * EEPROM address wraps around current page.
1629 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1631 DEBUGOUT1("Detected EEPROM page size = %d words.",
1632 hw->eeprom.word_page_size);
1638 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1639 * @hw: pointer to hardware structure
1640 * @offset: offset of word in the EEPROM to read
1641 * @data: word read from the EEPROM
1643 * Reads a 16 bit word from the EEPROM using the EERD register.
1645 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1647 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1651 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1652 * @hw: pointer to hardware structure
1653 * @offset: offset of word in the EEPROM to write
1654 * @words: number of word(s)
1655 * @data: word(s) write to the EEPROM
1657 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1659 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1660 u16 words, u16 *data)
1663 s32 status = IXGBE_SUCCESS;
1666 DEBUGFUNC("ixgbe_write_eewr_generic");
1668 hw->eeprom.ops.init_params(hw);
1671 status = IXGBE_ERR_INVALID_ARGUMENT;
1672 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1676 if (offset >= hw->eeprom.word_size) {
1677 status = IXGBE_ERR_EEPROM;
1678 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1682 for (i = 0; i < words; i++) {
1683 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1684 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1685 IXGBE_EEPROM_RW_REG_START;
1687 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1688 if (status != IXGBE_SUCCESS) {
1689 DEBUGOUT("Eeprom write EEWR timed out\n");
1693 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1695 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1696 if (status != IXGBE_SUCCESS) {
1697 DEBUGOUT("Eeprom write EEWR timed out\n");
1707 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1708 * @hw: pointer to hardware structure
1709 * @offset: offset of word in the EEPROM to write
1710 * @data: word write to the EEPROM
1712 * Write a 16 bit word to the EEPROM using the EEWR register.
1714 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1716 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1720 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1721 * @hw: pointer to hardware structure
1722 * @ee_reg: EEPROM flag for polling
1724 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1725 * read or write is done respectively.
1727 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1731 s32 status = IXGBE_ERR_EEPROM;
1733 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1735 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1736 if (ee_reg == IXGBE_NVM_POLL_READ)
1737 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1739 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1741 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1742 status = IXGBE_SUCCESS;
1748 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1749 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1750 "EEPROM read/write done polling timed out");
1756 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1757 * @hw: pointer to hardware structure
1759 * Prepares EEPROM for access using bit-bang method. This function should
1760 * be called before issuing a command to the EEPROM.
1762 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1764 s32 status = IXGBE_SUCCESS;
1768 DEBUGFUNC("ixgbe_acquire_eeprom");
1770 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1772 status = IXGBE_ERR_SWFW_SYNC;
1774 if (status == IXGBE_SUCCESS) {
1775 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1777 /* Request EEPROM Access */
1778 eec |= IXGBE_EEC_REQ;
1779 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1781 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1782 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1783 if (eec & IXGBE_EEC_GNT)
1788 /* Release if grant not acquired */
1789 if (!(eec & IXGBE_EEC_GNT)) {
1790 eec &= ~IXGBE_EEC_REQ;
1791 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1792 DEBUGOUT("Could not acquire EEPROM grant\n");
1794 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1795 status = IXGBE_ERR_EEPROM;
1798 /* Setup EEPROM for Read/Write */
1799 if (status == IXGBE_SUCCESS) {
1800 /* Clear CS and SK */
1801 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1802 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1803 IXGBE_WRITE_FLUSH(hw);
1811 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1812 * @hw: pointer to hardware structure
1814 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1816 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1818 s32 status = IXGBE_ERR_EEPROM;
1823 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1826 /* Get SMBI software semaphore between device drivers first */
1827 for (i = 0; i < timeout; i++) {
1829 * If the SMBI bit is 0 when we read it, then the bit will be
1830 * set and we have the semaphore
1832 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1833 if (!(swsm & IXGBE_SWSM_SMBI)) {
1834 status = IXGBE_SUCCESS;
1841 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1844 * this release is particularly important because our attempts
1845 * above to get the semaphore may have succeeded, and if there
1846 * was a timeout, we should unconditionally clear the semaphore
1847 * bits to free the driver to make progress
1849 ixgbe_release_eeprom_semaphore(hw);
1854 * If the SMBI bit is 0 when we read it, then the bit will be
1855 * set and we have the semaphore
1857 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1858 if (!(swsm & IXGBE_SWSM_SMBI))
1859 status = IXGBE_SUCCESS;
1862 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1863 if (status == IXGBE_SUCCESS) {
1864 for (i = 0; i < timeout; i++) {
1865 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1867 /* Set the SW EEPROM semaphore bit to request access */
1868 swsm |= IXGBE_SWSM_SWESMBI;
1869 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1872 * If we set the bit successfully then we got the
1875 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1876 if (swsm & IXGBE_SWSM_SWESMBI)
1883 * Release semaphores and return error if SW EEPROM semaphore
1884 * was not granted because we don't have access to the EEPROM
1887 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1888 "SWESMBI Software EEPROM semaphore not granted.\n");
1889 ixgbe_release_eeprom_semaphore(hw);
1890 status = IXGBE_ERR_EEPROM;
1893 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1894 "Software semaphore SMBI between device drivers "
1902 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1903 * @hw: pointer to hardware structure
1905 * This function clears hardware semaphore bits.
1907 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1911 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1913 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1915 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1916 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1917 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1918 IXGBE_WRITE_FLUSH(hw);
1922 * ixgbe_ready_eeprom - Polls for EEPROM ready
1923 * @hw: pointer to hardware structure
1925 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1927 s32 status = IXGBE_SUCCESS;
1931 DEBUGFUNC("ixgbe_ready_eeprom");
1934 * Read "Status Register" repeatedly until the LSB is cleared. The
1935 * EEPROM will signal that the command has been completed by clearing
1936 * bit 0 of the internal status register. If it's not cleared within
1937 * 5 milliseconds, then error out.
1939 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1940 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1941 IXGBE_EEPROM_OPCODE_BITS);
1942 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1943 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1947 ixgbe_standby_eeprom(hw);
1951 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1952 * devices (and only 0-5mSec on 5V devices)
1954 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1955 DEBUGOUT("SPI EEPROM Status error\n");
1956 status = IXGBE_ERR_EEPROM;
1963 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1964 * @hw: pointer to hardware structure
1966 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1970 DEBUGFUNC("ixgbe_standby_eeprom");
1972 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1974 /* Toggle CS to flush commands */
1975 eec |= IXGBE_EEC_CS;
1976 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1977 IXGBE_WRITE_FLUSH(hw);
1979 eec &= ~IXGBE_EEC_CS;
1980 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1981 IXGBE_WRITE_FLUSH(hw);
1986 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1987 * @hw: pointer to hardware structure
1988 * @data: data to send to the EEPROM
1989 * @count: number of bits to shift out
1991 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1998 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
2000 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2003 * Mask is used to shift "count" bits of "data" out to the EEPROM
2004 * one bit at a time. Determine the starting bit based on count
2006 mask = 0x01 << (count - 1);
2008 for (i = 0; i < count; i++) {
2010 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
2011 * "1", and then raising and then lowering the clock (the SK
2012 * bit controls the clock input to the EEPROM). A "0" is
2013 * shifted out to the EEPROM by setting "DI" to "0" and then
2014 * raising and then lowering the clock.
2017 eec |= IXGBE_EEC_DI;
2019 eec &= ~IXGBE_EEC_DI;
2021 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2022 IXGBE_WRITE_FLUSH(hw);
2026 ixgbe_raise_eeprom_clk(hw, &eec);
2027 ixgbe_lower_eeprom_clk(hw, &eec);
2030 * Shift mask to signify next bit of data to shift in to the
2036 /* We leave the "DI" bit set to "0" when we leave this routine. */
2037 eec &= ~IXGBE_EEC_DI;
2038 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2039 IXGBE_WRITE_FLUSH(hw);
2043 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2044 * @hw: pointer to hardware structure
2046 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2052 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2055 * In order to read a register from the EEPROM, we need to shift
2056 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2057 * the clock input to the EEPROM (setting the SK bit), and then reading
2058 * the value of the "DO" bit. During this "shifting in" process the
2059 * "DI" bit should always be clear.
2061 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2063 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2065 for (i = 0; i < count; i++) {
2067 ixgbe_raise_eeprom_clk(hw, &eec);
2069 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2071 eec &= ~(IXGBE_EEC_DI);
2072 if (eec & IXGBE_EEC_DO)
2075 ixgbe_lower_eeprom_clk(hw, &eec);
2082 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2083 * @hw: pointer to hardware structure
2084 * @eec: EEC register's current value
2086 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2088 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2091 * Raise the clock input to the EEPROM
2092 * (setting the SK bit), then delay
2094 *eec = *eec | IXGBE_EEC_SK;
2095 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2096 IXGBE_WRITE_FLUSH(hw);
2101 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2102 * @hw: pointer to hardware structure
2103 * @eecd: EECD's current value
2105 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2107 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2110 * Lower the clock input to the EEPROM (clearing the SK bit), then
2113 *eec = *eec & ~IXGBE_EEC_SK;
2114 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2115 IXGBE_WRITE_FLUSH(hw);
2120 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2121 * @hw: pointer to hardware structure
2123 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2127 DEBUGFUNC("ixgbe_release_eeprom");
2129 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2131 eec |= IXGBE_EEC_CS; /* Pull CS high */
2132 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2134 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2135 IXGBE_WRITE_FLUSH(hw);
2139 /* Stop requesting EEPROM access */
2140 eec &= ~IXGBE_EEC_REQ;
2141 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2143 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2145 /* Delay before attempt to obtain semaphore again to allow FW access */
2146 msec_delay(hw->eeprom.semaphore_delay);
2150 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2151 * @hw: pointer to hardware structure
2153 * Returns a negative error code on error, or the 16-bit checksum
2155 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2164 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2166 /* Include 0x0-0x3F in the checksum */
2167 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2168 if (hw->eeprom.ops.read(hw, i, &word)) {
2169 DEBUGOUT("EEPROM read failed\n");
2170 return IXGBE_ERR_EEPROM;
2175 /* Include all data from pointers except for the fw pointer */
2176 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2177 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2178 DEBUGOUT("EEPROM read failed\n");
2179 return IXGBE_ERR_EEPROM;
2182 /* If the pointer seems invalid */
2183 if (pointer == 0xFFFF || pointer == 0)
2186 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2187 DEBUGOUT("EEPROM read failed\n");
2188 return IXGBE_ERR_EEPROM;
2191 if (length == 0xFFFF || length == 0)
2194 for (j = pointer + 1; j <= pointer + length; j++) {
2195 if (hw->eeprom.ops.read(hw, j, &word)) {
2196 DEBUGOUT("EEPROM read failed\n");
2197 return IXGBE_ERR_EEPROM;
2203 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2205 return (s32)checksum;
2209 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2210 * @hw: pointer to hardware structure
2211 * @checksum_val: calculated checksum
2213 * Performs checksum calculation and validates the EEPROM checksum. If the
2214 * caller does not need checksum_val, the value can be NULL.
2216 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2221 u16 read_checksum = 0;
2223 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2225 /* Read the first word from the EEPROM. If this times out or fails, do
2226 * not continue or we could be in for a very long wait while every
2229 status = hw->eeprom.ops.read(hw, 0, &checksum);
2231 DEBUGOUT("EEPROM read failed\n");
2235 status = hw->eeprom.ops.calc_checksum(hw);
2239 checksum = (u16)(status & 0xffff);
2241 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2243 DEBUGOUT("EEPROM read failed\n");
2247 /* Verify read checksum from EEPROM is the same as
2248 * calculated checksum
2250 if (read_checksum != checksum)
2251 status = IXGBE_ERR_EEPROM_CHECKSUM;
2253 /* If the user cares, return the calculated checksum */
2255 *checksum_val = checksum;
2261 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2262 * @hw: pointer to hardware structure
2264 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2269 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2271 /* Read the first word from the EEPROM. If this times out or fails, do
2272 * not continue or we could be in for a very long wait while every
2275 status = hw->eeprom.ops.read(hw, 0, &checksum);
2277 DEBUGOUT("EEPROM read failed\n");
2281 status = hw->eeprom.ops.calc_checksum(hw);
2285 checksum = (u16)(status & 0xffff);
2287 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2293 * ixgbe_validate_mac_addr - Validate MAC address
2294 * @mac_addr: pointer to MAC address.
2296 * Tests a MAC address to ensure it is a valid Individual Address.
2298 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2300 s32 status = IXGBE_SUCCESS;
2302 DEBUGFUNC("ixgbe_validate_mac_addr");
2304 /* Make sure it is not a multicast address */
2305 if (IXGBE_IS_MULTICAST(mac_addr)) {
2306 status = IXGBE_ERR_INVALID_MAC_ADDR;
2307 /* Not a broadcast address */
2308 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2309 status = IXGBE_ERR_INVALID_MAC_ADDR;
2310 /* Reject the zero address */
2311 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2312 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2313 status = IXGBE_ERR_INVALID_MAC_ADDR;
2319 * ixgbe_set_rar_generic - Set Rx address register
2320 * @hw: pointer to hardware structure
2321 * @index: Receive address register to write
2322 * @addr: Address to put into receive address register
2323 * @vmdq: VMDq "set" or "pool" index
2324 * @enable_addr: set flag that address is active
2326 * Puts an ethernet address into a receive address register.
2328 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2331 u32 rar_low, rar_high;
2332 u32 rar_entries = hw->mac.num_rar_entries;
2334 DEBUGFUNC("ixgbe_set_rar_generic");
2336 /* Make sure we are using a valid rar index range */
2337 if (index >= rar_entries) {
2338 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2339 "RAR index %d is out of range.\n", index);
2340 return IXGBE_ERR_INVALID_ARGUMENT;
2343 /* setup VMDq pool selection before this RAR gets enabled */
2344 hw->mac.ops.set_vmdq(hw, index, vmdq);
2347 * HW expects these in little endian so we reverse the byte
2348 * order from network order (big endian) to little endian
2350 rar_low = ((u32)addr[0] |
2351 ((u32)addr[1] << 8) |
2352 ((u32)addr[2] << 16) |
2353 ((u32)addr[3] << 24));
2355 * Some parts put the VMDq setting in the extra RAH bits,
2356 * so save everything except the lower 16 bits that hold part
2357 * of the address and the address valid bit.
2359 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2360 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2361 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2363 if (enable_addr != 0)
2364 rar_high |= IXGBE_RAH_AV;
2366 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2367 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2369 return IXGBE_SUCCESS;
2373 * ixgbe_clear_rar_generic - Remove Rx address register
2374 * @hw: pointer to hardware structure
2375 * @index: Receive address register to write
2377 * Clears an ethernet address from a receive address register.
2379 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2382 u32 rar_entries = hw->mac.num_rar_entries;
2384 DEBUGFUNC("ixgbe_clear_rar_generic");
2386 /* Make sure we are using a valid rar index range */
2387 if (index >= rar_entries) {
2388 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2389 "RAR index %d is out of range.\n", index);
2390 return IXGBE_ERR_INVALID_ARGUMENT;
2394 * Some parts put the VMDq setting in the extra RAH bits,
2395 * so save everything except the lower 16 bits that hold part
2396 * of the address and the address valid bit.
2398 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2399 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2401 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2402 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2404 /* clear VMDq pool/queue selection for this RAR */
2405 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2407 return IXGBE_SUCCESS;
2411 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2412 * @hw: pointer to hardware structure
2414 * Places the MAC address in receive address register 0 and clears the rest
2415 * of the receive address registers. Clears the multicast table. Assumes
2416 * the receiver is in reset when the routine is called.
2418 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2421 u32 rar_entries = hw->mac.num_rar_entries;
2423 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2426 * If the current mac address is valid, assume it is a software override
2427 * to the permanent address.
2428 * Otherwise, use the permanent address from the eeprom.
2430 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2431 IXGBE_ERR_INVALID_MAC_ADDR) {
2432 /* Get the MAC address from the RAR0 for later reference */
2433 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2435 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2436 hw->mac.addr[0], hw->mac.addr[1],
2438 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2439 hw->mac.addr[4], hw->mac.addr[5]);
2441 /* Setup the receive address. */
2442 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2443 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2444 hw->mac.addr[0], hw->mac.addr[1],
2446 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2447 hw->mac.addr[4], hw->mac.addr[5]);
2449 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2452 /* clear VMDq pool/queue selection for RAR 0 */
2453 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2455 hw->addr_ctrl.overflow_promisc = 0;
2457 hw->addr_ctrl.rar_used_count = 1;
2459 /* Zero out the other receive addresses. */
2460 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2461 for (i = 1; i < rar_entries; i++) {
2462 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2463 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2467 hw->addr_ctrl.mta_in_use = 0;
2468 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2470 DEBUGOUT(" Clearing MTA\n");
2471 for (i = 0; i < hw->mac.mcft_size; i++)
2472 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2474 ixgbe_init_uta_tables(hw);
2476 return IXGBE_SUCCESS;
2480 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2481 * @hw: pointer to hardware structure
2482 * @addr: new address
2484 * Adds it to unused receive address register or goes into promiscuous mode.
2486 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2488 u32 rar_entries = hw->mac.num_rar_entries;
2491 DEBUGFUNC("ixgbe_add_uc_addr");
2493 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2494 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2497 * Place this address in the RAR if there is room,
2498 * else put the controller into promiscuous mode
2500 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2501 rar = hw->addr_ctrl.rar_used_count;
2502 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2503 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2504 hw->addr_ctrl.rar_used_count++;
2506 hw->addr_ctrl.overflow_promisc++;
2509 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2513 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2514 * @hw: pointer to hardware structure
2515 * @addr_list: the list of new addresses
2516 * @addr_count: number of addresses
2517 * @next: iterator function to walk the address list
2519 * The given list replaces any existing list. Clears the secondary addrs from
2520 * receive address registers. Uses unused receive address registers for the
2521 * first secondary addresses, and falls back to promiscuous mode as needed.
2523 * Drivers using secondary unicast addresses must set user_set_promisc when
2524 * manually putting the device into promiscuous mode.
2526 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2527 u32 addr_count, ixgbe_mc_addr_itr next)
2531 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2536 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2539 * Clear accounting of old secondary address list,
2540 * don't count RAR[0]
2542 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2543 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2544 hw->addr_ctrl.overflow_promisc = 0;
2546 /* Zero out the other receive addresses */
2547 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2548 for (i = 0; i < uc_addr_in_use; i++) {
2549 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2550 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2553 /* Add the new addresses */
2554 for (i = 0; i < addr_count; i++) {
2555 DEBUGOUT(" Adding the secondary addresses:\n");
2556 addr = next(hw, &addr_list, &vmdq);
2557 ixgbe_add_uc_addr(hw, addr, vmdq);
2560 if (hw->addr_ctrl.overflow_promisc) {
2561 /* enable promisc if not already in overflow or set by user */
2562 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2563 DEBUGOUT(" Entering address overflow promisc mode\n");
2564 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2565 fctrl |= IXGBE_FCTRL_UPE;
2566 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2569 /* only disable if set by overflow, not by user */
2570 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2571 DEBUGOUT(" Leaving address overflow promisc mode\n");
2572 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2573 fctrl &= ~IXGBE_FCTRL_UPE;
2574 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2578 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2579 return IXGBE_SUCCESS;
2583 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2584 * @hw: pointer to hardware structure
2585 * @mc_addr: the multicast address
2587 * Extracts the 12 bits, from a multicast address, to determine which
2588 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2589 * incoming rx multicast addresses, to determine the bit-vector to check in
2590 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2591 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2592 * to mc_filter_type.
2594 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2598 DEBUGFUNC("ixgbe_mta_vector");
2600 switch (hw->mac.mc_filter_type) {
2601 case 0: /* use bits [47:36] of the address */
2602 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2604 case 1: /* use bits [46:35] of the address */
2605 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2607 case 2: /* use bits [45:34] of the address */
2608 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2610 case 3: /* use bits [43:32] of the address */
2611 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2613 default: /* Invalid mc_filter_type */
2614 DEBUGOUT("MC filter type param set incorrectly\n");
2619 /* vector can only be 12-bits or boundary will be exceeded */
2625 * ixgbe_set_mta - Set bit-vector in multicast table
2626 * @hw: pointer to hardware structure
2627 * @hash_value: Multicast address hash value
2629 * Sets the bit-vector in the multicast table.
2631 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2637 DEBUGFUNC("ixgbe_set_mta");
2639 hw->addr_ctrl.mta_in_use++;
2641 vector = ixgbe_mta_vector(hw, mc_addr);
2642 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2645 * The MTA is a register array of 128 32-bit registers. It is treated
2646 * like an array of 4096 bits. We want to set bit
2647 * BitArray[vector_value]. So we figure out what register the bit is
2648 * in, read it, OR in the new bit, then write back the new value. The
2649 * register is determined by the upper 7 bits of the vector value and
2650 * the bit within that register are determined by the lower 5 bits of
2653 vector_reg = (vector >> 5) & 0x7F;
2654 vector_bit = vector & 0x1F;
2655 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2659 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2660 * @hw: pointer to hardware structure
2661 * @mc_addr_list: the list of new multicast addresses
2662 * @mc_addr_count: number of addresses
2663 * @next: iterator function to walk the multicast address list
2664 * @clear: flag, when set clears the table beforehand
2666 * When the clear flag is set, the given list replaces any existing list.
2667 * Hashes the given addresses into the multicast table.
2669 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2670 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2676 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2679 * Set the new number of MC addresses that we are being requested to
2682 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2683 hw->addr_ctrl.mta_in_use = 0;
2685 /* Clear mta_shadow */
2687 DEBUGOUT(" Clearing MTA\n");
2688 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2691 /* Update mta_shadow */
2692 for (i = 0; i < mc_addr_count; i++) {
2693 DEBUGOUT(" Adding the multicast addresses:\n");
2694 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2698 for (i = 0; i < hw->mac.mcft_size; i++)
2699 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2700 hw->mac.mta_shadow[i]);
2702 if (hw->addr_ctrl.mta_in_use > 0)
2703 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2704 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2706 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2707 return IXGBE_SUCCESS;
2711 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2712 * @hw: pointer to hardware structure
2714 * Enables multicast address in RAR and the use of the multicast hash table.
2716 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2718 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2720 DEBUGFUNC("ixgbe_enable_mc_generic");
2722 if (a->mta_in_use > 0)
2723 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2724 hw->mac.mc_filter_type);
2726 return IXGBE_SUCCESS;
2730 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2731 * @hw: pointer to hardware structure
2733 * Disables multicast address in RAR and the use of the multicast hash table.
2735 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2737 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2739 DEBUGFUNC("ixgbe_disable_mc_generic");
2741 if (a->mta_in_use > 0)
2742 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2744 return IXGBE_SUCCESS;
2748 * ixgbe_fc_enable_generic - Enable flow control
2749 * @hw: pointer to hardware structure
2751 * Enable flow control according to the current settings.
2753 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2755 s32 ret_val = IXGBE_SUCCESS;
2756 u32 mflcn_reg, fccfg_reg;
2761 DEBUGFUNC("ixgbe_fc_enable_generic");
2763 /* Validate the water mark configuration */
2764 if (!hw->fc.pause_time) {
2765 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2769 /* Low water mark of zero causes XOFF floods */
2770 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2771 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2772 hw->fc.high_water[i]) {
2773 if (!hw->fc.low_water[i] ||
2774 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2775 DEBUGOUT("Invalid water mark configuration\n");
2776 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2782 /* Negotiate the fc mode to use */
2783 hw->mac.ops.fc_autoneg(hw);
2785 /* Disable any previous flow control settings */
2786 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2787 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2789 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2790 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2793 * The possible values of fc.current_mode are:
2794 * 0: Flow control is completely disabled
2795 * 1: Rx flow control is enabled (we can receive pause frames,
2796 * but not send pause frames).
2797 * 2: Tx flow control is enabled (we can send pause frames but
2798 * we do not support receiving pause frames).
2799 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2802 switch (hw->fc.current_mode) {
2805 * Flow control is disabled by software override or autoneg.
2806 * The code below will actually disable it in the HW.
2809 case ixgbe_fc_rx_pause:
2811 * Rx Flow control is enabled and Tx Flow control is
2812 * disabled by software override. Since there really
2813 * isn't a way to advertise that we are capable of RX
2814 * Pause ONLY, we will advertise that we support both
2815 * symmetric and asymmetric Rx PAUSE. Later, we will
2816 * disable the adapter's ability to send PAUSE frames.
2818 mflcn_reg |= IXGBE_MFLCN_RFCE;
2820 case ixgbe_fc_tx_pause:
2822 * Tx Flow control is enabled, and Rx Flow control is
2823 * disabled by software override.
2825 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2828 /* Flow control (both Rx and Tx) is enabled by SW override. */
2829 mflcn_reg |= IXGBE_MFLCN_RFCE;
2830 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2833 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2834 "Flow control param set incorrectly\n");
2835 ret_val = IXGBE_ERR_CONFIG;
2840 /* Set 802.3x based flow control settings. */
2841 mflcn_reg |= IXGBE_MFLCN_DPF;
2842 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2843 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2846 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2847 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2848 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2849 hw->fc.high_water[i]) {
2850 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2851 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2852 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2854 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2856 * In order to prevent Tx hangs when the internal Tx
2857 * switch is enabled we must set the high water mark
2858 * to the Rx packet buffer size - 24KB. This allows
2859 * the Tx switch to function even under heavy Rx
2862 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2865 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2868 /* Configure pause time (2 TCs per register) */
2869 reg = hw->fc.pause_time * 0x00010001;
2870 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2871 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2873 /* Configure flow control refresh threshold value */
2874 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2881 * ixgbe_negotiate_fc - Negotiate flow control
2882 * @hw: pointer to hardware structure
2883 * @adv_reg: flow control advertised settings
2884 * @lp_reg: link partner's flow control settings
2885 * @adv_sym: symmetric pause bit in advertisement
2886 * @adv_asm: asymmetric pause bit in advertisement
2887 * @lp_sym: symmetric pause bit in link partner advertisement
2888 * @lp_asm: asymmetric pause bit in link partner advertisement
2890 * Find the intersection between advertised settings and link partner's
2891 * advertised settings
2893 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2894 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2896 if ((!(adv_reg)) || (!(lp_reg))) {
2897 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2898 "Local or link partner's advertised flow control "
2899 "settings are NULL. Local: %x, link partner: %x\n",
2901 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2904 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2906 * Now we need to check if the user selected Rx ONLY
2907 * of pause frames. In this case, we had to advertise
2908 * FULL flow control because we could not advertise RX
2909 * ONLY. Hence, we must now check to see if we need to
2910 * turn OFF the TRANSMISSION of PAUSE frames.
2912 if (hw->fc.requested_mode == ixgbe_fc_full) {
2913 hw->fc.current_mode = ixgbe_fc_full;
2914 DEBUGOUT("Flow Control = FULL.\n");
2916 hw->fc.current_mode = ixgbe_fc_rx_pause;
2917 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2919 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2920 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2921 hw->fc.current_mode = ixgbe_fc_tx_pause;
2922 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2923 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2924 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2925 hw->fc.current_mode = ixgbe_fc_rx_pause;
2926 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2928 hw->fc.current_mode = ixgbe_fc_none;
2929 DEBUGOUT("Flow Control = NONE.\n");
2931 return IXGBE_SUCCESS;
2935 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2936 * @hw: pointer to hardware structure
2938 * Enable flow control according on 1 gig fiber.
2940 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2942 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2943 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2946 * On multispeed fiber at 1g, bail out if
2947 * - link is up but AN did not complete, or if
2948 * - link is up and AN completed but timed out
2951 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2952 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2953 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2954 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
2958 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2959 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2961 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2962 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2963 IXGBE_PCS1GANA_ASM_PAUSE,
2964 IXGBE_PCS1GANA_SYM_PAUSE,
2965 IXGBE_PCS1GANA_ASM_PAUSE);
2972 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2973 * @hw: pointer to hardware structure
2975 * Enable flow control according to IEEE clause 37.
2977 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2979 u32 links2, anlp1_reg, autoc_reg, links;
2980 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2983 * On backplane, bail out if
2984 * - backplane autoneg was not completed, or if
2985 * - we are 82599 and link partner is not AN enabled
2987 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2988 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2989 DEBUGOUT("Auto-Negotiation did not complete\n");
2993 if (hw->mac.type == ixgbe_mac_82599EB) {
2994 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2995 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2996 DEBUGOUT("Link partner is not AN enabled\n");
3001 * Read the 10g AN autoc and LP ability registers and resolve
3002 * local flow control settings accordingly
3004 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3005 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
3007 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
3008 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
3009 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
3016 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
3017 * @hw: pointer to hardware structure
3019 * Enable flow control according to IEEE clause 37.
3021 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
3023 u16 technology_ability_reg = 0;
3024 u16 lp_technology_ability_reg = 0;
3026 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3027 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3028 &technology_ability_reg);
3029 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3030 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3031 &lp_technology_ability_reg);
3033 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
3034 (u32)lp_technology_ability_reg,
3035 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
3036 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
3040 * ixgbe_fc_autoneg - Configure flow control
3041 * @hw: pointer to hardware structure
3043 * Compares our advertised flow control capabilities to those advertised by
3044 * our link partner, and determines the proper flow control mode to use.
3046 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3048 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3049 ixgbe_link_speed speed;
3052 DEBUGFUNC("ixgbe_fc_autoneg");
3055 * AN should have completed when the cable was plugged in.
3056 * Look for reasons to bail out. Bail out if:
3057 * - FC autoneg is disabled, or if
3060 if (hw->fc.disable_fc_autoneg) {
3061 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3062 "Flow control autoneg is disabled");
3066 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3068 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3072 switch (hw->phy.media_type) {
3073 /* Autoneg flow control on fiber adapters */
3074 case ixgbe_media_type_fiber_fixed:
3075 case ixgbe_media_type_fiber_qsfp:
3076 case ixgbe_media_type_fiber:
3077 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3078 ret_val = ixgbe_fc_autoneg_fiber(hw);
3081 /* Autoneg flow control on backplane adapters */
3082 case ixgbe_media_type_backplane:
3083 ret_val = ixgbe_fc_autoneg_backplane(hw);
3086 /* Autoneg flow control on copper adapters */
3087 case ixgbe_media_type_copper:
3088 if (ixgbe_device_supports_autoneg_fc(hw))
3089 ret_val = ixgbe_fc_autoneg_copper(hw);
3097 if (ret_val == IXGBE_SUCCESS) {
3098 hw->fc.fc_was_autonegged = true;
3100 hw->fc.fc_was_autonegged = false;
3101 hw->fc.current_mode = hw->fc.requested_mode;
3106 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3107 * @hw: pointer to hardware structure
3109 * System-wide timeout range is encoded in PCIe Device Control2 register.
3111 * Add 10% to specified maximum and return the number of times to poll for
3112 * completion timeout, in units of 100 microsec. Never return less than
3113 * 800 = 80 millisec.
3115 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3120 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3121 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3124 case IXGBE_PCIDEVCTRL2_65_130ms:
3125 pollcnt = 1300; /* 130 millisec */
3127 case IXGBE_PCIDEVCTRL2_260_520ms:
3128 pollcnt = 5200; /* 520 millisec */
3130 case IXGBE_PCIDEVCTRL2_1_2s:
3131 pollcnt = 20000; /* 2 sec */
3133 case IXGBE_PCIDEVCTRL2_4_8s:
3134 pollcnt = 80000; /* 8 sec */
3136 case IXGBE_PCIDEVCTRL2_17_34s:
3137 pollcnt = 34000; /* 34 sec */
3139 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3140 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3141 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3142 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3144 pollcnt = 800; /* 80 millisec minimum */
3148 /* add 10% to spec maximum */
3149 return (pollcnt * 11) / 10;
3153 * ixgbe_disable_pcie_master - Disable PCI-express master access
3154 * @hw: pointer to hardware structure
3156 * Disables PCI-Express master access and verifies there are no pending
3157 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3158 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3159 * is returned signifying master requests disabled.
3161 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3163 s32 status = IXGBE_SUCCESS;
3167 DEBUGFUNC("ixgbe_disable_pcie_master");
3169 /* Always set this bit to ensure any future transactions are blocked */
3170 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3172 /* Exit if master requests are blocked */
3173 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3174 IXGBE_REMOVED(hw->hw_addr))
3177 /* Poll for master request bit to clear */
3178 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3180 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3185 * Two consecutive resets are required via CTRL.RST per datasheet
3186 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3187 * of this need. The first reset prevents new master requests from
3188 * being issued by our device. We then must wait 1usec or more for any
3189 * remaining completions from the PCIe bus to trickle in, and then reset
3190 * again to clear out any effects they may have had on our device.
3192 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3193 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3195 if (hw->mac.type >= ixgbe_mac_X550)
3199 * Before proceeding, make sure that the PCIe block does not have
3200 * transactions pending.
3202 poll = ixgbe_pcie_timeout_poll(hw);
3203 for (i = 0; i < poll; i++) {
3205 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3206 if (IXGBE_REMOVED(hw->hw_addr))
3208 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3212 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3213 "PCIe transaction pending bit also did not clear.\n");
3214 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3221 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3222 * @hw: pointer to hardware structure
3223 * @mask: Mask to specify which semaphore to acquire
3225 * Acquires the SWFW semaphore through the GSSR register for the specified
3226 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3228 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3232 u32 fwmask = mask << 5;
3236 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3238 for (i = 0; i < timeout; i++) {
3240 * SW NVM semaphore bit is used for access to all
3241 * SW_FW_SYNC bits (not just NVM)
3243 if (ixgbe_get_eeprom_semaphore(hw))
3244 return IXGBE_ERR_SWFW_SYNC;
3246 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3247 if (!(gssr & (fwmask | swmask))) {
3249 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3250 ixgbe_release_eeprom_semaphore(hw);
3251 return IXGBE_SUCCESS;
3253 /* Resource is currently in use by FW or SW */
3254 ixgbe_release_eeprom_semaphore(hw);
3259 /* If time expired clear the bits holding the lock and retry */
3260 if (gssr & (fwmask | swmask))
3261 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3264 return IXGBE_ERR_SWFW_SYNC;
3268 * ixgbe_release_swfw_sync - Release SWFW semaphore
3269 * @hw: pointer to hardware structure
3270 * @mask: Mask to specify which semaphore to release
3272 * Releases the SWFW semaphore through the GSSR register for the specified
3273 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3275 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3280 DEBUGFUNC("ixgbe_release_swfw_sync");
3282 ixgbe_get_eeprom_semaphore(hw);
3284 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3286 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3288 ixgbe_release_eeprom_semaphore(hw);
3292 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3293 * @hw: pointer to hardware structure
3295 * Stops the receive data path and waits for the HW to internally empty
3296 * the Rx security block
3298 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3300 #define IXGBE_MAX_SECRX_POLL 40
3305 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3308 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3309 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3310 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3311 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3312 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3313 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3316 /* Use interrupt-safe sleep just in case */
3320 /* For informational purposes only */
3321 if (i >= IXGBE_MAX_SECRX_POLL)
3322 DEBUGOUT("Rx unit being enabled before security "
3323 "path fully disabled. Continuing with init.\n");
3325 return IXGBE_SUCCESS;
3329 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3330 * @hw: pointer to hardware structure
3331 * @reg_val: Value we read from AUTOC
3333 * The default case requires no protection so just to the register read.
3335 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3338 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3339 return IXGBE_SUCCESS;
3343 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3344 * @hw: pointer to hardware structure
3345 * @reg_val: value to write to AUTOC
3346 * @locked: bool to indicate whether the SW/FW lock was already taken by
3349 * The default case requires no protection so just to the register write.
3351 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3353 UNREFERENCED_1PARAMETER(locked);
3355 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3356 return IXGBE_SUCCESS;
3360 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3361 * @hw: pointer to hardware structure
3363 * Enables the receive data path.
3365 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3369 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3371 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3372 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3373 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3374 IXGBE_WRITE_FLUSH(hw);
3376 return IXGBE_SUCCESS;
3380 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3381 * @hw: pointer to hardware structure
3382 * @regval: register value to write to RXCTRL
3384 * Enables the Rx DMA unit
3386 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3388 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3390 if (regval & IXGBE_RXCTRL_RXEN)
3391 ixgbe_enable_rx(hw);
3393 ixgbe_disable_rx(hw);
3395 return IXGBE_SUCCESS;
3399 * ixgbe_blink_led_start_generic - Blink LED based on index.
3400 * @hw: pointer to hardware structure
3401 * @index: led number to blink
3403 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3405 ixgbe_link_speed speed = 0;
3408 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3409 s32 ret_val = IXGBE_SUCCESS;
3410 bool locked = false;
3412 DEBUGFUNC("ixgbe_blink_led_start_generic");
3415 return IXGBE_ERR_PARAM;
3418 * Link must be up to auto-blink the LEDs;
3419 * Force it if link is down.
3421 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3424 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3425 if (ret_val != IXGBE_SUCCESS)
3428 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3429 autoc_reg |= IXGBE_AUTOC_FLU;
3431 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3432 if (ret_val != IXGBE_SUCCESS)
3435 IXGBE_WRITE_FLUSH(hw);
3439 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3440 led_reg |= IXGBE_LED_BLINK(index);
3441 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3442 IXGBE_WRITE_FLUSH(hw);
3449 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3450 * @hw: pointer to hardware structure
3451 * @index: led number to stop blinking
3453 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3456 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3457 s32 ret_val = IXGBE_SUCCESS;
3458 bool locked = false;
3460 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3463 return IXGBE_ERR_PARAM;
3466 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3467 if (ret_val != IXGBE_SUCCESS)
3470 autoc_reg &= ~IXGBE_AUTOC_FLU;
3471 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3473 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3474 if (ret_val != IXGBE_SUCCESS)
3477 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3478 led_reg &= ~IXGBE_LED_BLINK(index);
3479 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3480 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3481 IXGBE_WRITE_FLUSH(hw);
3488 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3489 * @hw: pointer to hardware structure
3490 * @san_mac_offset: SAN MAC address offset
3492 * This function will read the EEPROM location for the SAN MAC address
3493 * pointer, and returns the value at that location. This is used in both
3494 * get and set mac_addr routines.
3496 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3497 u16 *san_mac_offset)
3501 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3504 * First read the EEPROM pointer to see if the MAC addresses are
3507 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3510 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3511 "eeprom at offset %d failed",
3512 IXGBE_SAN_MAC_ADDR_PTR);
3519 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3520 * @hw: pointer to hardware structure
3521 * @san_mac_addr: SAN MAC address
3523 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3524 * per-port, so set_lan_id() must be called before reading the addresses.
3525 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3526 * upon for non-SFP connections, so we must call it here.
3528 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3530 u16 san_mac_data, san_mac_offset;
3534 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3537 * First read the EEPROM pointer to see if the MAC addresses are
3538 * available. If they're not, no point in calling set_lan_id() here.
3540 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3541 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3542 goto san_mac_addr_out;
3544 /* make sure we know which port we need to program */
3545 hw->mac.ops.set_lan_id(hw);
3546 /* apply the port offset to the address offset */
3547 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3548 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3549 for (i = 0; i < 3; i++) {
3550 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3553 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3554 "eeprom read at offset %d failed",
3556 goto san_mac_addr_out;
3558 san_mac_addr[i * 2] = (u8)(san_mac_data);
3559 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3562 return IXGBE_SUCCESS;
3566 * No addresses available in this EEPROM. It's not an
3567 * error though, so just wipe the local address and return.
3569 for (i = 0; i < 6; i++)
3570 san_mac_addr[i] = 0xFF;
3571 return IXGBE_SUCCESS;
3575 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3576 * @hw: pointer to hardware structure
3577 * @san_mac_addr: SAN MAC address
3579 * Write a SAN MAC address to the EEPROM.
3581 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3584 u16 san_mac_data, san_mac_offset;
3587 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3589 /* Look for SAN mac address pointer. If not defined, return */
3590 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3591 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3592 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3594 /* Make sure we know which port we need to write */
3595 hw->mac.ops.set_lan_id(hw);
3596 /* Apply the port offset to the address offset */
3597 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3598 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3600 for (i = 0; i < 3; i++) {
3601 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3602 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3603 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3607 return IXGBE_SUCCESS;
3611 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3612 * @hw: pointer to hardware structure
3614 * Read PCIe configuration space, and get the MSI-X vector count from
3615 * the capabilities table.
3617 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3623 switch (hw->mac.type) {
3624 case ixgbe_mac_82598EB:
3625 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3626 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3628 case ixgbe_mac_82599EB:
3629 case ixgbe_mac_X540:
3630 case ixgbe_mac_X550:
3631 case ixgbe_mac_X550EM_x:
3632 case ixgbe_mac_X550EM_a:
3633 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3634 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3640 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3641 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3642 if (IXGBE_REMOVED(hw->hw_addr))
3644 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3646 /* MSI-X count is zero-based in HW */
3649 if (msix_count > max_msix_count)
3650 msix_count = max_msix_count;
3656 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3657 * @hw: pointer to hardware structure
3658 * @addr: Address to put into receive address register
3659 * @vmdq: VMDq pool to assign
3661 * Puts an ethernet address into a receive address register, or
3662 * finds the rar that it is aleady in; adds to the pool list
3664 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3666 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3667 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3669 u32 rar_low, rar_high;
3670 u32 addr_low, addr_high;
3672 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3674 /* swap bytes for HW little endian */
3675 addr_low = addr[0] | (addr[1] << 8)
3678 addr_high = addr[4] | (addr[5] << 8);
3681 * Either find the mac_id in rar or find the first empty space.
3682 * rar_highwater points to just after the highest currently used
3683 * rar in order to shorten the search. It grows when we add a new
3686 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3687 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3689 if (((IXGBE_RAH_AV & rar_high) == 0)
3690 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3691 first_empty_rar = rar;
3692 } else if ((rar_high & 0xFFFF) == addr_high) {
3693 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3694 if (rar_low == addr_low)
3695 break; /* found it already in the rars */
3699 if (rar < hw->mac.rar_highwater) {
3700 /* already there so just add to the pool bits */
3701 ixgbe_set_vmdq(hw, rar, vmdq);
3702 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3703 /* stick it into first empty RAR slot we found */
3704 rar = first_empty_rar;
3705 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3706 } else if (rar == hw->mac.rar_highwater) {
3707 /* add it to the top of the list and inc the highwater mark */
3708 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3709 hw->mac.rar_highwater++;
3710 } else if (rar >= hw->mac.num_rar_entries) {
3711 return IXGBE_ERR_INVALID_MAC_ADDR;
3715 * If we found rar[0], make sure the default pool bit (we use pool 0)
3716 * remains cleared to be sure default pool packets will get delivered
3719 ixgbe_clear_vmdq(hw, rar, 0);
3725 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3726 * @hw: pointer to hardware struct
3727 * @rar: receive address register index to disassociate
3728 * @vmdq: VMDq pool index to remove from the rar
3730 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3732 u32 mpsar_lo, mpsar_hi;
3733 u32 rar_entries = hw->mac.num_rar_entries;
3735 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3737 /* Make sure we are using a valid rar index range */
3738 if (rar >= rar_entries) {
3739 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3740 "RAR index %d is out of range.\n", rar);
3741 return IXGBE_ERR_INVALID_ARGUMENT;
3744 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3745 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3747 if (IXGBE_REMOVED(hw->hw_addr))
3750 if (!mpsar_lo && !mpsar_hi)
3753 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3755 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3759 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3762 } else if (vmdq < 32) {
3763 mpsar_lo &= ~(1 << vmdq);
3764 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3766 mpsar_hi &= ~(1 << (vmdq - 32));
3767 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3770 /* was that the last pool using this rar? */
3771 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3772 hw->mac.ops.clear_rar(hw, rar);
3774 return IXGBE_SUCCESS;
3778 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3779 * @hw: pointer to hardware struct
3780 * @rar: receive address register index to associate with a VMDq index
3781 * @vmdq: VMDq pool index
3783 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3786 u32 rar_entries = hw->mac.num_rar_entries;
3788 DEBUGFUNC("ixgbe_set_vmdq_generic");
3790 /* Make sure we are using a valid rar index range */
3791 if (rar >= rar_entries) {
3792 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3793 "RAR index %d is out of range.\n", rar);
3794 return IXGBE_ERR_INVALID_ARGUMENT;
3798 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3800 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3802 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3803 mpsar |= 1 << (vmdq - 32);
3804 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3806 return IXGBE_SUCCESS;
3810 * This function should only be involved in the IOV mode.
3811 * In IOV mode, Default pool is next pool after the number of
3812 * VFs advertized and not 0.
3813 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3815 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3816 * @hw: pointer to hardware struct
3817 * @vmdq: VMDq pool index
3819 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3821 u32 rar = hw->mac.san_mac_rar_index;
3823 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3826 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3827 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3829 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3830 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3833 return IXGBE_SUCCESS;
3837 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3838 * @hw: pointer to hardware structure
3840 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3844 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3845 DEBUGOUT(" Clearing UTA\n");
3847 for (i = 0; i < 128; i++)
3848 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3850 return IXGBE_SUCCESS;
3854 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3855 * @hw: pointer to hardware structure
3856 * @vlan: VLAN id to write to VLAN filter
3858 * return the VLVF index where this VLAN id should be placed
3861 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3863 s32 regindex, first_empty_slot;
3866 /* short cut the special case */
3870 /* if vlvf_bypass is set we don't want to use an empty slot, we
3871 * will simply bypass the VLVF if there are no entries present in the
3872 * VLVF that contain our VLAN
3874 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3876 /* add VLAN enable bit for comparison */
3877 vlan |= IXGBE_VLVF_VIEN;
3879 /* Search for the vlan id in the VLVF entries. Save off the first empty
3880 * slot found along the way.
3882 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3884 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3885 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3888 if (!first_empty_slot && !bits)
3889 first_empty_slot = regindex;
3892 /* If we are here then we didn't find the VLAN. Return first empty
3893 * slot we found during our search, else error.
3895 if (!first_empty_slot)
3896 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n");
3898 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE;
3902 * ixgbe_set_vfta_generic - Set VLAN filter table
3903 * @hw: pointer to hardware structure
3904 * @vlan: VLAN id to write to VLAN filter
3905 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3906 * @vlan_on: boolean flag to turn on/off VLAN
3907 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3909 * Turn on/off specified VLAN in the VLAN filter table.
3911 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3912 bool vlan_on, bool vlvf_bypass)
3914 u32 regidx, vfta_delta, vfta;
3917 DEBUGFUNC("ixgbe_set_vfta_generic");
3919 if (vlan > 4095 || vind > 63)
3920 return IXGBE_ERR_PARAM;
3923 * this is a 2 part operation - first the VFTA, then the
3924 * VLVF and VLVFB if VT Mode is set
3925 * We don't write the VFTA until we know the VLVF part succeeded.
3929 * The VFTA is a bitstring made up of 128 32-bit registers
3930 * that enable the particular VLAN id, much like the MTA:
3931 * bits[11-5]: which register
3932 * bits[4-0]: which bit in the register
3935 vfta_delta = 1 << (vlan % 32);
3936 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3939 * vfta_delta represents the difference between the current value
3940 * of vfta and the value we want in the register. Since the diff
3941 * is an XOR mask we can just update the vfta using an XOR
3943 vfta_delta &= vlan_on ? ~vfta : vfta;
3947 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3949 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
3951 if (ret_val != IXGBE_SUCCESS) {
3958 /* Update VFTA now that we are ready for traffic */
3960 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
3962 return IXGBE_SUCCESS;
3966 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3967 * @hw: pointer to hardware structure
3968 * @vlan: VLAN id to write to VLAN filter
3969 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3970 * @vlan_on: boolean flag to turn on/off VLAN in VLVF
3971 * @vfta_delta: pointer to the difference between the current value of VFTA
3972 * and the desired value
3973 * @vfta: the desired value of the VFTA
3974 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3976 * Turn on/off specified bit in VLVF table.
3978 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3979 bool vlan_on, u32 *vfta_delta, u32 vfta,
3985 DEBUGFUNC("ixgbe_set_vlvf_generic");
3987 if (vlan > 4095 || vind > 63)
3988 return IXGBE_ERR_PARAM;
3990 /* If VT Mode is set
3992 * make sure the vlan is in VLVF
3993 * set the vind bit in the matching VLVFB
3995 * clear the pool bit and possibly the vind
3997 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
3998 return IXGBE_SUCCESS;
4000 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
4004 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
4006 /* set the pool bit */
4007 bits |= 1 << (vind % 32);
4011 /* clear the pool bit */
4012 bits ^= 1 << (vind % 32);
4015 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
4016 /* Clear VFTA first, then disable VLVF. Otherwise
4017 * we run the risk of stray packets leaking into
4018 * the PF via the default pool
4021 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
4023 /* disable VLVF and clear remaining bit from pool */
4024 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4025 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
4027 return IXGBE_SUCCESS;
4030 /* If there are still bits set in the VLVFB registers
4031 * for the VLAN ID indicated we need to see if the
4032 * caller is requesting that we clear the VFTA entry bit.
4033 * If the caller has requested that we clear the VFTA
4034 * entry bit but there are still pools/VFs using this VLAN
4035 * ID entry then ignore the request. We're not worried
4036 * about the case where we're turning the VFTA VLAN ID
4037 * entry bit on, only when requested to turn it off as
4038 * there may be multiple pools and/or VFs using the
4039 * VLAN ID entry. In that case we cannot clear the
4040 * VFTA bit until all pools/VFs using that VLAN ID have also
4041 * been cleared. This will be indicated by "bits" being
4047 /* record pool change and enable VLAN ID if not already enabled */
4048 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
4049 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
4051 return IXGBE_SUCCESS;
4055 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4056 * @hw: pointer to hardware structure
4058 * Clears the VLAN filer table, and the VMDq index associated with the filter
4060 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4064 DEBUGFUNC("ixgbe_clear_vfta_generic");
4066 for (offset = 0; offset < hw->mac.vft_size; offset++)
4067 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4069 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4070 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4071 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4072 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
4075 return IXGBE_SUCCESS;
4079 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
4080 * @hw: pointer to hardware structure
4082 * Contains the logic to identify if we need to verify link for the
4085 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
4088 /* Does FW say we need the fix */
4089 if (!hw->need_crosstalk_fix)
4092 /* Only consider SFP+ PHYs i.e. media type fiber */
4093 switch (hw->mac.ops.get_media_type(hw)) {
4094 case ixgbe_media_type_fiber:
4095 case ixgbe_media_type_fiber_qsfp:
4105 * ixgbe_check_mac_link_generic - Determine link and speed status
4106 * @hw: pointer to hardware structure
4107 * @speed: pointer to link speed
4108 * @link_up: true when link is up
4109 * @link_up_wait_to_complete: bool used to wait for link up or not
4111 * Reads the links register to determine if link is up and the current speed
4113 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4114 bool *link_up, bool link_up_wait_to_complete)
4116 u32 links_reg, links_orig;
4119 DEBUGFUNC("ixgbe_check_mac_link_generic");
4121 /* If Crosstalk fix enabled do the sanity check of making sure
4122 * the SFP+ cage is full.
4124 if (ixgbe_need_crosstalk_fix(hw)) {
4127 switch (hw->mac.type) {
4128 case ixgbe_mac_82599EB:
4129 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4132 case ixgbe_mac_X550EM_x:
4133 case ixgbe_mac_X550EM_a:
4134 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4138 /* sanity check - No SFP+ devices here */
4139 sfp_cage_full = false;
4143 if (!sfp_cage_full) {
4145 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4146 return IXGBE_SUCCESS;
4150 /* clear the old state */
4151 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4153 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4155 if (links_orig != links_reg) {
4156 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4157 links_orig, links_reg);
4160 if (link_up_wait_to_complete) {
4161 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4162 if (links_reg & IXGBE_LINKS_UP) {
4169 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4172 if (links_reg & IXGBE_LINKS_UP)
4178 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4179 case IXGBE_LINKS_SPEED_10G_82599:
4180 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4181 if (hw->mac.type >= ixgbe_mac_X550) {
4182 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4183 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4186 case IXGBE_LINKS_SPEED_1G_82599:
4187 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4189 case IXGBE_LINKS_SPEED_100_82599:
4190 *speed = IXGBE_LINK_SPEED_100_FULL;
4191 if (hw->mac.type >= ixgbe_mac_X550) {
4192 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4193 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4196 case IXGBE_LINKS_SPEED_10_X550EM_A:
4197 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4198 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4199 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
4200 *speed = IXGBE_LINK_SPEED_10_FULL;
4204 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4207 return IXGBE_SUCCESS;
4211 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4213 * @hw: pointer to hardware structure
4214 * @wwnn_prefix: the alternative WWNN prefix
4215 * @wwpn_prefix: the alternative WWPN prefix
4217 * This function will read the EEPROM from the alternative SAN MAC address
4218 * block to check the support for the alternative WWNN/WWPN prefix support.
4220 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4224 u16 alt_san_mac_blk_offset;
4226 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4228 /* clear output first */
4229 *wwnn_prefix = 0xFFFF;
4230 *wwpn_prefix = 0xFFFF;
4232 /* check if alternative SAN MAC is supported */
4233 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4234 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4235 goto wwn_prefix_err;
4237 if ((alt_san_mac_blk_offset == 0) ||
4238 (alt_san_mac_blk_offset == 0xFFFF))
4239 goto wwn_prefix_out;
4241 /* check capability in alternative san mac address block */
4242 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4243 if (hw->eeprom.ops.read(hw, offset, &caps))
4244 goto wwn_prefix_err;
4245 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4246 goto wwn_prefix_out;
4248 /* get the corresponding prefix for WWNN/WWPN */
4249 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4250 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4251 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4252 "eeprom read at offset %d failed", offset);
4255 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4256 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4257 goto wwn_prefix_err;
4260 return IXGBE_SUCCESS;
4263 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4264 "eeprom read at offset %d failed", offset);
4265 return IXGBE_SUCCESS;
4269 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4270 * @hw: pointer to hardware structure
4271 * @bs: the fcoe boot status
4273 * This function will read the FCOE boot status from the iSCSI FCOE block
4275 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4277 u16 offset, caps, flags;
4280 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4282 /* clear output first */
4283 *bs = ixgbe_fcoe_bootstatus_unavailable;
4285 /* check if FCOE IBA block is present */
4286 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4287 status = hw->eeprom.ops.read(hw, offset, &caps);
4288 if (status != IXGBE_SUCCESS)
4291 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4294 /* check if iSCSI FCOE block is populated */
4295 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4296 if (status != IXGBE_SUCCESS)
4299 if ((offset == 0) || (offset == 0xFFFF))
4302 /* read fcoe flags in iSCSI FCOE block */
4303 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4304 status = hw->eeprom.ops.read(hw, offset, &flags);
4305 if (status != IXGBE_SUCCESS)
4308 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4309 *bs = ixgbe_fcoe_bootstatus_enabled;
4311 *bs = ixgbe_fcoe_bootstatus_disabled;
4318 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4319 * @hw: pointer to hardware structure
4320 * @enable: enable or disable switch for MAC anti-spoofing
4321 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
4324 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4326 int vf_target_reg = vf >> 3;
4327 int vf_target_shift = vf % 8;
4330 if (hw->mac.type == ixgbe_mac_82598EB)
4333 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4335 pfvfspoof |= (1 << vf_target_shift);
4337 pfvfspoof &= ~(1 << vf_target_shift);
4338 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4342 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4343 * @hw: pointer to hardware structure
4344 * @enable: enable or disable switch for VLAN anti-spoofing
4345 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4348 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4350 int vf_target_reg = vf >> 3;
4351 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4354 if (hw->mac.type == ixgbe_mac_82598EB)
4357 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4359 pfvfspoof |= (1 << vf_target_shift);
4361 pfvfspoof &= ~(1 << vf_target_shift);
4362 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4366 * ixgbe_get_device_caps_generic - Get additional device capabilities
4367 * @hw: pointer to hardware structure
4368 * @device_caps: the EEPROM word with the extra device capabilities
4370 * This function will read the EEPROM location for the device capabilities,
4371 * and return the word through device_caps.
4373 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4375 DEBUGFUNC("ixgbe_get_device_caps_generic");
4377 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4379 return IXGBE_SUCCESS;
4383 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4384 * @hw: pointer to hardware structure
4387 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4392 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4394 /* Enable relaxed ordering */
4395 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4396 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4397 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4398 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4401 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4402 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4403 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4404 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4405 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4411 * ixgbe_calculate_checksum - Calculate checksum for buffer
4412 * @buffer: pointer to EEPROM
4413 * @length: size of EEPROM to calculate a checksum for
4414 * Calculates the checksum for some buffer on a specified length. The
4415 * checksum calculated is returned.
4417 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4422 DEBUGFUNC("ixgbe_calculate_checksum");
4427 for (i = 0; i < length; i++)
4430 return (u8) (0 - sum);
4434 * ixgbe_hic_unlocked - Issue command to manageability block unlocked
4435 * @hw: pointer to the HW structure
4436 * @buffer: command to write and where the return status will be placed
4437 * @length: length of buffer, must be multiple of 4 bytes
4438 * @timeout: time in ms to wait for command completion
4440 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4441 * else returns semaphore error when encountering an error acquiring
4442 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4444 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held
4447 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
4453 DEBUGFUNC("ixgbe_hic_unlocked");
4455 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4456 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4457 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4460 /* Set bit 9 of FWSTS clearing FW reset indication */
4461 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4462 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4464 /* Check that the host interface is enabled. */
4465 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4466 if (!(hicr & IXGBE_HICR_EN)) {
4467 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4468 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4471 /* Calculate length in DWORDs. We must be DWORD aligned */
4472 if (length % sizeof(u32)) {
4473 DEBUGOUT("Buffer length failure, not aligned to dword");
4474 return IXGBE_ERR_INVALID_ARGUMENT;
4477 dword_len = length >> 2;
4479 /* The device driver writes the relevant command block
4480 * into the ram area.
4482 for (i = 0; i < dword_len; i++)
4483 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4484 i, IXGBE_CPU_TO_LE32(buffer[i]));
4486 /* Setting this bit tells the ARC that a new command is pending. */
4487 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4489 for (i = 0; i < timeout; i++) {
4490 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4491 if (!(hicr & IXGBE_HICR_C))
4496 /* Check command completion */
4497 if ((timeout && i == timeout) ||
4498 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4499 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4500 "Command has failed with no status valid.\n");
4501 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4504 return IXGBE_SUCCESS;
4508 * ixgbe_host_interface_command - Issue command to manageability block
4509 * @hw: pointer to the HW structure
4510 * @buffer: contains the command to write and where the return status will
4512 * @length: length of buffer, must be multiple of 4 bytes
4513 * @timeout: time in ms to wait for command completion
4514 * @return_data: read and return data from the buffer (true) or not (false)
4515 * Needed because FW structures are big endian and decoding of
4516 * these fields can be 8 bit or 16 bit based on command. Decoding
4517 * is not easily understood without making a table of commands.
4518 * So we will leave this up to the caller to read back the data
4521 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4522 * else returns semaphore error when encountering an error acquiring
4523 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4525 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4526 u32 length, u32 timeout, bool return_data)
4528 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4534 DEBUGFUNC("ixgbe_host_interface_command");
4536 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4537 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4538 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4541 /* Take management host interface semaphore */
4542 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4546 status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
4553 /* Calculate length in DWORDs */
4554 dword_len = hdr_size >> 2;
4556 /* first pull in the header so we know the buffer length */
4557 for (bi = 0; bi < dword_len; bi++) {
4558 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4559 IXGBE_LE32_TO_CPUS((uintptr_t)&buffer[bi]);
4562 /* If there is any thing in data position pull it in */
4563 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4567 if (length < buf_len + hdr_size) {
4568 DEBUGOUT("Buffer not large enough for reply message.\n");
4569 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4573 /* Calculate length in DWORDs, add 3 for odd lengths */
4574 dword_len = (buf_len + 3) >> 2;
4576 /* Pull in the rest of the buffer (bi is where we left off) */
4577 for (; bi <= dword_len; bi++) {
4578 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4579 IXGBE_LE32_TO_CPUS((uintptr_t)&buffer[bi]);
4583 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4589 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4590 * @hw: pointer to the HW structure
4591 * @maj: driver version major number
4592 * @min: driver version minor number
4593 * @build: driver version build number
4594 * @sub: driver version sub build number
4596 * Sends driver version number to firmware through the manageability
4597 * block. On success return IXGBE_SUCCESS
4598 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4599 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4601 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4604 struct ixgbe_hic_drv_info fw_cmd;
4606 s32 ret_val = IXGBE_SUCCESS;
4608 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4610 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4611 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4612 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4613 fw_cmd.port_num = (u8)hw->bus.func;
4614 fw_cmd.ver_maj = maj;
4615 fw_cmd.ver_min = min;
4616 fw_cmd.ver_build = build;
4617 fw_cmd.ver_sub = sub;
4618 fw_cmd.hdr.checksum = 0;
4619 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4620 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4624 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4625 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4627 IXGBE_HI_COMMAND_TIMEOUT,
4629 if (ret_val != IXGBE_SUCCESS)
4632 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4633 FW_CEM_RESP_STATUS_SUCCESS)
4634 ret_val = IXGBE_SUCCESS;
4636 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4645 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4646 * @hw: pointer to hardware structure
4647 * @num_pb: number of packet buffers to allocate
4648 * @headroom: reserve n KB of headroom
4649 * @strategy: packet buffer allocation strategy
4651 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4654 u32 pbsize = hw->mac.rx_pb_size;
4656 u32 rxpktsize, txpktsize, txpbthresh;
4658 /* Reserve headroom */
4664 /* Divide remaining packet buffer space amongst the number of packet
4665 * buffers requested using supplied strategy.
4668 case PBA_STRATEGY_WEIGHTED:
4669 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4670 * buffer with 5/8 of the packet buffer space.
4672 rxpktsize = (pbsize * 5) / (num_pb * 4);
4673 pbsize -= rxpktsize * (num_pb / 2);
4674 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4675 for (; i < (num_pb / 2); i++)
4676 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4677 /* Fall through to configure remaining packet buffers */
4678 case PBA_STRATEGY_EQUAL:
4679 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4680 for (; i < num_pb; i++)
4681 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4687 /* Only support an equally distributed Tx packet buffer strategy. */
4688 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4689 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4690 for (i = 0; i < num_pb; i++) {
4691 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4692 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4695 /* Clear unused TCs, if any, to zero buffer size*/
4696 for (; i < IXGBE_MAX_PB; i++) {
4697 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4698 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4699 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4704 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4705 * @hw: pointer to the hardware structure
4707 * The 82599 and x540 MACs can experience issues if TX work is still pending
4708 * when a reset occurs. This function prevents this by flushing the PCIe
4709 * buffers on the system.
4711 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4713 u32 gcr_ext, hlreg0, i, poll;
4717 * If double reset is not requested then all transactions should
4718 * already be clear and as such there is no work to do
4720 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4724 * Set loopback enable to prevent any transmits from being sent
4725 * should the link come up. This assumes that the RXCTRL.RXEN bit
4726 * has already been cleared.
4728 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4729 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4731 /* Wait for a last completion before clearing buffers */
4732 IXGBE_WRITE_FLUSH(hw);
4736 * Before proceeding, make sure that the PCIe block does not have
4737 * transactions pending.
4739 poll = ixgbe_pcie_timeout_poll(hw);
4740 for (i = 0; i < poll; i++) {
4742 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4743 if (IXGBE_REMOVED(hw->hw_addr))
4745 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4750 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4751 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4752 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4753 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4755 /* Flush all writes and allow 20usec for all transactions to clear */
4756 IXGBE_WRITE_FLUSH(hw);
4759 /* restore previous register values */
4760 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4761 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4764 STATIC const u8 ixgbe_emc_temp_data[4] = {
4765 IXGBE_EMC_INTERNAL_DATA,
4766 IXGBE_EMC_DIODE1_DATA,
4767 IXGBE_EMC_DIODE2_DATA,
4768 IXGBE_EMC_DIODE3_DATA
4770 STATIC const u8 ixgbe_emc_therm_limit[4] = {
4771 IXGBE_EMC_INTERNAL_THERM_LIMIT,
4772 IXGBE_EMC_DIODE1_THERM_LIMIT,
4773 IXGBE_EMC_DIODE2_THERM_LIMIT,
4774 IXGBE_EMC_DIODE3_THERM_LIMIT
4778 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
4779 * @hw: pointer to hardware structure
4780 * @data: pointer to the thermal sensor data structure
4782 * Returns the thermal sensor data structure
4784 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
4786 s32 status = IXGBE_SUCCESS;
4794 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4796 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic");
4798 /* Only support thermal sensors attached to 82599 physical port 0 */
4799 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4800 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
4801 status = IXGBE_NOT_IMPLEMENTED;
4805 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4809 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
4810 status = IXGBE_NOT_IMPLEMENTED;
4814 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4818 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4819 != IXGBE_ETS_TYPE_EMC) {
4820 status = IXGBE_NOT_IMPLEMENTED;
4824 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4825 if (num_sensors > IXGBE_MAX_SENSORS)
4826 num_sensors = IXGBE_MAX_SENSORS;
4828 for (i = 0; i < num_sensors; i++) {
4829 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
4834 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4835 IXGBE_ETS_DATA_INDEX_SHIFT);
4836 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4837 IXGBE_ETS_DATA_LOC_SHIFT);
4839 if (sensor_location != 0) {
4840 status = hw->phy.ops.read_i2c_byte(hw,
4841 ixgbe_emc_temp_data[sensor_index],
4842 IXGBE_I2C_THERMAL_SENSOR_ADDR,
4843 &data->sensor[i].temp);
4853 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4854 * @hw: pointer to hardware structure
4856 * Inits the thermal sensor thresholds according to the NVM map
4857 * and save off the threshold and location values into mac.thermal_sensor_data
4859 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4861 s32 status = IXGBE_SUCCESS;
4866 u8 low_thresh_delta;
4872 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4874 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic");
4876 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4878 /* Only support thermal sensors attached to 82599 physical port 0 */
4879 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4880 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4881 return IXGBE_NOT_IMPLEMENTED;
4883 offset = IXGBE_ETS_CFG;
4884 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
4886 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4887 return IXGBE_NOT_IMPLEMENTED;
4889 offset = ets_offset;
4890 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
4892 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4893 != IXGBE_ETS_TYPE_EMC)
4894 return IXGBE_NOT_IMPLEMENTED;
4896 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4897 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4898 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4900 for (i = 0; i < num_sensors; i++) {
4901 offset = ets_offset + 1 + i;
4902 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
4903 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4904 "eeprom read at offset %d failed",
4908 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4909 IXGBE_ETS_DATA_INDEX_SHIFT);
4910 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4911 IXGBE_ETS_DATA_LOC_SHIFT);
4912 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4914 hw->phy.ops.write_i2c_byte(hw,
4915 ixgbe_emc_therm_limit[sensor_index],
4916 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4918 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
4919 data->sensor[i].location = sensor_location;
4920 data->sensor[i].caution_thresh = therm_limit;
4921 data->sensor[i].max_op_thresh = therm_limit -
4928 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4929 "eeprom read at offset %d failed", offset);
4930 return IXGBE_NOT_IMPLEMENTED;
4935 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4936 * @hw: pointer to hardware structure
4937 * @map: pointer to u8 arr for returning map
4939 * Read the rtrup2tc HW register and resolve its content into map
4941 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4945 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4946 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4947 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4948 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4952 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4957 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4958 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4959 if (hw->mac.type != ixgbe_mac_82598EB) {
4960 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4961 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4962 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4963 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4964 hw->mac.set_lben = true;
4966 hw->mac.set_lben = false;
4969 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4970 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4974 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4979 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4980 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4982 if (hw->mac.type != ixgbe_mac_82598EB) {
4983 if (hw->mac.set_lben) {
4984 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4985 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4986 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4987 hw->mac.set_lben = false;
4993 * ixgbe_mng_present - returns true when management capability is present
4994 * @hw: pointer to hardware structure
4996 bool ixgbe_mng_present(struct ixgbe_hw *hw)
5000 if (hw->mac.type < ixgbe_mac_82599EB)
5003 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5004 fwsm &= IXGBE_FWSM_MODE_MASK;
5005 return fwsm == IXGBE_FWSM_FW_MODE_PT;
5009 * ixgbe_mng_enabled - Is the manageability engine enabled?
5010 * @hw: pointer to hardware structure
5012 * Returns true if the manageability engine is enabled.
5014 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
5016 u32 fwsm, manc, factps;
5018 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5019 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
5022 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
5023 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
5026 if (hw->mac.type <= ixgbe_mac_X540) {
5027 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
5028 if (factps & IXGBE_FACTPS_MNGCG)
5036 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
5037 * @hw: pointer to hardware structure
5038 * @speed: new link speed
5039 * @autoneg_wait_to_complete: true when waiting for completion is needed
5041 * Set the link speed in the MAC and/or PHY register and restarts link.
5043 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
5044 ixgbe_link_speed speed,
5045 bool autoneg_wait_to_complete)
5047 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5048 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5049 s32 status = IXGBE_SUCCESS;
5052 bool autoneg, link_up = false;
5054 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
5056 /* Mask off requested but non-supported speeds */
5057 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
5058 if (status != IXGBE_SUCCESS)
5061 speed &= link_speed;
5063 /* Try each speed one by one, highest priority first. We do this in
5064 * software because 10Gb fiber doesn't support speed autonegotiation.
5066 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
5068 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5070 /* Set the module link speed */
5071 switch (hw->phy.media_type) {
5072 case ixgbe_media_type_fiber_fixed:
5073 case ixgbe_media_type_fiber:
5074 ixgbe_set_rate_select_speed(hw,
5075 IXGBE_LINK_SPEED_10GB_FULL);
5077 case ixgbe_media_type_fiber_qsfp:
5078 /* QSFP module automatically detects MAC link speed */
5081 DEBUGOUT("Unexpected media type.\n");
5085 /* Allow module to change analog characteristics (1G->10G) */
5088 status = ixgbe_setup_mac_link(hw,
5089 IXGBE_LINK_SPEED_10GB_FULL,
5090 autoneg_wait_to_complete);
5091 if (status != IXGBE_SUCCESS)
5094 /* Flap the Tx laser if it has not already been done */
5095 ixgbe_flap_tx_laser(hw);
5097 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
5098 * Section 73.10.2, we may have to wait up to 500ms if KR is
5099 * attempted. 82599 uses the same timing for 10g SFI.
5101 for (i = 0; i < 5; i++) {
5102 /* Wait for the link partner to also set speed */
5105 /* If we have link, just jump out */
5106 status = ixgbe_check_link(hw, &link_speed,
5108 if (status != IXGBE_SUCCESS)
5116 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
5118 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
5119 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
5121 /* Set the module link speed */
5122 switch (hw->phy.media_type) {
5123 case ixgbe_media_type_fiber_fixed:
5124 case ixgbe_media_type_fiber:
5125 ixgbe_set_rate_select_speed(hw,
5126 IXGBE_LINK_SPEED_1GB_FULL);
5128 case ixgbe_media_type_fiber_qsfp:
5129 /* QSFP module automatically detects link speed */
5132 DEBUGOUT("Unexpected media type.\n");
5136 /* Allow module to change analog characteristics (10G->1G) */
5139 status = ixgbe_setup_mac_link(hw,
5140 IXGBE_LINK_SPEED_1GB_FULL,
5141 autoneg_wait_to_complete);
5142 if (status != IXGBE_SUCCESS)
5145 /* Flap the Tx laser if it has not already been done */
5146 ixgbe_flap_tx_laser(hw);
5148 /* Wait for the link partner to also set speed */
5151 /* If we have link, just jump out */
5152 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5153 if (status != IXGBE_SUCCESS)
5160 /* We didn't get link. Configure back to the highest speed we tried,
5161 * (if there was more than one). We call ourselves back with just the
5162 * single highest speed that the user requested.
5165 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5167 autoneg_wait_to_complete);
5170 /* Set autoneg_advertised value based on input link speed */
5171 hw->phy.autoneg_advertised = 0;
5173 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
5174 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5176 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
5177 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5183 * ixgbe_set_soft_rate_select_speed - Set module link speed
5184 * @hw: pointer to hardware structure
5185 * @speed: link speed to set
5187 * Set module link speed via the soft rate select.
5189 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5190 ixgbe_link_speed speed)
5196 case IXGBE_LINK_SPEED_10GB_FULL:
5197 /* one bit mask same as setting on */
5198 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
5200 case IXGBE_LINK_SPEED_1GB_FULL:
5201 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
5204 DEBUGOUT("Invalid fixed module speed\n");
5209 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5210 IXGBE_I2C_EEPROM_DEV_ADDR2,
5213 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
5217 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5219 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5220 IXGBE_I2C_EEPROM_DEV_ADDR2,
5223 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
5228 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5229 IXGBE_I2C_EEPROM_DEV_ADDR2,
5232 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
5236 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5238 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5239 IXGBE_I2C_EEPROM_DEV_ADDR2,
5242 DEBUGOUT("Failed to write Rx Rate Select RS1\n");