1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
44 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw);
47 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
48 * @hw: pointer to hardware structure
50 * Initialize the function pointers and assign the MAC type for X550.
51 * Does not touch the hardware.
53 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
55 struct ixgbe_mac_info *mac = &hw->mac;
56 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
59 DEBUGFUNC("ixgbe_init_ops_X550");
61 ret_val = ixgbe_init_ops_X540(hw);
62 mac->ops.dmac_config = ixgbe_dmac_config_X550;
63 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
64 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
65 mac->ops.setup_eee = ixgbe_setup_eee_X550;
66 mac->ops.set_source_address_pruning =
67 ixgbe_set_source_address_pruning_X550;
68 mac->ops.set_ethertype_anti_spoofing =
69 ixgbe_set_ethertype_anti_spoofing_X550;
71 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
72 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
73 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
74 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
75 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
76 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
77 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
78 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
79 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
81 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
82 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
83 mac->ops.mdd_event = ixgbe_mdd_event_X550;
84 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
85 mac->ops.disable_rx = ixgbe_disable_rx_x550;
86 switch (hw->device_id) {
87 case IXGBE_DEV_ID_X550EM_X_10G_T:
88 case IXGBE_DEV_ID_X550EM_A_10G_T:
89 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
90 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
99 * ixgbe_read_cs4227 - Read CS4227 register
100 * @hw: pointer to hardware structure
101 * @reg: register number to write
102 * @value: pointer to receive value read
104 * Returns status code
106 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
108 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
112 * ixgbe_write_cs4227 - Write CS4227 register
113 * @hw: pointer to hardware structure
114 * @reg: register number to write
115 * @value: value to write to register
117 * Returns status code
119 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
121 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
125 * ixgbe_read_pe - Read register from port expander
126 * @hw: pointer to hardware structure
127 * @reg: register number to read
128 * @value: pointer to receive read value
130 * Returns status code
132 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
136 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
137 if (status != IXGBE_SUCCESS)
138 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
139 "port expander access failed with %d\n", status);
144 * ixgbe_write_pe - Write register to port expander
145 * @hw: pointer to hardware structure
146 * @reg: register number to write
147 * @value: value to write
149 * Returns status code
151 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
155 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
156 if (status != IXGBE_SUCCESS)
157 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
158 "port expander access failed with %d\n", status);
163 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
164 * @hw: pointer to hardware structure
166 * This function assumes that the caller has acquired the proper semaphore.
169 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
176 /* Trigger hard reset. */
177 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
178 if (status != IXGBE_SUCCESS)
180 reg |= IXGBE_PE_BIT1;
181 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
182 if (status != IXGBE_SUCCESS)
185 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
186 if (status != IXGBE_SUCCESS)
188 reg &= ~IXGBE_PE_BIT1;
189 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
190 if (status != IXGBE_SUCCESS)
193 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
194 if (status != IXGBE_SUCCESS)
196 reg &= ~IXGBE_PE_BIT1;
197 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
198 if (status != IXGBE_SUCCESS)
201 usec_delay(IXGBE_CS4227_RESET_HOLD);
203 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
204 if (status != IXGBE_SUCCESS)
206 reg |= IXGBE_PE_BIT1;
207 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
208 if (status != IXGBE_SUCCESS)
211 /* Wait for the reset to complete. */
212 msec_delay(IXGBE_CS4227_RESET_DELAY);
213 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
214 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
216 if (status == IXGBE_SUCCESS &&
217 value == IXGBE_CS4227_EEPROM_LOAD_OK)
219 msec_delay(IXGBE_CS4227_CHECK_DELAY);
221 if (retry == IXGBE_CS4227_RETRIES) {
222 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
223 "CS4227 reset did not complete.");
224 return IXGBE_ERR_PHY;
227 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
228 if (status != IXGBE_SUCCESS ||
229 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
230 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
231 "CS4227 EEPROM did not load successfully.");
232 return IXGBE_ERR_PHY;
235 return IXGBE_SUCCESS;
239 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
240 * @hw: pointer to hardware structure
242 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
244 s32 status = IXGBE_SUCCESS;
245 u32 swfw_mask = hw->phy.phy_semaphore_mask;
249 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
250 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
251 if (status != IXGBE_SUCCESS) {
252 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
253 "semaphore failed with %d", status);
254 msec_delay(IXGBE_CS4227_CHECK_DELAY);
258 /* Get status of reset flow. */
259 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
261 if (status == IXGBE_SUCCESS &&
262 value == IXGBE_CS4227_RESET_COMPLETE)
265 if (status != IXGBE_SUCCESS ||
266 value != IXGBE_CS4227_RESET_PENDING)
269 /* Reset is pending. Wait and check again. */
270 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
271 msec_delay(IXGBE_CS4227_CHECK_DELAY);
274 /* If still pending, assume other instance failed. */
275 if (retry == IXGBE_CS4227_RETRIES) {
276 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
277 if (status != IXGBE_SUCCESS) {
278 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
279 "semaphore failed with %d", status);
284 /* Reset the CS4227. */
285 status = ixgbe_reset_cs4227(hw);
286 if (status != IXGBE_SUCCESS) {
287 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
288 "CS4227 reset failed: %d", status);
292 /* Reset takes so long, temporarily release semaphore in case the
293 * other driver instance is waiting for the reset indication.
295 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
296 IXGBE_CS4227_RESET_PENDING);
297 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
299 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
300 if (status != IXGBE_SUCCESS) {
301 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
302 "semaphore failed with %d", status);
306 /* Record completion for next time. */
307 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
308 IXGBE_CS4227_RESET_COMPLETE);
311 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
312 msec_delay(hw->eeprom.semaphore_delay);
316 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
317 * @hw: pointer to hardware structure
319 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
321 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
323 if (hw->bus.lan_id) {
324 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
325 esdp |= IXGBE_ESDP_SDP1_DIR;
327 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
328 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
329 IXGBE_WRITE_FLUSH(hw);
333 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
334 * @hw: pointer to hardware structure
335 * @reg_addr: 32 bit address of PHY register to read
336 * @dev_type: always unused
337 * @phy_data: Pointer to read data from PHY register
339 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
340 u32 dev_type, u16 *phy_data)
342 u32 i, data, command;
343 UNREFERENCED_1PARAMETER(dev_type);
345 /* Setup and write the read command */
346 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
347 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
348 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
349 IXGBE_MSCA_MDI_COMMAND;
351 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
353 /* Check every 10 usec to see if the access completed.
354 * The MDI Command bit will clear when the operation is
357 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
360 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
361 if (!(command & IXGBE_MSCA_MDI_COMMAND))
365 if (command & IXGBE_MSCA_MDI_COMMAND) {
366 ERROR_REPORT1(IXGBE_ERROR_POLLING,
367 "PHY read command did not complete.\n");
368 return IXGBE_ERR_PHY;
371 /* Read operation is complete. Get the data from MSRWD */
372 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
373 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
374 *phy_data = (u16)data;
376 return IXGBE_SUCCESS;
380 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
381 * @hw: pointer to hardware structure
382 * @reg_addr: 32 bit PHY register to write
383 * @dev_type: always unused
384 * @phy_data: Data to write to the PHY register
386 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
387 u32 dev_type, u16 phy_data)
390 UNREFERENCED_1PARAMETER(dev_type);
392 /* Put the data in the MDI single read and write data register*/
393 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
395 /* Setup and write the write command */
396 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
397 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
398 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
399 IXGBE_MSCA_MDI_COMMAND;
401 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
403 /* Check every 10 usec to see if the access completed.
404 * The MDI Command bit will clear when the operation is
407 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
410 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
411 if (!(command & IXGBE_MSCA_MDI_COMMAND))
415 if (command & IXGBE_MSCA_MDI_COMMAND) {
416 ERROR_REPORT1(IXGBE_ERROR_POLLING,
417 "PHY write cmd didn't complete\n");
418 return IXGBE_ERR_PHY;
421 return IXGBE_SUCCESS;
425 * ixgbe_identify_phy_x550em - Get PHY type based on device id
426 * @hw: pointer to hardware structure
430 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
432 hw->mac.ops.set_lan_id(hw);
434 ixgbe_read_mng_if_sel_x550em(hw);
436 switch (hw->device_id) {
437 case IXGBE_DEV_ID_X550EM_A_SFP:
438 return ixgbe_identify_module_generic(hw);
439 case IXGBE_DEV_ID_X550EM_X_SFP:
440 /* set up for CS4227 usage */
441 ixgbe_setup_mux_ctl(hw);
442 ixgbe_check_cs4227(hw);
445 case IXGBE_DEV_ID_X550EM_A_SFP_N:
446 return ixgbe_identify_module_generic(hw);
448 case IXGBE_DEV_ID_X550EM_X_KX4:
449 hw->phy.type = ixgbe_phy_x550em_kx4;
451 case IXGBE_DEV_ID_X550EM_X_KR:
452 case IXGBE_DEV_ID_X550EM_A_KR:
453 case IXGBE_DEV_ID_X550EM_A_KR_L:
454 hw->phy.type = ixgbe_phy_x550em_kr;
456 case IXGBE_DEV_ID_X550EM_A_10G_T:
457 case IXGBE_DEV_ID_X550EM_A_1G_T:
458 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
459 case IXGBE_DEV_ID_X550EM_X_1G_T:
460 case IXGBE_DEV_ID_X550EM_X_10G_T:
461 return ixgbe_identify_phy_generic(hw);
465 return IXGBE_SUCCESS;
468 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
469 u32 device_type, u16 *phy_data)
471 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
472 return IXGBE_NOT_IMPLEMENTED;
475 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
476 u32 device_type, u16 phy_data)
478 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
479 return IXGBE_NOT_IMPLEMENTED;
483 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
484 * @hw: pointer to the hardware structure
485 * @addr: I2C bus address to read from
486 * @reg: I2C device register to read from
487 * @val: pointer to location to receive read value
489 * Returns an error code on error.
491 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
494 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
498 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
499 * @hw: pointer to the hardware structure
500 * @addr: I2C bus address to read from
501 * @reg: I2C device register to read from
502 * @val: pointer to location to receive read value
504 * Returns an error code on error.
507 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
510 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
514 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
515 * @hw: pointer to the hardware structure
516 * @addr: I2C bus address to write to
517 * @reg: I2C device register to write to
518 * @val: value to write
520 * Returns an error code on error.
522 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
523 u8 addr, u16 reg, u16 val)
525 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
529 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
530 * @hw: pointer to the hardware structure
531 * @addr: I2C bus address to write to
532 * @reg: I2C device register to write to
533 * @val: value to write
535 * Returns an error code on error.
538 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
539 u8 addr, u16 reg, u16 val)
541 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
545 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
546 * @hw: pointer to hardware structure
548 * Initialize the function pointers and for MAC type X550EM.
549 * Does not touch the hardware.
551 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
553 struct ixgbe_mac_info *mac = &hw->mac;
554 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
555 struct ixgbe_phy_info *phy = &hw->phy;
558 DEBUGFUNC("ixgbe_init_ops_X550EM");
560 /* Similar to X550 so start there. */
561 ret_val = ixgbe_init_ops_X550(hw);
563 /* Since this function eventually calls
564 * ixgbe_init_ops_540 by design, we are setting
565 * the pointers to NULL explicitly here to overwrite
566 * the values being set in the x540 function.
568 /* Thermal sensor not supported in x550EM */
569 mac->ops.get_thermal_sensor_data = NULL;
570 mac->ops.init_thermal_sensor_thresh = NULL;
571 mac->thermal_sensor_enabled = false;
573 /* FCOE not supported in x550EM */
574 mac->ops.get_san_mac_addr = NULL;
575 mac->ops.set_san_mac_addr = NULL;
576 mac->ops.get_wwn_prefix = NULL;
577 mac->ops.get_fcoe_boot_status = NULL;
579 /* IPsec not supported in x550EM */
580 mac->ops.disable_sec_rx_path = NULL;
581 mac->ops.enable_sec_rx_path = NULL;
583 /* AUTOC register is not present in x550EM. */
584 mac->ops.prot_autoc_read = NULL;
585 mac->ops.prot_autoc_write = NULL;
587 /* X550EM bus type is internal*/
588 hw->bus.type = ixgbe_bus_type_internal;
589 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
592 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
593 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
594 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
595 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
596 mac->ops.get_supported_physical_layer =
597 ixgbe_get_supported_physical_layer_X550em;
599 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
600 mac->ops.setup_fc = ixgbe_setup_fc_generic;
602 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
604 switch (hw->device_id) {
605 case IXGBE_DEV_ID_X550EM_X_KR:
606 case IXGBE_DEV_ID_X550EM_A_KR:
607 case IXGBE_DEV_ID_X550EM_A_KR_L:
610 mac->ops.setup_eee = NULL;
614 phy->ops.init = ixgbe_init_phy_ops_X550em;
615 phy->ops.identify = ixgbe_identify_phy_x550em;
616 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
617 phy->ops.set_phy_power = NULL;
621 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
622 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
623 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
624 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
625 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
626 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
627 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
628 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
634 * ixgbe_init_ops_X550EM_a - Inits func ptrs and MAC type
635 * @hw: pointer to hardware structure
637 * Initialize the function pointers and for MAC type X550EM_a.
638 * Does not touch the hardware.
640 s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw)
642 struct ixgbe_mac_info *mac = &hw->mac;
645 DEBUGFUNC("ixgbe_init_ops_X550EM_a");
647 /* Start with generic X550EM init */
648 ret_val = ixgbe_init_ops_X550EM(hw);
650 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
651 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) {
652 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
653 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
655 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
656 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
658 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
659 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
661 switch (mac->ops.get_media_type(hw)) {
662 case ixgbe_media_type_fiber:
663 mac->ops.setup_fc = NULL;
664 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
666 case ixgbe_media_type_backplane:
667 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
668 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
674 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T) ||
675 (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)) {
676 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
677 mac->ops.setup_fc = ixgbe_setup_fc_sgmii_x550em_a;
684 * ixgbe_init_ops_X550EM_x - Inits func ptrs and MAC type
685 * @hw: pointer to hardware structure
687 * Initialize the function pointers and for MAC type X550EM_x.
688 * Does not touch the hardware.
690 s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw)
692 struct ixgbe_mac_info *mac = &hw->mac;
693 struct ixgbe_link_info *link = &hw->link;
696 DEBUGFUNC("ixgbe_init_ops_X550EM_x");
698 /* Start with generic X550EM init */
699 ret_val = ixgbe_init_ops_X550EM(hw);
701 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
702 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
703 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
704 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
705 link->ops.read_link = ixgbe_read_i2c_combined_generic;
706 link->ops.read_link_unlocked = ixgbe_read_i2c_combined_generic_unlocked;
707 link->ops.write_link = ixgbe_write_i2c_combined_generic;
708 link->ops.write_link_unlocked =
709 ixgbe_write_i2c_combined_generic_unlocked;
710 link->addr = IXGBE_CS4227;
716 * ixgbe_dmac_config_X550
717 * @hw: pointer to hardware structure
719 * Configure DMA coalescing. If enabling dmac, dmac is activated.
720 * When disabling dmac, dmac enable dmac bit is cleared.
722 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
724 u32 reg, high_pri_tc;
726 DEBUGFUNC("ixgbe_dmac_config_X550");
728 /* Disable DMA coalescing before configuring */
729 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
730 reg &= ~IXGBE_DMACR_DMAC_EN;
731 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
733 /* Disable DMA Coalescing if the watchdog timer is 0 */
734 if (!hw->mac.dmac_config.watchdog_timer)
737 ixgbe_dmac_config_tcs_X550(hw);
739 /* Configure DMA Coalescing Control Register */
740 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
742 /* Set the watchdog timer in units of 40.96 usec */
743 reg &= ~IXGBE_DMACR_DMACWT_MASK;
744 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
746 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
747 /* If fcoe is enabled, set high priority traffic class */
748 if (hw->mac.dmac_config.fcoe_en) {
749 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
750 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
751 IXGBE_DMACR_HIGH_PRI_TC_MASK);
753 reg |= IXGBE_DMACR_EN_MNG_IND;
755 /* Enable DMA coalescing after configuration */
756 reg |= IXGBE_DMACR_DMAC_EN;
757 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
760 return IXGBE_SUCCESS;
764 * ixgbe_dmac_config_tcs_X550
765 * @hw: pointer to hardware structure
767 * Configure DMA coalescing threshold per TC. The dmac enable bit must
768 * be cleared before configuring.
770 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
772 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
774 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
776 /* Configure DMA coalescing enabled */
777 switch (hw->mac.dmac_config.link_speed) {
778 case IXGBE_LINK_SPEED_10_FULL:
779 case IXGBE_LINK_SPEED_100_FULL:
780 pb_headroom = IXGBE_DMACRXT_100M;
782 case IXGBE_LINK_SPEED_1GB_FULL:
783 pb_headroom = IXGBE_DMACRXT_1G;
786 pb_headroom = IXGBE_DMACRXT_10G;
790 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
791 IXGBE_MHADD_MFS_SHIFT) / 1024);
793 /* Set the per Rx packet buffer receive threshold */
794 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
795 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
796 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
798 if (tc < hw->mac.dmac_config.num_tcs) {
800 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
801 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
802 IXGBE_RXPBSIZE_SHIFT;
804 /* Calculate receive buffer threshold in kilobytes */
805 if (rx_pb_size > pb_headroom)
806 rx_pb_size = rx_pb_size - pb_headroom;
810 /* Minimum of MFS shall be set for DMCTH */
811 reg |= (rx_pb_size > maxframe_size_kb) ?
812 rx_pb_size : maxframe_size_kb;
814 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
816 return IXGBE_SUCCESS;
820 * ixgbe_dmac_update_tcs_X550
821 * @hw: pointer to hardware structure
823 * Disables dmac, updates per TC settings, and then enables dmac.
825 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
829 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
831 /* Disable DMA coalescing before configuring */
832 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
833 reg &= ~IXGBE_DMACR_DMAC_EN;
834 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
836 ixgbe_dmac_config_tcs_X550(hw);
838 /* Enable DMA coalescing after configuration */
839 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
840 reg |= IXGBE_DMACR_DMAC_EN;
841 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
843 return IXGBE_SUCCESS;
847 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
848 * @hw: pointer to hardware structure
850 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
851 * ixgbe_hw struct in order to set up EEPROM access.
853 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
855 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
859 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
861 if (eeprom->type == ixgbe_eeprom_uninitialized) {
862 eeprom->semaphore_delay = 10;
863 eeprom->type = ixgbe_flash;
865 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
866 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
867 IXGBE_EEC_SIZE_SHIFT);
868 eeprom->word_size = 1 << (eeprom_size +
869 IXGBE_EEPROM_WORD_SIZE_SHIFT);
871 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
872 eeprom->type, eeprom->word_size);
875 return IXGBE_SUCCESS;
879 * ixgbe_enable_eee_x550 - Enable EEE support
880 * @hw: pointer to hardware structure
882 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
888 if (hw->mac.type == ixgbe_mac_X550) {
889 /* Advertise EEE capability */
890 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
891 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
894 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
895 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
896 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
898 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
899 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
901 return IXGBE_SUCCESS;
904 switch (hw->device_id) {
905 case IXGBE_DEV_ID_X550EM_X_KR:
906 case IXGBE_DEV_ID_X550EM_A_KR:
907 case IXGBE_DEV_ID_X550EM_A_KR_L:
908 status = hw->mac.ops.read_iosf_sb_reg(hw,
909 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
910 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
911 if (status != IXGBE_SUCCESS)
914 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
915 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
917 /* Don't advertise FEC capability when EEE enabled. */
918 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
920 status = hw->mac.ops.write_iosf_sb_reg(hw,
921 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
922 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
923 if (status != IXGBE_SUCCESS)
930 return IXGBE_SUCCESS;
934 * ixgbe_disable_eee_x550 - Disable EEE support
935 * @hw: pointer to hardware structure
937 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
943 if (hw->mac.type == ixgbe_mac_X550) {
944 /* Disable advertised EEE capability */
945 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
946 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
949 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
950 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
951 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
953 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
954 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
956 return IXGBE_SUCCESS;
959 switch (hw->device_id) {
960 case IXGBE_DEV_ID_X550EM_X_KR:
961 case IXGBE_DEV_ID_X550EM_A_KR:
962 case IXGBE_DEV_ID_X550EM_A_KR_L:
963 status = hw->mac.ops.read_iosf_sb_reg(hw,
964 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
965 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
966 if (status != IXGBE_SUCCESS)
969 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
970 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
972 /* Advertise FEC capability when EEE is disabled. */
973 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
975 status = hw->mac.ops.write_iosf_sb_reg(hw,
976 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
977 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
978 if (status != IXGBE_SUCCESS)
985 return IXGBE_SUCCESS;
989 * ixgbe_setup_eee_X550 - Enable/disable EEE support
990 * @hw: pointer to the HW structure
991 * @enable_eee: boolean flag to enable EEE
993 * Enable/disable EEE based on enable_eee flag.
994 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
998 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
1003 DEBUGFUNC("ixgbe_setup_eee_X550");
1005 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
1006 /* Enable or disable EEE per flag */
1008 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1010 /* Not supported on first revision of X550EM_x. */
1011 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1012 !(IXGBE_FUSES0_REV_MASK &
1013 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1014 return IXGBE_SUCCESS;
1016 status = ixgbe_enable_eee_x550(hw);
1020 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1022 status = ixgbe_disable_eee_x550(hw);
1026 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1028 return IXGBE_SUCCESS;
1032 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1033 * @hw: pointer to hardware structure
1034 * @enable: enable or disable source address pruning
1035 * @pool: Rx pool to set source address pruning for
1037 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1042 /* max rx pool is 63 */
1046 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1047 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1050 pfflp |= (1ULL << pool);
1052 pfflp &= ~(1ULL << pool);
1054 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1055 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1059 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1060 * @hw: pointer to hardware structure
1061 * @enable: enable or disable switch for Ethertype anti-spoofing
1062 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1065 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1066 bool enable, int vf)
1068 int vf_target_reg = vf >> 3;
1069 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1072 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1074 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1076 pfvfspoof |= (1 << vf_target_shift);
1078 pfvfspoof &= ~(1 << vf_target_shift);
1080 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1084 * ixgbe_iosf_wait - Wait for IOSF command completion
1085 * @hw: pointer to hardware structure
1086 * @ctrl: pointer to location to receive final IOSF control value
1088 * Returns failing status on timeout
1090 * Note: ctrl can be NULL if the IOSF control register value is not needed
1092 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1096 /* Check every 10 usec to see if the address cycle completed.
1097 * The SB IOSF BUSY bit will clear when the operation is
1100 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1101 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1102 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1108 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1109 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1110 return IXGBE_ERR_PHY;
1113 return IXGBE_SUCCESS;
1117 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register
1118 * of the IOSF device
1119 * @hw: pointer to hardware structure
1120 * @reg_addr: 32 bit PHY register to write
1121 * @device_type: 3 bit device type
1122 * @data: Data to write to the register
1124 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1125 u32 device_type, u32 data)
1127 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1131 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1132 if (ret != IXGBE_SUCCESS)
1135 ret = ixgbe_iosf_wait(hw, NULL);
1136 if (ret != IXGBE_SUCCESS)
1139 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1140 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1142 /* Write IOSF control register */
1143 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1145 /* Write IOSF data register */
1146 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1148 ret = ixgbe_iosf_wait(hw, &command);
1150 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1151 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1152 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1153 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1154 "Failed to write, error %x\n", error);
1155 ret = IXGBE_ERR_PHY;
1159 ixgbe_release_swfw_semaphore(hw, gssr);
1164 * ixgbe_read_iosf_sb_reg_x550 - Reads specified register of the IOSF device
1165 * @hw: pointer to hardware structure
1166 * @reg_addr: 32 bit PHY register to write
1167 * @device_type: 3 bit device type
1168 * @data: Pointer to read data from the register
1170 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1171 u32 device_type, u32 *data)
1173 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1177 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1178 if (ret != IXGBE_SUCCESS)
1181 ret = ixgbe_iosf_wait(hw, NULL);
1182 if (ret != IXGBE_SUCCESS)
1185 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1186 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1188 /* Write IOSF control register */
1189 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1191 ret = ixgbe_iosf_wait(hw, &command);
1193 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1194 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1195 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1196 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1197 "Failed to read, error %x\n", error);
1198 ret = IXGBE_ERR_PHY;
1201 if (ret == IXGBE_SUCCESS)
1202 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1205 ixgbe_release_swfw_semaphore(hw, gssr);
1210 * ixgbe_get_phy_token - Get the token for shared phy access
1211 * @hw: Pointer to hardware structure
1214 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1216 struct ixgbe_hic_phy_token_req token_cmd;
1219 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1220 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1221 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1222 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1223 token_cmd.port_number = hw->bus.lan_id;
1224 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1226 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1228 IXGBE_HI_COMMAND_TIMEOUT,
1232 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1233 return IXGBE_SUCCESS;
1234 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1235 return IXGBE_ERR_FW_RESP_INVALID;
1237 return IXGBE_ERR_TOKEN_RETRY;
1241 * ixgbe_put_phy_token - Put the token for shared phy access
1242 * @hw: Pointer to hardware structure
1245 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1247 struct ixgbe_hic_phy_token_req token_cmd;
1250 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1251 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1252 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1253 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1254 token_cmd.port_number = hw->bus.lan_id;
1255 token_cmd.command_type = FW_PHY_TOKEN_REL;
1257 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1259 IXGBE_HI_COMMAND_TIMEOUT,
1263 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1264 return IXGBE_SUCCESS;
1266 DEBUGOUT("Put PHY Token host interface command failed");
1267 return IXGBE_ERR_FW_RESP_INVALID;
1271 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1272 * of the IOSF device
1273 * @hw: pointer to hardware structure
1274 * @reg_addr: 32 bit PHY register to write
1275 * @device_type: 3 bit device type
1276 * @data: Data to write to the register
1278 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1279 u32 device_type, u32 data)
1281 struct ixgbe_hic_internal_phy_req write_cmd;
1283 UNREFERENCED_1PARAMETER(device_type);
1285 memset(&write_cmd, 0, sizeof(write_cmd));
1286 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1287 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1288 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1289 write_cmd.port_number = hw->bus.lan_id;
1290 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1291 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1292 write_cmd.write_data = IXGBE_CPU_TO_BE32(data);
1294 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1296 IXGBE_HI_COMMAND_TIMEOUT, false);
1302 * ixgbe_read_iosf_sb_reg_x550a - Reads specified register of the IOSF device
1303 * @hw: pointer to hardware structure
1304 * @reg_addr: 32 bit PHY register to write
1305 * @device_type: 3 bit device type
1306 * @data: Pointer to read data from the register
1308 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1309 u32 device_type, u32 *data)
1312 struct ixgbe_hic_internal_phy_req cmd;
1313 struct ixgbe_hic_internal_phy_resp rsp;
1316 UNREFERENCED_1PARAMETER(device_type);
1318 memset(&hic, 0, sizeof(hic));
1319 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1320 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1321 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1322 hic.cmd.port_number = hw->bus.lan_id;
1323 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1324 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1326 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1328 IXGBE_HI_COMMAND_TIMEOUT, true);
1330 /* Extract the register value from the response. */
1331 *data = IXGBE_BE32_TO_CPU(hic.rsp.read_data);
1337 * ixgbe_disable_mdd_X550
1338 * @hw: pointer to hardware structure
1340 * Disable malicious driver detection
1342 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1346 DEBUGFUNC("ixgbe_disable_mdd_X550");
1348 /* Disable MDD for TX DMA and interrupt */
1349 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1350 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1351 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1353 /* Disable MDD for RX and interrupt */
1354 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1355 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1356 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1360 * ixgbe_enable_mdd_X550
1361 * @hw: pointer to hardware structure
1363 * Enable malicious driver detection
1365 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1369 DEBUGFUNC("ixgbe_enable_mdd_X550");
1371 /* Enable MDD for TX DMA and interrupt */
1372 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1373 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1374 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1376 /* Enable MDD for RX and interrupt */
1377 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1378 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1379 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1383 * ixgbe_restore_mdd_vf_X550
1384 * @hw: pointer to hardware structure
1387 * Restore VF that was disabled during malicious driver detection event
1389 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1391 u32 idx, reg, num_qs, start_q, bitmask;
1393 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1395 /* Map VF to queues */
1396 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1397 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1398 case IXGBE_MRQC_VMDQRT8TCEN:
1399 num_qs = 8; /* 16 VFs / pools */
1400 bitmask = 0x000000FF;
1402 case IXGBE_MRQC_VMDQRSS32EN:
1403 case IXGBE_MRQC_VMDQRT4TCEN:
1404 num_qs = 4; /* 32 VFs / pools */
1405 bitmask = 0x0000000F;
1407 default: /* 64 VFs / pools */
1409 bitmask = 0x00000003;
1412 start_q = vf * num_qs;
1414 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1417 reg |= (bitmask << (start_q % 32));
1418 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1419 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1423 * ixgbe_mdd_event_X550
1424 * @hw: pointer to hardware structure
1425 * @vf_bitmap: vf bitmap of malicious vfs
1427 * Handle malicious driver detection event.
1429 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1432 u32 i, j, reg, q, shift, vf, idx;
1434 DEBUGFUNC("ixgbe_mdd_event_X550");
1436 /* figure out pool size for mapping to vf's */
1437 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1438 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1439 case IXGBE_MRQC_VMDQRT8TCEN:
1440 shift = 3; /* 16 VFs / pools */
1442 case IXGBE_MRQC_VMDQRSS32EN:
1443 case IXGBE_MRQC_VMDQRT4TCEN:
1444 shift = 2; /* 32 VFs / pools */
1447 shift = 1; /* 64 VFs / pools */
1451 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1452 for (i = 0; i < 4; i++) {
1453 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1454 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1459 /* Get malicious queue */
1460 for (j = 0; j < 32 && wqbr; j++) {
1462 if (!(wqbr & (1 << j)))
1465 /* Get queue from bitmask */
1468 /* Map queue to vf */
1471 /* Set vf bit in vf_bitmap */
1473 vf_bitmap[idx] |= (1 << (vf % 32));
1480 * ixgbe_get_media_type_X550em - Get media type
1481 * @hw: pointer to hardware structure
1483 * Returns the media type (fiber, copper, backplane)
1485 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1487 enum ixgbe_media_type media_type;
1489 DEBUGFUNC("ixgbe_get_media_type_X550em");
1491 /* Detect if there is a copper PHY attached. */
1492 switch (hw->device_id) {
1493 case IXGBE_DEV_ID_X550EM_X_KR:
1494 case IXGBE_DEV_ID_X550EM_X_KX4:
1495 case IXGBE_DEV_ID_X550EM_A_KR:
1496 case IXGBE_DEV_ID_X550EM_A_KR_L:
1497 media_type = ixgbe_media_type_backplane;
1499 case IXGBE_DEV_ID_X550EM_X_SFP:
1500 case IXGBE_DEV_ID_X550EM_A_SFP:
1501 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1502 case IXGBE_DEV_ID_X550EM_A_QSFP:
1503 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1504 media_type = ixgbe_media_type_fiber;
1506 case IXGBE_DEV_ID_X550EM_X_1G_T:
1507 case IXGBE_DEV_ID_X550EM_X_10G_T:
1508 case IXGBE_DEV_ID_X550EM_A_10G_T:
1509 media_type = ixgbe_media_type_copper;
1511 case IXGBE_DEV_ID_X550EM_A_SGMII:
1512 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1513 media_type = ixgbe_media_type_backplane;
1514 hw->phy.type = ixgbe_phy_sgmii;
1516 case IXGBE_DEV_ID_X550EM_A_1G_T:
1517 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1518 media_type = ixgbe_media_type_copper;
1521 media_type = ixgbe_media_type_unknown;
1528 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1529 * @hw: pointer to hardware structure
1530 * @linear: true if SFP module is linear
1532 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1534 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1536 switch (hw->phy.sfp_type) {
1537 case ixgbe_sfp_type_not_present:
1538 return IXGBE_ERR_SFP_NOT_PRESENT;
1539 case ixgbe_sfp_type_da_cu_core0:
1540 case ixgbe_sfp_type_da_cu_core1:
1543 case ixgbe_sfp_type_srlr_core0:
1544 case ixgbe_sfp_type_srlr_core1:
1545 case ixgbe_sfp_type_da_act_lmt_core0:
1546 case ixgbe_sfp_type_da_act_lmt_core1:
1547 case ixgbe_sfp_type_1g_sx_core0:
1548 case ixgbe_sfp_type_1g_sx_core1:
1549 case ixgbe_sfp_type_1g_lx_core0:
1550 case ixgbe_sfp_type_1g_lx_core1:
1553 case ixgbe_sfp_type_unknown:
1554 case ixgbe_sfp_type_1g_cu_core0:
1555 case ixgbe_sfp_type_1g_cu_core1:
1557 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1560 return IXGBE_SUCCESS;
1564 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1565 * @hw: pointer to hardware structure
1567 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1569 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1574 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1576 status = ixgbe_identify_module_generic(hw);
1578 if (status != IXGBE_SUCCESS)
1581 /* Check if SFP module is supported */
1582 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1588 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1589 * @hw: pointer to hardware structure
1591 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1596 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1598 /* Check if SFP module is supported */
1599 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1601 if (status != IXGBE_SUCCESS)
1604 ixgbe_init_mac_link_ops_X550em(hw);
1605 hw->phy.ops.reset = NULL;
1607 return IXGBE_SUCCESS;
1611 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1613 * @hw: pointer to hardware structure
1615 STATIC s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1620 /* Restart auto-negotiation. */
1621 status = hw->mac.ops.read_iosf_sb_reg(hw,
1622 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1623 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1626 DEBUGOUT("Auto-negotiation did not complete\n");
1630 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1631 status = hw->mac.ops.write_iosf_sb_reg(hw,
1632 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1633 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1635 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1638 /* Indicate to FW that AN restart has been asserted */
1639 status = hw->mac.ops.read_iosf_sb_reg(hw,
1640 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1641 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1644 DEBUGOUT("Auto-negotiation did not complete\n");
1648 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1649 status = hw->mac.ops.write_iosf_sb_reg(hw,
1650 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1651 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1658 * ixgbe_setup_sgmii - Set up link for sgmii
1659 * @hw: pointer to hardware structure
1661 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1664 struct ixgbe_mac_info *mac = &hw->mac;
1665 u32 lval, sval, flx_val;
1668 rc = mac->ops.read_iosf_sb_reg(hw,
1669 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1670 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1674 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1675 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1676 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1677 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1678 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1679 rc = mac->ops.write_iosf_sb_reg(hw,
1680 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1681 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1685 rc = mac->ops.read_iosf_sb_reg(hw,
1686 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1687 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1691 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1692 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1693 rc = mac->ops.write_iosf_sb_reg(hw,
1694 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1695 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1699 rc = mac->ops.read_iosf_sb_reg(hw,
1700 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1701 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1705 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1706 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1707 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1708 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1709 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1711 rc = mac->ops.write_iosf_sb_reg(hw,
1712 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1713 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1717 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1721 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1725 * ixgbe_setup_sgmii_m88 - Set up link for sgmii with Marvell PHYs
1726 * @hw: pointer to hardware structure
1728 STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1731 struct ixgbe_mac_info *mac = &hw->mac;
1732 u32 lval, sval, flx_val;
1735 rc = mac->ops.read_iosf_sb_reg(hw,
1736 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1737 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1741 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1742 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1743 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1744 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1745 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1746 rc = mac->ops.write_iosf_sb_reg(hw,
1747 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1748 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1752 rc = mac->ops.read_iosf_sb_reg(hw,
1753 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1754 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1758 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1759 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1760 rc = mac->ops.write_iosf_sb_reg(hw,
1761 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1762 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1766 rc = mac->ops.write_iosf_sb_reg(hw,
1767 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1768 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1772 rc = mac->ops.read_iosf_sb_reg(hw,
1773 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1774 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1778 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1779 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1780 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1781 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1782 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1784 rc = mac->ops.write_iosf_sb_reg(hw,
1785 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1786 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1790 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1792 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1796 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1797 * @hw: pointer to hardware structure
1799 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1801 struct ixgbe_mac_info *mac = &hw->mac;
1803 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1805 switch (hw->mac.ops.get_media_type(hw)) {
1806 case ixgbe_media_type_fiber:
1807 /* CS4227 does not support autoneg, so disable the laser control
1808 * functions for SFP+ fiber
1810 mac->ops.disable_tx_laser = NULL;
1811 mac->ops.enable_tx_laser = NULL;
1812 mac->ops.flap_tx_laser = NULL;
1813 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1814 mac->ops.set_rate_select_speed =
1815 ixgbe_set_soft_rate_select_speed;
1817 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1818 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1819 mac->ops.setup_mac_link =
1820 ixgbe_setup_mac_link_sfp_x550a;
1822 mac->ops.setup_mac_link =
1823 ixgbe_setup_mac_link_sfp_x550em;
1825 case ixgbe_media_type_copper:
1826 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1827 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
1828 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
1829 mac->ops.setup_link = ixgbe_setup_sgmii_m88;
1831 mac->ops.setup_link =
1832 ixgbe_setup_mac_link_t_X550em;
1835 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1836 mac->ops.check_link = ixgbe_check_link_t_X550em;
1839 case ixgbe_media_type_backplane:
1840 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1841 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1842 mac->ops.setup_link = ixgbe_setup_sgmii;
1850 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1851 * @hw: pointer to hardware structure
1852 * @speed: pointer to link speed
1853 * @autoneg: true when autoneg or autotry is enabled
1855 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1856 ixgbe_link_speed *speed,
1859 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1863 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1865 /* CS4227 SFP must not enable auto-negotiation */
1868 /* Check if 1G SFP module. */
1869 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1870 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1871 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1872 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1873 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1874 return IXGBE_SUCCESS;
1877 /* Link capabilities are based on SFP */
1878 if (hw->phy.multispeed_fiber)
1879 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1880 IXGBE_LINK_SPEED_1GB_FULL;
1882 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1884 switch (hw->phy.type) {
1886 *speed = IXGBE_LINK_SPEED_1GB_FULL |
1887 IXGBE_LINK_SPEED_100_FULL |
1888 IXGBE_LINK_SPEED_10_FULL;
1890 case ixgbe_phy_sgmii:
1891 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1893 case ixgbe_phy_x550em_kr:
1894 if (hw->mac.type == ixgbe_mac_X550EM_a) {
1895 /* check different backplane modes */
1896 if (hw->phy.nw_mng_if_sel &
1897 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
1898 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
1900 } else if (hw->device_id ==
1901 IXGBE_DEV_ID_X550EM_A_KR_L) {
1902 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1908 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1909 IXGBE_LINK_SPEED_1GB_FULL;
1915 return IXGBE_SUCCESS;
1919 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1920 * @hw: pointer to hardware structure
1921 * @lsc: pointer to boolean flag which indicates whether external Base T
1922 * PHY interrupt is lsc
1924 * Determime if external Base T PHY interrupt cause is high temperature
1925 * failure alarm or link status change.
1927 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1928 * failure alarm, else return PHY access status.
1930 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1937 /* Vendor alarm triggered */
1938 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1939 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1942 if (status != IXGBE_SUCCESS ||
1943 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1946 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1947 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1948 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1951 if (status != IXGBE_SUCCESS ||
1952 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1953 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1956 /* Global alarm triggered */
1957 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1958 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1961 if (status != IXGBE_SUCCESS)
1964 /* If high temperature failure, then return over temp error and exit */
1965 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1966 /* power down the PHY in case the PHY FW didn't already */
1967 ixgbe_set_copper_phy_power(hw, false);
1968 return IXGBE_ERR_OVERTEMP;
1969 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1970 /* device fault alarm triggered */
1971 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1972 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1975 if (status != IXGBE_SUCCESS)
1978 /* if device fault was due to high temp alarm handle and exit */
1979 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1980 /* power down the PHY in case the PHY FW didn't */
1981 ixgbe_set_copper_phy_power(hw, false);
1982 return IXGBE_ERR_OVERTEMP;
1986 /* Vendor alarm 2 triggered */
1987 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1988 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1990 if (status != IXGBE_SUCCESS ||
1991 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1994 /* link connect/disconnect event occurred */
1995 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1996 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1998 if (status != IXGBE_SUCCESS)
2002 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2005 return IXGBE_SUCCESS;
2009 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2010 * @hw: pointer to hardware structure
2012 * Enable link status change and temperature failure alarm for the external
2015 * Returns PHY access status
2017 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2023 /* Clear interrupt flags */
2024 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2026 /* Enable link status change alarm */
2027 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2028 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
2030 if (status != IXGBE_SUCCESS)
2033 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2035 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2036 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
2038 if (status != IXGBE_SUCCESS)
2041 /* Enable high temperature failure and global fault alarms */
2042 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2043 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2046 if (status != IXGBE_SUCCESS)
2049 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2050 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2052 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2053 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2056 if (status != IXGBE_SUCCESS)
2059 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2060 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2061 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2064 if (status != IXGBE_SUCCESS)
2067 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2068 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2070 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2071 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2074 if (status != IXGBE_SUCCESS)
2077 /* Enable chip-wide vendor alarm */
2078 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2079 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2082 if (status != IXGBE_SUCCESS)
2085 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2087 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2088 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2095 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2096 * @hw: pointer to hardware structure
2097 * @speed: link speed
2099 * Configures the integrated KR PHY.
2101 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2102 ixgbe_link_speed speed)
2107 status = hw->mac.ops.read_iosf_sb_reg(hw,
2108 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2109 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2113 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2114 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2115 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2117 /* Advertise 10G support. */
2118 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2119 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2121 /* Advertise 1G support. */
2122 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2123 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2125 status = hw->mac.ops.write_iosf_sb_reg(hw,
2126 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2127 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2129 if (hw->mac.type == ixgbe_mac_X550EM_a) {
2130 /* Set lane mode to KR auto negotiation */
2131 status = hw->mac.ops.read_iosf_sb_reg(hw,
2132 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2133 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2138 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2139 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2140 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2141 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2142 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2144 status = hw->mac.ops.write_iosf_sb_reg(hw,
2145 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2146 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2149 return ixgbe_restart_an_internal_phy_x550em(hw);
2153 * ixgbe_setup_m88 - setup m88 PHY
2154 * @hw: pointer to hardware structure
2156 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2158 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2162 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2163 return IXGBE_SUCCESS;
2165 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2169 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2172 if (reg & IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN) {
2173 reg &= ~IXGBE_M88E1500_COPPER_CTRL_POWER_DOWN;
2174 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2178 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, ®);
2181 if (reg & IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN) {
2182 reg &= ~IXGBE_M88E1500_MAC_CTRL_1_POWER_DOWN;
2183 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0,
2187 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 2);
2191 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2195 if (reg & IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN) {
2196 reg &= ~IXGBE_M88E1500_MAC_SPEC_CTRL_POWER_DOWN;
2197 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_SPEC_CTRL, 0,
2199 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2203 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2207 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2208 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2212 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0,
2218 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2222 if (!(reg & IXGBE_M88E1500_COPPER_CTRL_AN_EN)) {
2223 reg |= IXGBE_M88E1500_COPPER_CTRL_AN_EN;
2224 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2228 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, ®);
2231 reg &= ~IXGBE_M88E1500_1000T_CTRL_HALF_DUPLEX;
2232 reg &= ~IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2233 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2234 reg |= IXGBE_M88E1500_1000T_CTRL_FULL_DUPLEX;
2235 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_1000T_CTRL, 0, reg);
2237 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, ®);
2240 reg &= ~IXGBE_M88E1500_COPPER_AN_T4;
2241 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_FD;
2242 reg &= ~IXGBE_M88E1500_COPPER_AN_100TX_HD;
2243 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_FD;
2244 reg &= ~IXGBE_M88E1500_COPPER_AN_10TX_HD;
2246 /* Flow control auto negotiation configuration was moved from here to
2247 * the function ixgbe_setup_fc_sgmii_x550em_a()
2250 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
2251 reg |= IXGBE_M88E1500_COPPER_AN_100TX_FD;
2252 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
2253 reg |= IXGBE_M88E1500_COPPER_AN_10TX_FD;
2254 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_AN, 0, reg);
2256 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2259 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
2260 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2263 hw->mac.ops.release_swfw_sync(hw, mask);
2267 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2268 hw->mac.ops.release_swfw_sync(hw, mask);
2273 * ixgbe_reset_phy_m88e1500 - Reset m88e1500 PHY
2274 * @hw: pointer to hardware structure
2276 * The PHY token must be held when calling this function.
2278 static s32 ixgbe_reset_phy_m88e1500(struct ixgbe_hw *hw)
2283 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2287 rc = hw->phy.ops.read_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, ®);
2291 reg |= IXGBE_M88E1500_COPPER_CTRL_RESET;
2292 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2300 * ixgbe_reset_phy_m88e1543 - Reset m88e1543 PHY
2301 * @hw: pointer to hardware structure
2303 * The PHY token must be held when calling this function.
2305 static s32 ixgbe_reset_phy_m88e1543(struct ixgbe_hw *hw)
2307 return hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2311 * ixgbe_reset_phy_m88 - Reset m88 PHY
2312 * @hw: pointer to hardware structure
2314 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2316 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2320 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2321 return IXGBE_SUCCESS;
2323 rc = hw->mac.ops.acquire_swfw_sync(hw, mask);
2327 switch (hw->phy.id) {
2328 case IXGBE_M88E1500_E_PHY_ID:
2329 rc = ixgbe_reset_phy_m88e1500(hw);
2331 case IXGBE_M88E1543_E_PHY_ID:
2332 rc = ixgbe_reset_phy_m88e1543(hw);
2339 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2343 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2344 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2345 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2346 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2350 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2354 reg = IXGBE_M88E1500_GEN_CTRL_RESET |
2355 IXGBE_M88E1500_GEN_CTRL_MODE_SGMII_COPPER;
2356 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_GEN_CTRL, 0, reg);
2360 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2364 reg = IXGBE_M88E1500_FIBER_CTRL_RESET |
2365 IXGBE_M88E1500_FIBER_CTRL_AN_EN |
2366 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2367 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB;
2368 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_FIBER_CTRL, 0, reg);
2372 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2376 reg = (IXGBE_M88E1500_MAC_CTRL_1_DWN_4X <<
2377 IXGBE_M88E1500_MAC_CTRL_1_DWN_SHIFT) |
2378 (IXGBE_M88E1500_MAC_CTRL_1_ED_TM <<
2379 IXGBE_M88E1500_MAC_CTRL_1_ED_SHIFT) |
2380 (IXGBE_M88E1500_MAC_CTRL_1_MDIX_AUTO <<
2381 IXGBE_M88E1500_MAC_CTRL_1_MDIX_SHIFT);
2382 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_MAC_CTRL_1, 0, reg);
2386 reg = IXGBE_M88E1500_COPPER_CTRL_RESET |
2387 IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2388 IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2389 IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2390 IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB;
2391 rc = hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_COPPER_CTRL, 0, reg);
2395 hw->mac.ops.release_swfw_sync(hw, mask);
2397 /* In case of first reset set advertised speeds to default value */
2398 if (!hw->phy.autoneg_advertised)
2399 hw->phy.autoneg_advertised = IXGBE_LINK_SPEED_1GB_FULL |
2400 IXGBE_LINK_SPEED_100_FULL |
2401 IXGBE_LINK_SPEED_10_FULL;
2403 return ixgbe_setup_m88(hw);
2406 hw->phy.ops.write_reg_mdi(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2407 hw->mac.ops.release_swfw_sync(hw, mask);
2412 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2413 * @hw: pointer to hardware structure
2415 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2418 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2420 /* Save NW management interface connected on board. This is used
2421 * to determine internal PHY mode.
2423 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2425 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2426 * PHY address. This register field was has only been used for X552.
2428 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2429 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2430 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2431 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2432 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2435 return IXGBE_SUCCESS;
2439 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2440 * @hw: pointer to hardware structure
2442 * Initialize any function pointers that were not able to be
2443 * set during init_shared_code because the PHY/SFP type was
2444 * not known. Perform the SFP init if necessary.
2446 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2448 struct ixgbe_phy_info *phy = &hw->phy;
2451 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2453 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2454 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2455 ixgbe_setup_mux_ctl(hw);
2456 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2459 switch (hw->device_id) {
2460 case IXGBE_DEV_ID_X550EM_A_1G_T:
2461 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2462 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2463 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2464 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2465 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2467 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2469 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2472 case IXGBE_DEV_ID_X550EM_A_10G_T:
2473 case IXGBE_DEV_ID_X550EM_A_SFP:
2474 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
2475 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
2477 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
2479 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
2481 case IXGBE_DEV_ID_X550EM_X_SFP:
2482 /* set up for CS4227 usage */
2483 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2489 /* Identify the PHY or SFP module */
2490 ret_val = phy->ops.identify(hw);
2491 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2494 /* Setup function pointers based on detected hardware */
2495 ixgbe_init_mac_link_ops_X550em(hw);
2496 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2497 phy->ops.reset = NULL;
2499 /* Set functions pointers based on phy type */
2500 switch (hw->phy.type) {
2501 case ixgbe_phy_x550em_kx4:
2502 phy->ops.setup_link = NULL;
2503 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2504 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2506 case ixgbe_phy_x550em_kr:
2507 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2508 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2509 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2511 case ixgbe_phy_x550em_ext_t:
2512 /* If internal link mode is XFI, then setup iXFI internal link,
2513 * else setup KR now.
2515 phy->ops.setup_internal_link =
2516 ixgbe_setup_internal_phy_t_x550em;
2518 /* setup SW LPLU only for first revision of X550EM_x */
2519 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2520 !(IXGBE_FUSES0_REV_MASK &
2521 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2522 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2524 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2525 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2527 case ixgbe_phy_sgmii:
2528 phy->ops.setup_link = NULL;
2531 phy->ops.setup_link = ixgbe_setup_m88;
2532 phy->ops.reset = ixgbe_reset_phy_m88;
2541 * ixgbe_set_mdio_speed - Set MDIO clock speed
2542 * @hw: pointer to hardware structure
2544 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2548 switch (hw->device_id) {
2549 case IXGBE_DEV_ID_X550EM_X_10G_T:
2550 case IXGBE_DEV_ID_X550EM_A_SGMII:
2551 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2552 case IXGBE_DEV_ID_X550EM_A_1G_T:
2553 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2554 case IXGBE_DEV_ID_X550EM_A_10G_T:
2555 case IXGBE_DEV_ID_X550EM_A_SFP:
2556 case IXGBE_DEV_ID_X550EM_A_QSFP:
2557 /* Config MDIO clock speed before the first MDIO PHY access */
2558 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2559 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2560 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2568 * ixgbe_reset_hw_X550em - Perform hardware reset
2569 * @hw: pointer to hardware structure
2571 * Resets the hardware by resetting the transmit and receive units, masks
2572 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2575 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2577 ixgbe_link_speed link_speed;
2581 bool link_up = false;
2583 DEBUGFUNC("ixgbe_reset_hw_X550em");
2585 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2586 status = hw->mac.ops.stop_adapter(hw);
2587 if (status != IXGBE_SUCCESS)
2590 /* flush pending Tx transactions */
2591 ixgbe_clear_tx_pending(hw);
2593 ixgbe_set_mdio_speed(hw);
2595 /* PHY ops must be identified and initialized prior to reset */
2596 status = hw->phy.ops.init(hw);
2598 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2601 /* start the external PHY */
2602 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2603 status = ixgbe_init_ext_t_x550em(hw);
2608 /* Setup SFP module if there is one present. */
2609 if (hw->phy.sfp_setup_needed) {
2610 status = hw->mac.ops.setup_sfp(hw);
2611 hw->phy.sfp_setup_needed = false;
2614 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2618 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2619 hw->phy.ops.reset(hw);
2622 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2623 * If link reset is used when link is up, it might reset the PHY when
2624 * mng is using it. If link is down or the flag to force full link
2625 * reset is set, then perform link reset.
2627 ctrl = IXGBE_CTRL_LNK_RST;
2628 if (!hw->force_full_reset) {
2629 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2631 ctrl = IXGBE_CTRL_RST;
2634 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2635 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2636 IXGBE_WRITE_FLUSH(hw);
2638 /* Poll for reset bit to self-clear meaning reset is complete */
2639 for (i = 0; i < 10; i++) {
2641 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2642 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2646 if (ctrl & IXGBE_CTRL_RST_MASK) {
2647 status = IXGBE_ERR_RESET_FAILED;
2648 DEBUGOUT("Reset polling failed to complete.\n");
2653 /* Double resets are required for recovery from certain error
2654 * conditions. Between resets, it is necessary to stall to
2655 * allow time for any pending HW events to complete.
2657 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2658 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2662 /* Store the permanent mac address */
2663 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2665 /* Store MAC address from RAR0, clear receive address registers, and
2666 * clear the multicast table. Also reset num_rar_entries to 128,
2667 * since we modify this value when programming the SAN MAC address.
2669 hw->mac.num_rar_entries = 128;
2670 hw->mac.ops.init_rx_addrs(hw);
2672 ixgbe_set_mdio_speed(hw);
2674 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2675 ixgbe_setup_mux_ctl(hw);
2681 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2682 * @hw: pointer to hardware structure
2684 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2689 status = hw->phy.ops.read_reg(hw,
2690 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2691 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2694 if (status != IXGBE_SUCCESS)
2697 /* If PHY FW reset completed bit is set then this is the first
2698 * SW instance after a power on so the PHY FW must be un-stalled.
2700 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2701 status = hw->phy.ops.read_reg(hw,
2702 IXGBE_MDIO_GLOBAL_RES_PR_10,
2703 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2706 if (status != IXGBE_SUCCESS)
2709 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2711 status = hw->phy.ops.write_reg(hw,
2712 IXGBE_MDIO_GLOBAL_RES_PR_10,
2713 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2716 if (status != IXGBE_SUCCESS)
2724 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2725 * @hw: pointer to hardware structure
2727 * Configures the integrated KR PHY for X550EM_x.
2729 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2731 if (hw->mac.type != ixgbe_mac_X550EM_x)
2732 return IXGBE_SUCCESS;
2734 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2738 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2739 * @hw: pointer to hardware structure
2741 * Configure the external PHY and the integrated KR PHY for SFP support.
2743 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2744 ixgbe_link_speed speed,
2745 bool autoneg_wait_to_complete)
2748 u16 reg_slice, reg_val;
2749 bool setup_linear = false;
2750 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2752 /* Check if SFP module is supported and linear */
2753 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2755 /* If no SFP module present, then return success. Return success since
2756 * there is no reason to configure CS4227 and SFP not present error is
2757 * not excepted in the setup MAC link flow.
2759 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2760 return IXGBE_SUCCESS;
2762 if (ret_val != IXGBE_SUCCESS)
2765 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2766 /* Configure CS4227 LINE side to 10G SR. */
2767 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2768 (hw->bus.lan_id << 12);
2769 reg_val = IXGBE_CS4227_SPEED_10G;
2770 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2773 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2774 (hw->bus.lan_id << 12);
2775 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2776 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2779 /* Configure CS4227 for HOST connection rate then type. */
2780 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2781 (hw->bus.lan_id << 12);
2782 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2783 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2784 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2787 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2788 (hw->bus.lan_id << 12);
2790 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2792 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2793 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2796 /* Setup XFI internal link. */
2797 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2799 /* Configure internal PHY for KR/KX. */
2800 ixgbe_setup_kr_speed_x550em(hw, speed);
2802 /* Configure CS4227 LINE side to proper mode. */
2803 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2804 (hw->bus.lan_id << 12);
2806 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2808 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2809 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2816 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
2817 * @hw: pointer to hardware structure
2818 * @speed: the link speed to force
2820 * Configures the integrated PHY for native SFI mode. Used to connect the
2821 * internal PHY directly to an SFP cage, without autonegotiation.
2823 STATIC s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2825 struct ixgbe_mac_info *mac = &hw->mac;
2829 /* Disable all AN and force speed to 10G Serial. */
2830 status = mac->ops.read_iosf_sb_reg(hw,
2831 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2832 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2833 if (status != IXGBE_SUCCESS)
2836 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2837 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2838 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2839 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2841 /* Select forced link speed for internal PHY. */
2843 case IXGBE_LINK_SPEED_10GB_FULL:
2844 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2846 case IXGBE_LINK_SPEED_1GB_FULL:
2847 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2850 /* Other link speeds are not supported by internal PHY. */
2851 return IXGBE_ERR_LINK_SETUP;
2854 status = mac->ops.write_iosf_sb_reg(hw,
2855 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2856 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2858 /* Toggle port SW reset by AN reset. */
2859 status = ixgbe_restart_an_internal_phy_x550em(hw);
2865 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2866 * @hw: pointer to hardware structure
2868 * Configure the the integrated PHY for SFP support.
2870 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2871 ixgbe_link_speed speed,
2872 bool autoneg_wait_to_complete)
2876 bool setup_linear = false;
2877 u32 reg_slice, reg_phy_int, slice_offset;
2879 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2881 /* Check if SFP module is supported and linear */
2882 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2884 /* If no SFP module present, then return success. Return success since
2885 * SFP not present error is not excepted in the setup MAC link flow.
2887 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2888 return IXGBE_SUCCESS;
2890 if (ret_val != IXGBE_SUCCESS)
2893 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2894 /* Configure internal PHY for native SFI based on module type */
2895 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2896 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2897 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2899 if (ret_val != IXGBE_SUCCESS)
2902 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
2904 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
2906 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2907 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2908 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2910 if (ret_val != IXGBE_SUCCESS)
2913 /* Setup SFI internal link. */
2914 ret_val = ixgbe_setup_sfi_x550a(hw, &speed);
2916 /* Configure internal PHY for KR/KX. */
2917 ixgbe_setup_kr_speed_x550em(hw, speed);
2919 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2921 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2922 return IXGBE_ERR_PHY_ADDR_INVALID;
2925 /* Get external PHY device id */
2926 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2927 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2929 if (ret_val != IXGBE_SUCCESS)
2932 /* When configuring quad port CS4223, the MAC instance is part
2933 * of the slice offset.
2935 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2936 slice_offset = (hw->bus.lan_id +
2937 (hw->bus.instance_id << 1)) << 12;
2939 slice_offset = hw->bus.lan_id << 12;
2941 /* Configure CS4227/CS4223 LINE side to proper mode. */
2942 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2944 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2946 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2947 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2948 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2954 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2955 * @hw: pointer to hardware structure
2957 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2959 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2961 struct ixgbe_mac_info *mac = &hw->mac;
2965 /* Disable training protocol FSM. */
2966 status = mac->ops.read_iosf_sb_reg(hw,
2967 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2968 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2969 if (status != IXGBE_SUCCESS)
2971 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2972 status = mac->ops.write_iosf_sb_reg(hw,
2973 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2974 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2975 if (status != IXGBE_SUCCESS)
2978 /* Disable Flex from training TXFFE. */
2979 status = mac->ops.read_iosf_sb_reg(hw,
2980 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2981 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2982 if (status != IXGBE_SUCCESS)
2984 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2985 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2986 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2987 status = mac->ops.write_iosf_sb_reg(hw,
2988 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2989 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2990 if (status != IXGBE_SUCCESS)
2992 status = mac->ops.read_iosf_sb_reg(hw,
2993 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2994 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2995 if (status != IXGBE_SUCCESS)
2997 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2998 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2999 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
3000 status = mac->ops.write_iosf_sb_reg(hw,
3001 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
3002 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3003 if (status != IXGBE_SUCCESS)
3006 /* Enable override for coefficients. */
3007 status = mac->ops.read_iosf_sb_reg(hw,
3008 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3009 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3010 if (status != IXGBE_SUCCESS)
3012 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
3013 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
3014 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
3015 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
3016 status = mac->ops.write_iosf_sb_reg(hw,
3017 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
3018 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3023 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
3024 * @hw: pointer to hardware structure
3025 * @speed: the link speed to force
3027 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
3028 * internal and external PHY at a specific speed, without autonegotiation.
3030 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
3032 struct ixgbe_mac_info *mac = &hw->mac;
3036 /* Disable AN and force speed to 10G Serial. */
3037 status = mac->ops.read_iosf_sb_reg(hw,
3038 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3039 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3040 if (status != IXGBE_SUCCESS)
3043 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3044 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3046 /* Select forced link speed for internal PHY. */
3048 case IXGBE_LINK_SPEED_10GB_FULL:
3049 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3051 case IXGBE_LINK_SPEED_1GB_FULL:
3052 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
3055 /* Other link speeds are not supported by internal KR PHY. */
3056 return IXGBE_ERR_LINK_SETUP;
3059 status = mac->ops.write_iosf_sb_reg(hw,
3060 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3061 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3062 if (status != IXGBE_SUCCESS)
3065 /* Additional configuration needed for x550em_x */
3066 if (hw->mac.type == ixgbe_mac_X550EM_x) {
3067 status = ixgbe_setup_ixfi_x550em_x(hw);
3068 if (status != IXGBE_SUCCESS)
3072 /* Toggle port SW reset by AN reset. */
3073 status = ixgbe_restart_an_internal_phy_x550em(hw);
3079 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
3080 * @hw: address of hardware structure
3081 * @link_up: address of boolean to indicate link status
3083 * Returns error code if unable to get link status.
3085 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
3092 /* read this twice back to back to indicate current status */
3093 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3094 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3096 if (ret != IXGBE_SUCCESS)
3099 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3100 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3102 if (ret != IXGBE_SUCCESS)
3105 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
3107 return IXGBE_SUCCESS;
3111 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
3112 * @hw: point to hardware structure
3114 * Configures the link between the integrated KR PHY and the external X557 PHY
3115 * The driver will call this function when it gets a link status change
3116 * interrupt from the X557 PHY. This function configures the link speed
3117 * between the PHYs to match the link speed of the BASE-T link.
3119 * A return of a non-zero value indicates an error, and the base driver should
3120 * not report link up.
3122 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
3124 ixgbe_link_speed force_speed;
3129 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3130 return IXGBE_ERR_CONFIG;
3132 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3133 /* If link is down, there is no setup necessary so return */
3134 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3135 if (status != IXGBE_SUCCESS)
3139 return IXGBE_SUCCESS;
3141 status = hw->phy.ops.read_reg(hw,
3142 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3143 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3145 if (status != IXGBE_SUCCESS)
3148 /* If link is still down - no setup is required so return */
3149 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3150 if (status != IXGBE_SUCCESS)
3153 return IXGBE_SUCCESS;
3155 /* clear everything but the speed and duplex bits */
3156 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
3159 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
3160 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3162 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
3163 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3166 /* Internal PHY does not support anything else */
3167 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3170 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
3172 speed = IXGBE_LINK_SPEED_10GB_FULL |
3173 IXGBE_LINK_SPEED_1GB_FULL;
3174 return ixgbe_setup_kr_speed_x550em(hw, speed);
3179 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
3180 * @hw: pointer to hardware structure
3182 * Configures the integrated KR PHY to use internal loopback mode.
3184 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
3189 /* Disable AN and force speed to 10G Serial. */
3190 status = hw->mac.ops.read_iosf_sb_reg(hw,
3191 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3192 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3193 if (status != IXGBE_SUCCESS)
3195 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3196 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3197 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3198 status = hw->mac.ops.write_iosf_sb_reg(hw,
3199 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3200 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3201 if (status != IXGBE_SUCCESS)
3204 /* Set near-end loopback clocks. */
3205 status = hw->mac.ops.read_iosf_sb_reg(hw,
3206 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3207 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3208 if (status != IXGBE_SUCCESS)
3210 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3211 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3212 status = hw->mac.ops.write_iosf_sb_reg(hw,
3213 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
3214 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3215 if (status != IXGBE_SUCCESS)
3218 /* Set loopback enable. */
3219 status = hw->mac.ops.read_iosf_sb_reg(hw,
3220 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3221 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3222 if (status != IXGBE_SUCCESS)
3224 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3225 status = hw->mac.ops.write_iosf_sb_reg(hw,
3226 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
3227 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3228 if (status != IXGBE_SUCCESS)
3231 /* Training bypass. */
3232 status = hw->mac.ops.read_iosf_sb_reg(hw,
3233 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3234 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3235 if (status != IXGBE_SUCCESS)
3237 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3238 status = hw->mac.ops.write_iosf_sb_reg(hw,
3239 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
3240 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3246 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
3247 * assuming that the semaphore is already obtained.
3248 * @hw: pointer to hardware structure
3249 * @offset: offset of word in the EEPROM to read
3250 * @data: word read from the EEPROM
3252 * Reads a 16 bit word from the EEPROM using the hostif.
3254 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
3256 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3257 struct ixgbe_hic_read_shadow_ram buffer;
3260 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
3261 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3262 buffer.hdr.req.buf_lenh = 0;
3263 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3264 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3266 /* convert offset from words to bytes */
3267 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3269 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3271 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3275 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3276 IXGBE_HI_COMMAND_TIMEOUT);
3278 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3279 FW_NVM_DATA_OFFSET);
3282 hw->mac.ops.release_swfw_sync(hw, mask);
3287 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
3288 * @hw: pointer to hardware structure
3289 * @offset: offset of word in the EEPROM to read
3290 * @words: number of words
3291 * @data: word(s) read from the EEPROM
3293 * Reads a 16 bit word(s) from the EEPROM using the hostif.
3295 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3296 u16 offset, u16 words, u16 *data)
3298 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
3299 struct ixgbe_hic_read_shadow_ram buffer;
3300 u32 current_word = 0;
3305 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
3307 /* Take semaphore for the entire operation. */
3308 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
3310 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
3315 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
3316 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
3318 words_to_read = words;
3320 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
3321 buffer.hdr.req.buf_lenh = 0;
3322 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
3323 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3325 /* convert offset from words to bytes */
3326 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
3327 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
3329 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
3330 IXGBE_HI_COMMAND_TIMEOUT);
3333 DEBUGOUT("Host interface command failed\n");
3337 for (i = 0; i < words_to_read; i++) {
3338 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
3340 u32 value = IXGBE_READ_REG(hw, reg);
3342 data[current_word] = (u16)(value & 0xffff);
3345 if (i < words_to_read) {
3347 data[current_word] = (u16)(value & 0xffff);
3351 words -= words_to_read;
3355 hw->mac.ops.release_swfw_sync(hw, mask);
3360 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3361 * @hw: pointer to hardware structure
3362 * @offset: offset of word in the EEPROM to write
3363 * @data: word write to the EEPROM
3365 * Write a 16 bit word to the EEPROM using the hostif.
3367 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3371 struct ixgbe_hic_write_shadow_ram buffer;
3373 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3375 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3376 buffer.hdr.req.buf_lenh = 0;
3377 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3378 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3381 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3383 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3385 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3387 IXGBE_HI_COMMAND_TIMEOUT, false);
3393 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3394 * @hw: pointer to hardware structure
3395 * @offset: offset of word in the EEPROM to write
3396 * @data: word write to the EEPROM
3398 * Write a 16 bit word to the EEPROM using the hostif.
3400 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3403 s32 status = IXGBE_SUCCESS;
3405 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3407 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3409 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3410 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3412 DEBUGOUT("write ee hostif failed to get semaphore");
3413 status = IXGBE_ERR_SWFW_SYNC;
3420 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3421 * @hw: pointer to hardware structure
3422 * @offset: offset of word in the EEPROM to write
3423 * @words: number of words
3424 * @data: word(s) write to the EEPROM
3426 * Write a 16 bit word(s) to the EEPROM using the hostif.
3428 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3429 u16 offset, u16 words, u16 *data)
3431 s32 status = IXGBE_SUCCESS;
3434 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3436 /* Take semaphore for the entire operation. */
3437 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3438 if (status != IXGBE_SUCCESS) {
3439 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3443 for (i = 0; i < words; i++) {
3444 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3447 if (status != IXGBE_SUCCESS) {
3448 DEBUGOUT("Eeprom buffered write failed\n");
3453 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3460 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3461 * @hw: pointer to hardware structure
3462 * @ptr: pointer offset in eeprom
3463 * @size: size of section pointed by ptr, if 0 first word will be used as size
3464 * @csum: address of checksum to update
3466 * Returns error status for any failure
3468 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3469 u16 size, u16 *csum, u16 *buffer,
3474 u16 length, bufsz, i, start;
3477 bufsz = sizeof(buf) / sizeof(buf[0]);
3479 /* Read a chunk at the pointer location */
3481 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3483 DEBUGOUT("Failed to read EEPROM image\n");
3488 if (buffer_size < ptr)
3489 return IXGBE_ERR_PARAM;
3490 local_buffer = &buffer[ptr];
3498 length = local_buffer[0];
3500 /* Skip pointer section if length is invalid. */
3501 if (length == 0xFFFF || length == 0 ||
3502 (ptr + length) >= hw->eeprom.word_size)
3503 return IXGBE_SUCCESS;
3506 if (buffer && ((u32)start + (u32)length > buffer_size))
3507 return IXGBE_ERR_PARAM;
3509 for (i = start; length; i++, length--) {
3510 if (i == bufsz && !buffer) {
3516 /* Read a chunk at the pointer location */
3517 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3520 DEBUGOUT("Failed to read EEPROM image\n");
3524 *csum += local_buffer[i];
3526 return IXGBE_SUCCESS;
3530 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3531 * @hw: pointer to hardware structure
3532 * @buffer: pointer to buffer containing calculated checksum
3533 * @buffer_size: size of buffer
3535 * Returns a negative error code on error, or the 16-bit checksum
3537 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3539 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3543 u16 pointer, i, size;
3545 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3547 hw->eeprom.ops.init_params(hw);
3550 /* Read pointer area */
3551 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3552 IXGBE_EEPROM_LAST_WORD + 1,
3555 DEBUGOUT("Failed to read EEPROM image\n");
3558 local_buffer = eeprom_ptrs;
3560 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3561 return IXGBE_ERR_PARAM;
3562 local_buffer = buffer;
3566 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3567 * checksum word itself
3569 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3570 if (i != IXGBE_EEPROM_CHECKSUM)
3571 checksum += local_buffer[i];
3574 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3575 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3577 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3578 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3581 pointer = local_buffer[i];
3583 /* Skip pointer section if the pointer is invalid. */
3584 if (pointer == 0xFFFF || pointer == 0 ||
3585 pointer >= hw->eeprom.word_size)
3589 case IXGBE_PCIE_GENERAL_PTR:
3590 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3592 case IXGBE_PCIE_CONFIG0_PTR:
3593 case IXGBE_PCIE_CONFIG1_PTR:
3594 size = IXGBE_PCIE_CONFIG_SIZE;
3601 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3602 buffer, buffer_size);
3607 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3609 return (s32)checksum;
3613 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3614 * @hw: pointer to hardware structure
3616 * Returns a negative error code on error, or the 16-bit checksum
3618 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3620 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3624 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3625 * @hw: pointer to hardware structure
3626 * @checksum_val: calculated checksum
3628 * Performs checksum calculation and validates the EEPROM checksum. If the
3629 * caller does not need checksum_val, the value can be NULL.
3631 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3635 u16 read_checksum = 0;
3637 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3639 /* Read the first word from the EEPROM. If this times out or fails, do
3640 * not continue or we could be in for a very long wait while every
3643 status = hw->eeprom.ops.read(hw, 0, &checksum);
3645 DEBUGOUT("EEPROM read failed\n");
3649 status = hw->eeprom.ops.calc_checksum(hw);
3653 checksum = (u16)(status & 0xffff);
3655 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3660 /* Verify read checksum from EEPROM is the same as
3661 * calculated checksum
3663 if (read_checksum != checksum) {
3664 status = IXGBE_ERR_EEPROM_CHECKSUM;
3665 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3666 "Invalid EEPROM checksum");
3669 /* If the user cares, return the calculated checksum */
3671 *checksum_val = checksum;
3677 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3678 * @hw: pointer to hardware structure
3680 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3681 * checksum and updates the EEPROM and instructs the hardware to update
3684 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3689 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3691 /* Read the first word from the EEPROM. If this times out or fails, do
3692 * not continue or we could be in for a very long wait while every
3695 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3697 DEBUGOUT("EEPROM read failed\n");
3701 status = ixgbe_calc_eeprom_checksum_X550(hw);
3705 checksum = (u16)(status & 0xffff);
3707 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3712 status = ixgbe_update_flash_X550(hw);
3718 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3719 * @hw: pointer to hardware structure
3721 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3723 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3725 s32 status = IXGBE_SUCCESS;
3726 union ixgbe_hic_hdr2 buffer;
3728 DEBUGFUNC("ixgbe_update_flash_X550");
3730 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3731 buffer.req.buf_lenh = 0;
3732 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3733 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3735 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3737 IXGBE_HI_COMMAND_TIMEOUT, false);
3743 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3744 * @hw: pointer to hardware structure
3746 * Determines physical layer capabilities of the current configuration.
3748 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3750 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3751 u16 ext_ability = 0;
3753 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3755 hw->phy.ops.identify(hw);
3757 switch (hw->phy.type) {
3758 case ixgbe_phy_x550em_kr:
3759 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3760 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3762 case ixgbe_phy_x550em_kx4:
3763 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3764 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3766 case ixgbe_phy_x550em_ext_t:
3767 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3768 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3770 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3771 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3772 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3773 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3779 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3780 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3782 return physical_layer;
3786 * ixgbe_get_bus_info_x550em - Set PCI bus info
3787 * @hw: pointer to hardware structure
3789 * Sets bus link width and speed to unknown because X550em is
3792 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3795 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3797 hw->bus.width = ixgbe_bus_width_unknown;
3798 hw->bus.speed = ixgbe_bus_speed_unknown;
3800 hw->mac.ops.set_lan_id(hw);
3802 return IXGBE_SUCCESS;
3806 * ixgbe_disable_rx_x550 - Disable RX unit
3808 * Enables the Rx DMA unit for x550
3810 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3812 u32 rxctrl, pfdtxgswc;
3814 struct ixgbe_hic_disable_rxen fw_cmd;
3816 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3818 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3819 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3820 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3821 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3822 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3823 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3824 hw->mac.set_lben = true;
3826 hw->mac.set_lben = false;
3829 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3830 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3831 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3832 fw_cmd.port_number = (u8)hw->bus.lan_id;
3834 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3835 sizeof(struct ixgbe_hic_disable_rxen),
3836 IXGBE_HI_COMMAND_TIMEOUT, true);
3838 /* If we fail - disable RX using register write */
3840 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3841 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3842 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3843 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3850 * ixgbe_enter_lplu_x550em - Transition to low power states
3851 * @hw: pointer to hardware structure
3853 * Configures Low Power Link Up on transition to low power states
3854 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3855 * X557 PHY immediately prior to entering LPLU.
3857 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3859 u16 an_10g_cntl_reg, autoneg_reg, speed;
3861 ixgbe_link_speed lcd_speed;
3865 /* SW LPLU not required on later HW revisions. */
3866 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3867 (IXGBE_FUSES0_REV_MASK &
3868 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3869 return IXGBE_SUCCESS;
3871 /* If blocked by MNG FW, then don't restart AN */
3872 if (ixgbe_check_reset_blocked(hw))
3873 return IXGBE_SUCCESS;
3875 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3876 if (status != IXGBE_SUCCESS)
3879 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3881 if (status != IXGBE_SUCCESS)
3884 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3885 * disabled, then force link down by entering low power mode.
3887 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3888 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3889 return ixgbe_set_copper_phy_power(hw, FALSE);
3892 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3894 if (status != IXGBE_SUCCESS)
3897 /* If no valid LCD link speed, then force link down and exit. */
3898 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3899 return ixgbe_set_copper_phy_power(hw, FALSE);
3901 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3902 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3905 if (status != IXGBE_SUCCESS)
3908 /* If no link now, speed is invalid so take link down */
3909 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3910 if (status != IXGBE_SUCCESS)
3911 return ixgbe_set_copper_phy_power(hw, false);
3913 /* clear everything but the speed bits */
3914 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3916 /* If current speed is already LCD, then exit. */
3917 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3918 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3919 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3920 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3923 /* Clear AN completed indication */
3924 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3925 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3928 if (status != IXGBE_SUCCESS)
3931 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3932 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3935 if (status != IXGBE_SUCCESS)
3938 status = hw->phy.ops.read_reg(hw,
3939 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3940 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3943 if (status != IXGBE_SUCCESS)
3946 save_autoneg = hw->phy.autoneg_advertised;
3948 /* Setup link at least common link speed */
3949 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3951 /* restore autoneg from before setting lplu speed */
3952 hw->phy.autoneg_advertised = save_autoneg;
3958 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3959 * @hw: pointer to hardware structure
3960 * @lcd_speed: pointer to lowest common link speed
3962 * Determine lowest common link speed with link partner.
3964 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3968 u16 word = hw->eeprom.ctrl_word_3;
3970 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3972 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3973 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3976 if (status != IXGBE_SUCCESS)
3979 /* If link partner advertised 1G, return 1G */
3980 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3981 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3985 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3986 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3987 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3990 /* Link partner not capable of lower speeds, return 10G */
3991 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3996 * ixgbe_setup_fc_X550em - Set up flow control
3997 * @hw: pointer to hardware structure
3999 * Called at init time to set up flow control.
4001 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
4003 s32 ret_val = IXGBE_SUCCESS;
4004 u32 pause, asm_dir, reg_val;
4006 DEBUGFUNC("ixgbe_setup_fc_X550em");
4008 /* Validate the requested mode */
4009 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4010 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4011 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4012 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4016 /* 10gig parts do not have a word in the EEPROM to determine the
4017 * default flow control setting, so we explicitly set it to full.
4019 if (hw->fc.requested_mode == ixgbe_fc_default)
4020 hw->fc.requested_mode = ixgbe_fc_full;
4022 /* Determine PAUSE and ASM_DIR bits. */
4023 switch (hw->fc.requested_mode) {
4028 case ixgbe_fc_tx_pause:
4032 case ixgbe_fc_rx_pause:
4033 /* Rx Flow control is enabled and Tx Flow control is
4034 * disabled by software override. Since there really
4035 * isn't a way to advertise that we are capable of RX
4036 * Pause ONLY, we will advertise that we support both
4037 * symmetric and asymmetric Rx PAUSE, as such we fall
4038 * through to the fc_full statement. Later, we will
4039 * disable the adapter's ability to send PAUSE frames.
4046 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4047 "Flow control param set incorrectly\n");
4048 ret_val = IXGBE_ERR_CONFIG;
4052 switch (hw->device_id) {
4053 case IXGBE_DEV_ID_X550EM_X_KR:
4054 case IXGBE_DEV_ID_X550EM_A_KR:
4055 case IXGBE_DEV_ID_X550EM_A_KR_L:
4056 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
4057 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4058 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
4059 if (ret_val != IXGBE_SUCCESS)
4061 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4062 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4064 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4066 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4067 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
4068 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4069 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4071 /* This device does not fully support AN. */
4072 hw->fc.disable_fc_autoneg = true;
4083 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
4084 * @hw: pointer to hardware structure
4086 * Enable flow control according to IEEE clause 37.
4088 void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
4090 u32 link_s1, lp_an_page_low, an_cntl_1;
4091 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4092 ixgbe_link_speed speed;
4095 /* AN should have completed when the cable was plugged in.
4096 * Look for reasons to bail out. Bail out if:
4097 * - FC autoneg is disabled, or if
4100 if (hw->fc.disable_fc_autoneg) {
4101 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4102 "Flow control autoneg is disabled");
4106 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4108 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4112 /* Check at auto-negotiation has completed */
4113 status = hw->mac.ops.read_iosf_sb_reg(hw,
4114 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
4115 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
4117 if (status != IXGBE_SUCCESS ||
4118 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
4119 DEBUGOUT("Auto-Negotiation did not complete\n");
4120 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4124 /* Read the 10g AN autoc and LP ability registers and resolve
4125 * local flow control settings accordingly
4127 status = hw->mac.ops.read_iosf_sb_reg(hw,
4128 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4129 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
4131 if (status != IXGBE_SUCCESS) {
4132 DEBUGOUT("Auto-Negotiation did not complete\n");
4136 status = hw->mac.ops.read_iosf_sb_reg(hw,
4137 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
4138 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
4140 if (status != IXGBE_SUCCESS) {
4141 DEBUGOUT("Auto-Negotiation did not complete\n");
4145 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
4146 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
4147 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
4148 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
4149 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
4152 if (status == IXGBE_SUCCESS) {
4153 hw->fc.fc_was_autonegged = true;
4155 hw->fc.fc_was_autonegged = false;
4156 hw->fc.current_mode = hw->fc.requested_mode;
4161 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
4162 * @hw: pointer to hardware structure
4165 void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
4167 hw->fc.fc_was_autonegged = false;
4168 hw->fc.current_mode = hw->fc.requested_mode;
4172 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
4173 * @hw: pointer to hardware structure
4175 * Enable flow control according to IEEE clause 37.
4177 void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
4179 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4180 u16 reg, pcs_an_lp, pcs_an;
4181 ixgbe_link_speed speed;
4184 /* AN should have completed when the cable was plugged in.
4185 * Look for reasons to bail out. Bail out if:
4186 * - FC autoneg is disabled, or if
4189 if (hw->fc.disable_fc_autoneg) {
4190 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4191 "Flow control autoneg is disabled");
4195 hw->mac.ops.check_link(hw, &speed, &link_up, false);
4197 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
4201 /* Check if auto-negotiation has completed */
4202 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_STATUS,
4203 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4204 if (status != IXGBE_SUCCESS ||
4205 (reg & IXGBE_M88E1500_COPPER_STATUS_AN_DONE) == 0) {
4206 DEBUGOUT("Auto-Negotiation did not complete\n");
4207 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
4211 /* Get the advertized flow control */
4212 status = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4213 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an);
4214 if (status != IXGBE_SUCCESS)
4217 /* Get link partner's flow control */
4218 status = hw->phy.ops.read_reg(hw,
4219 IXGBE_M88E1500_COPPER_AN_LP_ABILITY,
4220 IXGBE_MDIO_ZERO_DEV_TYPE, &pcs_an_lp);
4221 if (status != IXGBE_SUCCESS)
4224 /* Negotiate the flow control */
4225 status = ixgbe_negotiate_fc(hw, (u32)pcs_an, (u32)pcs_an_lp,
4226 IXGBE_M88E1500_COPPER_AN_PAUSE,
4227 IXGBE_M88E1500_COPPER_AN_AS_PAUSE,
4228 IXGBE_M88E1500_COPPER_AN_LP_PAUSE,
4229 IXGBE_M88E1500_COPPER_AN_LP_AS_PAUSE);
4232 if (status == IXGBE_SUCCESS) {
4233 hw->fc.fc_was_autonegged = true;
4235 hw->fc.fc_was_autonegged = false;
4236 hw->fc.current_mode = hw->fc.requested_mode;
4241 * ixgbe_setup_fc_sgmii_x550em_a - Set up flow control
4242 * @hw: pointer to hardware structure
4244 * Called at init time to set up flow control.
4246 s32 ixgbe_setup_fc_sgmii_x550em_a(struct ixgbe_hw *hw)
4251 /* Validate the requested mode */
4252 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4253 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4254 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4255 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4258 if (hw->fc.requested_mode == ixgbe_fc_default)
4259 hw->fc.requested_mode = ixgbe_fc_full;
4261 /* Read contents of the Auto-Negotiation register, page 0 reg 4 */
4262 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_AN,
4263 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4267 /* Disable all the settings related to Flow control Auto-negotiation */
4268 reg &= ~IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4269 reg &= ~IXGBE_M88E1500_COPPER_AN_PAUSE;
4271 /* Configure the Asymmetric and symmetric pause according to the user
4274 switch (hw->fc.requested_mode) {
4276 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4277 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4279 case ixgbe_fc_rx_pause:
4280 reg |= IXGBE_M88E1500_COPPER_AN_PAUSE;
4281 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4283 case ixgbe_fc_tx_pause:
4284 reg |= IXGBE_M88E1500_COPPER_AN_AS_PAUSE;
4290 /* Write back to the Auto-Negotiation register with newly configured
4293 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_AN,
4294 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4296 /* In this section of the code we restart Auto-negotiation */
4298 /* Read the CONTROL register, Page 0 reg 0 */
4299 rc = hw->phy.ops.read_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4300 IXGBE_MDIO_ZERO_DEV_TYPE, ®);
4304 /* Set the bit to restart Auto-Neg. The bit to enable Auto-neg is ON
4307 reg |= IXGBE_M88E1500_COPPER_CTRL_RESTART_AN;
4309 /* write the new values to the register to restart Auto-Negotiation */
4310 hw->phy.ops.write_reg(hw, IXGBE_M88E1500_COPPER_CTRL,
4311 IXGBE_MDIO_ZERO_DEV_TYPE, reg);
4318 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
4319 * @hw: pointer to hardware structure
4321 * Called at init time to set up flow control.
4323 s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
4325 s32 status = IXGBE_SUCCESS;
4328 DEBUGFUNC("ixgbe_setup_fc_backplane_x550em_a");
4330 /* Validate the requested mode */
4331 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
4332 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
4333 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
4334 return IXGBE_ERR_INVALID_LINK_SETTINGS;
4337 if (hw->fc.requested_mode == ixgbe_fc_default)
4338 hw->fc.requested_mode = ixgbe_fc_full;
4340 /* Set up the 1G and 10G flow control advertisement registers so the
4341 * HW will be able to do FC autoneg once the cable is plugged in. If
4342 * we link at 10G, the 1G advertisement is harmless and vice versa.
4344 status = hw->mac.ops.read_iosf_sb_reg(hw,
4345 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4346 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
4348 if (status != IXGBE_SUCCESS) {
4349 DEBUGOUT("Auto-Negotiation did not complete\n");
4353 /* The possible values of fc.requested_mode are:
4354 * 0: Flow control is completely disabled
4355 * 1: Rx flow control is enabled (we can receive pause frames,
4356 * but not send pause frames).
4357 * 2: Tx flow control is enabled (we can send pause frames but
4358 * we do not support receiving pause frames).
4359 * 3: Both Rx and Tx flow control (symmetric) are enabled.
4362 switch (hw->fc.requested_mode) {
4364 /* Flow control completely disabled by software override. */
4365 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4366 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
4368 case ixgbe_fc_tx_pause:
4369 /* Tx Flow control is enabled, and Rx Flow control is
4370 * disabled by software override.
4372 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4373 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4375 case ixgbe_fc_rx_pause:
4376 /* Rx Flow control is enabled and Tx Flow control is
4377 * disabled by software override. Since there really
4378 * isn't a way to advertise that we are capable of RX
4379 * Pause ONLY, we will advertise that we support both
4380 * symmetric and asymmetric Rx PAUSE, as such we fall
4381 * through to the fc_full statement. Later, we will
4382 * disable the adapter's ability to send PAUSE frames.
4385 /* Flow control (both Rx and Tx) is enabled by SW override. */
4386 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4387 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4390 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
4391 "Flow control param set incorrectly\n");
4392 return IXGBE_ERR_CONFIG;
4395 status = hw->mac.ops.write_iosf_sb_reg(hw,
4396 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
4397 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
4399 /* Restart auto-negotiation. */
4400 status = ixgbe_restart_an_internal_phy_x550em(hw);
4406 * ixgbe_set_mux - Set mux for port 1 access with CS4227
4407 * @hw: pointer to hardware structure
4408 * @state: set mux if 1, clear if 0
4410 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
4414 if (!hw->bus.lan_id)
4416 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4418 esdp |= IXGBE_ESDP_SDP1;
4420 esdp &= ~IXGBE_ESDP_SDP1;
4421 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4422 IXGBE_WRITE_FLUSH(hw);
4426 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
4427 * @hw: pointer to hardware structure
4428 * @mask: Mask to specify which semaphore to acquire
4430 * Acquires the SWFW semaphore and sets the I2C MUX
4432 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4436 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
4438 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
4442 if (mask & IXGBE_GSSR_I2C_MASK)
4443 ixgbe_set_mux(hw, 1);
4445 return IXGBE_SUCCESS;
4449 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
4450 * @hw: pointer to hardware structure
4451 * @mask: Mask to specify which semaphore to release
4453 * Releases the SWFW semaphore and sets the I2C MUX
4455 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
4457 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
4459 if (mask & IXGBE_GSSR_I2C_MASK)
4460 ixgbe_set_mux(hw, 0);
4462 ixgbe_release_swfw_sync_X540(hw, mask);
4466 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
4467 * @hw: pointer to hardware structure
4468 * @mask: Mask to specify which semaphore to acquire
4470 * Acquires the SWFW semaphore and get the shared phy token as needed
4472 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4474 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4475 int retries = FW_PHY_TOKEN_RETRIES;
4476 s32 status = IXGBE_SUCCESS;
4478 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
4481 status = IXGBE_SUCCESS;
4483 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
4486 if (!(mask & IXGBE_GSSR_TOKEN_SM))
4487 return IXGBE_SUCCESS;
4489 status = ixgbe_get_phy_token(hw);
4490 if (status == IXGBE_SUCCESS)
4491 return IXGBE_SUCCESS;
4494 ixgbe_release_swfw_sync_X540(hw, hmask);
4495 if (status != IXGBE_ERR_TOKEN_RETRY)
4503 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4504 * @hw: pointer to hardware structure
4505 * @mask: Mask to specify which semaphore to release
4507 * Releases the SWFW semaphore and puts the shared phy token as needed
4509 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4511 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4513 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4515 if (mask & IXGBE_GSSR_TOKEN_SM)
4516 ixgbe_put_phy_token(hw);
4519 ixgbe_release_swfw_sync_X540(hw, hmask);
4523 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
4524 * @hw: pointer to hardware structure
4525 * @reg_addr: 32 bit address of PHY register to read
4526 * @phy_data: Pointer to read data from PHY register
4528 * Reads a value from a specified PHY register using the SWFW lock and PHY
4529 * Token. The PHY Token is needed since the MDIO is shared between to MAC
4532 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4533 u32 device_type, u16 *phy_data)
4536 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4538 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4540 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4541 return IXGBE_ERR_SWFW_SYNC;
4543 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4545 hw->mac.ops.release_swfw_sync(hw, mask);
4551 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
4552 * @hw: pointer to hardware structure
4553 * @reg_addr: 32 bit PHY register to write
4554 * @device_type: 5 bit device type
4555 * @phy_data: Data to write to the PHY register
4557 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
4558 * The PHY Token is needed since the MDIO is shared between to MAC instances.
4560 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4561 u32 device_type, u16 phy_data)
4564 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4566 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4568 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4569 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
4571 hw->mac.ops.release_swfw_sync(hw, mask);
4573 status = IXGBE_ERR_SWFW_SYNC;
4580 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4581 * @hw: pointer to hardware structure
4583 * Handle external Base T PHY interrupt. If high temperature
4584 * failure alarm then return error, else if link status change
4585 * then setup internal/external PHY link
4587 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4588 * failure alarm, else return PHY access status.
4590 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4595 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4597 if (status != IXGBE_SUCCESS)
4601 return ixgbe_setup_internal_phy(hw);
4603 return IXGBE_SUCCESS;
4607 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4608 * @hw: pointer to hardware structure
4609 * @speed: new link speed
4610 * @autoneg_wait_to_complete: true when waiting for completion is needed
4612 * Setup internal/external PHY link speed based on link speed, then set
4613 * external PHY auto advertised link speed.
4615 * Returns error status for any failure
4617 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4618 ixgbe_link_speed speed,
4619 bool autoneg_wait_to_complete)
4622 ixgbe_link_speed force_speed;
4624 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4626 /* Setup internal/external PHY link speed to iXFI (10G), unless
4627 * only 1G is auto advertised then setup KX link.
4629 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4630 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4632 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4634 /* If internal link mode is XFI, then setup XFI internal link. */
4635 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4636 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4638 if (status != IXGBE_SUCCESS)
4642 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4646 * ixgbe_check_link_t_X550em - Determine link and speed status
4647 * @hw: pointer to hardware structure
4648 * @speed: pointer to link speed
4649 * @link_up: true when link is up
4650 * @link_up_wait_to_complete: bool used to wait for link up or not
4652 * Check that both the MAC and X557 external PHY have link.
4654 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4655 bool *link_up, bool link_up_wait_to_complete)
4660 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4661 return IXGBE_ERR_CONFIG;
4663 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4664 link_up_wait_to_complete);
4666 /* If check link fails or MAC link is not up, then return */
4667 if (status != IXGBE_SUCCESS || !(*link_up))
4670 /* MAC link is up, so check external PHY link.
4671 * Read this twice back to back to indicate current status.
4673 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4674 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4677 if (status != IXGBE_SUCCESS)
4680 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4681 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4684 if (status != IXGBE_SUCCESS)
4687 /* If external PHY link is not up, then indicate link not up */
4688 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4691 return IXGBE_SUCCESS;
4695 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4696 * @hw: pointer to hardware structure
4698 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4702 status = ixgbe_reset_phy_generic(hw);
4704 if (status != IXGBE_SUCCESS)
4707 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4708 return ixgbe_enable_lasi_ext_t_x550em(hw);
4712 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4713 * @hw: pointer to hardware structure
4714 * @led_idx: led number to turn on
4716 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4720 DEBUGFUNC("ixgbe_led_on_t_X550em");
4722 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4723 return IXGBE_ERR_PARAM;
4725 /* To turn on the LED, set mode to ON. */
4726 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4727 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4728 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4729 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4730 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4732 return IXGBE_SUCCESS;
4736 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4737 * @hw: pointer to hardware structure
4738 * @led_idx: led number to turn off
4740 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4744 DEBUGFUNC("ixgbe_led_off_t_X550em");
4746 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4747 return IXGBE_ERR_PARAM;
4749 /* To turn on the LED, set mode to ON. */
4750 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4751 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4752 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4753 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4754 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4756 return IXGBE_SUCCESS;