1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
46 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
47 * @hw: pointer to hardware structure
49 * Initialize the function pointers and assign the MAC type for X550.
50 * Does not touch the hardware.
52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
54 struct ixgbe_mac_info *mac = &hw->mac;
55 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
58 DEBUGFUNC("ixgbe_init_ops_X550");
60 ret_val = ixgbe_init_ops_X540(hw);
61 mac->ops.dmac_config = ixgbe_dmac_config_X550;
62 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
63 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
64 mac->ops.setup_eee = ixgbe_setup_eee_X550;
65 mac->ops.set_source_address_pruning =
66 ixgbe_set_source_address_pruning_X550;
67 mac->ops.set_ethertype_anti_spoofing =
68 ixgbe_set_ethertype_anti_spoofing_X550;
70 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
71 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
72 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
73 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
74 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
75 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
76 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
77 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
78 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
80 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
81 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
82 mac->ops.mdd_event = ixgbe_mdd_event_X550;
83 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
84 mac->ops.disable_rx = ixgbe_disable_rx_x550;
85 switch (hw->device_id) {
86 case IXGBE_DEV_ID_X550EM_X_10G_T:
87 case IXGBE_DEV_ID_X550EM_A_10G_T:
88 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
89 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
98 * ixgbe_read_cs4227 - Read CS4227 register
99 * @hw: pointer to hardware structure
100 * @reg: register number to write
101 * @value: pointer to receive value read
103 * Returns status code
105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
107 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
111 * ixgbe_write_cs4227 - Write CS4227 register
112 * @hw: pointer to hardware structure
113 * @reg: register number to write
114 * @value: value to write to register
116 * Returns status code
118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
120 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
124 * ixgbe_read_pe - Read register from port expander
125 * @hw: pointer to hardware structure
126 * @reg: register number to read
127 * @value: pointer to receive read value
129 * Returns status code
131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
135 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
136 if (status != IXGBE_SUCCESS)
137 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
138 "port expander access failed with %d\n", status);
143 * ixgbe_write_pe - Write register to port expander
144 * @hw: pointer to hardware structure
145 * @reg: register number to write
146 * @value: value to write
148 * Returns status code
150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
154 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
155 if (status != IXGBE_SUCCESS)
156 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
157 "port expander access failed with %d\n", status);
162 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
163 * @hw: pointer to hardware structure
165 * This function assumes that the caller has acquired the proper semaphore.
168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
175 /* Trigger hard reset. */
176 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
177 if (status != IXGBE_SUCCESS)
179 reg |= IXGBE_PE_BIT1;
180 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
181 if (status != IXGBE_SUCCESS)
184 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
185 if (status != IXGBE_SUCCESS)
187 reg &= ~IXGBE_PE_BIT1;
188 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
189 if (status != IXGBE_SUCCESS)
192 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
193 if (status != IXGBE_SUCCESS)
195 reg &= ~IXGBE_PE_BIT1;
196 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
197 if (status != IXGBE_SUCCESS)
200 usec_delay(IXGBE_CS4227_RESET_HOLD);
202 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
203 if (status != IXGBE_SUCCESS)
205 reg |= IXGBE_PE_BIT1;
206 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
207 if (status != IXGBE_SUCCESS)
210 /* Wait for the reset to complete. */
211 msec_delay(IXGBE_CS4227_RESET_DELAY);
212 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
213 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
215 if (status == IXGBE_SUCCESS &&
216 value == IXGBE_CS4227_EEPROM_LOAD_OK)
218 msec_delay(IXGBE_CS4227_CHECK_DELAY);
220 if (retry == IXGBE_CS4227_RETRIES) {
221 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
222 "CS4227 reset did not complete.");
223 return IXGBE_ERR_PHY;
226 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
227 if (status != IXGBE_SUCCESS ||
228 !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
229 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
230 "CS4227 EEPROM did not load successfully.");
231 return IXGBE_ERR_PHY;
234 return IXGBE_SUCCESS;
238 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
239 * @hw: pointer to hardware structure
241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
243 s32 status = IXGBE_SUCCESS;
244 u32 swfw_mask = hw->phy.phy_semaphore_mask;
248 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
249 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
250 if (status != IXGBE_SUCCESS) {
251 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
252 "semaphore failed with %d", status);
253 msec_delay(IXGBE_CS4227_CHECK_DELAY);
257 /* Get status of reset flow. */
258 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
260 if (status == IXGBE_SUCCESS &&
261 value == IXGBE_CS4227_RESET_COMPLETE)
264 if (status != IXGBE_SUCCESS ||
265 value != IXGBE_CS4227_RESET_PENDING)
268 /* Reset is pending. Wait and check again. */
269 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 msec_delay(IXGBE_CS4227_CHECK_DELAY);
273 /* If still pending, assume other instance failed. */
274 if (retry == IXGBE_CS4227_RETRIES) {
275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
276 if (status != IXGBE_SUCCESS) {
277 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
278 "semaphore failed with %d", status);
283 /* Reset the CS4227. */
284 status = ixgbe_reset_cs4227(hw);
285 if (status != IXGBE_SUCCESS) {
286 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
287 "CS4227 reset failed: %d", status);
291 /* Reset takes so long, temporarily release semaphore in case the
292 * other driver instance is waiting for the reset indication.
294 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
295 IXGBE_CS4227_RESET_PENDING);
296 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
298 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
299 if (status != IXGBE_SUCCESS) {
300 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
301 "semaphore failed with %d", status);
305 /* Record completion for next time. */
306 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
307 IXGBE_CS4227_RESET_COMPLETE);
310 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
311 msec_delay(hw->eeprom.semaphore_delay);
315 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
316 * @hw: pointer to hardware structure
318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
320 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
322 if (hw->bus.lan_id) {
323 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
324 esdp |= IXGBE_ESDP_SDP1_DIR;
326 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
327 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
328 IXGBE_WRITE_FLUSH(hw);
332 * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
333 * @hw: pointer to hardware structure
334 * @reg_addr: 32 bit address of PHY register to read
335 * @dev_type: always unused
336 * @phy_data: Pointer to read data from PHY register
338 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
339 u32 dev_type, u16 *phy_data)
341 u32 i, data, command;
342 UNREFERENCED_1PARAMETER(dev_type);
344 /* Setup and write the read command */
345 command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
346 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
347 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
348 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ |
349 IXGBE_MSCA_MDI_COMMAND;
351 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
353 /* Check every 10 usec to see if the access completed.
354 * The MDI Command bit will clear when the operation is
357 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
360 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
361 if (!(command & IXGBE_MSCA_MDI_COMMAND))
365 if (command & IXGBE_MSCA_MDI_COMMAND) {
366 ERROR_REPORT1(IXGBE_ERROR_POLLING,
367 "PHY read command did not complete.\n");
368 return IXGBE_ERR_PHY;
371 /* Read operation is complete. Get the data from MSRWD */
372 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
373 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
374 *phy_data = (u16)data;
376 return IXGBE_SUCCESS;
380 * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
381 * @hw: pointer to hardware structure
382 * @reg_addr: 32 bit PHY register to write
383 * @dev_type: always unused
384 * @phy_data: Data to write to the PHY register
386 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
387 u32 dev_type, u16 phy_data)
390 UNREFERENCED_1PARAMETER(dev_type);
392 /* Put the data in the MDI single read and write data register*/
393 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
395 /* Setup and write the write command */
396 command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
397 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
398 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
399 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
400 IXGBE_MSCA_MDI_COMMAND;
402 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
404 /* Check every 10 usec to see if the access completed.
405 * The MDI Command bit will clear when the operation is
408 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
411 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
412 if (!(command & IXGBE_MSCA_MDI_COMMAND))
416 if (command & IXGBE_MSCA_MDI_COMMAND) {
417 ERROR_REPORT1(IXGBE_ERROR_POLLING,
418 "PHY write cmd didn't complete\n");
419 return IXGBE_ERR_PHY;
422 return IXGBE_SUCCESS;
426 * ixgbe_identify_phy_1g - Get 1g PHY type based on device id
427 * @hw: pointer to hardware structure
431 STATIC s32 ixgbe_identify_phy_1g(struct ixgbe_hw *hw)
433 u32 swfw_mask = hw->phy.phy_semaphore_mask;
438 rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
442 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_HIGH, 0,
447 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_LOW, 0,
452 hw->phy.id = (u32)phy_id_high << 16;
453 hw->phy.id |= phy_id_low & IXGBE_PHY_REVISION_MASK;
454 hw->phy.revision = (u32)phy_id_low & ~IXGBE_PHY_REVISION_MASK;
457 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
463 * ixgbe_identify_phy_x550em - Get PHY type based on device id
464 * @hw: pointer to hardware structure
468 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
470 switch (hw->device_id) {
471 case IXGBE_DEV_ID_X550EM_A_SFP:
472 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
473 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
475 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
477 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
478 return ixgbe_identify_module_generic(hw);
479 case IXGBE_DEV_ID_X550EM_X_SFP:
480 /* set up for CS4227 usage */
481 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
482 ixgbe_setup_mux_ctl(hw);
483 ixgbe_check_cs4227(hw);
486 case IXGBE_DEV_ID_X550EM_A_SFP_N:
487 return ixgbe_identify_module_generic(hw);
489 case IXGBE_DEV_ID_X550EM_X_KX4:
490 hw->phy.type = ixgbe_phy_x550em_kx4;
492 case IXGBE_DEV_ID_X550EM_X_KR:
493 case IXGBE_DEV_ID_X550EM_A_KR:
494 case IXGBE_DEV_ID_X550EM_A_KR_L:
495 hw->phy.type = ixgbe_phy_x550em_kr;
497 case IXGBE_DEV_ID_X550EM_X_1G_T:
498 case IXGBE_DEV_ID_X550EM_X_10G_T:
499 case IXGBE_DEV_ID_X550EM_A_10G_T:
500 return ixgbe_identify_phy_generic(hw);
501 case IXGBE_DEV_ID_X550EM_A_1G_T:
502 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
503 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
504 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
506 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
508 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
509 return ixgbe_identify_phy_1g(hw);
513 return IXGBE_SUCCESS;
516 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
517 u32 device_type, u16 *phy_data)
519 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
520 return IXGBE_NOT_IMPLEMENTED;
523 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
524 u32 device_type, u16 phy_data)
526 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
527 return IXGBE_NOT_IMPLEMENTED;
531 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
532 * @hw: pointer to the hardware structure
533 * @addr: I2C bus address to read from
534 * @reg: I2C device register to read from
535 * @val: pointer to location to receive read value
537 * Returns an error code on error.
539 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
542 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
546 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
547 * @hw: pointer to the hardware structure
548 * @addr: I2C bus address to read from
549 * @reg: I2C device register to read from
550 * @val: pointer to location to receive read value
552 * Returns an error code on error.
555 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
558 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
562 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
563 * @hw: pointer to the hardware structure
564 * @addr: I2C bus address to write to
565 * @reg: I2C device register to write to
566 * @val: value to write
568 * Returns an error code on error.
570 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
571 u8 addr, u16 reg, u16 val)
573 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
577 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
578 * @hw: pointer to the hardware structure
579 * @addr: I2C bus address to write to
580 * @reg: I2C device register to write to
581 * @val: value to write
583 * Returns an error code on error.
586 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
587 u8 addr, u16 reg, u16 val)
589 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
593 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
594 * @hw: pointer to hardware structure
596 * Initialize the function pointers and for MAC type X550EM.
597 * Does not touch the hardware.
599 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
601 struct ixgbe_mac_info *mac = &hw->mac;
602 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
603 struct ixgbe_phy_info *phy = &hw->phy;
604 struct ixgbe_link_info *link = &hw->link;
607 DEBUGFUNC("ixgbe_init_ops_X550EM");
609 /* Similar to X550 so start there. */
610 ret_val = ixgbe_init_ops_X550(hw);
612 /* Since this function eventually calls
613 * ixgbe_init_ops_540 by design, we are setting
614 * the pointers to NULL explicitly here to overwrite
615 * the values being set in the x540 function.
617 /* Thermal sensor not supported in x550EM */
618 mac->ops.get_thermal_sensor_data = NULL;
619 mac->ops.init_thermal_sensor_thresh = NULL;
620 mac->thermal_sensor_enabled = false;
622 /* FCOE not supported in x550EM */
623 mac->ops.get_san_mac_addr = NULL;
624 mac->ops.set_san_mac_addr = NULL;
625 mac->ops.get_wwn_prefix = NULL;
626 mac->ops.get_fcoe_boot_status = NULL;
628 /* IPsec not supported in x550EM */
629 mac->ops.disable_sec_rx_path = NULL;
630 mac->ops.enable_sec_rx_path = NULL;
632 /* AUTOC register is not present in x550EM. */
633 mac->ops.prot_autoc_read = NULL;
634 mac->ops.prot_autoc_write = NULL;
636 /* X550EM bus type is internal*/
637 hw->bus.type = ixgbe_bus_type_internal;
638 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
640 if (hw->mac.type == ixgbe_mac_X550EM_x) {
641 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
642 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
643 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
644 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
645 link->ops.read_link = ixgbe_read_i2c_combined_generic;
646 link->ops.read_link_unlocked =
647 ixgbe_read_i2c_combined_generic_unlocked;
648 link->ops.write_link = ixgbe_write_i2c_combined_generic;
649 link->ops.write_link_unlocked =
650 ixgbe_write_i2c_combined_generic_unlocked;
651 link->addr = IXGBE_CS4227;
653 if (hw->mac.type == ixgbe_mac_X550EM_a) {
654 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
655 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
656 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
657 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
660 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
661 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
662 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
663 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
664 mac->ops.get_supported_physical_layer =
665 ixgbe_get_supported_physical_layer_X550em;
667 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
668 mac->ops.setup_fc = ixgbe_setup_fc_generic;
669 else if (hw->mac.type == ixgbe_mac_X550EM_a) {
670 mac->ops.setup_fc = ixgbe_setup_fc_x550a;
671 mac->ops.fc_autoneg = ixgbe_fc_autoneg_x550a;
674 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
676 switch (hw->device_id) {
677 case IXGBE_DEV_ID_X550EM_X_KR:
678 case IXGBE_DEV_ID_X550EM_A_KR:
679 case IXGBE_DEV_ID_X550EM_A_KR_L:
682 mac->ops.setup_eee = NULL;
686 phy->ops.init = ixgbe_init_phy_ops_X550em;
687 phy->ops.identify = ixgbe_identify_phy_x550em;
688 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
689 phy->ops.set_phy_power = NULL;
693 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
694 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
695 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
696 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
697 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
698 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
699 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
700 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
706 * ixgbe_dmac_config_X550
707 * @hw: pointer to hardware structure
709 * Configure DMA coalescing. If enabling dmac, dmac is activated.
710 * When disabling dmac, dmac enable dmac bit is cleared.
712 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
714 u32 reg, high_pri_tc;
716 DEBUGFUNC("ixgbe_dmac_config_X550");
718 /* Disable DMA coalescing before configuring */
719 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
720 reg &= ~IXGBE_DMACR_DMAC_EN;
721 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
723 /* Disable DMA Coalescing if the watchdog timer is 0 */
724 if (!hw->mac.dmac_config.watchdog_timer)
727 ixgbe_dmac_config_tcs_X550(hw);
729 /* Configure DMA Coalescing Control Register */
730 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
732 /* Set the watchdog timer in units of 40.96 usec */
733 reg &= ~IXGBE_DMACR_DMACWT_MASK;
734 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
736 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
737 /* If fcoe is enabled, set high priority traffic class */
738 if (hw->mac.dmac_config.fcoe_en) {
739 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
740 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
741 IXGBE_DMACR_HIGH_PRI_TC_MASK);
743 reg |= IXGBE_DMACR_EN_MNG_IND;
745 /* Enable DMA coalescing after configuration */
746 reg |= IXGBE_DMACR_DMAC_EN;
747 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
750 return IXGBE_SUCCESS;
754 * ixgbe_dmac_config_tcs_X550
755 * @hw: pointer to hardware structure
757 * Configure DMA coalescing threshold per TC. The dmac enable bit must
758 * be cleared before configuring.
760 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
762 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
764 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
766 /* Configure DMA coalescing enabled */
767 switch (hw->mac.dmac_config.link_speed) {
768 case IXGBE_LINK_SPEED_100_FULL:
769 pb_headroom = IXGBE_DMACRXT_100M;
771 case IXGBE_LINK_SPEED_1GB_FULL:
772 pb_headroom = IXGBE_DMACRXT_1G;
775 pb_headroom = IXGBE_DMACRXT_10G;
779 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
780 IXGBE_MHADD_MFS_SHIFT) / 1024);
782 /* Set the per Rx packet buffer receive threshold */
783 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
784 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
785 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
787 if (tc < hw->mac.dmac_config.num_tcs) {
789 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
790 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
791 IXGBE_RXPBSIZE_SHIFT;
793 /* Calculate receive buffer threshold in kilobytes */
794 if (rx_pb_size > pb_headroom)
795 rx_pb_size = rx_pb_size - pb_headroom;
799 /* Minimum of MFS shall be set for DMCTH */
800 reg |= (rx_pb_size > maxframe_size_kb) ?
801 rx_pb_size : maxframe_size_kb;
803 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
805 return IXGBE_SUCCESS;
809 * ixgbe_dmac_update_tcs_X550
810 * @hw: pointer to hardware structure
812 * Disables dmac, updates per TC settings, and then enables dmac.
814 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
818 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
820 /* Disable DMA coalescing before configuring */
821 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
822 reg &= ~IXGBE_DMACR_DMAC_EN;
823 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
825 ixgbe_dmac_config_tcs_X550(hw);
827 /* Enable DMA coalescing after configuration */
828 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
829 reg |= IXGBE_DMACR_DMAC_EN;
830 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
832 return IXGBE_SUCCESS;
836 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
837 * @hw: pointer to hardware structure
839 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
840 * ixgbe_hw struct in order to set up EEPROM access.
842 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
844 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
848 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
850 if (eeprom->type == ixgbe_eeprom_uninitialized) {
851 eeprom->semaphore_delay = 10;
852 eeprom->type = ixgbe_flash;
854 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
855 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
856 IXGBE_EEC_SIZE_SHIFT);
857 eeprom->word_size = 1 << (eeprom_size +
858 IXGBE_EEPROM_WORD_SIZE_SHIFT);
860 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
861 eeprom->type, eeprom->word_size);
864 return IXGBE_SUCCESS;
868 * ixgbe_enable_eee_x550 - Enable EEE support
869 * @hw: pointer to hardware structure
871 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
877 if (hw->mac.type == ixgbe_mac_X550) {
878 /* Advertise EEE capability */
879 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
880 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
883 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
884 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
885 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
887 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
888 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
890 return IXGBE_SUCCESS;
893 switch (hw->device_id) {
894 case IXGBE_DEV_ID_X550EM_X_KR:
895 case IXGBE_DEV_ID_X550EM_A_KR:
896 case IXGBE_DEV_ID_X550EM_A_KR_L:
897 status = hw->mac.ops.read_iosf_sb_reg(hw,
898 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
899 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
900 if (status != IXGBE_SUCCESS)
903 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
904 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
906 /* Don't advertise FEC capability when EEE enabled. */
907 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
909 status = hw->mac.ops.write_iosf_sb_reg(hw,
910 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
911 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
912 if (status != IXGBE_SUCCESS)
919 return IXGBE_SUCCESS;
923 * ixgbe_disable_eee_x550 - Disable EEE support
924 * @hw: pointer to hardware structure
926 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
932 if (hw->mac.type == ixgbe_mac_X550) {
933 /* Disable advertised EEE capability */
934 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
935 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
938 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
939 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
940 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
942 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
943 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
945 return IXGBE_SUCCESS;
948 switch (hw->device_id) {
949 case IXGBE_DEV_ID_X550EM_X_KR:
950 case IXGBE_DEV_ID_X550EM_A_KR:
951 case IXGBE_DEV_ID_X550EM_A_KR_L:
952 status = hw->mac.ops.read_iosf_sb_reg(hw,
953 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
954 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
955 if (status != IXGBE_SUCCESS)
958 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
959 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
961 /* Advertise FEC capability when EEE is disabled. */
962 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
964 status = hw->mac.ops.write_iosf_sb_reg(hw,
965 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
966 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
967 if (status != IXGBE_SUCCESS)
974 return IXGBE_SUCCESS;
978 * ixgbe_setup_eee_X550 - Enable/disable EEE support
979 * @hw: pointer to the HW structure
980 * @enable_eee: boolean flag to enable EEE
982 * Enable/disable EEE based on enable_eee flag.
983 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
987 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
992 DEBUGFUNC("ixgbe_setup_eee_X550");
994 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
995 /* Enable or disable EEE per flag */
997 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
999 /* Not supported on first revision of X550EM_x. */
1000 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1001 !(IXGBE_FUSES0_REV_MASK &
1002 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1003 return IXGBE_SUCCESS;
1004 status = ixgbe_enable_eee_x550(hw);
1008 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1010 status = ixgbe_disable_eee_x550(hw);
1014 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1016 return IXGBE_SUCCESS;
1020 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1021 * @hw: pointer to hardware structure
1022 * @enable: enable or disable source address pruning
1023 * @pool: Rx pool to set source address pruning for
1025 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1030 /* max rx pool is 63 */
1034 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1035 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1038 pfflp |= (1ULL << pool);
1040 pfflp &= ~(1ULL << pool);
1042 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1043 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1047 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1048 * @hw: pointer to hardware structure
1049 * @enable: enable or disable switch for Ethertype anti-spoofing
1050 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1053 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1054 bool enable, int vf)
1056 int vf_target_reg = vf >> 3;
1057 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1060 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1062 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1064 pfvfspoof |= (1 << vf_target_shift);
1066 pfvfspoof &= ~(1 << vf_target_shift);
1068 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1072 * ixgbe_iosf_wait - Wait for IOSF command completion
1073 * @hw: pointer to hardware structure
1074 * @ctrl: pointer to location to receive final IOSF control value
1076 * Returns failing status on timeout
1078 * Note: ctrl can be NULL if the IOSF control register value is not needed
1080 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1084 /* Check every 10 usec to see if the address cycle completed.
1085 * The SB IOSF BUSY bit will clear when the operation is
1088 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1089 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1090 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1096 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1097 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1098 return IXGBE_ERR_PHY;
1101 return IXGBE_SUCCESS;
1105 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1107 * @hw: pointer to hardware structure
1108 * @reg_addr: 32 bit PHY register to write
1109 * @device_type: 3 bit device type
1110 * @data: Data to write to the register
1112 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1113 u32 device_type, u32 data)
1115 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1119 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1120 if (ret != IXGBE_SUCCESS)
1123 ret = ixgbe_iosf_wait(hw, NULL);
1124 if (ret != IXGBE_SUCCESS)
1127 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1128 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1130 /* Write IOSF control register */
1131 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1133 /* Write IOSF data register */
1134 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1136 ret = ixgbe_iosf_wait(hw, &command);
1138 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1139 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1140 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1141 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1142 "Failed to write, error %x\n", error);
1143 ret = IXGBE_ERR_PHY;
1147 ixgbe_release_swfw_semaphore(hw, gssr);
1152 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1154 * @hw: pointer to hardware structure
1155 * @reg_addr: 32 bit PHY register to write
1156 * @device_type: 3 bit device type
1157 * @phy_data: Pointer to read data from the register
1159 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1160 u32 device_type, u32 *data)
1162 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1166 ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1167 if (ret != IXGBE_SUCCESS)
1170 ret = ixgbe_iosf_wait(hw, NULL);
1171 if (ret != IXGBE_SUCCESS)
1174 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1175 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1177 /* Write IOSF control register */
1178 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1180 ret = ixgbe_iosf_wait(hw, &command);
1182 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1183 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1184 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1185 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1186 "Failed to read, error %x\n", error);
1187 ret = IXGBE_ERR_PHY;
1190 if (ret == IXGBE_SUCCESS)
1191 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1194 ixgbe_release_swfw_semaphore(hw, gssr);
1199 * ixgbe_get_phy_token - Get the token for shared phy access
1200 * @hw: Pointer to hardware structure
1203 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1205 struct ixgbe_hic_phy_token_req token_cmd;
1208 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1209 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1210 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1211 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1212 token_cmd.port_number = hw->bus.lan_id;
1213 token_cmd.command_type = FW_PHY_TOKEN_REQ;
1215 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1217 IXGBE_HI_COMMAND_TIMEOUT,
1221 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1222 return IXGBE_SUCCESS;
1223 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1224 return IXGBE_ERR_FW_RESP_INVALID;
1226 return IXGBE_ERR_TOKEN_RETRY;
1230 * ixgbe_put_phy_token - Put the token for shared phy access
1231 * @hw: Pointer to hardware structure
1234 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1236 struct ixgbe_hic_phy_token_req token_cmd;
1239 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1240 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1241 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1242 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1243 token_cmd.port_number = hw->bus.lan_id;
1244 token_cmd.command_type = FW_PHY_TOKEN_REL;
1246 status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1248 IXGBE_HI_COMMAND_TIMEOUT,
1252 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1253 return IXGBE_SUCCESS;
1255 DEBUGOUT("Put PHY Token host interface command failed");
1256 return IXGBE_ERR_FW_RESP_INVALID;
1260 * ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1261 * of the IOSF device
1262 * @hw: pointer to hardware structure
1263 * @reg_addr: 32 bit PHY register to write
1264 * @device_type: 3 bit device type
1265 * @data: Data to write to the register
1267 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1268 u32 device_type, u32 data)
1270 struct ixgbe_hic_internal_phy_req write_cmd;
1272 UNREFERENCED_1PARAMETER(device_type);
1274 memset(&write_cmd, 0, sizeof(write_cmd));
1275 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1276 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1277 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1278 write_cmd.port_number = hw->bus.lan_id;
1279 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1280 write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1281 write_cmd.write_data = IXGBE_CPU_TO_LE32(data);
1283 status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1285 IXGBE_HI_COMMAND_TIMEOUT, false);
1291 * ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1292 * of the IOSF device.
1293 * @hw: pointer to hardware structure
1294 * @reg_addr: 32 bit PHY register to write
1295 * @device_type: 3 bit device type
1296 * @data: Pointer to read data from the register
1298 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1299 u32 device_type, u32 *data)
1302 struct ixgbe_hic_internal_phy_req cmd;
1303 struct ixgbe_hic_internal_phy_resp rsp;
1306 UNREFERENCED_1PARAMETER(device_type);
1308 memset(&hic, 0, sizeof(hic));
1309 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1310 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1311 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1312 hic.cmd.port_number = hw->bus.lan_id;
1313 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1314 hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1316 status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1318 IXGBE_HI_COMMAND_TIMEOUT, true);
1320 /* Extract the register value from the response. */
1321 *data = IXGBE_LE32_TO_CPU(hic.rsp.read_data);
1327 * ixgbe_disable_mdd_X550
1328 * @hw: pointer to hardware structure
1330 * Disable malicious driver detection
1332 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1336 DEBUGFUNC("ixgbe_disable_mdd_X550");
1338 /* Disable MDD for TX DMA and interrupt */
1339 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1340 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1341 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1343 /* Disable MDD for RX and interrupt */
1344 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1345 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1346 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1350 * ixgbe_enable_mdd_X550
1351 * @hw: pointer to hardware structure
1353 * Enable malicious driver detection
1355 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1359 DEBUGFUNC("ixgbe_enable_mdd_X550");
1361 /* Enable MDD for TX DMA and interrupt */
1362 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1363 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1364 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1366 /* Enable MDD for RX and interrupt */
1367 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1368 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1369 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1373 * ixgbe_restore_mdd_vf_X550
1374 * @hw: pointer to hardware structure
1377 * Restore VF that was disabled during malicious driver detection event
1379 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1381 u32 idx, reg, num_qs, start_q, bitmask;
1383 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1385 /* Map VF to queues */
1386 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1387 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1388 case IXGBE_MRQC_VMDQRT8TCEN:
1389 num_qs = 8; /* 16 VFs / pools */
1390 bitmask = 0x000000FF;
1392 case IXGBE_MRQC_VMDQRSS32EN:
1393 case IXGBE_MRQC_VMDQRT4TCEN:
1394 num_qs = 4; /* 32 VFs / pools */
1395 bitmask = 0x0000000F;
1397 default: /* 64 VFs / pools */
1399 bitmask = 0x00000003;
1402 start_q = vf * num_qs;
1404 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1407 reg |= (bitmask << (start_q % 32));
1408 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1409 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1413 * ixgbe_mdd_event_X550
1414 * @hw: pointer to hardware structure
1415 * @vf_bitmap: vf bitmap of malicious vfs
1417 * Handle malicious driver detection event.
1419 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1422 u32 i, j, reg, q, shift, vf, idx;
1424 DEBUGFUNC("ixgbe_mdd_event_X550");
1426 /* figure out pool size for mapping to vf's */
1427 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1428 switch (reg & IXGBE_MRQC_MRQE_MASK) {
1429 case IXGBE_MRQC_VMDQRT8TCEN:
1430 shift = 3; /* 16 VFs / pools */
1432 case IXGBE_MRQC_VMDQRSS32EN:
1433 case IXGBE_MRQC_VMDQRT4TCEN:
1434 shift = 2; /* 32 VFs / pools */
1437 shift = 1; /* 64 VFs / pools */
1441 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1442 for (i = 0; i < 4; i++) {
1443 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1444 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1449 /* Get malicious queue */
1450 for (j = 0; j < 32 && wqbr; j++) {
1452 if (!(wqbr & (1 << j)))
1455 /* Get queue from bitmask */
1458 /* Map queue to vf */
1461 /* Set vf bit in vf_bitmap */
1463 vf_bitmap[idx] |= (1 << (vf % 32));
1470 * ixgbe_get_media_type_X550em - Get media type
1471 * @hw: pointer to hardware structure
1473 * Returns the media type (fiber, copper, backplane)
1475 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1477 enum ixgbe_media_type media_type;
1479 DEBUGFUNC("ixgbe_get_media_type_X550em");
1481 /* Detect if there is a copper PHY attached. */
1482 switch (hw->device_id) {
1483 case IXGBE_DEV_ID_X550EM_X_KR:
1484 case IXGBE_DEV_ID_X550EM_X_KX4:
1485 case IXGBE_DEV_ID_X550EM_A_KR:
1486 case IXGBE_DEV_ID_X550EM_A_KR_L:
1487 media_type = ixgbe_media_type_backplane;
1489 case IXGBE_DEV_ID_X550EM_X_SFP:
1490 case IXGBE_DEV_ID_X550EM_A_SFP:
1491 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1492 case IXGBE_DEV_ID_X550EM_A_QSFP:
1493 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1494 media_type = ixgbe_media_type_fiber;
1496 case IXGBE_DEV_ID_X550EM_X_1G_T:
1497 case IXGBE_DEV_ID_X550EM_X_10G_T:
1498 case IXGBE_DEV_ID_X550EM_A_10G_T:
1499 media_type = ixgbe_media_type_copper;
1501 case IXGBE_DEV_ID_X550EM_A_SGMII:
1502 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1503 media_type = ixgbe_media_type_backplane;
1504 hw->phy.type = ixgbe_phy_sgmii;
1506 case IXGBE_DEV_ID_X550EM_A_1G_T:
1507 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1508 media_type = ixgbe_media_type_copper;
1509 hw->phy.type = ixgbe_phy_m88;
1512 media_type = ixgbe_media_type_unknown;
1519 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1520 * @hw: pointer to hardware structure
1521 * @linear: true if SFP module is linear
1523 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1525 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1527 switch (hw->phy.sfp_type) {
1528 case ixgbe_sfp_type_not_present:
1529 return IXGBE_ERR_SFP_NOT_PRESENT;
1530 case ixgbe_sfp_type_da_cu_core0:
1531 case ixgbe_sfp_type_da_cu_core1:
1534 case ixgbe_sfp_type_srlr_core0:
1535 case ixgbe_sfp_type_srlr_core1:
1536 case ixgbe_sfp_type_da_act_lmt_core0:
1537 case ixgbe_sfp_type_da_act_lmt_core1:
1538 case ixgbe_sfp_type_1g_sx_core0:
1539 case ixgbe_sfp_type_1g_sx_core1:
1540 case ixgbe_sfp_type_1g_lx_core0:
1541 case ixgbe_sfp_type_1g_lx_core1:
1544 case ixgbe_sfp_type_unknown:
1545 case ixgbe_sfp_type_1g_cu_core0:
1546 case ixgbe_sfp_type_1g_cu_core1:
1548 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1551 return IXGBE_SUCCESS;
1555 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1556 * @hw: pointer to hardware structure
1558 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1560 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1565 DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1567 status = ixgbe_identify_module_generic(hw);
1569 if (status != IXGBE_SUCCESS)
1572 /* Check if SFP module is supported */
1573 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1579 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1580 * @hw: pointer to hardware structure
1582 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1587 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1589 /* Check if SFP module is supported */
1590 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1592 if (status != IXGBE_SUCCESS)
1595 ixgbe_init_mac_link_ops_X550em(hw);
1596 hw->phy.ops.reset = NULL;
1598 return IXGBE_SUCCESS;
1602 * ixgbe_setup_sgmii - Set up link for sgmii
1603 * @hw: pointer to hardware structure
1605 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1606 bool autoneg_wait_to_complete)
1608 struct ixgbe_mac_info *mac = &hw->mac;
1611 UNREFERENCED_2PARAMETER(speed, autoneg_wait_to_complete);
1613 rc = mac->ops.read_iosf_sb_reg(hw,
1614 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1615 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1619 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1620 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1621 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1622 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1623 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1624 rc = mac->ops.write_iosf_sb_reg(hw,
1625 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1626 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1630 rc = mac->ops.read_iosf_sb_reg(hw,
1631 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1632 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1636 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1637 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1638 rc = mac->ops.write_iosf_sb_reg(hw,
1639 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1640 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1644 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1645 rc = mac->ops.write_iosf_sb_reg(hw,
1646 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1647 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1653 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1654 * @hw: pointer to hardware structure
1656 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1658 struct ixgbe_mac_info *mac = &hw->mac;
1660 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1662 switch (hw->mac.ops.get_media_type(hw)) {
1663 case ixgbe_media_type_fiber:
1664 /* CS4227 does not support autoneg, so disable the laser control
1665 * functions for SFP+ fiber
1667 mac->ops.disable_tx_laser = NULL;
1668 mac->ops.enable_tx_laser = NULL;
1669 mac->ops.flap_tx_laser = NULL;
1670 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1671 mac->ops.set_rate_select_speed =
1672 ixgbe_set_soft_rate_select_speed;
1673 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1674 (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1675 mac->ops.setup_mac_link =
1676 ixgbe_setup_mac_link_sfp_x550a;
1678 mac->ops.setup_mac_link =
1679 ixgbe_setup_mac_link_sfp_x550em;
1681 case ixgbe_media_type_copper:
1682 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1683 mac->ops.check_link = ixgbe_check_link_t_X550em;
1685 case ixgbe_media_type_backplane:
1686 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1687 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1688 mac->ops.setup_link = ixgbe_setup_sgmii;
1696 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
1697 * @hw: pointer to hardware structure
1698 * @speed: pointer to link speed
1699 * @autoneg: true when autoneg or autotry is enabled
1701 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1702 ixgbe_link_speed *speed,
1705 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1708 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1710 /* CS4227 SFP must not enable auto-negotiation */
1713 /* Check if 1G SFP module. */
1714 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1715 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1716 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1717 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1718 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1719 return IXGBE_SUCCESS;
1722 /* Link capabilities are based on SFP */
1723 if (hw->phy.multispeed_fiber)
1724 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1725 IXGBE_LINK_SPEED_1GB_FULL;
1727 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1729 switch (hw->phy.type) {
1731 *speed = IXGBE_LINK_SPEED_100_FULL |
1732 IXGBE_LINK_SPEED_1GB_FULL;
1734 case ixgbe_phy_sgmii:
1735 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1738 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1739 IXGBE_LINK_SPEED_1GB_FULL;
1745 return IXGBE_SUCCESS;
1749 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1750 * @hw: pointer to hardware structure
1751 * @lsc: pointer to boolean flag which indicates whether external Base T
1752 * PHY interrupt is lsc
1754 * Determime if external Base T PHY interrupt cause is high temperature
1755 * failure alarm or link status change.
1757 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1758 * failure alarm, else return PHY access status.
1760 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1767 /* Vendor alarm triggered */
1768 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1769 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1772 if (status != IXGBE_SUCCESS ||
1773 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1776 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1777 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1778 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1781 if (status != IXGBE_SUCCESS ||
1782 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1783 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1786 /* Global alarm triggered */
1787 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1788 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1791 if (status != IXGBE_SUCCESS)
1794 /* If high temperature failure, then return over temp error and exit */
1795 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1796 /* power down the PHY in case the PHY FW didn't already */
1797 ixgbe_set_copper_phy_power(hw, false);
1798 return IXGBE_ERR_OVERTEMP;
1799 } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1800 /* device fault alarm triggered */
1801 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1802 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1805 if (status != IXGBE_SUCCESS)
1808 /* if device fault was due to high temp alarm handle and exit */
1809 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1810 /* power down the PHY in case the PHY FW didn't */
1811 ixgbe_set_copper_phy_power(hw, false);
1812 return IXGBE_ERR_OVERTEMP;
1816 /* Vendor alarm 2 triggered */
1817 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1818 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1820 if (status != IXGBE_SUCCESS ||
1821 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1824 /* link connect/disconnect event occurred */
1825 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1826 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1828 if (status != IXGBE_SUCCESS)
1832 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1835 return IXGBE_SUCCESS;
1839 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1840 * @hw: pointer to hardware structure
1842 * Enable link status change and temperature failure alarm for the external
1845 * Returns PHY access status
1847 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1853 /* Clear interrupt flags */
1854 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1856 /* Enable link status change alarm */
1857 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1858 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);
1860 if (status != IXGBE_SUCCESS)
1863 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1865 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1866 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1868 if (status != IXGBE_SUCCESS)
1871 /* Enable high temperature failure and global fault alarms */
1872 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1873 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1876 if (status != IXGBE_SUCCESS)
1879 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1880 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1882 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1883 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1886 if (status != IXGBE_SUCCESS)
1889 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1890 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1891 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1894 if (status != IXGBE_SUCCESS)
1897 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1898 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1900 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1901 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1904 if (status != IXGBE_SUCCESS)
1907 /* Enable chip-wide vendor alarm */
1908 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1909 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1912 if (status != IXGBE_SUCCESS)
1915 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1917 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1918 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1925 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1926 * @hw: pointer to hardware structure
1927 * @speed: link speed
1929 * Configures the integrated KR PHY.
1931 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1932 ixgbe_link_speed speed)
1937 status = hw->mac.ops.read_iosf_sb_reg(hw,
1938 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1939 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1943 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1944 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1945 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1947 /* Advertise 10G support. */
1948 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1949 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1951 /* Advertise 1G support. */
1952 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1953 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1955 /* Restart auto-negotiation. */
1956 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1957 status = hw->mac.ops.write_iosf_sb_reg(hw,
1958 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1959 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1965 * ixgbe_set_master_slave_mode - Set up PHY for master/slave mode
1966 * @hw: pointer to hardware structure
1968 * Must be called while holding the PHY semaphore and token
1970 STATIC s32 ixgbe_set_master_slave_mode(struct ixgbe_hw *hw)
1975 /* Resolve master/slave mode */
1976 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
1981 /* load defaults for future use */
1982 if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_ENABLE) {
1983 if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_VALUE)
1984 hw->phy.original_ms_type = ixgbe_ms_force_master;
1986 hw->phy.original_ms_type = ixgbe_ms_force_slave;
1988 hw->phy.original_ms_type = ixgbe_ms_auto;
1991 switch (hw->phy.ms_type) {
1992 case ixgbe_ms_force_master:
1993 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1994 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
1996 case ixgbe_ms_force_slave:
1997 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1998 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
2001 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
2007 return ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
2012 * ixgbe_reset_phy_m88_nolock - Reset m88 PHY without locking
2013 * @hw: pointer to hardware structure
2015 * Must be called while holding the PHY semaphore and token
2017 STATIC s32 ixgbe_reset_phy_m88_nolock(struct ixgbe_hw *hw)
2021 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2025 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_FIBER_CTRL, 0,
2026 IXGBE_M88E1500_FIBER_CTRL_RESET |
2027 IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2028 IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB);
2032 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2036 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_GEN_CTRL, 0,
2037 IXGBE_M88E1500_GEN_CTRL_RESET |
2038 IXGBE_M88E1500_GEN_CTRL_SGMII_COPPER);
2042 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2046 rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2047 IXGBE_M88E1500_COPPER_CTRL_RESET |
2048 IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2049 IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2050 IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2051 IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB);
2054 ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2059 * ixgbe_reset_phy_m88 - Reset m88 PHY
2060 * @hw: pointer to hardware structure
2062 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2064 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2067 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2068 return IXGBE_SUCCESS;
2070 rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2074 rc = ixgbe_reset_phy_m88_nolock(hw);
2076 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2081 * ixgbe_setup_m88 - setup m88 PHY
2082 * @hw: pointer to hardware structure
2084 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2086 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2087 struct ixgbe_phy_info *phy = &hw->phy;
2091 if (phy->reset_disable || ixgbe_check_reset_blocked(hw))
2092 return IXGBE_SUCCESS;
2094 rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2098 rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2103 /* Enable downshift and setting it to X6 */
2104 phy_data &= ~IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2105 phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_6X;
2106 phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2107 rc = ixgbe_write_phy_reg_mdi_22(hw,
2108 IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2113 ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2115 /* Commit the changes */
2116 rc = ixgbe_reset_phy_m88_nolock(hw);
2118 DEBUGOUT("Error committing the PHY changes\n");
2122 rc = ixgbe_set_master_slave_mode(hw);
2124 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2128 ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2129 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2134 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2135 * @hw: pointer to hardware structure
2137 * Read NW_MNG_IF_SEL register and save field values, and check for valid field
2140 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2142 /* Save NW management interface connected on board. This is used
2143 * to determine internal PHY mode.
2145 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2147 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2148 * PHY address. This register field was has only been used for X552.
2150 if (hw->mac.type == ixgbe_mac_X550EM_a &&
2151 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2152 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2153 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2154 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2157 return IXGBE_SUCCESS;
2161 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2162 * @hw: pointer to hardware structure
2164 * Initialize any function pointers that were not able to be
2165 * set during init_shared_code because the PHY/SFP type was
2166 * not known. Perform the SFP init if necessary.
2168 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2170 struct ixgbe_phy_info *phy = &hw->phy;
2173 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2175 hw->mac.ops.set_lan_id(hw);
2177 ixgbe_read_mng_if_sel_x550em(hw);
2179 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2180 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2181 ixgbe_setup_mux_ctl(hw);
2182 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2185 /* Identify the PHY or SFP module */
2186 ret_val = phy->ops.identify(hw);
2187 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2190 /* Setup function pointers based on detected hardware */
2191 ixgbe_init_mac_link_ops_X550em(hw);
2192 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2193 phy->ops.reset = NULL;
2195 /* Set functions pointers based on phy type */
2196 switch (hw->phy.type) {
2197 case ixgbe_phy_x550em_kx4:
2198 phy->ops.setup_link = NULL;
2199 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2200 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2202 case ixgbe_phy_x550em_kr:
2203 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2204 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2205 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2207 case ixgbe_phy_x550em_ext_t:
2208 /* If internal link mode is XFI, then setup iXFI internal link,
2209 * else setup KR now.
2211 phy->ops.setup_internal_link =
2212 ixgbe_setup_internal_phy_t_x550em;
2214 /* setup SW LPLU only for first revision of X550EM_x */
2215 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2216 !(IXGBE_FUSES0_REV_MASK &
2217 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2218 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2220 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2221 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2223 case ixgbe_phy_sgmii:
2224 phy->ops.setup_link = NULL;
2227 phy->ops.setup_link = ixgbe_setup_m88;
2228 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2229 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2230 phy->ops.reset = ixgbe_reset_phy_m88;
2239 * ixgbe_set_mdio_speed - Set MDIO clock speed
2240 * @hw: pointer to hardware structure
2242 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2246 switch (hw->device_id) {
2247 case IXGBE_DEV_ID_X550EM_X_10G_T:
2248 case IXGBE_DEV_ID_X550EM_A_SGMII:
2249 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2250 case IXGBE_DEV_ID_X550EM_A_1G_T:
2251 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2252 case IXGBE_DEV_ID_X550EM_A_10G_T:
2253 case IXGBE_DEV_ID_X550EM_A_SFP:
2254 case IXGBE_DEV_ID_X550EM_A_QSFP:
2255 /* Config MDIO clock speed before the first MDIO PHY access */
2256 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2257 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2258 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2266 * ixgbe_reset_hw_X550em - Perform hardware reset
2267 * @hw: pointer to hardware structure
2269 * Resets the hardware by resetting the transmit and receive units, masks
2270 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2273 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2275 ixgbe_link_speed link_speed;
2279 bool link_up = false;
2281 DEBUGFUNC("ixgbe_reset_hw_X550em");
2283 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2284 status = hw->mac.ops.stop_adapter(hw);
2285 if (status != IXGBE_SUCCESS)
2288 /* flush pending Tx transactions */
2289 ixgbe_clear_tx_pending(hw);
2291 ixgbe_set_mdio_speed(hw);
2293 /* PHY ops must be identified and initialized prior to reset */
2294 status = hw->phy.ops.init(hw);
2296 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2299 /* start the external PHY */
2300 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2301 status = ixgbe_init_ext_t_x550em(hw);
2306 /* Setup SFP module if there is one present. */
2307 if (hw->phy.sfp_setup_needed) {
2308 status = hw->mac.ops.setup_sfp(hw);
2309 hw->phy.sfp_setup_needed = false;
2312 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2316 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2317 hw->phy.ops.reset(hw);
2320 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2321 * If link reset is used when link is up, it might reset the PHY when
2322 * mng is using it. If link is down or the flag to force full link
2323 * reset is set, then perform link reset.
2325 ctrl = IXGBE_CTRL_LNK_RST;
2326 if (!hw->force_full_reset) {
2327 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2329 ctrl = IXGBE_CTRL_RST;
2332 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2333 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2334 IXGBE_WRITE_FLUSH(hw);
2336 /* Poll for reset bit to self-clear meaning reset is complete */
2337 for (i = 0; i < 10; i++) {
2339 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2340 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2344 if (ctrl & IXGBE_CTRL_RST_MASK) {
2345 status = IXGBE_ERR_RESET_FAILED;
2346 DEBUGOUT("Reset polling failed to complete.\n");
2351 /* Double resets are required for recovery from certain error
2352 * conditions. Between resets, it is necessary to stall to
2353 * allow time for any pending HW events to complete.
2355 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2356 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2360 /* Store the permanent mac address */
2361 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2363 /* Store MAC address from RAR0, clear receive address registers, and
2364 * clear the multicast table. Also reset num_rar_entries to 128,
2365 * since we modify this value when programming the SAN MAC address.
2367 hw->mac.num_rar_entries = 128;
2368 hw->mac.ops.init_rx_addrs(hw);
2370 ixgbe_set_mdio_speed(hw);
2372 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2373 ixgbe_setup_mux_ctl(hw);
2379 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2380 * @hw: pointer to hardware structure
2382 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2387 status = hw->phy.ops.read_reg(hw,
2388 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2389 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2392 if (status != IXGBE_SUCCESS)
2395 /* If PHY FW reset completed bit is set then this is the first
2396 * SW instance after a power on so the PHY FW must be un-stalled.
2398 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2399 status = hw->phy.ops.read_reg(hw,
2400 IXGBE_MDIO_GLOBAL_RES_PR_10,
2401 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2404 if (status != IXGBE_SUCCESS)
2407 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2409 status = hw->phy.ops.write_reg(hw,
2410 IXGBE_MDIO_GLOBAL_RES_PR_10,
2411 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2414 if (status != IXGBE_SUCCESS)
2422 * ixgbe_setup_kr_x550em - Configure the KR PHY.
2423 * @hw: pointer to hardware structure
2425 * Configures the integrated KR PHY for X550EM_x.
2427 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2429 if (hw->mac.type != ixgbe_mac_X550EM_x)
2430 return IXGBE_SUCCESS;
2432 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2436 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2437 * @hw: pointer to hardware structure
2439 * Configure the external PHY and the integrated KR PHY for SFP support.
2441 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2442 ixgbe_link_speed speed,
2443 bool autoneg_wait_to_complete)
2446 u16 reg_slice, reg_val;
2447 bool setup_linear = false;
2448 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2450 /* Check if SFP module is supported and linear */
2451 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2453 /* If no SFP module present, then return success. Return success since
2454 * there is no reason to configure CS4227 and SFP not present error is
2455 * not excepted in the setup MAC link flow.
2457 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2458 return IXGBE_SUCCESS;
2460 if (ret_val != IXGBE_SUCCESS)
2463 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2464 /* Configure CS4227 LINE side to 10G SR. */
2465 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2466 (hw->bus.lan_id << 12);
2467 reg_val = IXGBE_CS4227_SPEED_10G;
2468 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2471 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2472 (hw->bus.lan_id << 12);
2473 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2474 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2477 /* Configure CS4227 for HOST connection rate then type. */
2478 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2479 (hw->bus.lan_id << 12);
2480 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2481 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2482 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2485 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2486 (hw->bus.lan_id << 12);
2488 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2490 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2491 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2494 /* Setup XFI internal link. */
2495 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2497 /* Configure internal PHY for KR/KX. */
2498 ixgbe_setup_kr_speed_x550em(hw, speed);
2500 /* Configure CS4227 LINE side to proper mode. */
2501 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2502 (hw->bus.lan_id << 12);
2504 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2506 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2507 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2514 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2515 * @hw: pointer to hardware structure
2517 * Configure the the integrated PHY for SFP support.
2519 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2520 ixgbe_link_speed speed,
2521 bool autoneg_wait_to_complete)
2525 bool setup_linear = false;
2526 u32 reg_slice, reg_phy_int, slice_offset;
2528 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2530 /* Check if SFP module is supported and linear */
2531 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2533 /* If no SFP module present, then return success. Return success since
2534 * SFP not present error is not excepted in the setup MAC link flow.
2536 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2537 return IXGBE_SUCCESS;
2539 if (ret_val != IXGBE_SUCCESS)
2542 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2543 /* Configure internal PHY for native SFI */
2544 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2545 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2546 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
2548 if (ret_val != IXGBE_SUCCESS)
2552 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2553 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2555 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2556 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2559 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2560 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2561 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2563 if (ret_val != IXGBE_SUCCESS)
2566 /* Setup XFI/SFI internal link. */
2567 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2569 /* Configure internal PHY for KR/KX. */
2570 ixgbe_setup_kr_speed_x550em(hw, speed);
2572 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2574 DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2575 return IXGBE_ERR_PHY_ADDR_INVALID;
2578 /* Get external PHY device id */
2579 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2580 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
2582 if (ret_val != IXGBE_SUCCESS)
2585 /* When configuring quad port CS4223, the MAC instance is part
2586 * of the slice offset.
2588 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2589 slice_offset = (hw->bus.lan_id +
2590 (hw->bus.instance_id << 1)) << 12;
2592 slice_offset = hw->bus.lan_id << 12;
2594 /* Configure CS4227/CS4223 LINE side to proper mode. */
2595 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2597 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2599 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2600 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2601 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2607 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2608 * @hw: pointer to hardware structure
2610 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2612 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2617 /* Disable training protocol FSM. */
2618 status = ixgbe_read_iosf_sb_reg_x550(hw,
2619 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2620 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2621 if (status != IXGBE_SUCCESS)
2623 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2624 status = ixgbe_write_iosf_sb_reg_x550(hw,
2625 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2626 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2627 if (status != IXGBE_SUCCESS)
2630 /* Disable Flex from training TXFFE. */
2631 status = ixgbe_read_iosf_sb_reg_x550(hw,
2632 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2633 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2634 if (status != IXGBE_SUCCESS)
2636 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2637 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2638 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2639 status = ixgbe_write_iosf_sb_reg_x550(hw,
2640 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2641 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2642 if (status != IXGBE_SUCCESS)
2644 status = ixgbe_read_iosf_sb_reg_x550(hw,
2645 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2646 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2647 if (status != IXGBE_SUCCESS)
2649 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2650 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2651 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2652 status = ixgbe_write_iosf_sb_reg_x550(hw,
2653 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2654 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2655 if (status != IXGBE_SUCCESS)
2658 /* Enable override for coefficients. */
2659 status = ixgbe_read_iosf_sb_reg_x550(hw,
2660 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2661 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2662 if (status != IXGBE_SUCCESS)
2664 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2665 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2666 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2667 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2668 status = ixgbe_write_iosf_sb_reg_x550(hw,
2669 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2670 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2675 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2676 * @hw: pointer to hardware structure
2677 * @speed: the link speed to force
2679 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
2680 * internal and external PHY at a specific speed, without autonegotiation.
2682 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2687 /* Disable AN and force speed to 10G Serial. */
2688 status = ixgbe_read_iosf_sb_reg_x550(hw,
2689 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2690 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2691 if (status != IXGBE_SUCCESS)
2694 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2695 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2697 /* Select forced link speed for internal PHY. */
2699 case IXGBE_LINK_SPEED_10GB_FULL:
2700 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2702 case IXGBE_LINK_SPEED_1GB_FULL:
2703 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2706 /* Other link speeds are not supported by internal KR PHY. */
2707 return IXGBE_ERR_LINK_SETUP;
2710 status = ixgbe_write_iosf_sb_reg_x550(hw,
2711 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2712 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2713 if (status != IXGBE_SUCCESS)
2716 /* Additional configuration needed for x550em_x */
2717 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2718 status = ixgbe_setup_ixfi_x550em_x(hw);
2719 if (status != IXGBE_SUCCESS)
2723 /* Toggle port SW reset by AN reset. */
2724 status = ixgbe_read_iosf_sb_reg_x550(hw,
2725 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2726 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2727 if (status != IXGBE_SUCCESS)
2729 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2730 status = ixgbe_write_iosf_sb_reg_x550(hw,
2731 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2732 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2738 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2739 * @hw: address of hardware structure
2740 * @link_up: address of boolean to indicate link status
2742 * Returns error code if unable to get link status.
2744 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2751 /* read this twice back to back to indicate current status */
2752 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2753 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2755 if (ret != IXGBE_SUCCESS)
2758 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2759 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2761 if (ret != IXGBE_SUCCESS)
2764 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2766 return IXGBE_SUCCESS;
2770 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2771 * @hw: point to hardware structure
2773 * Configures the link between the integrated KR PHY and the external X557 PHY
2774 * The driver will call this function when it gets a link status change
2775 * interrupt from the X557 PHY. This function configures the link speed
2776 * between the PHYs to match the link speed of the BASE-T link.
2778 * A return of a non-zero value indicates an error, and the base driver should
2779 * not report link up.
2781 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2783 ixgbe_link_speed force_speed;
2788 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2789 return IXGBE_ERR_CONFIG;
2791 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2792 /* If link is down, there is no setup necessary so return */
2793 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2794 if (status != IXGBE_SUCCESS)
2798 return IXGBE_SUCCESS;
2800 status = hw->phy.ops.read_reg(hw,
2801 IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2802 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2804 if (status != IXGBE_SUCCESS)
2807 /* If link is still down - no setup is required so return */
2808 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2809 if (status != IXGBE_SUCCESS)
2812 return IXGBE_SUCCESS;
2814 /* clear everything but the speed and duplex bits */
2815 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2818 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2819 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2821 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2822 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2825 /* Internal PHY does not support anything else */
2826 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2829 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2831 speed = IXGBE_LINK_SPEED_10GB_FULL |
2832 IXGBE_LINK_SPEED_1GB_FULL;
2833 return ixgbe_setup_kr_speed_x550em(hw, speed);
2838 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2839 * @hw: pointer to hardware structure
2841 * Configures the integrated KR PHY to use internal loopback mode.
2843 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2848 /* Disable AN and force speed to 10G Serial. */
2849 status = hw->mac.ops.read_iosf_sb_reg(hw,
2850 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2851 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2852 if (status != IXGBE_SUCCESS)
2854 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2855 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2856 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2857 status = hw->mac.ops.write_iosf_sb_reg(hw,
2858 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2859 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2860 if (status != IXGBE_SUCCESS)
2863 /* Set near-end loopback clocks. */
2864 status = hw->mac.ops.read_iosf_sb_reg(hw,
2865 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2866 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2867 if (status != IXGBE_SUCCESS)
2869 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2870 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2871 status = hw->mac.ops.write_iosf_sb_reg(hw,
2872 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2873 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2874 if (status != IXGBE_SUCCESS)
2877 /* Set loopback enable. */
2878 status = hw->mac.ops.read_iosf_sb_reg(hw,
2879 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2880 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2881 if (status != IXGBE_SUCCESS)
2883 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2884 status = hw->mac.ops.write_iosf_sb_reg(hw,
2885 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2886 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2887 if (status != IXGBE_SUCCESS)
2890 /* Training bypass. */
2891 status = hw->mac.ops.read_iosf_sb_reg(hw,
2892 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2893 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2894 if (status != IXGBE_SUCCESS)
2896 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2897 status = hw->mac.ops.write_iosf_sb_reg(hw,
2898 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2899 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2905 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2906 * assuming that the semaphore is already obtained.
2907 * @hw: pointer to hardware structure
2908 * @offset: offset of word in the EEPROM to read
2909 * @data: word read from the EEPROM
2911 * Reads a 16 bit word from the EEPROM using the hostif.
2913 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
2915 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
2916 struct ixgbe_hic_read_shadow_ram buffer;
2919 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2920 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2921 buffer.hdr.req.buf_lenh = 0;
2922 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2923 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2925 /* convert offset from words to bytes */
2926 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2928 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2930 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
2934 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
2935 IXGBE_HI_COMMAND_TIMEOUT);
2937 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2938 FW_NVM_DATA_OFFSET);
2941 hw->mac.ops.release_swfw_sync(hw, mask);
2946 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2947 * @hw: pointer to hardware structure
2948 * @offset: offset of word in the EEPROM to read
2949 * @words: number of words
2950 * @data: word(s) read from the EEPROM
2952 * Reads a 16 bit word(s) from the EEPROM using the hostif.
2954 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2955 u16 offset, u16 words, u16 *data)
2957 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
2958 struct ixgbe_hic_read_shadow_ram buffer;
2959 u32 current_word = 0;
2964 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2966 /* Take semaphore for the entire operation. */
2967 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
2969 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2973 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2974 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2976 words_to_read = words;
2978 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2979 buffer.hdr.req.buf_lenh = 0;
2980 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2981 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2983 /* convert offset from words to bytes */
2984 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2985 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2987 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
2988 IXGBE_HI_COMMAND_TIMEOUT);
2991 DEBUGOUT("Host interface command failed\n");
2995 for (i = 0; i < words_to_read; i++) {
2996 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2998 u32 value = IXGBE_READ_REG(hw, reg);
3000 data[current_word] = (u16)(value & 0xffff);
3003 if (i < words_to_read) {
3005 data[current_word] = (u16)(value & 0xffff);
3009 words -= words_to_read;
3013 hw->mac.ops.release_swfw_sync(hw, mask);
3018 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3019 * @hw: pointer to hardware structure
3020 * @offset: offset of word in the EEPROM to write
3021 * @data: word write to the EEPROM
3023 * Write a 16 bit word to the EEPROM using the hostif.
3025 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3029 struct ixgbe_hic_write_shadow_ram buffer;
3031 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3033 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3034 buffer.hdr.req.buf_lenh = 0;
3035 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3036 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3039 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3041 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3043 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3045 IXGBE_HI_COMMAND_TIMEOUT, false);
3051 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3052 * @hw: pointer to hardware structure
3053 * @offset: offset of word in the EEPROM to write
3054 * @data: word write to the EEPROM
3056 * Write a 16 bit word to the EEPROM using the hostif.
3058 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3061 s32 status = IXGBE_SUCCESS;
3063 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3065 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3067 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3068 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3070 DEBUGOUT("write ee hostif failed to get semaphore");
3071 status = IXGBE_ERR_SWFW_SYNC;
3078 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3079 * @hw: pointer to hardware structure
3080 * @offset: offset of word in the EEPROM to write
3081 * @words: number of words
3082 * @data: word(s) write to the EEPROM
3084 * Write a 16 bit word(s) to the EEPROM using the hostif.
3086 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3087 u16 offset, u16 words, u16 *data)
3089 s32 status = IXGBE_SUCCESS;
3092 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3094 /* Take semaphore for the entire operation. */
3095 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3096 if (status != IXGBE_SUCCESS) {
3097 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3101 for (i = 0; i < words; i++) {
3102 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3105 if (status != IXGBE_SUCCESS) {
3106 DEBUGOUT("Eeprom buffered write failed\n");
3111 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3118 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3119 * @hw: pointer to hardware structure
3120 * @ptr: pointer offset in eeprom
3121 * @size: size of section pointed by ptr, if 0 first word will be used as size
3122 * @csum: address of checksum to update
3124 * Returns error status for any failure
3126 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3127 u16 size, u16 *csum, u16 *buffer,
3132 u16 length, bufsz, i, start;
3135 bufsz = sizeof(buf) / sizeof(buf[0]);
3137 /* Read a chunk at the pointer location */
3139 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3141 DEBUGOUT("Failed to read EEPROM image\n");
3146 if (buffer_size < ptr)
3147 return IXGBE_ERR_PARAM;
3148 local_buffer = &buffer[ptr];
3156 length = local_buffer[0];
3158 /* Skip pointer section if length is invalid. */
3159 if (length == 0xFFFF || length == 0 ||
3160 (ptr + length) >= hw->eeprom.word_size)
3161 return IXGBE_SUCCESS;
3164 if (buffer && ((u32)start + (u32)length > buffer_size))
3165 return IXGBE_ERR_PARAM;
3167 for (i = start; length; i++, length--) {
3168 if (i == bufsz && !buffer) {
3174 /* Read a chunk at the pointer location */
3175 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3178 DEBUGOUT("Failed to read EEPROM image\n");
3182 *csum += local_buffer[i];
3184 return IXGBE_SUCCESS;
3188 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3189 * @hw: pointer to hardware structure
3190 * @buffer: pointer to buffer containing calculated checksum
3191 * @buffer_size: size of buffer
3193 * Returns a negative error code on error, or the 16-bit checksum
3195 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3197 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3201 u16 pointer, i, size;
3203 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3205 hw->eeprom.ops.init_params(hw);
3208 /* Read pointer area */
3209 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3210 IXGBE_EEPROM_LAST_WORD + 1,
3213 DEBUGOUT("Failed to read EEPROM image\n");
3216 local_buffer = eeprom_ptrs;
3218 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3219 return IXGBE_ERR_PARAM;
3220 local_buffer = buffer;
3224 * For X550 hardware include 0x0-0x41 in the checksum, skip the
3225 * checksum word itself
3227 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3228 if (i != IXGBE_EEPROM_CHECKSUM)
3229 checksum += local_buffer[i];
3232 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
3233 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3235 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3236 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3239 pointer = local_buffer[i];
3241 /* Skip pointer section if the pointer is invalid. */
3242 if (pointer == 0xFFFF || pointer == 0 ||
3243 pointer >= hw->eeprom.word_size)
3247 case IXGBE_PCIE_GENERAL_PTR:
3248 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3250 case IXGBE_PCIE_CONFIG0_PTR:
3251 case IXGBE_PCIE_CONFIG1_PTR:
3252 size = IXGBE_PCIE_CONFIG_SIZE;
3259 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3260 buffer, buffer_size);
3265 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3267 return (s32)checksum;
3271 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3272 * @hw: pointer to hardware structure
3274 * Returns a negative error code on error, or the 16-bit checksum
3276 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3278 return ixgbe_calc_checksum_X550(hw, NULL, 0);
3282 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3283 * @hw: pointer to hardware structure
3284 * @checksum_val: calculated checksum
3286 * Performs checksum calculation and validates the EEPROM checksum. If the
3287 * caller does not need checksum_val, the value can be NULL.
3289 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3293 u16 read_checksum = 0;
3295 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3297 /* Read the first word from the EEPROM. If this times out or fails, do
3298 * not continue or we could be in for a very long wait while every
3301 status = hw->eeprom.ops.read(hw, 0, &checksum);
3303 DEBUGOUT("EEPROM read failed\n");
3307 status = hw->eeprom.ops.calc_checksum(hw);
3311 checksum = (u16)(status & 0xffff);
3313 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3318 /* Verify read checksum from EEPROM is the same as
3319 * calculated checksum
3321 if (read_checksum != checksum) {
3322 status = IXGBE_ERR_EEPROM_CHECKSUM;
3323 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3324 "Invalid EEPROM checksum");
3327 /* If the user cares, return the calculated checksum */
3329 *checksum_val = checksum;
3335 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3336 * @hw: pointer to hardware structure
3338 * After writing EEPROM to shadow RAM using EEWR register, software calculates
3339 * checksum and updates the EEPROM and instructs the hardware to update
3342 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3347 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3349 /* Read the first word from the EEPROM. If this times out or fails, do
3350 * not continue or we could be in for a very long wait while every
3353 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3355 DEBUGOUT("EEPROM read failed\n");
3359 status = ixgbe_calc_eeprom_checksum_X550(hw);
3363 checksum = (u16)(status & 0xffff);
3365 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3370 status = ixgbe_update_flash_X550(hw);
3376 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3377 * @hw: pointer to hardware structure
3379 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3381 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3383 s32 status = IXGBE_SUCCESS;
3384 union ixgbe_hic_hdr2 buffer;
3386 DEBUGFUNC("ixgbe_update_flash_X550");
3388 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3389 buffer.req.buf_lenh = 0;
3390 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3391 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3393 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3395 IXGBE_HI_COMMAND_TIMEOUT, false);
3401 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3402 * @hw: pointer to hardware structure
3404 * Determines physical layer capabilities of the current configuration.
3406 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3408 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3409 u16 ext_ability = 0;
3411 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3413 hw->phy.ops.identify(hw);
3415 switch (hw->phy.type) {
3416 case ixgbe_phy_x550em_kr:
3417 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3418 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3420 case ixgbe_phy_x550em_kx4:
3421 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3422 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3424 case ixgbe_phy_x550em_ext_t:
3425 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3426 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3428 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3429 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3430 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3431 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3437 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3438 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3440 return physical_layer;
3444 * ixgbe_get_bus_info_x550em - Set PCI bus info
3445 * @hw: pointer to hardware structure
3447 * Sets bus link width and speed to unknown because X550em is
3450 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3453 DEBUGFUNC("ixgbe_get_bus_info_x550em");
3455 hw->bus.width = ixgbe_bus_width_unknown;
3456 hw->bus.speed = ixgbe_bus_speed_unknown;
3458 hw->mac.ops.set_lan_id(hw);
3460 return IXGBE_SUCCESS;
3464 * ixgbe_disable_rx_x550 - Disable RX unit
3466 * Enables the Rx DMA unit for x550
3468 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3470 u32 rxctrl, pfdtxgswc;
3472 struct ixgbe_hic_disable_rxen fw_cmd;
3474 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3476 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3477 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3478 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3479 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3480 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3481 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3482 hw->mac.set_lben = true;
3484 hw->mac.set_lben = false;
3487 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3488 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3489 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3490 fw_cmd.port_number = (u8)hw->bus.lan_id;
3492 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3493 sizeof(struct ixgbe_hic_disable_rxen),
3494 IXGBE_HI_COMMAND_TIMEOUT, true);
3496 /* If we fail - disable RX using register write */
3498 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3499 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3500 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3501 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3508 * ixgbe_enter_lplu_x550em - Transition to low power states
3509 * @hw: pointer to hardware structure
3511 * Configures Low Power Link Up on transition to low power states
3512 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3513 * X557 PHY immediately prior to entering LPLU.
3515 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3517 u16 an_10g_cntl_reg, autoneg_reg, speed;
3519 ixgbe_link_speed lcd_speed;
3523 /* SW LPLU not required on later HW revisions. */
3524 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3525 (IXGBE_FUSES0_REV_MASK &
3526 IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3527 return IXGBE_SUCCESS;
3529 /* If blocked by MNG FW, then don't restart AN */
3530 if (ixgbe_check_reset_blocked(hw))
3531 return IXGBE_SUCCESS;
3533 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3534 if (status != IXGBE_SUCCESS)
3537 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3539 if (status != IXGBE_SUCCESS)
3542 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3543 * disabled, then force link down by entering low power mode.
3545 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3546 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3547 return ixgbe_set_copper_phy_power(hw, FALSE);
3550 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3552 if (status != IXGBE_SUCCESS)
3555 /* If no valid LCD link speed, then force link down and exit. */
3556 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3557 return ixgbe_set_copper_phy_power(hw, FALSE);
3559 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3560 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3563 if (status != IXGBE_SUCCESS)
3566 /* If no link now, speed is invalid so take link down */
3567 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3568 if (status != IXGBE_SUCCESS)
3569 return ixgbe_set_copper_phy_power(hw, false);
3571 /* clear everything but the speed bits */
3572 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3574 /* If current speed is already LCD, then exit. */
3575 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3576 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3577 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3578 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3581 /* Clear AN completed indication */
3582 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3583 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3586 if (status != IXGBE_SUCCESS)
3589 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3590 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3593 if (status != IXGBE_SUCCESS)
3596 status = hw->phy.ops.read_reg(hw,
3597 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3598 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3601 if (status != IXGBE_SUCCESS)
3604 save_autoneg = hw->phy.autoneg_advertised;
3606 /* Setup link at least common link speed */
3607 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3609 /* restore autoneg from before setting lplu speed */
3610 hw->phy.autoneg_advertised = save_autoneg;
3616 * ixgbe_get_lcd_x550em - Determine lowest common denominator
3617 * @hw: pointer to hardware structure
3618 * @lcd_speed: pointer to lowest common link speed
3620 * Determine lowest common link speed with link partner.
3622 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3626 u16 word = hw->eeprom.ctrl_word_3;
3628 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3630 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3631 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3634 if (status != IXGBE_SUCCESS)
3637 /* If link partner advertised 1G, return 1G */
3638 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3639 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3643 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3644 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3645 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3648 /* Link partner not capable of lower speeds, return 10G */
3649 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3654 * ixgbe_setup_fc_X550em - Set up flow control
3655 * @hw: pointer to hardware structure
3657 * Called at init time to set up flow control.
3659 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3661 s32 ret_val = IXGBE_SUCCESS;
3662 u32 pause, asm_dir, reg_val;
3664 DEBUGFUNC("ixgbe_setup_fc_X550em");
3666 /* Validate the requested mode */
3667 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3668 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3669 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3670 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3674 /* 10gig parts do not have a word in the EEPROM to determine the
3675 * default flow control setting, so we explicitly set it to full.
3677 if (hw->fc.requested_mode == ixgbe_fc_default)
3678 hw->fc.requested_mode = ixgbe_fc_full;
3680 /* Determine PAUSE and ASM_DIR bits. */
3681 switch (hw->fc.requested_mode) {
3686 case ixgbe_fc_tx_pause:
3690 case ixgbe_fc_rx_pause:
3691 /* Rx Flow control is enabled and Tx Flow control is
3692 * disabled by software override. Since there really
3693 * isn't a way to advertise that we are capable of RX
3694 * Pause ONLY, we will advertise that we support both
3695 * symmetric and asymmetric Rx PAUSE, as such we fall
3696 * through to the fc_full statement. Later, we will
3697 * disable the adapter's ability to send PAUSE frames.
3704 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3705 "Flow control param set incorrectly\n");
3706 ret_val = IXGBE_ERR_CONFIG;
3710 switch (hw->device_id) {
3711 case IXGBE_DEV_ID_X550EM_X_KR:
3712 case IXGBE_DEV_ID_X550EM_A_KR:
3713 case IXGBE_DEV_ID_X550EM_A_KR_L:
3714 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3715 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3716 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3717 if (ret_val != IXGBE_SUCCESS)
3719 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3720 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3722 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3724 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3725 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3726 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3727 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3729 /* This device does not fully support AN. */
3730 hw->fc.disable_fc_autoneg = true;
3741 * ixgbe_fc_autoneg_x550a - Enable flow control IEEE clause 37
3742 * @hw: pointer to hardware structure
3744 * Enable flow control according to IEEE clause 37.
3746 void ixgbe_fc_autoneg_x550a(struct ixgbe_hw *hw)
3748 u32 link_s1, lp_an_page_low, an_cntl_1;
3749 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3750 ixgbe_link_speed speed;
3753 /* AN should have completed when the cable was plugged in.
3754 * Look for reasons to bail out. Bail out if:
3755 * - FC autoneg is disabled, or if
3758 if (hw->fc.disable_fc_autoneg) {
3759 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3760 "Flow control autoneg is disabled");
3764 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3766 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3770 /* Check at auto-negotiation has completed */
3771 status = hw->mac.ops.read_iosf_sb_reg(hw,
3772 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
3773 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
3775 if (status != IXGBE_SUCCESS ||
3776 (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
3777 DEBUGOUT("Auto-Negotiation did not complete\n");
3781 /* Read the 10g AN autoc and LP ability registers and resolve
3782 * local flow control settings accordingly
3784 status = hw->mac.ops.read_iosf_sb_reg(hw,
3785 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3786 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
3788 if (status != IXGBE_SUCCESS) {
3789 DEBUGOUT("Auto-Negotiation did not complete\n");
3793 status = hw->mac.ops.read_iosf_sb_reg(hw,
3794 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
3795 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
3797 if (status != IXGBE_SUCCESS) {
3798 DEBUGOUT("Auto-Negotiation did not complete\n");
3802 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
3803 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
3804 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
3805 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
3806 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
3809 if (status == IXGBE_SUCCESS) {
3810 hw->fc.fc_was_autonegged = true;
3812 hw->fc.fc_was_autonegged = false;
3813 hw->fc.current_mode = hw->fc.requested_mode;
3818 * ixgbe_setup_fc_x550em - Set up flow control
3819 * @hw: pointer to hardware structure
3821 * Called at init time to set up flow control.
3823 s32 ixgbe_setup_fc_x550a(struct ixgbe_hw *hw)
3825 s32 status = IXGBE_SUCCESS;
3826 u32 an_cntl, link_ctrl = 0;
3828 DEBUGFUNC("ixgbe_setup_fc_x550em");
3830 /* Validate the requested mode */
3831 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3832 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3833 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3834 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3837 if (hw->fc.requested_mode == ixgbe_fc_default)
3838 hw->fc.requested_mode = ixgbe_fc_full;
3840 /* Set up the 1G and 10G flow control advertisement registers so the
3841 * HW will be able to do FC autoneg once the cable is plugged in. If
3842 * we link at 10G, the 1G advertisement is harmless and vice versa.
3844 status = hw->mac.ops.read_iosf_sb_reg(hw,
3845 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3846 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
3848 if (status != IXGBE_SUCCESS) {
3849 DEBUGOUT("Auto-Negotiation did not complete\n");
3853 /* The possible values of fc.requested_mode are:
3854 * 0: Flow control is completely disabled
3855 * 1: Rx flow control is enabled (we can receive pause frames,
3856 * but not send pause frames).
3857 * 2: Tx flow control is enabled (we can send pause frames but
3858 * we do not support receiving pause frames).
3859 * 3: Both Rx and Tx flow control (symmetric) are enabled.
3862 switch (hw->fc.requested_mode) {
3864 /* Flow control completely disabled by software override. */
3865 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3866 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3868 case ixgbe_fc_tx_pause:
3869 /* Tx Flow control is enabled, and Rx Flow control is
3870 * disabled by software override.
3872 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3873 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3875 case ixgbe_fc_rx_pause:
3876 /* Rx Flow control is enabled and Tx Flow control is
3877 * disabled by software override. Since there really
3878 * isn't a way to advertise that we are capable of RX
3879 * Pause ONLY, we will advertise that we support both
3880 * symmetric and asymmetric Rx PAUSE, as such we fall
3881 * through to the fc_full statement. Later, we will
3882 * disable the adapter's ability to send PAUSE frames.
3885 /* Flow control (both Rx and Tx) is enabled by SW override. */
3886 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3887 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3890 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3891 "Flow control param set incorrectly\n");
3892 return IXGBE_ERR_CONFIG;
3895 status = hw->mac.ops.write_iosf_sb_reg(hw,
3896 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3897 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
3899 /* Restart auto-negotiation. */
3900 status = hw->mac.ops.read_iosf_sb_reg(hw,
3901 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3902 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
3904 if (status != IXGBE_SUCCESS) {
3905 DEBUGOUT("Auto-Negotiation did not complete\n");
3909 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
3910 status = hw->mac.ops.write_iosf_sb_reg(hw,
3911 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3912 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
3918 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3919 * @hw: pointer to hardware structure
3920 * @state: set mux if 1, clear if 0
3922 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3926 if (!hw->bus.lan_id)
3928 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3930 esdp |= IXGBE_ESDP_SDP1;
3932 esdp &= ~IXGBE_ESDP_SDP1;
3933 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3934 IXGBE_WRITE_FLUSH(hw);
3938 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3939 * @hw: pointer to hardware structure
3940 * @mask: Mask to specify which semaphore to acquire
3942 * Acquires the SWFW semaphore and sets the I2C MUX
3944 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3948 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3950 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3954 if (mask & IXGBE_GSSR_I2C_MASK)
3955 ixgbe_set_mux(hw, 1);
3957 return IXGBE_SUCCESS;
3961 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3962 * @hw: pointer to hardware structure
3963 * @mask: Mask to specify which semaphore to release
3965 * Releases the SWFW semaphore and sets the I2C MUX
3967 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3969 DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3971 if (mask & IXGBE_GSSR_I2C_MASK)
3972 ixgbe_set_mux(hw, 0);
3974 ixgbe_release_swfw_sync_X540(hw, mask);
3978 * ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3979 * @hw: pointer to hardware structure
3980 * @mask: Mask to specify which semaphore to acquire
3982 * Acquires the SWFW semaphore and get the shared phy token as needed
3984 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3986 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3987 int retries = FW_PHY_TOKEN_RETRIES;
3988 s32 status = IXGBE_SUCCESS;
3990 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3993 status = IXGBE_SUCCESS;
3995 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3998 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3999 return IXGBE_SUCCESS;
4001 status = ixgbe_get_phy_token(hw);
4002 if (status == IXGBE_SUCCESS)
4003 return IXGBE_SUCCESS;
4006 ixgbe_release_swfw_sync_X540(hw, hmask);
4007 if (status != IXGBE_ERR_TOKEN_RETRY)
4009 msec_delay(FW_PHY_TOKEN_DELAY);
4016 * ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4017 * @hw: pointer to hardware structure
4018 * @mask: Mask to specify which semaphore to release
4020 * Releases the SWFW semaphore and puts the shared phy token as needed
4022 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4024 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4026 DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4028 if (mask & IXGBE_GSSR_TOKEN_SM)
4029 ixgbe_put_phy_token(hw);
4032 ixgbe_release_swfw_sync_X540(hw, hmask);
4036 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
4037 * @hw: pointer to hardware structure
4038 * @reg_addr: 32 bit address of PHY register to read
4039 * @phy_data: Pointer to read data from PHY register
4041 * Reads a value from a specified PHY register using the SWFW lock and PHY
4042 * Token. The PHY Token is needed since the MDIO is shared between to MAC
4045 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4046 u32 device_type, u16 *phy_data)
4049 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4051 DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4053 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4054 return IXGBE_ERR_SWFW_SYNC;
4056 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4058 hw->mac.ops.release_swfw_sync(hw, mask);
4064 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
4065 * @hw: pointer to hardware structure
4066 * @reg_addr: 32 bit PHY register to write
4067 * @device_type: 5 bit device type
4068 * @phy_data: Data to write to the PHY register
4070 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
4071 * The PHY Token is needed since the MDIO is shared between to MAC instances.
4073 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4074 u32 device_type, u16 phy_data)
4077 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4079 DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4081 if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4082 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
4084 hw->mac.ops.release_swfw_sync(hw, mask);
4086 status = IXGBE_ERR_SWFW_SYNC;
4093 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4094 * @hw: pointer to hardware structure
4096 * Handle external Base T PHY interrupt. If high temperature
4097 * failure alarm then return error, else if link status change
4098 * then setup internal/external PHY link
4100 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4101 * failure alarm, else return PHY access status.
4103 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4108 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4110 if (status != IXGBE_SUCCESS)
4114 return ixgbe_setup_internal_phy(hw);
4116 return IXGBE_SUCCESS;
4120 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4121 * @hw: pointer to hardware structure
4122 * @speed: new link speed
4123 * @autoneg_wait_to_complete: true when waiting for completion is needed
4125 * Setup internal/external PHY link speed based on link speed, then set
4126 * external PHY auto advertised link speed.
4128 * Returns error status for any failure
4130 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4131 ixgbe_link_speed speed,
4132 bool autoneg_wait_to_complete)
4135 ixgbe_link_speed force_speed;
4137 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4139 /* Setup internal/external PHY link speed to iXFI (10G), unless
4140 * only 1G is auto advertised then setup KX link.
4142 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4143 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4145 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4147 /* If internal link mode is XFI, then setup XFI internal link. */
4148 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4149 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4151 if (status != IXGBE_SUCCESS)
4155 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4159 * ixgbe_check_link_t_X550em - Determine link and speed status
4160 * @hw: pointer to hardware structure
4161 * @speed: pointer to link speed
4162 * @link_up: true when link is up
4163 * @link_up_wait_to_complete: bool used to wait for link up or not
4165 * Check that both the MAC and X557 external PHY have link.
4167 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4168 bool *link_up, bool link_up_wait_to_complete)
4173 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4174 return IXGBE_ERR_CONFIG;
4176 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4177 link_up_wait_to_complete);
4179 /* If check link fails or MAC link is not up, then return */
4180 if (status != IXGBE_SUCCESS || !(*link_up))
4183 /* MAC link is up, so check external PHY link.
4184 * Read this twice back to back to indicate current status.
4186 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4187 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4190 if (status != IXGBE_SUCCESS)
4193 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4194 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4197 if (status != IXGBE_SUCCESS)
4200 /* If external PHY link is not up, then indicate link not up */
4201 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4204 return IXGBE_SUCCESS;
4208 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4209 * @hw: pointer to hardware structure
4211 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4215 status = ixgbe_reset_phy_generic(hw);
4217 if (status != IXGBE_SUCCESS)
4220 /* Configure Link Status Alarm and Temperature Threshold interrupts */
4221 return ixgbe_enable_lasi_ext_t_x550em(hw);
4225 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4226 * @hw: pointer to hardware structure
4227 * @led_idx: led number to turn on
4229 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4233 DEBUGFUNC("ixgbe_led_on_t_X550em");
4235 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4236 return IXGBE_ERR_PARAM;
4238 /* To turn on the LED, set mode to ON. */
4239 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4240 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4241 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4242 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4243 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4245 return IXGBE_SUCCESS;
4249 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4250 * @hw: pointer to hardware structure
4251 * @led_idx: led number to turn off
4253 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4257 DEBUGFUNC("ixgbe_led_off_t_X550em");
4259 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4260 return IXGBE_ERR_PARAM;
4262 /* To turn on the LED, set mode to ON. */
4263 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4264 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4265 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4266 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4267 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4269 return IXGBE_SUCCESS;