4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
75 #include "rte_pmd_ixgbe.h"
78 * High threshold controlling when to start sending XOFF frames. Must be at
79 * least 8 bytes less than receive packet buffer size. This value is in units
82 #define IXGBE_FC_HI 0x80
85 * Low threshold controlling when to start sending XON frames. This value is
86 * in units of 1024 bytes.
88 #define IXGBE_FC_LO 0x40
90 /* Default minimum inter-interrupt interval for EITR configuration */
91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
93 /* Timer value included in XOFF frames. */
94 #define IXGBE_FC_PAUSE 0x680
96 /*Default value of Max Rx Queue*/
97 #define IXGBE_MAX_RX_QUEUE_NUM 128
99 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
100 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
101 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
103 #define IXGBE_MMW_SIZE_DEFAULT 0x4
104 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
105 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
108 * Default values for RX/TX configuration
110 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_RX_PTHRESH 8
112 #define IXGBE_DEFAULT_RX_HTHRESH 8
113 #define IXGBE_DEFAULT_RX_WTHRESH 0
115 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
116 #define IXGBE_DEFAULT_TX_PTHRESH 32
117 #define IXGBE_DEFAULT_TX_HTHRESH 0
118 #define IXGBE_DEFAULT_TX_WTHRESH 0
119 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
121 /* Bit shift and mask */
122 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
123 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
124 #define IXGBE_8_BIT_WIDTH CHAR_BIT
125 #define IXGBE_8_BIT_MASK UINT8_MAX
127 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
129 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
131 #define IXGBE_HKEY_MAX_INDEX 10
133 /* Additional timesync values. */
134 #define NSEC_PER_SEC 1000000000L
135 #define IXGBE_INCVAL_10GB 0x66666666
136 #define IXGBE_INCVAL_1GB 0x40000000
137 #define IXGBE_INCVAL_100 0x50000000
138 #define IXGBE_INCVAL_SHIFT_10GB 28
139 #define IXGBE_INCVAL_SHIFT_1GB 24
140 #define IXGBE_INCVAL_SHIFT_100 21
141 #define IXGBE_INCVAL_SHIFT_82599 7
142 #define IXGBE_INCPER_SHIFT_82599 24
144 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
146 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
147 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
148 #define DEFAULT_ETAG_ETYPE 0x893f
149 #define IXGBE_ETAG_ETYPE 0x00005084
150 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
151 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
152 #define IXGBE_RAH_ADTYPE 0x40000000
153 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
154 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
155 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
156 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
157 #define IXGBE_QDE_STRIP_TAG 0x00000004
158 #define IXGBE_VTEICR_MASK 0x07
160 enum ixgbevf_xcast_modes {
161 IXGBEVF_XCAST_MODE_NONE = 0,
162 IXGBEVF_XCAST_MODE_MULTI,
163 IXGBEVF_XCAST_MODE_ALLMULTI,
166 #define IXGBE_EXVET_VET_EXT_SHIFT 16
167 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
169 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
170 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
171 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
172 static int ixgbe_dev_start(struct rte_eth_dev *dev);
173 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
174 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
175 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
176 static void ixgbe_dev_close(struct rte_eth_dev *dev);
177 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
178 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
179 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
180 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
181 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
182 int wait_to_complete);
183 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
184 struct rte_eth_stats *stats);
185 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
186 struct rte_eth_xstat *xstats, unsigned n);
187 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
188 struct rte_eth_xstat *xstats, unsigned n);
189 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
190 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
191 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
192 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
193 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
194 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
195 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
199 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
200 struct rte_eth_dev_info *dev_info);
201 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
202 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
203 struct rte_eth_dev_info *dev_info);
204 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
206 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
207 uint16_t vlan_id, int on);
208 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
209 enum rte_vlan_type vlan_type,
211 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
212 uint16_t queue, bool on);
213 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
215 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
216 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
217 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
218 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
219 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
221 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
222 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
223 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
224 struct rte_eth_fc_conf *fc_conf);
225 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
226 struct rte_eth_fc_conf *fc_conf);
227 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
228 struct rte_eth_pfc_conf *pfc_conf);
229 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
230 struct rte_eth_rss_reta_entry64 *reta_conf,
232 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
233 struct rte_eth_rss_reta_entry64 *reta_conf,
235 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
236 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
237 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
238 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
239 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
240 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
242 static void ixgbe_dev_interrupt_delayed_handler(void *param);
243 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
244 uint32_t index, uint32_t pool);
245 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
246 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
247 struct ether_addr *mac_addr);
248 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
250 /* For Virtual Function support */
251 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
252 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
253 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
254 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
255 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
256 int wait_to_complete);
257 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
258 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
259 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
260 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
261 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
262 struct rte_eth_stats *stats);
263 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
264 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
265 uint16_t vlan_id, int on);
266 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
267 uint16_t queue, int on);
268 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
269 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
270 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
272 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
274 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
275 uint8_t queue, uint8_t msix_vector);
276 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
277 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
278 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
280 /* For Eth VMDQ APIs support */
281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
282 ether_addr * mac_addr, uint8_t on);
283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
284 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
285 uint16_t rx_mask, uint8_t on);
286 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
287 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
288 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
289 uint64_t pool_mask, uint8_t vlan_on);
290 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
291 struct rte_eth_mirror_conf *mirror_conf,
292 uint8_t rule_id, uint8_t on);
293 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
295 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
297 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
299 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
300 uint8_t queue, uint8_t msix_vector);
301 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
303 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
304 uint16_t queue_idx, uint16_t tx_rate);
305 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
306 uint16_t tx_rate, uint64_t q_msk);
308 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
309 struct ether_addr *mac_addr,
310 uint32_t index, uint32_t pool);
311 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
312 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
313 struct ether_addr *mac_addr);
314 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
315 struct rte_eth_syn_filter *filter,
317 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
318 struct rte_eth_syn_filter *filter);
319 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
320 enum rte_filter_op filter_op,
322 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
323 struct ixgbe_5tuple_filter *filter);
324 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
325 struct ixgbe_5tuple_filter *filter);
326 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
327 struct rte_eth_ntuple_filter *filter,
329 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
330 enum rte_filter_op filter_op,
332 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
333 struct rte_eth_ntuple_filter *filter);
334 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
335 struct rte_eth_ethertype_filter *filter,
337 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
338 enum rte_filter_op filter_op,
340 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
341 struct rte_eth_ethertype_filter *filter);
342 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
343 enum rte_filter_type filter_type,
344 enum rte_filter_op filter_op,
346 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
348 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
349 struct ether_addr *mc_addr_set,
350 uint32_t nb_mc_addr);
351 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
352 struct rte_eth_dcb_info *dcb_info);
354 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
355 static int ixgbe_get_regs(struct rte_eth_dev *dev,
356 struct rte_dev_reg_info *regs);
357 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
358 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
359 struct rte_dev_eeprom_info *eeprom);
360 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
361 struct rte_dev_eeprom_info *eeprom);
363 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
364 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
365 struct rte_dev_reg_info *regs);
367 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
368 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
369 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
370 struct timespec *timestamp,
372 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
373 struct timespec *timestamp);
374 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
375 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
376 struct timespec *timestamp);
377 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
378 const struct timespec *timestamp);
379 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
382 static int ixgbe_dev_l2_tunnel_eth_type_conf
383 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
384 static int ixgbe_dev_l2_tunnel_offload_set
385 (struct rte_eth_dev *dev,
386 struct rte_eth_l2_tunnel_conf *l2_tunnel,
389 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
390 enum rte_filter_op filter_op,
393 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
394 struct rte_eth_udp_tunnel *udp_tunnel);
395 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
396 struct rte_eth_udp_tunnel *udp_tunnel);
399 * Define VF Stats MACRO for Non "cleared on read" register
401 #define UPDATE_VF_STAT(reg, last, cur) \
403 uint32_t latest = IXGBE_READ_REG(hw, reg); \
404 cur += (latest - last) & UINT_MAX; \
408 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
410 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
411 u64 new_msb = IXGBE_READ_REG(hw, msb); \
412 u64 latest = ((new_msb << 32) | new_lsb); \
413 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
417 #define IXGBE_SET_HWSTRIP(h, q) do {\
418 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
419 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
420 (h)->bitmap[idx] |= 1 << bit;\
423 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
424 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
425 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
426 (h)->bitmap[idx] &= ~(1 << bit);\
429 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
430 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
431 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
432 (r) = (h)->bitmap[idx] >> bit & 1;\
436 * The set of PCI devices this driver supports
438 static const struct rte_pci_id pci_id_ixgbe_map[] = {
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
486 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
488 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
489 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
492 #ifdef RTE_NIC_BYPASS
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
495 { .vendor_id = 0, /* sentinel */ },
499 * The set of PCI devices this driver supports (for 82599 VF)
501 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
504 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
505 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
506 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
507 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
508 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
509 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
510 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
511 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
512 { .vendor_id = 0, /* sentinel */ },
515 static const struct rte_eth_desc_lim rx_desc_lim = {
516 .nb_max = IXGBE_MAX_RING_DESC,
517 .nb_min = IXGBE_MIN_RING_DESC,
518 .nb_align = IXGBE_RXD_ALIGN,
521 static const struct rte_eth_desc_lim tx_desc_lim = {
522 .nb_max = IXGBE_MAX_RING_DESC,
523 .nb_min = IXGBE_MIN_RING_DESC,
524 .nb_align = IXGBE_TXD_ALIGN,
527 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
528 .dev_configure = ixgbe_dev_configure,
529 .dev_start = ixgbe_dev_start,
530 .dev_stop = ixgbe_dev_stop,
531 .dev_set_link_up = ixgbe_dev_set_link_up,
532 .dev_set_link_down = ixgbe_dev_set_link_down,
533 .dev_close = ixgbe_dev_close,
534 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
535 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
536 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
537 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
538 .link_update = ixgbe_dev_link_update,
539 .stats_get = ixgbe_dev_stats_get,
540 .xstats_get = ixgbe_dev_xstats_get,
541 .stats_reset = ixgbe_dev_stats_reset,
542 .xstats_reset = ixgbe_dev_xstats_reset,
543 .xstats_get_names = ixgbe_dev_xstats_get_names,
544 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
545 .dev_infos_get = ixgbe_dev_info_get,
546 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
547 .mtu_set = ixgbe_dev_mtu_set,
548 .vlan_filter_set = ixgbe_vlan_filter_set,
549 .vlan_tpid_set = ixgbe_vlan_tpid_set,
550 .vlan_offload_set = ixgbe_vlan_offload_set,
551 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
552 .rx_queue_start = ixgbe_dev_rx_queue_start,
553 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
554 .tx_queue_start = ixgbe_dev_tx_queue_start,
555 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
556 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
557 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
558 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
559 .rx_queue_release = ixgbe_dev_rx_queue_release,
560 .rx_queue_count = ixgbe_dev_rx_queue_count,
561 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
562 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
563 .tx_queue_release = ixgbe_dev_tx_queue_release,
564 .dev_led_on = ixgbe_dev_led_on,
565 .dev_led_off = ixgbe_dev_led_off,
566 .flow_ctrl_get = ixgbe_flow_ctrl_get,
567 .flow_ctrl_set = ixgbe_flow_ctrl_set,
568 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
569 .mac_addr_add = ixgbe_add_rar,
570 .mac_addr_remove = ixgbe_remove_rar,
571 .mac_addr_set = ixgbe_set_default_mac_addr,
572 .uc_hash_table_set = ixgbe_uc_hash_table_set,
573 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
574 .mirror_rule_set = ixgbe_mirror_rule_set,
575 .mirror_rule_reset = ixgbe_mirror_rule_reset,
576 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
577 .set_vf_rx = ixgbe_set_pool_rx,
578 .set_vf_tx = ixgbe_set_pool_tx,
579 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
580 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
581 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
582 .reta_update = ixgbe_dev_rss_reta_update,
583 .reta_query = ixgbe_dev_rss_reta_query,
584 #ifdef RTE_NIC_BYPASS
585 .bypass_init = ixgbe_bypass_init,
586 .bypass_state_set = ixgbe_bypass_state_store,
587 .bypass_state_show = ixgbe_bypass_state_show,
588 .bypass_event_set = ixgbe_bypass_event_store,
589 .bypass_event_show = ixgbe_bypass_event_show,
590 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
591 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
592 .bypass_ver_show = ixgbe_bypass_ver_show,
593 .bypass_wd_reset = ixgbe_bypass_wd_reset,
594 #endif /* RTE_NIC_BYPASS */
595 .rss_hash_update = ixgbe_dev_rss_hash_update,
596 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
597 .filter_ctrl = ixgbe_dev_filter_ctrl,
598 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
599 .rxq_info_get = ixgbe_rxq_info_get,
600 .txq_info_get = ixgbe_txq_info_get,
601 .timesync_enable = ixgbe_timesync_enable,
602 .timesync_disable = ixgbe_timesync_disable,
603 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
604 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
605 .get_reg = ixgbe_get_regs,
606 .get_eeprom_length = ixgbe_get_eeprom_length,
607 .get_eeprom = ixgbe_get_eeprom,
608 .set_eeprom = ixgbe_set_eeprom,
609 .get_dcb_info = ixgbe_dev_get_dcb_info,
610 .timesync_adjust_time = ixgbe_timesync_adjust_time,
611 .timesync_read_time = ixgbe_timesync_read_time,
612 .timesync_write_time = ixgbe_timesync_write_time,
613 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
614 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
615 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
616 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
620 * dev_ops for virtual function, bare necessities for basic vf
621 * operation have been implemented
623 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
624 .dev_configure = ixgbevf_dev_configure,
625 .dev_start = ixgbevf_dev_start,
626 .dev_stop = ixgbevf_dev_stop,
627 .link_update = ixgbevf_dev_link_update,
628 .stats_get = ixgbevf_dev_stats_get,
629 .xstats_get = ixgbevf_dev_xstats_get,
630 .stats_reset = ixgbevf_dev_stats_reset,
631 .xstats_reset = ixgbevf_dev_stats_reset,
632 .xstats_get_names = ixgbevf_dev_xstats_get_names,
633 .dev_close = ixgbevf_dev_close,
634 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
635 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
636 .dev_infos_get = ixgbevf_dev_info_get,
637 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
638 .mtu_set = ixgbevf_dev_set_mtu,
639 .vlan_filter_set = ixgbevf_vlan_filter_set,
640 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
641 .vlan_offload_set = ixgbevf_vlan_offload_set,
642 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
643 .rx_queue_release = ixgbe_dev_rx_queue_release,
644 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
645 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
646 .tx_queue_release = ixgbe_dev_tx_queue_release,
647 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
648 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
649 .mac_addr_add = ixgbevf_add_mac_addr,
650 .mac_addr_remove = ixgbevf_remove_mac_addr,
651 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
652 .rxq_info_get = ixgbe_rxq_info_get,
653 .txq_info_get = ixgbe_txq_info_get,
654 .mac_addr_set = ixgbevf_set_default_mac_addr,
655 .get_reg = ixgbevf_get_regs,
656 .reta_update = ixgbe_dev_rss_reta_update,
657 .reta_query = ixgbe_dev_rss_reta_query,
658 .rss_hash_update = ixgbe_dev_rss_hash_update,
659 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
662 /* store statistics names and its offset in stats structure */
663 struct rte_ixgbe_xstats_name_off {
664 char name[RTE_ETH_XSTATS_NAME_SIZE];
668 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
669 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
670 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
671 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
672 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
673 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
674 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
675 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
676 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
677 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
678 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
679 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
680 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
681 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
682 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
683 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
685 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
687 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
688 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
689 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
690 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
691 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
692 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
693 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
694 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
695 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
696 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
697 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
698 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
699 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
700 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
701 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
702 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
703 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
705 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
707 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
708 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
709 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
710 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
712 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
714 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
716 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
718 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
720 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
722 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
725 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
726 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
727 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
729 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
730 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
731 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
732 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
733 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
735 {"rx_fcoe_no_direct_data_placement_ext_buff",
736 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
738 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
740 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
742 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
744 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
746 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
749 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
750 sizeof(rte_ixgbe_stats_strings[0]))
752 /* Per-queue statistics */
753 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
754 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
755 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
756 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
757 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
760 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
761 sizeof(rte_ixgbe_rxq_strings[0]))
762 #define IXGBE_NB_RXQ_PRIO_VALUES 8
764 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
765 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
766 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
767 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
771 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
772 sizeof(rte_ixgbe_txq_strings[0]))
773 #define IXGBE_NB_TXQ_PRIO_VALUES 8
775 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
776 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
779 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
780 sizeof(rte_ixgbevf_stats_strings[0]))
783 * Atomically reads the link status information from global
784 * structure rte_eth_dev.
787 * - Pointer to the structure rte_eth_dev to read from.
788 * - Pointer to the buffer to be saved with the link status.
791 * - On success, zero.
792 * - On failure, negative value.
795 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
796 struct rte_eth_link *link)
798 struct rte_eth_link *dst = link;
799 struct rte_eth_link *src = &(dev->data->dev_link);
801 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
802 *(uint64_t *)src) == 0)
809 * Atomically writes the link status information into global
810 * structure rte_eth_dev.
813 * - Pointer to the structure rte_eth_dev to read from.
814 * - Pointer to the buffer to be saved with the link status.
817 * - On success, zero.
818 * - On failure, negative value.
821 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
822 struct rte_eth_link *link)
824 struct rte_eth_link *dst = &(dev->data->dev_link);
825 struct rte_eth_link *src = link;
827 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
828 *(uint64_t *)src) == 0)
835 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
838 ixgbe_is_sfp(struct ixgbe_hw *hw)
840 switch (hw->phy.type) {
841 case ixgbe_phy_sfp_avago:
842 case ixgbe_phy_sfp_ftl:
843 case ixgbe_phy_sfp_intel:
844 case ixgbe_phy_sfp_unknown:
845 case ixgbe_phy_sfp_passive_tyco:
846 case ixgbe_phy_sfp_passive_unknown:
853 static inline int32_t
854 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
859 status = ixgbe_reset_hw(hw);
861 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
862 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
863 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
864 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
865 IXGBE_WRITE_FLUSH(hw);
871 ixgbe_enable_intr(struct rte_eth_dev *dev)
873 struct ixgbe_interrupt *intr =
874 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
875 struct ixgbe_hw *hw =
876 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
878 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
879 IXGBE_WRITE_FLUSH(hw);
883 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
886 ixgbe_disable_intr(struct ixgbe_hw *hw)
888 PMD_INIT_FUNC_TRACE();
890 if (hw->mac.type == ixgbe_mac_82598EB) {
891 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
893 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
894 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
895 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
897 IXGBE_WRITE_FLUSH(hw);
901 * This function resets queue statistics mapping registers.
902 * From Niantic datasheet, Initialization of Statistics section:
903 * "...if software requires the queue counters, the RQSMR and TQSM registers
904 * must be re-programmed following a device reset.
907 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
911 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
912 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
913 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
919 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
924 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
925 #define NB_QMAP_FIELDS_PER_QSM_REG 4
926 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
928 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
929 struct ixgbe_stat_mapping_registers *stat_mappings =
930 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
931 uint32_t qsmr_mask = 0;
932 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
936 if ((hw->mac.type != ixgbe_mac_82599EB) &&
937 (hw->mac.type != ixgbe_mac_X540) &&
938 (hw->mac.type != ixgbe_mac_X550) &&
939 (hw->mac.type != ixgbe_mac_X550EM_x) &&
940 (hw->mac.type != ixgbe_mac_X550EM_a))
943 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
944 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
947 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
948 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
949 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
952 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
954 /* Now clear any previous stat_idx set */
955 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
957 stat_mappings->tqsm[n] &= ~clearing_mask;
959 stat_mappings->rqsmr[n] &= ~clearing_mask;
961 q_map = (uint32_t)stat_idx;
962 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
963 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
965 stat_mappings->tqsm[n] |= qsmr_mask;
967 stat_mappings->rqsmr[n] |= qsmr_mask;
969 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
970 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
972 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
973 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
975 /* Now write the mapping in the appropriate register */
977 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
978 stat_mappings->rqsmr[n], n);
979 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
981 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
982 stat_mappings->tqsm[n], n);
983 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
989 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
991 struct ixgbe_stat_mapping_registers *stat_mappings =
992 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
993 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
996 /* write whatever was in stat mapping table to the NIC */
997 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
999 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1002 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1007 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1010 struct ixgbe_dcb_tc_config *tc;
1011 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1013 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1014 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1015 for (i = 0; i < dcb_max_tc; i++) {
1016 tc = &dcb_config->tc_config[i];
1017 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1018 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1019 (uint8_t)(100/dcb_max_tc + (i & 1));
1020 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1021 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1022 (uint8_t)(100/dcb_max_tc + (i & 1));
1023 tc->pfc = ixgbe_dcb_pfc_disabled;
1026 /* Initialize default user to priority mapping, UPx->TC0 */
1027 tc = &dcb_config->tc_config[0];
1028 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1029 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1030 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1031 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1032 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1034 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1035 dcb_config->pfc_mode_enable = false;
1036 dcb_config->vt_mode = true;
1037 dcb_config->round_robin_enable = false;
1038 /* support all DCB capabilities in 82599 */
1039 dcb_config->support.capabilities = 0xFF;
1041 /*we only support 4 Tcs for X540, X550 */
1042 if (hw->mac.type == ixgbe_mac_X540 ||
1043 hw->mac.type == ixgbe_mac_X550 ||
1044 hw->mac.type == ixgbe_mac_X550EM_x ||
1045 hw->mac.type == ixgbe_mac_X550EM_a) {
1046 dcb_config->num_tcs.pg_tcs = 4;
1047 dcb_config->num_tcs.pfc_tcs = 4;
1052 * Ensure that all locks are released before first NVM or PHY access
1055 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1060 * Phy lock should not fail in this early stage. If this is the case,
1061 * it is due to an improper exit of the application.
1062 * So force the release of the faulty lock. Release of common lock
1063 * is done automatically by swfw_sync function.
1065 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1066 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1067 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1069 ixgbe_release_swfw_semaphore(hw, mask);
1072 * These ones are more tricky since they are common to all ports; but
1073 * swfw_sync retries last long enough (1s) to be almost sure that if
1074 * lock can not be taken it is due to an improper lock of the
1077 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1078 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1079 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1081 ixgbe_release_swfw_semaphore(hw, mask);
1085 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1086 * It returns 0 on success.
1089 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1091 struct rte_pci_device *pci_dev;
1092 struct ixgbe_hw *hw =
1093 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1094 struct ixgbe_vfta *shadow_vfta =
1095 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1096 struct ixgbe_hwstrip *hwstrip =
1097 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1098 struct ixgbe_dcb_config *dcb_config =
1099 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1100 struct ixgbe_filter_info *filter_info =
1101 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1106 PMD_INIT_FUNC_TRACE();
1108 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1109 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1110 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1113 * For secondary processes, we don't initialise any further as primary
1114 * has already done this work. Only check we don't need a different
1115 * RX and TX function.
1117 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1118 struct ixgbe_tx_queue *txq;
1119 /* TX queue function in primary, set by last queue initialized
1120 * Tx queue may not initialized by primary process
1122 if (eth_dev->data->tx_queues) {
1123 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1124 ixgbe_set_tx_function(eth_dev, txq);
1126 /* Use default TX function if we get here */
1127 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1128 "Using default TX function.");
1131 ixgbe_set_rx_function(eth_dev);
1135 pci_dev = eth_dev->pci_dev;
1137 rte_eth_copy_pci_info(eth_dev, pci_dev);
1139 /* Vendor and Device ID need to be set before init of shared code */
1140 hw->device_id = pci_dev->id.device_id;
1141 hw->vendor_id = pci_dev->id.vendor_id;
1142 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1143 hw->allow_unsupported_sfp = 1;
1145 /* Initialize the shared code (base driver) */
1146 #ifdef RTE_NIC_BYPASS
1147 diag = ixgbe_bypass_init_shared_code(hw);
1149 diag = ixgbe_init_shared_code(hw);
1150 #endif /* RTE_NIC_BYPASS */
1152 if (diag != IXGBE_SUCCESS) {
1153 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1157 /* pick up the PCI bus settings for reporting later */
1158 ixgbe_get_bus_info(hw);
1160 /* Unlock any pending hardware semaphore */
1161 ixgbe_swfw_lock_reset(hw);
1163 /* Initialize DCB configuration*/
1164 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1165 ixgbe_dcb_init(hw, dcb_config);
1166 /* Get Hardware Flow Control setting */
1167 hw->fc.requested_mode = ixgbe_fc_full;
1168 hw->fc.current_mode = ixgbe_fc_full;
1169 hw->fc.pause_time = IXGBE_FC_PAUSE;
1170 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1171 hw->fc.low_water[i] = IXGBE_FC_LO;
1172 hw->fc.high_water[i] = IXGBE_FC_HI;
1174 hw->fc.send_xon = 1;
1176 /* Make sure we have a good EEPROM before we read from it */
1177 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1178 if (diag != IXGBE_SUCCESS) {
1179 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1183 #ifdef RTE_NIC_BYPASS
1184 diag = ixgbe_bypass_init_hw(hw);
1186 diag = ixgbe_init_hw(hw);
1187 #endif /* RTE_NIC_BYPASS */
1190 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1191 * is called too soon after the kernel driver unbinding/binding occurs.
1192 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1193 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1194 * also called. See ixgbe_identify_phy_82599(). The reason for the
1195 * failure is not known, and only occuts when virtualisation features
1196 * are disabled in the bios. A delay of 100ms was found to be enough by
1197 * trial-and-error, and is doubled to be safe.
1199 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1201 diag = ixgbe_init_hw(hw);
1204 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1205 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1206 "LOM. Please be aware there may be issues associated "
1207 "with your hardware.");
1208 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1209 "please contact your Intel or hardware representative "
1210 "who provided you with this hardware.");
1211 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1212 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1214 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1218 /* Reset the hw statistics */
1219 ixgbe_dev_stats_reset(eth_dev);
1221 /* disable interrupt */
1222 ixgbe_disable_intr(hw);
1224 /* reset mappings for queue statistics hw counters*/
1225 ixgbe_reset_qstat_mappings(hw);
1227 /* Allocate memory for storing MAC addresses */
1228 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1229 hw->mac.num_rar_entries, 0);
1230 if (eth_dev->data->mac_addrs == NULL) {
1232 "Failed to allocate %u bytes needed to store "
1234 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1237 /* Copy the permanent MAC address */
1238 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1239 ð_dev->data->mac_addrs[0]);
1241 /* Allocate memory for storing hash filter MAC addresses */
1242 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1243 IXGBE_VMDQ_NUM_UC_MAC, 0);
1244 if (eth_dev->data->hash_mac_addrs == NULL) {
1246 "Failed to allocate %d bytes needed to store MAC addresses",
1247 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1251 /* initialize the vfta */
1252 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1254 /* initialize the hw strip bitmap*/
1255 memset(hwstrip, 0, sizeof(*hwstrip));
1257 /* initialize PF if max_vfs not zero */
1258 ixgbe_pf_host_init(eth_dev);
1260 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1261 /* let hardware know driver is loaded */
1262 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1263 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1264 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1265 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1266 IXGBE_WRITE_FLUSH(hw);
1268 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1269 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1270 (int) hw->mac.type, (int) hw->phy.type,
1271 (int) hw->phy.sfp_type);
1273 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1274 (int) hw->mac.type, (int) hw->phy.type);
1276 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1277 eth_dev->data->port_id, pci_dev->id.vendor_id,
1278 pci_dev->id.device_id);
1280 rte_intr_callback_register(&pci_dev->intr_handle,
1281 ixgbe_dev_interrupt_handler,
1284 /* enable uio/vfio intr/eventfd mapping */
1285 rte_intr_enable(&pci_dev->intr_handle);
1287 /* enable support intr */
1288 ixgbe_enable_intr(eth_dev);
1290 /* initialize 5tuple filter list */
1291 TAILQ_INIT(&filter_info->fivetuple_list);
1292 memset(filter_info->fivetuple_mask, 0,
1293 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1299 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1301 struct rte_pci_device *pci_dev;
1302 struct ixgbe_hw *hw;
1304 PMD_INIT_FUNC_TRACE();
1306 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1309 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1310 pci_dev = eth_dev->pci_dev;
1312 if (hw->adapter_stopped == 0)
1313 ixgbe_dev_close(eth_dev);
1315 eth_dev->dev_ops = NULL;
1316 eth_dev->rx_pkt_burst = NULL;
1317 eth_dev->tx_pkt_burst = NULL;
1319 /* Unlock any pending hardware semaphore */
1320 ixgbe_swfw_lock_reset(hw);
1322 /* disable uio intr before callback unregister */
1323 rte_intr_disable(&(pci_dev->intr_handle));
1324 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1325 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1327 /* uninitialize PF if max_vfs not zero */
1328 ixgbe_pf_host_uninit(eth_dev);
1330 rte_free(eth_dev->data->mac_addrs);
1331 eth_dev->data->mac_addrs = NULL;
1333 rte_free(eth_dev->data->hash_mac_addrs);
1334 eth_dev->data->hash_mac_addrs = NULL;
1340 * Negotiate mailbox API version with the PF.
1341 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1342 * Then we try to negotiate starting with the most recent one.
1343 * If all negotiation attempts fail, then we will proceed with
1344 * the default one (ixgbe_mbox_api_10).
1347 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1351 /* start with highest supported, proceed down */
1352 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1359 i != RTE_DIM(sup_ver) &&
1360 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1366 generate_random_mac_addr(struct ether_addr *mac_addr)
1370 /* Set Organizationally Unique Identifier (OUI) prefix. */
1371 mac_addr->addr_bytes[0] = 0x00;
1372 mac_addr->addr_bytes[1] = 0x09;
1373 mac_addr->addr_bytes[2] = 0xC0;
1374 /* Force indication of locally assigned MAC address. */
1375 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1376 /* Generate the last 3 bytes of the MAC address with a random number. */
1377 random = rte_rand();
1378 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1382 * Virtual Function device init
1385 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1389 struct rte_pci_device *pci_dev;
1390 struct ixgbe_hw *hw =
1391 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1392 struct ixgbe_vfta *shadow_vfta =
1393 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1394 struct ixgbe_hwstrip *hwstrip =
1395 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1396 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1398 PMD_INIT_FUNC_TRACE();
1400 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1401 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1402 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1404 /* for secondary processes, we don't initialise any further as primary
1405 * has already done this work. Only check we don't need a different
1408 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1409 struct ixgbe_tx_queue *txq;
1410 /* TX queue function in primary, set by last queue initialized
1411 * Tx queue may not initialized by primary process
1413 if (eth_dev->data->tx_queues) {
1414 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1415 ixgbe_set_tx_function(eth_dev, txq);
1417 /* Use default TX function if we get here */
1418 PMD_INIT_LOG(NOTICE,
1419 "No TX queues configured yet. Using default TX function.");
1422 ixgbe_set_rx_function(eth_dev);
1427 pci_dev = eth_dev->pci_dev;
1429 rte_eth_copy_pci_info(eth_dev, pci_dev);
1431 hw->device_id = pci_dev->id.device_id;
1432 hw->vendor_id = pci_dev->id.vendor_id;
1433 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1435 /* initialize the vfta */
1436 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1438 /* initialize the hw strip bitmap*/
1439 memset(hwstrip, 0, sizeof(*hwstrip));
1441 /* Initialize the shared code (base driver) */
1442 diag = ixgbe_init_shared_code(hw);
1443 if (diag != IXGBE_SUCCESS) {
1444 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1448 /* init_mailbox_params */
1449 hw->mbx.ops.init_params(hw);
1451 /* Reset the hw statistics */
1452 ixgbevf_dev_stats_reset(eth_dev);
1454 /* Disable the interrupts for VF */
1455 ixgbevf_intr_disable(hw);
1457 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1458 diag = hw->mac.ops.reset_hw(hw);
1461 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1462 * the underlying PF driver has not assigned a MAC address to the VF.
1463 * In this case, assign a random MAC address.
1465 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1466 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1470 /* negotiate mailbox API version to use with the PF. */
1471 ixgbevf_negotiate_api(hw);
1473 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1474 ixgbevf_get_queues(hw, &tcs, &tc);
1476 /* Allocate memory for storing MAC addresses */
1477 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1478 hw->mac.num_rar_entries, 0);
1479 if (eth_dev->data->mac_addrs == NULL) {
1481 "Failed to allocate %u bytes needed to store "
1483 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1487 /* Generate a random MAC address, if none was assigned by PF. */
1488 if (is_zero_ether_addr(perm_addr)) {
1489 generate_random_mac_addr(perm_addr);
1490 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1492 rte_free(eth_dev->data->mac_addrs);
1493 eth_dev->data->mac_addrs = NULL;
1496 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1497 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1498 "%02x:%02x:%02x:%02x:%02x:%02x",
1499 perm_addr->addr_bytes[0],
1500 perm_addr->addr_bytes[1],
1501 perm_addr->addr_bytes[2],
1502 perm_addr->addr_bytes[3],
1503 perm_addr->addr_bytes[4],
1504 perm_addr->addr_bytes[5]);
1507 /* Copy the permanent MAC address */
1508 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1510 /* reset the hardware with the new settings */
1511 diag = hw->mac.ops.start_hw(hw);
1517 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1521 rte_intr_callback_register(&pci_dev->intr_handle,
1522 ixgbevf_dev_interrupt_handler,
1524 rte_intr_enable(&pci_dev->intr_handle);
1525 ixgbevf_intr_enable(hw);
1527 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1528 eth_dev->data->port_id, pci_dev->id.vendor_id,
1529 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1534 /* Virtual Function device uninit */
1537 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1539 struct ixgbe_hw *hw;
1540 struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1542 PMD_INIT_FUNC_TRACE();
1544 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1547 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1549 if (hw->adapter_stopped == 0)
1550 ixgbevf_dev_close(eth_dev);
1552 eth_dev->dev_ops = NULL;
1553 eth_dev->rx_pkt_burst = NULL;
1554 eth_dev->tx_pkt_burst = NULL;
1556 /* Disable the interrupts for VF */
1557 ixgbevf_intr_disable(hw);
1559 rte_free(eth_dev->data->mac_addrs);
1560 eth_dev->data->mac_addrs = NULL;
1562 rte_intr_disable(&pci_dev->intr_handle);
1563 rte_intr_callback_unregister(&pci_dev->intr_handle,
1564 ixgbevf_dev_interrupt_handler,
1570 static struct eth_driver rte_ixgbe_pmd = {
1572 .id_table = pci_id_ixgbe_map,
1573 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1574 RTE_PCI_DRV_DETACHABLE,
1575 .probe = rte_eth_dev_pci_probe,
1576 .remove = rte_eth_dev_pci_remove,
1578 .eth_dev_init = eth_ixgbe_dev_init,
1579 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1580 .dev_private_size = sizeof(struct ixgbe_adapter),
1584 * virtual function driver struct
1586 static struct eth_driver rte_ixgbevf_pmd = {
1588 .id_table = pci_id_ixgbevf_map,
1589 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1590 .probe = rte_eth_dev_pci_probe,
1591 .remove = rte_eth_dev_pci_remove,
1593 .eth_dev_init = eth_ixgbevf_dev_init,
1594 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1595 .dev_private_size = sizeof(struct ixgbe_adapter),
1599 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1601 struct ixgbe_hw *hw =
1602 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1603 struct ixgbe_vfta *shadow_vfta =
1604 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1609 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1610 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1611 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1616 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1618 /* update local VFTA copy */
1619 shadow_vfta->vfta[vid_idx] = vfta;
1625 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1628 ixgbe_vlan_hw_strip_enable(dev, queue);
1630 ixgbe_vlan_hw_strip_disable(dev, queue);
1634 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1635 enum rte_vlan_type vlan_type,
1638 struct ixgbe_hw *hw =
1639 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1644 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1645 qinq &= IXGBE_DMATXCTL_GDV;
1647 switch (vlan_type) {
1648 case ETH_VLAN_TYPE_INNER:
1650 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1651 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1652 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1653 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1654 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1655 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1656 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1659 PMD_DRV_LOG(ERR, "Inner type is not supported"
1663 case ETH_VLAN_TYPE_OUTER:
1665 /* Only the high 16-bits is valid */
1666 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1667 IXGBE_EXVET_VET_EXT_SHIFT);
1669 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1670 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1671 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1672 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1673 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1674 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1675 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1681 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1689 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1691 struct ixgbe_hw *hw =
1692 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1695 PMD_INIT_FUNC_TRACE();
1697 /* Filter Table Disable */
1698 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1699 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1701 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1705 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1707 struct ixgbe_hw *hw =
1708 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709 struct ixgbe_vfta *shadow_vfta =
1710 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1714 PMD_INIT_FUNC_TRACE();
1716 /* Filter Table Enable */
1717 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1718 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1719 vlnctrl |= IXGBE_VLNCTRL_VFE;
1721 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1723 /* write whatever is in local vfta copy */
1724 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1725 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1729 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1731 struct ixgbe_hwstrip *hwstrip =
1732 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1733 struct ixgbe_rx_queue *rxq;
1735 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1739 IXGBE_SET_HWSTRIP(hwstrip, queue);
1741 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1743 if (queue >= dev->data->nb_rx_queues)
1746 rxq = dev->data->rx_queues[queue];
1749 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1751 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1755 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1757 struct ixgbe_hw *hw =
1758 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1761 PMD_INIT_FUNC_TRACE();
1763 if (hw->mac.type == ixgbe_mac_82598EB) {
1764 /* No queue level support */
1765 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1769 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1770 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1771 ctrl &= ~IXGBE_RXDCTL_VME;
1772 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1774 /* record those setting for HW strip per queue */
1775 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1779 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1781 struct ixgbe_hw *hw =
1782 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1785 PMD_INIT_FUNC_TRACE();
1787 if (hw->mac.type == ixgbe_mac_82598EB) {
1788 /* No queue level supported */
1789 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1793 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1794 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1795 ctrl |= IXGBE_RXDCTL_VME;
1796 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1798 /* record those setting for HW strip per queue */
1799 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1803 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1805 struct ixgbe_hw *hw =
1806 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1809 struct ixgbe_rx_queue *rxq;
1811 PMD_INIT_FUNC_TRACE();
1813 if (hw->mac.type == ixgbe_mac_82598EB) {
1814 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1815 ctrl &= ~IXGBE_VLNCTRL_VME;
1816 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1818 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1819 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1820 rxq = dev->data->rx_queues[i];
1821 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1822 ctrl &= ~IXGBE_RXDCTL_VME;
1823 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1825 /* record those setting for HW strip per queue */
1826 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1832 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1834 struct ixgbe_hw *hw =
1835 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1838 struct ixgbe_rx_queue *rxq;
1840 PMD_INIT_FUNC_TRACE();
1842 if (hw->mac.type == ixgbe_mac_82598EB) {
1843 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1844 ctrl |= IXGBE_VLNCTRL_VME;
1845 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1847 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1848 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1849 rxq = dev->data->rx_queues[i];
1850 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1851 ctrl |= IXGBE_RXDCTL_VME;
1852 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1854 /* record those setting for HW strip per queue */
1855 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1861 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1863 struct ixgbe_hw *hw =
1864 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1867 PMD_INIT_FUNC_TRACE();
1869 /* DMATXCTRL: Geric Double VLAN Disable */
1870 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1871 ctrl &= ~IXGBE_DMATXCTL_GDV;
1872 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1874 /* CTRL_EXT: Global Double VLAN Disable */
1875 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1876 ctrl &= ~IXGBE_EXTENDED_VLAN;
1877 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1882 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1884 struct ixgbe_hw *hw =
1885 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1888 PMD_INIT_FUNC_TRACE();
1890 /* DMATXCTRL: Geric Double VLAN Enable */
1891 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1892 ctrl |= IXGBE_DMATXCTL_GDV;
1893 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1895 /* CTRL_EXT: Global Double VLAN Enable */
1896 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1897 ctrl |= IXGBE_EXTENDED_VLAN;
1898 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1900 /* Clear pooling mode of PFVTCTL. It's required by X550. */
1901 if (hw->mac.type == ixgbe_mac_X550 ||
1902 hw->mac.type == ixgbe_mac_X550EM_x ||
1903 hw->mac.type == ixgbe_mac_X550EM_a) {
1904 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1905 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1906 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1910 * VET EXT field in the EXVET register = 0x8100 by default
1911 * So no need to change. Same to VT field of DMATXCTL register
1916 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1918 if (mask & ETH_VLAN_STRIP_MASK) {
1919 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1920 ixgbe_vlan_hw_strip_enable_all(dev);
1922 ixgbe_vlan_hw_strip_disable_all(dev);
1925 if (mask & ETH_VLAN_FILTER_MASK) {
1926 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1927 ixgbe_vlan_hw_filter_enable(dev);
1929 ixgbe_vlan_hw_filter_disable(dev);
1932 if (mask & ETH_VLAN_EXTEND_MASK) {
1933 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1934 ixgbe_vlan_hw_extend_enable(dev);
1936 ixgbe_vlan_hw_extend_disable(dev);
1941 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1943 struct ixgbe_hw *hw =
1944 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1945 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1946 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1948 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1949 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1953 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1958 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1961 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1967 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1968 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1969 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1970 dev->pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1975 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1977 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1978 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1979 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1980 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1982 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1983 /* check multi-queue mode */
1984 switch (dev_conf->rxmode.mq_mode) {
1985 case ETH_MQ_RX_VMDQ_DCB:
1986 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1988 case ETH_MQ_RX_VMDQ_DCB_RSS:
1989 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1990 PMD_INIT_LOG(ERR, "SRIOV active,"
1991 " unsupported mq_mode rx %d.",
1992 dev_conf->rxmode.mq_mode);
1995 case ETH_MQ_RX_VMDQ_RSS:
1996 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1997 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1998 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1999 PMD_INIT_LOG(ERR, "SRIOV is active,"
2000 " invalid queue number"
2001 " for VMDQ RSS, allowed"
2002 " value are 1, 2 or 4.");
2006 case ETH_MQ_RX_VMDQ_ONLY:
2007 case ETH_MQ_RX_NONE:
2008 /* if nothing mq mode configure, use default scheme */
2009 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2011 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2012 /* SRIOV only works in VMDq enable mode */
2013 PMD_INIT_LOG(ERR, "SRIOV is active,"
2014 " wrong mq_mode rx %d.",
2015 dev_conf->rxmode.mq_mode);
2019 switch (dev_conf->txmode.mq_mode) {
2020 case ETH_MQ_TX_VMDQ_DCB:
2021 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2022 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2024 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2025 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2029 /* check valid queue number */
2030 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2031 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2032 PMD_INIT_LOG(ERR, "SRIOV is active,"
2033 " nb_rx_q=%d nb_tx_q=%d queue number"
2034 " must be less than or equal to %d.",
2036 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2040 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2041 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2045 /* check configuration for vmdb+dcb mode */
2046 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2047 const struct rte_eth_vmdq_dcb_conf *conf;
2049 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2050 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2051 IXGBE_VMDQ_DCB_NB_QUEUES);
2054 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2055 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2056 conf->nb_queue_pools == ETH_32_POOLS)) {
2057 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2058 " nb_queue_pools must be %d or %d.",
2059 ETH_16_POOLS, ETH_32_POOLS);
2063 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2064 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2066 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2067 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2068 IXGBE_VMDQ_DCB_NB_QUEUES);
2071 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2072 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2073 conf->nb_queue_pools == ETH_32_POOLS)) {
2074 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2075 " nb_queue_pools != %d and"
2076 " nb_queue_pools != %d.",
2077 ETH_16_POOLS, ETH_32_POOLS);
2082 /* For DCB mode check our configuration before we go further */
2083 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2084 const struct rte_eth_dcb_rx_conf *conf;
2086 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2087 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2088 IXGBE_DCB_NB_QUEUES);
2091 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2092 if (!(conf->nb_tcs == ETH_4_TCS ||
2093 conf->nb_tcs == ETH_8_TCS)) {
2094 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2095 " and nb_tcs != %d.",
2096 ETH_4_TCS, ETH_8_TCS);
2101 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2102 const struct rte_eth_dcb_tx_conf *conf;
2104 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2105 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2106 IXGBE_DCB_NB_QUEUES);
2109 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2110 if (!(conf->nb_tcs == ETH_4_TCS ||
2111 conf->nb_tcs == ETH_8_TCS)) {
2112 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2113 " and nb_tcs != %d.",
2114 ETH_4_TCS, ETH_8_TCS);
2120 * When DCB/VT is off, maximum number of queues changes,
2121 * except for 82598EB, which remains constant.
2123 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2124 hw->mac.type != ixgbe_mac_82598EB) {
2125 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2127 "Neither VT nor DCB are enabled, "
2129 IXGBE_NONE_MODE_TX_NB_QUEUES);
2138 ixgbe_dev_configure(struct rte_eth_dev *dev)
2140 struct ixgbe_interrupt *intr =
2141 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2142 struct ixgbe_adapter *adapter =
2143 (struct ixgbe_adapter *)dev->data->dev_private;
2146 PMD_INIT_FUNC_TRACE();
2147 /* multipe queue mode checking */
2148 ret = ixgbe_check_mq_mode(dev);
2150 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2155 /* set flag to update link status after init */
2156 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2159 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2160 * allocation or vector Rx preconditions we will reset it.
2162 adapter->rx_bulk_alloc_allowed = true;
2163 adapter->rx_vec_allowed = true;
2169 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2171 struct ixgbe_hw *hw =
2172 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173 struct ixgbe_interrupt *intr =
2174 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2177 /* only set up it on X550EM_X */
2178 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2179 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2180 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2181 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2182 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2183 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2188 * Configure device link speed and setup link.
2189 * It returns 0 on success.
2192 ixgbe_dev_start(struct rte_eth_dev *dev)
2194 struct ixgbe_hw *hw =
2195 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2196 struct ixgbe_vf_info *vfinfo =
2197 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2198 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2199 uint32_t intr_vector = 0;
2200 int err, link_up = 0, negotiate = 0;
2205 uint32_t *link_speeds;
2207 PMD_INIT_FUNC_TRACE();
2209 /* IXGBE devices don't support:
2210 * - half duplex (checked afterwards for valid speeds)
2211 * - fixed speed: TODO implement
2213 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2214 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2215 dev->data->port_id);
2219 /* disable uio/vfio intr/eventfd mapping */
2220 rte_intr_disable(intr_handle);
2223 hw->adapter_stopped = 0;
2224 ixgbe_stop_adapter(hw);
2226 /* reinitialize adapter
2227 * this calls reset and start
2229 status = ixgbe_pf_reset_hw(hw);
2232 hw->mac.ops.start_hw(hw);
2233 hw->mac.get_link_status = true;
2235 /* configure PF module if SRIOV enabled */
2236 ixgbe_pf_host_configure(dev);
2238 ixgbe_dev_phy_intr_setup(dev);
2240 /* check and configure queue intr-vector mapping */
2241 if ((rte_intr_cap_multiple(intr_handle) ||
2242 !RTE_ETH_DEV_SRIOV(dev).active) &&
2243 dev->data->dev_conf.intr_conf.rxq != 0) {
2244 intr_vector = dev->data->nb_rx_queues;
2245 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2246 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2247 IXGBE_MAX_INTR_QUEUE_NUM);
2250 if (rte_intr_efd_enable(intr_handle, intr_vector))
2254 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2255 intr_handle->intr_vec =
2256 rte_zmalloc("intr_vec",
2257 dev->data->nb_rx_queues * sizeof(int), 0);
2258 if (intr_handle->intr_vec == NULL) {
2259 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2260 " intr_vec\n", dev->data->nb_rx_queues);
2265 /* confiugre msix for sleep until rx interrupt */
2266 ixgbe_configure_msix(dev);
2268 /* initialize transmission unit */
2269 ixgbe_dev_tx_init(dev);
2271 /* This can fail when allocating mbufs for descriptor rings */
2272 err = ixgbe_dev_rx_init(dev);
2274 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2278 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2279 ETH_VLAN_EXTEND_MASK;
2280 ixgbe_vlan_offload_set(dev, mask);
2282 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2283 /* Enable vlan filtering for VMDq */
2284 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2287 /* Configure DCB hw */
2288 ixgbe_configure_dcb(dev);
2290 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2291 err = ixgbe_fdir_configure(dev);
2296 /* Restore vf rate limit */
2297 if (vfinfo != NULL) {
2298 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2299 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2300 if (vfinfo[vf].tx_rate[idx] != 0)
2301 ixgbe_set_vf_rate_limit(dev, vf,
2302 vfinfo[vf].tx_rate[idx],
2306 ixgbe_restore_statistics_mapping(dev);
2308 err = ixgbe_dev_rxtx_start(dev);
2310 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2314 /* Skip link setup if loopback mode is enabled for 82599. */
2315 if (hw->mac.type == ixgbe_mac_82599EB &&
2316 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2317 goto skip_link_setup;
2319 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2320 err = hw->mac.ops.setup_sfp(hw);
2325 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2326 /* Turn on the copper */
2327 ixgbe_set_phy_power(hw, true);
2329 /* Turn on the laser */
2330 ixgbe_enable_tx_laser(hw);
2333 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2336 dev->data->dev_link.link_status = link_up;
2338 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2342 link_speeds = &dev->data->dev_conf.link_speeds;
2343 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2344 ETH_LINK_SPEED_10G)) {
2345 PMD_INIT_LOG(ERR, "Invalid link setting");
2350 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2351 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2352 IXGBE_LINK_SPEED_82599_AUTONEG :
2353 IXGBE_LINK_SPEED_82598_AUTONEG;
2355 if (*link_speeds & ETH_LINK_SPEED_10G)
2356 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2357 if (*link_speeds & ETH_LINK_SPEED_1G)
2358 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2359 if (*link_speeds & ETH_LINK_SPEED_100M)
2360 speed |= IXGBE_LINK_SPEED_100_FULL;
2363 err = ixgbe_setup_link(hw, speed, link_up);
2369 if (rte_intr_allow_others(intr_handle)) {
2370 /* check if lsc interrupt is enabled */
2371 if (dev->data->dev_conf.intr_conf.lsc != 0)
2372 ixgbe_dev_lsc_interrupt_setup(dev);
2374 rte_intr_callback_unregister(intr_handle,
2375 ixgbe_dev_interrupt_handler,
2377 if (dev->data->dev_conf.intr_conf.lsc != 0)
2378 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2379 " no intr multiplex\n");
2382 /* check if rxq interrupt is enabled */
2383 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2384 rte_intr_dp_is_en(intr_handle))
2385 ixgbe_dev_rxq_interrupt_setup(dev);
2387 /* enable uio/vfio intr/eventfd mapping */
2388 rte_intr_enable(intr_handle);
2390 /* resume enabled intr since hw reset */
2391 ixgbe_enable_intr(dev);
2396 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2397 ixgbe_dev_clear_queues(dev);
2402 * Stop device: disable rx and tx functions to allow for reconfiguring.
2405 ixgbe_dev_stop(struct rte_eth_dev *dev)
2407 struct rte_eth_link link;
2408 struct ixgbe_hw *hw =
2409 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2410 struct ixgbe_vf_info *vfinfo =
2411 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2412 struct ixgbe_filter_info *filter_info =
2413 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2414 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2415 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2418 PMD_INIT_FUNC_TRACE();
2420 /* disable interrupts */
2421 ixgbe_disable_intr(hw);
2424 ixgbe_pf_reset_hw(hw);
2425 hw->adapter_stopped = 0;
2428 ixgbe_stop_adapter(hw);
2430 for (vf = 0; vfinfo != NULL &&
2431 vf < dev->pci_dev->max_vfs; vf++)
2432 vfinfo[vf].clear_to_send = false;
2434 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2435 /* Turn off the copper */
2436 ixgbe_set_phy_power(hw, false);
2438 /* Turn off the laser */
2439 ixgbe_disable_tx_laser(hw);
2442 ixgbe_dev_clear_queues(dev);
2444 /* Clear stored conf */
2445 dev->data->scattered_rx = 0;
2448 /* Clear recorded link status */
2449 memset(&link, 0, sizeof(link));
2450 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2452 /* Remove all ntuple filters of the device */
2453 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2454 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2455 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2456 TAILQ_REMOVE(&filter_info->fivetuple_list,
2460 memset(filter_info->fivetuple_mask, 0,
2461 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2463 if (!rte_intr_allow_others(intr_handle))
2464 /* resume to the default handler */
2465 rte_intr_callback_register(intr_handle,
2466 ixgbe_dev_interrupt_handler,
2469 /* Clean datapath event and queue/vec mapping */
2470 rte_intr_efd_disable(intr_handle);
2471 if (intr_handle->intr_vec != NULL) {
2472 rte_free(intr_handle->intr_vec);
2473 intr_handle->intr_vec = NULL;
2478 * Set device link up: enable tx.
2481 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2483 struct ixgbe_hw *hw =
2484 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2485 if (hw->mac.type == ixgbe_mac_82599EB) {
2486 #ifdef RTE_NIC_BYPASS
2487 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2488 /* Not suported in bypass mode */
2489 PMD_INIT_LOG(ERR, "Set link up is not supported "
2490 "by device id 0x%x", hw->device_id);
2496 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2497 /* Turn on the copper */
2498 ixgbe_set_phy_power(hw, true);
2500 /* Turn on the laser */
2501 ixgbe_enable_tx_laser(hw);
2508 * Set device link down: disable tx.
2511 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2513 struct ixgbe_hw *hw =
2514 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2515 if (hw->mac.type == ixgbe_mac_82599EB) {
2516 #ifdef RTE_NIC_BYPASS
2517 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2518 /* Not suported in bypass mode */
2519 PMD_INIT_LOG(ERR, "Set link down is not supported "
2520 "by device id 0x%x", hw->device_id);
2526 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2527 /* Turn off the copper */
2528 ixgbe_set_phy_power(hw, false);
2530 /* Turn off the laser */
2531 ixgbe_disable_tx_laser(hw);
2538 * Reest and stop device.
2541 ixgbe_dev_close(struct rte_eth_dev *dev)
2543 struct ixgbe_hw *hw =
2544 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2546 PMD_INIT_FUNC_TRACE();
2548 ixgbe_pf_reset_hw(hw);
2550 ixgbe_dev_stop(dev);
2551 hw->adapter_stopped = 1;
2553 ixgbe_dev_free_queues(dev);
2555 ixgbe_disable_pcie_master(hw);
2557 /* reprogram the RAR[0] in case user changed it. */
2558 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2562 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2563 struct ixgbe_hw_stats *hw_stats,
2564 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2565 uint64_t *total_qprc, uint64_t *total_qprdc)
2567 uint32_t bprc, lxon, lxoff, total;
2568 uint32_t delta_gprc = 0;
2570 /* Workaround for RX byte count not including CRC bytes when CRC
2571 + * strip is enabled. CRC bytes are removed from counters when crc_strip
2574 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2575 IXGBE_HLREG0_RXCRCSTRP);
2577 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2578 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2579 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2580 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2582 for (i = 0; i < 8; i++) {
2583 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2585 /* global total per queue */
2586 hw_stats->mpc[i] += mp;
2587 /* Running comprehensive total for stats display */
2588 *total_missed_rx += hw_stats->mpc[i];
2589 if (hw->mac.type == ixgbe_mac_82598EB) {
2590 hw_stats->rnbc[i] +=
2591 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2592 hw_stats->pxonrxc[i] +=
2593 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2594 hw_stats->pxoffrxc[i] +=
2595 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2597 hw_stats->pxonrxc[i] +=
2598 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2599 hw_stats->pxoffrxc[i] +=
2600 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2601 hw_stats->pxon2offc[i] +=
2602 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2604 hw_stats->pxontxc[i] +=
2605 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2606 hw_stats->pxofftxc[i] +=
2607 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2609 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2610 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2611 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2612 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2614 delta_gprc += delta_qprc;
2616 hw_stats->qprc[i] += delta_qprc;
2617 hw_stats->qptc[i] += delta_qptc;
2619 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2620 hw_stats->qbrc[i] +=
2621 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2623 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2625 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2626 hw_stats->qbtc[i] +=
2627 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2629 hw_stats->qprdc[i] += delta_qprdc;
2630 *total_qprdc += hw_stats->qprdc[i];
2632 *total_qprc += hw_stats->qprc[i];
2633 *total_qbrc += hw_stats->qbrc[i];
2635 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2636 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2637 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2640 * An errata states that gprc actually counts good + missed packets:
2641 * Workaround to set gprc to summated queue packet receives
2643 hw_stats->gprc = *total_qprc;
2645 if (hw->mac.type != ixgbe_mac_82598EB) {
2646 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2647 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2648 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2649 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2650 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2651 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2652 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2653 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2655 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2656 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2657 /* 82598 only has a counter in the high register */
2658 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2659 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2660 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2662 uint64_t old_tpr = hw_stats->tpr;
2664 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2665 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2668 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2670 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2671 hw_stats->gptc += delta_gptc;
2672 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2673 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2676 * Workaround: mprc hardware is incorrectly counting
2677 * broadcasts, so for now we subtract those.
2679 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2680 hw_stats->bprc += bprc;
2681 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2682 if (hw->mac.type == ixgbe_mac_82598EB)
2683 hw_stats->mprc -= bprc;
2685 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2686 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2687 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2688 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2689 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2690 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2692 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2693 hw_stats->lxontxc += lxon;
2694 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2695 hw_stats->lxofftxc += lxoff;
2696 total = lxon + lxoff;
2698 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2699 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2700 hw_stats->gptc -= total;
2701 hw_stats->mptc -= total;
2702 hw_stats->ptc64 -= total;
2703 hw_stats->gotc -= total * ETHER_MIN_LEN;
2705 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2706 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2707 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2708 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2709 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2710 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2711 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2712 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2713 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2714 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2715 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2716 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2717 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2718 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2719 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2720 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2721 /* Only read FCOE on 82599 */
2722 if (hw->mac.type != ixgbe_mac_82598EB) {
2723 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2724 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2725 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2726 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2727 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2730 /* Flow Director Stats registers */
2731 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2732 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2736 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2739 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2741 struct ixgbe_hw *hw =
2742 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2743 struct ixgbe_hw_stats *hw_stats =
2744 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2745 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2748 total_missed_rx = 0;
2753 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2754 &total_qprc, &total_qprdc);
2759 /* Fill out the rte_eth_stats statistics structure */
2760 stats->ipackets = total_qprc;
2761 stats->ibytes = total_qbrc;
2762 stats->opackets = hw_stats->gptc;
2763 stats->obytes = hw_stats->gotc;
2765 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2766 stats->q_ipackets[i] = hw_stats->qprc[i];
2767 stats->q_opackets[i] = hw_stats->qptc[i];
2768 stats->q_ibytes[i] = hw_stats->qbrc[i];
2769 stats->q_obytes[i] = hw_stats->qbtc[i];
2770 stats->q_errors[i] = hw_stats->qprdc[i];
2774 stats->imissed = total_missed_rx;
2775 stats->ierrors = hw_stats->crcerrs +
2791 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2793 struct ixgbe_hw_stats *stats =
2794 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2796 /* HW registers are cleared on read */
2797 ixgbe_dev_stats_get(dev, NULL);
2799 /* Reset software totals */
2800 memset(stats, 0, sizeof(*stats));
2803 /* This function calculates the number of xstats based on the current config */
2805 ixgbe_xstats_calc_num(void) {
2806 return IXGBE_NB_HW_STATS +
2807 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2808 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2811 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2812 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2814 const unsigned cnt_stats = ixgbe_xstats_calc_num();
2815 unsigned stat, i, count;
2817 if (xstats_names != NULL) {
2820 /* Note: limit >= cnt_stats checked upstream
2821 * in rte_eth_xstats_names()
2824 /* Extended stats from ixgbe_hw_stats */
2825 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2826 snprintf(xstats_names[count].name,
2827 sizeof(xstats_names[count].name),
2829 rte_ixgbe_stats_strings[i].name);
2833 /* RX Priority Stats */
2834 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2835 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2836 snprintf(xstats_names[count].name,
2837 sizeof(xstats_names[count].name),
2838 "rx_priority%u_%s", i,
2839 rte_ixgbe_rxq_strings[stat].name);
2844 /* TX Priority Stats */
2845 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2846 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2847 snprintf(xstats_names[count].name,
2848 sizeof(xstats_names[count].name),
2849 "tx_priority%u_%s", i,
2850 rte_ixgbe_txq_strings[stat].name);
2858 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2859 struct rte_eth_xstat_name *xstats_names, unsigned limit)
2863 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2866 if (xstats_names != NULL)
2867 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2868 snprintf(xstats_names[i].name,
2869 sizeof(xstats_names[i].name),
2870 "%s", rte_ixgbevf_stats_strings[i].name);
2871 return IXGBEVF_NB_XSTATS;
2875 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2878 struct ixgbe_hw *hw =
2879 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2880 struct ixgbe_hw_stats *hw_stats =
2881 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2882 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2883 unsigned i, stat, count = 0;
2885 count = ixgbe_xstats_calc_num();
2890 total_missed_rx = 0;
2895 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2896 &total_qprc, &total_qprdc);
2898 /* If this is a reset xstats is NULL, and we have cleared the
2899 * registers by reading them.
2904 /* Extended stats from ixgbe_hw_stats */
2906 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2907 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2908 rte_ixgbe_stats_strings[i].offset);
2909 xstats[count].id = count;
2913 /* RX Priority Stats */
2914 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2915 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2916 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2917 rte_ixgbe_rxq_strings[stat].offset +
2918 (sizeof(uint64_t) * i));
2919 xstats[count].id = count;
2924 /* TX Priority Stats */
2925 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2926 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2927 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2928 rte_ixgbe_txq_strings[stat].offset +
2929 (sizeof(uint64_t) * i));
2930 xstats[count].id = count;
2938 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2940 struct ixgbe_hw_stats *stats =
2941 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2943 unsigned count = ixgbe_xstats_calc_num();
2945 /* HW registers are cleared on read */
2946 ixgbe_dev_xstats_get(dev, NULL, count);
2948 /* Reset software totals */
2949 memset(stats, 0, sizeof(*stats));
2953 ixgbevf_update_stats(struct rte_eth_dev *dev)
2955 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2956 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2957 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2959 /* Good Rx packet, include VF loopback */
2960 UPDATE_VF_STAT(IXGBE_VFGPRC,
2961 hw_stats->last_vfgprc, hw_stats->vfgprc);
2963 /* Good Rx octets, include VF loopback */
2964 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2965 hw_stats->last_vfgorc, hw_stats->vfgorc);
2967 /* Good Tx packet, include VF loopback */
2968 UPDATE_VF_STAT(IXGBE_VFGPTC,
2969 hw_stats->last_vfgptc, hw_stats->vfgptc);
2971 /* Good Tx octets, include VF loopback */
2972 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2973 hw_stats->last_vfgotc, hw_stats->vfgotc);
2975 /* Rx Multicst Packet */
2976 UPDATE_VF_STAT(IXGBE_VFMPRC,
2977 hw_stats->last_vfmprc, hw_stats->vfmprc);
2981 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2984 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2985 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2988 if (n < IXGBEVF_NB_XSTATS)
2989 return IXGBEVF_NB_XSTATS;
2991 ixgbevf_update_stats(dev);
2996 /* Extended stats */
2997 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2999 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3000 rte_ixgbevf_stats_strings[i].offset);
3003 return IXGBEVF_NB_XSTATS;
3007 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3009 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3010 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3012 ixgbevf_update_stats(dev);
3017 stats->ipackets = hw_stats->vfgprc;
3018 stats->ibytes = hw_stats->vfgorc;
3019 stats->opackets = hw_stats->vfgptc;
3020 stats->obytes = hw_stats->vfgotc;
3024 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3026 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3027 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3029 /* Sync HW register to the last stats */
3030 ixgbevf_dev_stats_get(dev, NULL);
3032 /* reset HW current stats*/
3033 hw_stats->vfgprc = 0;
3034 hw_stats->vfgorc = 0;
3035 hw_stats->vfgptc = 0;
3036 hw_stats->vfgotc = 0;
3040 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3042 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3043 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3045 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3046 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3047 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3049 * When DCB/VT is off, maximum number of queues changes,
3050 * except for 82598EB, which remains constant.
3052 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3053 hw->mac.type != ixgbe_mac_82598EB)
3054 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3056 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3057 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3058 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3059 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3060 dev_info->max_vfs = dev->pci_dev->max_vfs;
3061 if (hw->mac.type == ixgbe_mac_82598EB)
3062 dev_info->max_vmdq_pools = ETH_16_POOLS;
3064 dev_info->max_vmdq_pools = ETH_64_POOLS;
3065 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3066 dev_info->rx_offload_capa =
3067 DEV_RX_OFFLOAD_VLAN_STRIP |
3068 DEV_RX_OFFLOAD_IPV4_CKSUM |
3069 DEV_RX_OFFLOAD_UDP_CKSUM |
3070 DEV_RX_OFFLOAD_TCP_CKSUM;
3073 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3076 if ((hw->mac.type == ixgbe_mac_82599EB ||
3077 hw->mac.type == ixgbe_mac_X540) &&
3078 !RTE_ETH_DEV_SRIOV(dev).active)
3079 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3081 if (hw->mac.type == ixgbe_mac_X550 ||
3082 hw->mac.type == ixgbe_mac_X550EM_x ||
3083 hw->mac.type == ixgbe_mac_X550EM_a)
3084 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3086 dev_info->tx_offload_capa =
3087 DEV_TX_OFFLOAD_VLAN_INSERT |
3088 DEV_TX_OFFLOAD_IPV4_CKSUM |
3089 DEV_TX_OFFLOAD_UDP_CKSUM |
3090 DEV_TX_OFFLOAD_TCP_CKSUM |
3091 DEV_TX_OFFLOAD_SCTP_CKSUM |
3092 DEV_TX_OFFLOAD_TCP_TSO;
3094 if (hw->mac.type == ixgbe_mac_X550 ||
3095 hw->mac.type == ixgbe_mac_X550EM_x ||
3096 hw->mac.type == ixgbe_mac_X550EM_a)
3097 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3099 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3101 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3102 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3103 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3105 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3109 dev_info->default_txconf = (struct rte_eth_txconf) {
3111 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3112 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3113 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3115 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3116 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3117 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3118 ETH_TXQ_FLAGS_NOOFFLOADS,
3121 dev_info->rx_desc_lim = rx_desc_lim;
3122 dev_info->tx_desc_lim = tx_desc_lim;
3124 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3125 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3126 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3128 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3129 if (hw->mac.type == ixgbe_mac_X540 ||
3130 hw->mac.type == ixgbe_mac_X540_vf ||
3131 hw->mac.type == ixgbe_mac_X550 ||
3132 hw->mac.type == ixgbe_mac_X550_vf) {
3133 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3137 static const uint32_t *
3138 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3140 static const uint32_t ptypes[] = {
3141 /* For non-vec functions,
3142 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3143 * for vec functions,
3144 * refers to _recv_raw_pkts_vec().
3148 RTE_PTYPE_L3_IPV4_EXT,
3150 RTE_PTYPE_L3_IPV6_EXT,
3154 RTE_PTYPE_TUNNEL_IP,
3155 RTE_PTYPE_INNER_L3_IPV6,
3156 RTE_PTYPE_INNER_L3_IPV6_EXT,
3157 RTE_PTYPE_INNER_L4_TCP,
3158 RTE_PTYPE_INNER_L4_UDP,
3162 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3163 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3164 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3165 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3171 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3172 struct rte_eth_dev_info *dev_info)
3174 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3176 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3177 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3178 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3179 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3180 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3181 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3182 dev_info->max_vfs = dev->pci_dev->max_vfs;
3183 if (hw->mac.type == ixgbe_mac_82598EB)
3184 dev_info->max_vmdq_pools = ETH_16_POOLS;
3186 dev_info->max_vmdq_pools = ETH_64_POOLS;
3187 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3188 DEV_RX_OFFLOAD_IPV4_CKSUM |
3189 DEV_RX_OFFLOAD_UDP_CKSUM |
3190 DEV_RX_OFFLOAD_TCP_CKSUM;
3191 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3192 DEV_TX_OFFLOAD_IPV4_CKSUM |
3193 DEV_TX_OFFLOAD_UDP_CKSUM |
3194 DEV_TX_OFFLOAD_TCP_CKSUM |
3195 DEV_TX_OFFLOAD_SCTP_CKSUM |
3196 DEV_TX_OFFLOAD_TCP_TSO;
3198 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3200 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3201 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3202 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3204 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3208 dev_info->default_txconf = (struct rte_eth_txconf) {
3210 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3211 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3212 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3214 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3215 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3216 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3217 ETH_TXQ_FLAGS_NOOFFLOADS,
3220 dev_info->rx_desc_lim = rx_desc_lim;
3221 dev_info->tx_desc_lim = tx_desc_lim;
3225 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3226 int *link_up, int wait_to_complete)
3229 * for a quick link status checking, wait_to_compelet == 0,
3230 * skip PF link status checking
3232 bool no_pflink_check = wait_to_complete == 0;
3233 struct ixgbe_mbx_info *mbx = &hw->mbx;
3234 struct ixgbe_mac_info *mac = &hw->mac;
3235 uint32_t links_reg, in_msg;
3238 /* If we were hit with a reset drop the link */
3239 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3240 mac->get_link_status = true;
3242 if (!mac->get_link_status)
3245 /* if link status is down no point in checking to see if pf is up */
3246 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3247 if (!(links_reg & IXGBE_LINKS_UP))
3250 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3251 * before the link status is correct
3253 if (mac->type == ixgbe_mac_82599_vf) {
3256 for (i = 0; i < 5; i++) {
3258 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3260 if (!(links_reg & IXGBE_LINKS_UP))
3265 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3266 case IXGBE_LINKS_SPEED_10G_82599:
3267 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3268 if (hw->mac.type >= ixgbe_mac_X550) {
3269 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3270 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3273 case IXGBE_LINKS_SPEED_1G_82599:
3274 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3276 case IXGBE_LINKS_SPEED_100_82599:
3277 *speed = IXGBE_LINK_SPEED_100_FULL;
3278 if (hw->mac.type == ixgbe_mac_X550) {
3279 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3280 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3283 case IXGBE_LINKS_SPEED_10_X550EM_A:
3284 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3285 /* Since Reserved in older MAC's */
3286 if (hw->mac.type >= ixgbe_mac_X550)
3287 *speed = IXGBE_LINK_SPEED_10_FULL;
3290 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3293 if (no_pflink_check) {
3294 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3295 mac->get_link_status = true;
3297 mac->get_link_status = false;
3301 /* if the read failed it could just be a mailbox collision, best wait
3302 * until we are called again and don't report an error
3304 if (mbx->ops.read(hw, &in_msg, 1, 0))
3307 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3308 /* msg is not CTS and is NACK we must have lost CTS status */
3309 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3314 /* the pf is talking, if we timed out in the past we reinit */
3315 if (!mbx->timeout) {
3320 /* if we passed all the tests above then the link is up and we no
3321 * longer need to check for link
3323 mac->get_link_status = false;
3326 *link_up = !mac->get_link_status;
3330 /* return 0 means link status changed, -1 means not changed */
3332 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3333 int wait_to_complete, int vf)
3335 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3336 struct rte_eth_link link, old;
3337 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3342 link.link_status = ETH_LINK_DOWN;
3343 link.link_speed = 0;
3344 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3345 link.link_autoneg = ETH_LINK_AUTONEG;
3346 memset(&old, 0, sizeof(old));
3347 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3349 hw->mac.get_link_status = true;
3351 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3352 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3356 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3358 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3361 link.link_speed = ETH_SPEED_NUM_100M;
3362 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3363 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3364 if (link.link_status == old.link_status)
3370 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3371 if (link.link_status == old.link_status)
3375 link.link_status = ETH_LINK_UP;
3376 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3378 switch (link_speed) {
3380 case IXGBE_LINK_SPEED_UNKNOWN:
3381 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3382 link.link_speed = ETH_SPEED_NUM_100M;
3385 case IXGBE_LINK_SPEED_100_FULL:
3386 link.link_speed = ETH_SPEED_NUM_100M;
3389 case IXGBE_LINK_SPEED_1GB_FULL:
3390 link.link_speed = ETH_SPEED_NUM_1G;
3393 case IXGBE_LINK_SPEED_10GB_FULL:
3394 link.link_speed = ETH_SPEED_NUM_10G;
3397 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3399 if (link.link_status == old.link_status)
3406 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3408 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3412 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3414 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3418 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3420 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3423 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3424 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3425 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3429 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3431 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3434 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3435 fctrl &= (~IXGBE_FCTRL_UPE);
3436 if (dev->data->all_multicast == 1)
3437 fctrl |= IXGBE_FCTRL_MPE;
3439 fctrl &= (~IXGBE_FCTRL_MPE);
3440 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3444 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3446 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3449 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3450 fctrl |= IXGBE_FCTRL_MPE;
3451 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3455 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3457 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3460 if (dev->data->promiscuous == 1)
3461 return; /* must remain in all_multicast mode */
3463 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3464 fctrl &= (~IXGBE_FCTRL_MPE);
3465 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3469 * It clears the interrupt causes and enables the interrupt.
3470 * It will be called once only during nic initialized.
3473 * Pointer to struct rte_eth_dev.
3476 * - On success, zero.
3477 * - On failure, a negative value.
3480 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3482 struct ixgbe_interrupt *intr =
3483 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3485 ixgbe_dev_link_status_print(dev);
3486 intr->mask |= IXGBE_EICR_LSC;
3492 * It clears the interrupt causes and enables the interrupt.
3493 * It will be called once only during nic initialized.
3496 * Pointer to struct rte_eth_dev.
3499 * - On success, zero.
3500 * - On failure, a negative value.
3503 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3505 struct ixgbe_interrupt *intr =
3506 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3508 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3514 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3517 * Pointer to struct rte_eth_dev.
3520 * - On success, zero.
3521 * - On failure, a negative value.
3524 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3527 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3528 struct ixgbe_interrupt *intr =
3529 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3531 /* clear all cause mask */
3532 ixgbe_disable_intr(hw);
3534 /* read-on-clear nic registers here */
3535 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3536 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3540 /* set flag for async link update */
3541 if (eicr & IXGBE_EICR_LSC)
3542 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3544 if (eicr & IXGBE_EICR_MAILBOX)
3545 intr->flags |= IXGBE_FLAG_MAILBOX;
3547 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3548 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3549 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3550 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3556 * It gets and then prints the link status.
3559 * Pointer to struct rte_eth_dev.
3562 * - On success, zero.
3563 * - On failure, a negative value.
3566 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3568 struct rte_eth_link link;
3570 memset(&link, 0, sizeof(link));
3571 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3572 if (link.link_status) {
3573 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3574 (int)(dev->data->port_id),
3575 (unsigned)link.link_speed,
3576 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3577 "full-duplex" : "half-duplex");
3579 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3580 (int)(dev->data->port_id));
3582 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3583 dev->pci_dev->addr.domain,
3584 dev->pci_dev->addr.bus,
3585 dev->pci_dev->addr.devid,
3586 dev->pci_dev->addr.function);
3590 * It executes link_update after knowing an interrupt occurred.
3593 * Pointer to struct rte_eth_dev.
3596 * - On success, zero.
3597 * - On failure, a negative value.
3600 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3602 struct ixgbe_interrupt *intr =
3603 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3605 struct rte_eth_link link;
3606 struct ixgbe_hw *hw =
3607 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3609 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3611 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3612 ixgbe_pf_mbx_process(dev);
3613 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3616 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3617 ixgbe_handle_lasi(hw);
3618 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3621 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3622 /* get the link status before link update, for predicting later */
3623 memset(&link, 0, sizeof(link));
3624 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3626 ixgbe_dev_link_update(dev, 0);
3629 if (!link.link_status)
3630 /* handle it 1 sec later, wait it being stable */
3631 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3632 /* likely to down */
3634 /* handle it 4 sec later, wait it being stable */
3635 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3637 ixgbe_dev_link_status_print(dev);
3638 intr->mask_original = intr->mask;
3639 /* only disable lsc interrupt */
3640 intr->mask &= ~IXGBE_EIMS_LSC;
3641 if (rte_eal_alarm_set(timeout * 1000,
3642 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3643 PMD_DRV_LOG(ERR, "Error setting alarm");
3645 intr->mask = intr->mask_original;
3648 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3649 ixgbe_enable_intr(dev);
3650 rte_intr_enable(&dev->pci_dev->intr_handle);
3656 * Interrupt handler which shall be registered for alarm callback for delayed
3657 * handling specific interrupt to wait for the stable nic state. As the
3658 * NIC interrupt state is not stable for ixgbe after link is just down,
3659 * it needs to wait 4 seconds to get the stable status.
3662 * Pointer to interrupt handle.
3664 * The address of parameter (struct rte_eth_dev *) regsitered before.
3670 ixgbe_dev_interrupt_delayed_handler(void *param)
3672 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3673 struct ixgbe_interrupt *intr =
3674 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3675 struct ixgbe_hw *hw =
3676 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3679 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3680 if (eicr & IXGBE_EICR_MAILBOX)
3681 ixgbe_pf_mbx_process(dev);
3683 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3684 ixgbe_handle_lasi(hw);
3685 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3688 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3689 ixgbe_dev_link_update(dev, 0);
3690 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3691 ixgbe_dev_link_status_print(dev);
3692 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3695 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3696 ixgbe_enable_intr(dev);
3697 rte_intr_enable(&(dev->pci_dev->intr_handle));
3701 * Interrupt handler triggered by NIC for handling
3702 * specific interrupt.
3705 * Pointer to interrupt handle.
3707 * The address of parameter (struct rte_eth_dev *) regsitered before.
3713 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3716 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3718 ixgbe_dev_interrupt_get_status(dev);
3719 ixgbe_dev_interrupt_action(dev);
3723 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3725 struct ixgbe_hw *hw;
3727 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3728 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3732 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3734 struct ixgbe_hw *hw;
3736 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3737 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3741 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3743 struct ixgbe_hw *hw;
3749 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3751 fc_conf->pause_time = hw->fc.pause_time;
3752 fc_conf->high_water = hw->fc.high_water[0];
3753 fc_conf->low_water = hw->fc.low_water[0];
3754 fc_conf->send_xon = hw->fc.send_xon;
3755 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3758 * Return rx_pause status according to actual setting of
3761 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3762 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3768 * Return tx_pause status according to actual setting of
3771 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3772 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3777 if (rx_pause && tx_pause)
3778 fc_conf->mode = RTE_FC_FULL;
3780 fc_conf->mode = RTE_FC_RX_PAUSE;
3782 fc_conf->mode = RTE_FC_TX_PAUSE;
3784 fc_conf->mode = RTE_FC_NONE;
3790 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3792 struct ixgbe_hw *hw;
3794 uint32_t rx_buf_size;
3795 uint32_t max_high_water;
3797 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3804 PMD_INIT_FUNC_TRACE();
3806 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3807 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3808 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3811 * At least reserve one Ethernet frame for watermark
3812 * high_water/low_water in kilo bytes for ixgbe
3814 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3815 if ((fc_conf->high_water > max_high_water) ||
3816 (fc_conf->high_water < fc_conf->low_water)) {
3817 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3818 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3822 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3823 hw->fc.pause_time = fc_conf->pause_time;
3824 hw->fc.high_water[0] = fc_conf->high_water;
3825 hw->fc.low_water[0] = fc_conf->low_water;
3826 hw->fc.send_xon = fc_conf->send_xon;
3827 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3829 err = ixgbe_fc_enable(hw);
3831 /* Not negotiated is not an error case */
3832 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3834 /* check if we want to forward MAC frames - driver doesn't have native
3835 * capability to do that, so we'll write the registers ourselves */
3837 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3839 /* set or clear MFLCN.PMCF bit depending on configuration */
3840 if (fc_conf->mac_ctrl_frame_fwd != 0)
3841 mflcn |= IXGBE_MFLCN_PMCF;
3843 mflcn &= ~IXGBE_MFLCN_PMCF;
3845 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3846 IXGBE_WRITE_FLUSH(hw);
3851 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3856 * ixgbe_pfc_enable_generic - Enable flow control
3857 * @hw: pointer to hardware structure
3858 * @tc_num: traffic class number
3859 * Enable flow control according to the current settings.
3862 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3865 uint32_t mflcn_reg, fccfg_reg;
3867 uint32_t fcrtl, fcrth;
3871 /* Validate the water mark configuration */
3872 if (!hw->fc.pause_time) {
3873 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3877 /* Low water mark of zero causes XOFF floods */
3878 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3879 /* High/Low water can not be 0 */
3880 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3881 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3882 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3886 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3887 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3888 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3892 /* Negotiate the fc mode to use */
3893 ixgbe_fc_autoneg(hw);
3895 /* Disable any previous flow control settings */
3896 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3897 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3899 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3900 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3902 switch (hw->fc.current_mode) {
3905 * If the count of enabled RX Priority Flow control >1,
3906 * and the TX pause can not be disabled
3909 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3910 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3911 if (reg & IXGBE_FCRTH_FCEN)
3915 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3917 case ixgbe_fc_rx_pause:
3919 * Rx Flow control is enabled and Tx Flow control is
3920 * disabled by software override. Since there really
3921 * isn't a way to advertise that we are capable of RX
3922 * Pause ONLY, we will advertise that we support both
3923 * symmetric and asymmetric Rx PAUSE. Later, we will
3924 * disable the adapter's ability to send PAUSE frames.
3926 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3928 * If the count of enabled RX Priority Flow control >1,
3929 * and the TX pause can not be disabled
3932 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3933 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3934 if (reg & IXGBE_FCRTH_FCEN)
3938 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3940 case ixgbe_fc_tx_pause:
3942 * Tx Flow control is enabled, and Rx Flow control is
3943 * disabled by software override.
3945 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3948 /* Flow control (both Rx and Tx) is enabled by SW override. */
3949 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3950 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3953 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3954 ret_val = IXGBE_ERR_CONFIG;
3958 /* Set 802.3x based flow control settings. */
3959 mflcn_reg |= IXGBE_MFLCN_DPF;
3960 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3961 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3963 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3964 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3965 hw->fc.high_water[tc_num]) {
3966 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3967 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3968 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3970 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3972 * In order to prevent Tx hangs when the internal Tx
3973 * switch is enabled we must set the high water mark
3974 * to the maximum FCRTH value. This allows the Tx
3975 * switch to function even under heavy Rx workloads.
3977 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3979 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3981 /* Configure pause time (2 TCs per register) */
3982 reg = hw->fc.pause_time * 0x00010001;
3983 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3984 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3986 /* Configure flow control refresh threshold value */
3987 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3994 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3996 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3997 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3999 if (hw->mac.type != ixgbe_mac_82598EB) {
4000 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4006 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4009 uint32_t rx_buf_size;
4010 uint32_t max_high_water;
4012 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4013 struct ixgbe_hw *hw =
4014 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4015 struct ixgbe_dcb_config *dcb_config =
4016 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4018 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4025 PMD_INIT_FUNC_TRACE();
4027 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4028 tc_num = map[pfc_conf->priority];
4029 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4030 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4032 * At least reserve one Ethernet frame for watermark
4033 * high_water/low_water in kilo bytes for ixgbe
4035 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4036 if ((pfc_conf->fc.high_water > max_high_water) ||
4037 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4038 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4039 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4043 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4044 hw->fc.pause_time = pfc_conf->fc.pause_time;
4045 hw->fc.send_xon = pfc_conf->fc.send_xon;
4046 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4047 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4049 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4051 /* Not negotiated is not an error case */
4052 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4055 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4060 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4061 struct rte_eth_rss_reta_entry64 *reta_conf,
4064 uint16_t i, sp_reta_size;
4067 uint16_t idx, shift;
4068 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4071 PMD_INIT_FUNC_TRACE();
4073 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4074 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4079 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4080 if (reta_size != sp_reta_size) {
4081 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4082 "(%d) doesn't match the number hardware can supported "
4083 "(%d)\n", reta_size, sp_reta_size);
4087 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4088 idx = i / RTE_RETA_GROUP_SIZE;
4089 shift = i % RTE_RETA_GROUP_SIZE;
4090 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4094 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4095 if (mask == IXGBE_4_BIT_MASK)
4098 r = IXGBE_READ_REG(hw, reta_reg);
4099 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4100 if (mask & (0x1 << j))
4101 reta |= reta_conf[idx].reta[shift + j] <<
4104 reta |= r & (IXGBE_8_BIT_MASK <<
4107 IXGBE_WRITE_REG(hw, reta_reg, reta);
4114 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4115 struct rte_eth_rss_reta_entry64 *reta_conf,
4118 uint16_t i, sp_reta_size;
4121 uint16_t idx, shift;
4122 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4125 PMD_INIT_FUNC_TRACE();
4126 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4127 if (reta_size != sp_reta_size) {
4128 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4129 "(%d) doesn't match the number hardware can supported "
4130 "(%d)\n", reta_size, sp_reta_size);
4134 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4135 idx = i / RTE_RETA_GROUP_SIZE;
4136 shift = i % RTE_RETA_GROUP_SIZE;
4137 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4142 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4143 reta = IXGBE_READ_REG(hw, reta_reg);
4144 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4145 if (mask & (0x1 << j))
4146 reta_conf[idx].reta[shift + j] =
4147 ((reta >> (CHAR_BIT * j)) &
4156 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4157 uint32_t index, uint32_t pool)
4159 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4160 uint32_t enable_addr = 1;
4162 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4166 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4168 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4170 ixgbe_clear_rar(hw, index);
4174 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4176 ixgbe_remove_rar(dev, 0);
4178 ixgbe_add_rar(dev, addr, 0, 0);
4182 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4183 struct ether_addr *mac_addr)
4185 struct ixgbe_hw *hw;
4186 struct ixgbe_vf_info *vfinfo;
4188 uint8_t *new_mac = (uint8_t *)(mac_addr);
4189 struct rte_eth_dev *dev;
4190 struct rte_eth_dev_info dev_info;
4192 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4194 dev = &rte_eth_devices[port];
4195 rte_eth_dev_info_get(port, &dev_info);
4197 if (vf >= dev_info.max_vfs)
4200 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4201 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4202 rar_entry = hw->mac.num_rar_entries - (vf + 1);
4204 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4205 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4207 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4214 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4218 struct ixgbe_hw *hw;
4219 struct rte_eth_dev_info dev_info;
4220 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4221 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4223 ixgbe_dev_info_get(dev, &dev_info);
4225 /* check that mtu is within the allowed range */
4226 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4229 /* refuse mtu that requires the support of scattered packets when this
4230 * feature has not been enabled before.
4232 if (!rx_conf->enable_scatter &&
4233 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4234 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4237 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4238 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4240 /* switch to jumbo mode if needed */
4241 if (frame_size > ETHER_MAX_LEN) {
4242 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4243 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4245 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4246 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4248 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4250 /* update max frame size */
4251 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4253 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4254 maxfrs &= 0x0000FFFF;
4255 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4256 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4262 * Virtual Function operations
4265 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4267 PMD_INIT_FUNC_TRACE();
4269 /* Clear interrupt mask to stop from interrupts being generated */
4270 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4272 IXGBE_WRITE_FLUSH(hw);
4276 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4278 PMD_INIT_FUNC_TRACE();
4280 /* VF enable interrupt autoclean */
4281 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4282 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4283 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4285 IXGBE_WRITE_FLUSH(hw);
4289 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4291 struct rte_eth_conf *conf = &dev->data->dev_conf;
4292 struct ixgbe_adapter *adapter =
4293 (struct ixgbe_adapter *)dev->data->dev_private;
4295 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4296 dev->data->port_id);
4299 * VF has no ability to enable/disable HW CRC
4300 * Keep the persistent behavior the same as Host PF
4302 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4303 if (!conf->rxmode.hw_strip_crc) {
4304 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4305 conf->rxmode.hw_strip_crc = 1;
4308 if (conf->rxmode.hw_strip_crc) {
4309 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4310 conf->rxmode.hw_strip_crc = 0;
4315 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4316 * allocation or vector Rx preconditions we will reset it.
4318 adapter->rx_bulk_alloc_allowed = true;
4319 adapter->rx_vec_allowed = true;
4325 ixgbevf_dev_start(struct rte_eth_dev *dev)
4327 struct ixgbe_hw *hw =
4328 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4329 uint32_t intr_vector = 0;
4330 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4334 PMD_INIT_FUNC_TRACE();
4336 err = hw->mac.ops.reset_hw(hw);
4338 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4341 hw->mac.get_link_status = true;
4343 /* negotiate mailbox API version to use with the PF. */
4344 ixgbevf_negotiate_api(hw);
4346 ixgbevf_dev_tx_init(dev);
4348 /* This can fail when allocating mbufs for descriptor rings */
4349 err = ixgbevf_dev_rx_init(dev);
4351 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4352 ixgbe_dev_clear_queues(dev);
4357 ixgbevf_set_vfta_all(dev, 1);
4360 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4361 ETH_VLAN_EXTEND_MASK;
4362 ixgbevf_vlan_offload_set(dev, mask);
4364 ixgbevf_dev_rxtx_start(dev);
4366 /* check and configure queue intr-vector mapping */
4367 if (rte_intr_cap_multiple(intr_handle) &&
4368 dev->data->dev_conf.intr_conf.rxq != 0) {
4369 intr_vector = dev->data->nb_rx_queues;
4370 if (rte_intr_efd_enable(intr_handle, intr_vector))
4374 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4375 intr_handle->intr_vec =
4376 rte_zmalloc("intr_vec",
4377 dev->data->nb_rx_queues * sizeof(int), 0);
4378 if (intr_handle->intr_vec == NULL) {
4379 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4380 " intr_vec\n", dev->data->nb_rx_queues);
4384 ixgbevf_configure_msix(dev);
4386 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
4387 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
4388 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
4389 * is not cleared, it will fail when following rte_intr_enable( ) tries
4390 * to map Rx queue interrupt to other VFIO vectors.
4391 * So clear uio/vfio intr/evevnfd first to avoid failure.
4393 rte_intr_disable(intr_handle);
4395 rte_intr_enable(intr_handle);
4397 /* Re-enable interrupt for VF */
4398 ixgbevf_intr_enable(hw);
4404 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4406 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4409 PMD_INIT_FUNC_TRACE();
4411 ixgbevf_intr_disable(hw);
4413 hw->adapter_stopped = 1;
4414 ixgbe_stop_adapter(hw);
4417 * Clear what we set, but we still keep shadow_vfta to
4418 * restore after device starts
4420 ixgbevf_set_vfta_all(dev, 0);
4422 /* Clear stored conf */
4423 dev->data->scattered_rx = 0;
4425 ixgbe_dev_clear_queues(dev);
4427 /* Clean datapath event and queue/vec mapping */
4428 rte_intr_efd_disable(intr_handle);
4429 if (intr_handle->intr_vec != NULL) {
4430 rte_free(intr_handle->intr_vec);
4431 intr_handle->intr_vec = NULL;
4436 ixgbevf_dev_close(struct rte_eth_dev *dev)
4438 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4440 PMD_INIT_FUNC_TRACE();
4444 ixgbevf_dev_stop(dev);
4446 ixgbe_dev_free_queues(dev);
4449 * Remove the VF MAC address ro ensure
4450 * that the VF traffic goes to the PF
4451 * after stop, close and detach of the VF
4453 ixgbevf_remove_mac_addr(dev, 0);
4456 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4458 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4459 struct ixgbe_vfta *shadow_vfta =
4460 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4461 int i = 0, j = 0, vfta = 0, mask = 1;
4463 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4464 vfta = shadow_vfta->vfta[i];
4467 for (j = 0; j < 32; j++) {
4469 ixgbe_set_vfta(hw, (i<<5)+j, 0,
4479 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4481 struct ixgbe_hw *hw =
4482 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4483 struct ixgbe_vfta *shadow_vfta =
4484 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4485 uint32_t vid_idx = 0;
4486 uint32_t vid_bit = 0;
4489 PMD_INIT_FUNC_TRACE();
4491 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4492 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4494 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4497 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4498 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4500 /* Save what we set and retore it after device reset */
4502 shadow_vfta->vfta[vid_idx] |= vid_bit;
4504 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4510 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4512 struct ixgbe_hw *hw =
4513 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4516 PMD_INIT_FUNC_TRACE();
4518 if (queue >= hw->mac.max_rx_queues)
4521 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4523 ctrl |= IXGBE_RXDCTL_VME;
4525 ctrl &= ~IXGBE_RXDCTL_VME;
4526 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4528 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4532 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4534 struct ixgbe_hw *hw =
4535 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4539 /* VF function only support hw strip feature, others are not support */
4540 if (mask & ETH_VLAN_STRIP_MASK) {
4541 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4543 for (i = 0; i < hw->mac.max_rx_queues; i++)
4544 ixgbevf_vlan_strip_queue_set(dev, i, on);
4549 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4553 /* we only need to do this if VMDq is enabled */
4554 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4555 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4556 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4564 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4566 uint32_t vector = 0;
4568 switch (hw->mac.mc_filter_type) {
4569 case 0: /* use bits [47:36] of the address */
4570 vector = ((uc_addr->addr_bytes[4] >> 4) |
4571 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4573 case 1: /* use bits [46:35] of the address */
4574 vector = ((uc_addr->addr_bytes[4] >> 3) |
4575 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4577 case 2: /* use bits [45:34] of the address */
4578 vector = ((uc_addr->addr_bytes[4] >> 2) |
4579 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4581 case 3: /* use bits [43:32] of the address */
4582 vector = ((uc_addr->addr_bytes[4]) |
4583 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4585 default: /* Invalid mc_filter_type */
4589 /* vector can only be 12-bits or boundary will be exceeded */
4595 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4603 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4604 const uint32_t ixgbe_uta_bit_shift = 5;
4605 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4606 const uint32_t bit1 = 0x1;
4608 struct ixgbe_hw *hw =
4609 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4610 struct ixgbe_uta_info *uta_info =
4611 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4613 /* The UTA table only exists on 82599 hardware and newer */
4614 if (hw->mac.type < ixgbe_mac_82599EB)
4617 vector = ixgbe_uta_vector(hw, mac_addr);
4618 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4619 uta_shift = vector & ixgbe_uta_bit_mask;
4621 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4625 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4627 uta_info->uta_in_use++;
4628 reg_val |= (bit1 << uta_shift);
4629 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4631 uta_info->uta_in_use--;
4632 reg_val &= ~(bit1 << uta_shift);
4633 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4636 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4638 if (uta_info->uta_in_use > 0)
4639 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4640 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4642 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4648 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4651 struct ixgbe_hw *hw =
4652 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4653 struct ixgbe_uta_info *uta_info =
4654 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4656 /* The UTA table only exists on 82599 hardware and newer */
4657 if (hw->mac.type < ixgbe_mac_82599EB)
4661 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4662 uta_info->uta_shadow[i] = ~0;
4663 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4666 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4667 uta_info->uta_shadow[i] = 0;
4668 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4676 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4678 uint32_t new_val = orig_val;
4680 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4681 new_val |= IXGBE_VMOLR_AUPE;
4682 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4683 new_val |= IXGBE_VMOLR_ROMPE;
4684 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4685 new_val |= IXGBE_VMOLR_ROPE;
4686 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4687 new_val |= IXGBE_VMOLR_BAM;
4688 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4689 new_val |= IXGBE_VMOLR_MPE;
4695 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4696 uint16_t rx_mask, uint8_t on)
4700 struct ixgbe_hw *hw =
4701 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4702 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4704 if (hw->mac.type == ixgbe_mac_82598EB) {
4705 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4706 " on 82599 hardware and newer");
4709 if (ixgbe_vmdq_mode_check(hw) < 0)
4712 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4719 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4725 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4729 const uint8_t bit1 = 0x1;
4731 struct ixgbe_hw *hw =
4732 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4734 if (ixgbe_vmdq_mode_check(hw) < 0)
4737 if (pool >= ETH_64_POOLS)
4740 /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4742 addr = IXGBE_VFRE(1);
4743 val = bit1 << (pool - 32);
4745 addr = IXGBE_VFRE(0);
4749 reg = IXGBE_READ_REG(hw, addr);
4756 IXGBE_WRITE_REG(hw, addr, reg);
4762 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4766 const uint8_t bit1 = 0x1;
4768 struct ixgbe_hw *hw =
4769 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4771 if (ixgbe_vmdq_mode_check(hw) < 0)
4774 if (pool >= ETH_64_POOLS)
4777 /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4779 addr = IXGBE_VFTE(1);
4780 val = bit1 << (pool - 32);
4782 addr = IXGBE_VFTE(0);
4786 reg = IXGBE_READ_REG(hw, addr);
4793 IXGBE_WRITE_REG(hw, addr, reg);
4799 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4800 uint64_t pool_mask, uint8_t vlan_on)
4804 struct ixgbe_hw *hw =
4805 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4807 if (ixgbe_vmdq_mode_check(hw) < 0)
4809 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4810 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4811 ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4822 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4824 struct ixgbe_hw *hw;
4825 struct ixgbe_mac_info *mac;
4826 struct rte_eth_dev *dev;
4827 struct rte_eth_dev_info dev_info;
4829 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4831 dev = &rte_eth_devices[port];
4832 rte_eth_dev_info_get(port, &dev_info);
4834 if (vf >= dev_info.max_vfs)
4840 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4843 mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4849 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4851 struct ixgbe_hw *hw;
4852 struct ixgbe_mac_info *mac;
4853 struct rte_eth_dev *dev;
4854 struct rte_eth_dev_info dev_info;
4856 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4858 dev = &rte_eth_devices[port];
4859 rte_eth_dev_info_get(port, &dev_info);
4861 if (vf >= dev_info.max_vfs)
4867 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4869 mac->ops.set_mac_anti_spoofing(hw, on, vf);
4875 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4877 struct ixgbe_hw *hw;
4879 struct rte_eth_dev *dev;
4880 struct rte_eth_dev_info dev_info;
4882 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4884 dev = &rte_eth_devices[port];
4885 rte_eth_dev_info_get(port, &dev_info);
4887 if (vf >= dev_info.max_vfs)
4893 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4894 ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4897 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4902 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4908 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4910 struct ixgbe_hw *hw;
4912 struct rte_eth_dev *dev;
4914 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4916 dev = &rte_eth_devices[port];
4921 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4922 ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4923 /* enable or disable VMDQ loopback */
4925 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4927 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4929 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4935 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4937 struct ixgbe_hw *hw;
4940 int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4941 struct rte_eth_dev *dev;
4943 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4945 dev = &rte_eth_devices[port];
4950 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4951 for (i = 0; i <= num_queues; i++) {
4952 reg_value = IXGBE_QDE_WRITE |
4953 (i << IXGBE_QDE_IDX_SHIFT) |
4954 (on & IXGBE_QDE_ENABLE);
4955 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4962 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4964 struct ixgbe_hw *hw;
4966 struct rte_eth_dev *dev;
4967 struct rte_eth_dev_info dev_info;
4969 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4971 dev = &rte_eth_devices[port];
4972 rte_eth_dev_info_get(port, &dev_info);
4974 /* only support VF's 0 to 63 */
4975 if ((vf >= dev_info.max_vfs) || (vf > 63))
4981 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4982 reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4984 reg_value |= IXGBE_SRRCTL_DROP_EN;
4986 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4988 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4994 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
4996 struct rte_eth_dev *dev;
4997 struct rte_eth_dev_info dev_info;
4998 uint16_t queues_per_pool;
5001 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5003 dev = &rte_eth_devices[port];
5004 rte_eth_dev_info_get(port, &dev_info);
5006 if (vf >= dev_info.max_vfs)
5012 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5014 /* The PF has 128 queue pairs and in SRIOV configuration
5015 * those queues will be assigned to VF's, so RXDCTL
5016 * registers will be dealing with queues which will be
5018 * Let's say we have SRIOV configured with 31 VF's then the
5019 * first 124 queues 0-123 will be allocated to VF's and only
5020 * the last 4 queues 123-127 will be assigned to the PF.
5023 queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
5025 for (q = 0; q < queues_per_pool; q++)
5026 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5027 q + vf * queues_per_pool, on);
5031 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5032 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5033 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5034 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5035 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5036 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5037 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5040 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5041 struct rte_eth_mirror_conf *mirror_conf,
5042 uint8_t rule_id, uint8_t on)
5044 uint32_t mr_ctl, vlvf;
5045 uint32_t mp_lsb = 0;
5046 uint32_t mv_msb = 0;
5047 uint32_t mv_lsb = 0;
5048 uint32_t mp_msb = 0;
5051 uint64_t vlan_mask = 0;
5053 const uint8_t pool_mask_offset = 32;
5054 const uint8_t vlan_mask_offset = 32;
5055 const uint8_t dst_pool_offset = 8;
5056 const uint8_t rule_mr_offset = 4;
5057 const uint8_t mirror_rule_mask = 0x0F;
5059 struct ixgbe_mirror_info *mr_info =
5060 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5061 struct ixgbe_hw *hw =
5062 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5063 uint8_t mirror_type = 0;
5065 if (ixgbe_vmdq_mode_check(hw) < 0)
5068 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5071 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5072 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5073 mirror_conf->rule_type);
5077 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5078 mirror_type |= IXGBE_MRCTL_VLME;
5079 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5080 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5081 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5082 /* search vlan id related pool vlan filter index */
5083 reg_index = ixgbe_find_vlvf_slot(hw,
5084 mirror_conf->vlan.vlan_id[i],
5088 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5089 if ((vlvf & IXGBE_VLVF_VIEN) &&
5090 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5091 mirror_conf->vlan.vlan_id[i]))
5092 vlan_mask |= (1ULL << reg_index);
5099 mv_lsb = vlan_mask & 0xFFFFFFFF;
5100 mv_msb = vlan_mask >> vlan_mask_offset;
5102 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5103 mirror_conf->vlan.vlan_mask;
5104 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5105 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5106 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5107 mirror_conf->vlan.vlan_id[i];
5112 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5113 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5114 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5119 * if enable pool mirror, write related pool mask register,if disable
5120 * pool mirror, clear PFMRVM register
5122 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5123 mirror_type |= IXGBE_MRCTL_VPME;
5125 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5126 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5127 mr_info->mr_conf[rule_id].pool_mask =
5128 mirror_conf->pool_mask;
5133 mr_info->mr_conf[rule_id].pool_mask = 0;
5136 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5137 mirror_type |= IXGBE_MRCTL_UPME;
5138 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5139 mirror_type |= IXGBE_MRCTL_DPME;
5141 /* read mirror control register and recalculate it */
5142 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5145 mr_ctl |= mirror_type;
5146 mr_ctl &= mirror_rule_mask;
5147 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5149 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5151 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5152 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5154 /* write mirrror control register */
5155 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5157 /* write pool mirrror control register */
5158 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5159 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5160 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5163 /* write VLAN mirrror control register */
5164 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5165 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5166 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5174 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5177 uint32_t lsb_val = 0;
5178 uint32_t msb_val = 0;
5179 const uint8_t rule_mr_offset = 4;
5181 struct ixgbe_hw *hw =
5182 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5183 struct ixgbe_mirror_info *mr_info =
5184 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5186 if (ixgbe_vmdq_mode_check(hw) < 0)
5189 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5192 memset(&mr_info->mr_conf[rule_id], 0,
5193 sizeof(struct rte_eth_mirror_conf));
5195 /* clear PFVMCTL register */
5196 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5198 /* clear pool mask register */
5199 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5200 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5202 /* clear vlan mask register */
5203 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5204 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5210 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5213 struct ixgbe_hw *hw =
5214 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5216 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5217 mask |= (1 << IXGBE_MISC_VEC_ID);
5218 RTE_SET_USED(queue_id);
5219 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5221 rte_intr_enable(&dev->pci_dev->intr_handle);
5227 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5230 struct ixgbe_hw *hw =
5231 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5233 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5234 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5235 RTE_SET_USED(queue_id);
5236 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5242 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5245 struct ixgbe_hw *hw =
5246 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5247 struct ixgbe_interrupt *intr =
5248 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5250 if (queue_id < 16) {
5251 ixgbe_disable_intr(hw);
5252 intr->mask |= (1 << queue_id);
5253 ixgbe_enable_intr(dev);
5254 } else if (queue_id < 32) {
5255 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5256 mask &= (1 << queue_id);
5257 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5258 } else if (queue_id < 64) {
5259 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5260 mask &= (1 << (queue_id - 32));
5261 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5263 rte_intr_enable(&dev->pci_dev->intr_handle);
5269 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5272 struct ixgbe_hw *hw =
5273 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5274 struct ixgbe_interrupt *intr =
5275 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5277 if (queue_id < 16) {
5278 ixgbe_disable_intr(hw);
5279 intr->mask &= ~(1 << queue_id);
5280 ixgbe_enable_intr(dev);
5281 } else if (queue_id < 32) {
5282 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5283 mask &= ~(1 << queue_id);
5284 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5285 } else if (queue_id < 64) {
5286 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5287 mask &= ~(1 << (queue_id - 32));
5288 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5295 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5296 uint8_t queue, uint8_t msix_vector)
5300 if (direction == -1) {
5302 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5303 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5306 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5308 /* rx or tx cause */
5309 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5310 idx = ((16 * (queue & 1)) + (8 * direction));
5311 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5312 tmp &= ~(0xFF << idx);
5313 tmp |= (msix_vector << idx);
5314 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5319 * set the IVAR registers, mapping interrupt causes to vectors
5321 * pointer to ixgbe_hw struct
5323 * 0 for Rx, 1 for Tx, -1 for other causes
5325 * queue to map the corresponding interrupt to
5327 * the vector to map to the corresponding queue
5330 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5331 uint8_t queue, uint8_t msix_vector)
5335 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5336 if (hw->mac.type == ixgbe_mac_82598EB) {
5337 if (direction == -1)
5339 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5340 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5341 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5342 tmp |= (msix_vector << (8 * (queue & 0x3)));
5343 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5344 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5345 (hw->mac.type == ixgbe_mac_X540) ||
5346 (hw->mac.type == ixgbe_mac_X550)) {
5347 if (direction == -1) {
5349 idx = ((queue & 1) * 8);
5350 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5351 tmp &= ~(0xFF << idx);
5352 tmp |= (msix_vector << idx);
5353 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5355 /* rx or tx causes */
5356 idx = ((16 * (queue & 1)) + (8 * direction));
5357 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5358 tmp &= ~(0xFF << idx);
5359 tmp |= (msix_vector << idx);
5360 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5366 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5368 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5369 struct ixgbe_hw *hw =
5370 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5372 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5374 /* Configure VF other cause ivar */
5375 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5377 /* won't configure msix register if no mapping is done
5378 * between intr vector and event fd.
5380 if (!rte_intr_dp_is_en(intr_handle))
5383 /* Configure all RX queues of VF */
5384 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5385 /* Force all queue use vector 0,
5386 * as IXGBE_VF_MAXMSIVECOTR = 1
5388 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5389 intr_handle->intr_vec[q_idx] = vector_idx;
5394 * Sets up the hardware to properly generate MSI-X interrupts
5396 * board private structure
5399 ixgbe_configure_msix(struct rte_eth_dev *dev)
5401 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5402 struct ixgbe_hw *hw =
5403 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5404 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5405 uint32_t vec = IXGBE_MISC_VEC_ID;
5409 /* won't configure msix register if no mapping is done
5410 * between intr vector and event fd
5412 if (!rte_intr_dp_is_en(intr_handle))
5415 if (rte_intr_allow_others(intr_handle))
5416 vec = base = IXGBE_RX_VEC_START;
5418 /* setup GPIE for MSI-x mode */
5419 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5420 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5421 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5422 /* auto clearing and auto setting corresponding bits in EIMS
5423 * when MSI-X interrupt is triggered
5425 if (hw->mac.type == ixgbe_mac_82598EB) {
5426 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5428 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5429 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5431 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5433 /* Populate the IVAR table and set the ITR values to the
5434 * corresponding register.
5436 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5438 /* by default, 1:1 mapping */
5439 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5440 intr_handle->intr_vec[queue_id] = vec;
5441 if (vec < base + intr_handle->nb_efd - 1)
5445 switch (hw->mac.type) {
5446 case ixgbe_mac_82598EB:
5447 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5450 case ixgbe_mac_82599EB:
5451 case ixgbe_mac_X540:
5452 case ixgbe_mac_X550:
5453 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5458 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5459 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5461 /* set up to autoclear timer, and the vectors */
5462 mask = IXGBE_EIMS_ENABLE_MASK;
5463 mask &= ~(IXGBE_EIMS_OTHER |
5464 IXGBE_EIMS_MAILBOX |
5467 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5470 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5471 uint16_t queue_idx, uint16_t tx_rate)
5473 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5474 uint32_t rf_dec, rf_int;
5476 uint16_t link_speed = dev->data->dev_link.link_speed;
5478 if (queue_idx >= hw->mac.max_tx_queues)
5482 /* Calculate the rate factor values to set */
5483 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5484 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5485 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5487 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5488 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5489 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5490 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5496 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5497 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5500 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5501 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5502 IXGBE_MAX_JUMBO_FRAME_SIZE))
5503 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5504 IXGBE_MMW_SIZE_JUMBO_FRAME);
5506 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5507 IXGBE_MMW_SIZE_DEFAULT);
5509 /* Set RTTBCNRC of queue X */
5510 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5511 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5512 IXGBE_WRITE_FLUSH(hw);
5517 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5518 uint16_t tx_rate, uint64_t q_msk)
5520 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5521 struct ixgbe_vf_info *vfinfo =
5522 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5523 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5524 uint32_t queue_stride =
5525 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5526 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5527 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5528 uint16_t total_rate = 0;
5530 if (queue_end >= hw->mac.max_tx_queues)
5533 if (vfinfo != NULL) {
5534 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
5537 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5539 total_rate += vfinfo[vf_idx].tx_rate[idx];
5544 /* Store tx_rate for this vf. */
5545 for (idx = 0; idx < nb_q_per_pool; idx++) {
5546 if (((uint64_t)0x1 << idx) & q_msk) {
5547 if (vfinfo[vf].tx_rate[idx] != tx_rate)
5548 vfinfo[vf].tx_rate[idx] = tx_rate;
5549 total_rate += tx_rate;
5553 if (total_rate > dev->data->dev_link.link_speed) {
5555 * Reset stored TX rate of the VF if it causes exceed
5558 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5562 /* Set RTTBCNRC of each queue/pool for vf X */
5563 for (; queue_idx <= queue_end; queue_idx++) {
5565 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5573 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5574 __attribute__((unused)) uint32_t index,
5575 __attribute__((unused)) uint32_t pool)
5577 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5581 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5582 * operation. Trap this case to avoid exhausting the [very limited]
5583 * set of PF resources used to store VF MAC addresses.
5585 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5587 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5590 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5594 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5596 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5597 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5598 struct ether_addr *mac_addr;
5603 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5604 * not support the deletion of a given MAC address.
5605 * Instead, it imposes to delete all MAC addresses, then to add again
5606 * all MAC addresses with the exception of the one to be deleted.
5608 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5611 * Add again all MAC addresses, with the exception of the deleted one
5612 * and of the permanent MAC address.
5614 for (i = 0, mac_addr = dev->data->mac_addrs;
5615 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5616 /* Skip the deleted MAC address */
5619 /* Skip NULL MAC addresses */
5620 if (is_zero_ether_addr(mac_addr))
5622 /* Skip the permanent MAC address */
5623 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5625 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5628 "Adding again MAC address "
5629 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5631 mac_addr->addr_bytes[0],
5632 mac_addr->addr_bytes[1],
5633 mac_addr->addr_bytes[2],
5634 mac_addr->addr_bytes[3],
5635 mac_addr->addr_bytes[4],
5636 mac_addr->addr_bytes[5],
5642 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5644 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5646 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5649 #define MAC_TYPE_FILTER_SUP(type) do {\
5650 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5651 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5652 (type) != ixgbe_mac_X550EM_a)\
5657 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5658 struct rte_eth_syn_filter *filter,
5661 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5664 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5667 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5670 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5672 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5673 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5675 if (filter->hig_pri)
5676 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5678 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5680 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5682 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5684 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5685 IXGBE_WRITE_FLUSH(hw);
5690 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5691 struct rte_eth_syn_filter *filter)
5693 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5694 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5696 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5697 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5698 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5705 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5706 enum rte_filter_op filter_op,
5709 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5712 MAC_TYPE_FILTER_SUP(hw->mac.type);
5714 if (filter_op == RTE_ETH_FILTER_NOP)
5718 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5723 switch (filter_op) {
5724 case RTE_ETH_FILTER_ADD:
5725 ret = ixgbe_syn_filter_set(dev,
5726 (struct rte_eth_syn_filter *)arg,
5729 case RTE_ETH_FILTER_DELETE:
5730 ret = ixgbe_syn_filter_set(dev,
5731 (struct rte_eth_syn_filter *)arg,
5734 case RTE_ETH_FILTER_GET:
5735 ret = ixgbe_syn_filter_get(dev,
5736 (struct rte_eth_syn_filter *)arg);
5739 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5748 static inline enum ixgbe_5tuple_protocol
5749 convert_protocol_type(uint8_t protocol_value)
5751 if (protocol_value == IPPROTO_TCP)
5752 return IXGBE_FILTER_PROTOCOL_TCP;
5753 else if (protocol_value == IPPROTO_UDP)
5754 return IXGBE_FILTER_PROTOCOL_UDP;
5755 else if (protocol_value == IPPROTO_SCTP)
5756 return IXGBE_FILTER_PROTOCOL_SCTP;
5758 return IXGBE_FILTER_PROTOCOL_NONE;
5762 * add a 5tuple filter
5765 * dev: Pointer to struct rte_eth_dev.
5766 * index: the index the filter allocates.
5767 * filter: ponter to the filter that will be added.
5768 * rx_queue: the queue id the filter assigned to.
5771 * - On success, zero.
5772 * - On failure, a negative value.
5775 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5776 struct ixgbe_5tuple_filter *filter)
5778 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5779 struct ixgbe_filter_info *filter_info =
5780 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5782 uint32_t ftqf, sdpqf;
5783 uint32_t l34timir = 0;
5784 uint8_t mask = 0xff;
5787 * look for an unused 5tuple filter index,
5788 * and insert the filter to list.
5790 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5791 idx = i / (sizeof(uint32_t) * NBBY);
5792 shift = i % (sizeof(uint32_t) * NBBY);
5793 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5794 filter_info->fivetuple_mask[idx] |= 1 << shift;
5796 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5802 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5803 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5807 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5808 IXGBE_SDPQF_DSTPORT_SHIFT);
5809 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5811 ftqf = (uint32_t)(filter->filter_info.proto &
5812 IXGBE_FTQF_PROTOCOL_MASK);
5813 ftqf |= (uint32_t)((filter->filter_info.priority &
5814 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5815 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5816 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5817 if (filter->filter_info.dst_ip_mask == 0)
5818 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5819 if (filter->filter_info.src_port_mask == 0)
5820 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5821 if (filter->filter_info.dst_port_mask == 0)
5822 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5823 if (filter->filter_info.proto_mask == 0)
5824 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5825 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5826 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5827 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5829 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5830 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5831 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5832 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5834 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5835 l34timir |= (uint32_t)(filter->queue <<
5836 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5837 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5842 * remove a 5tuple filter
5845 * dev: Pointer to struct rte_eth_dev.
5846 * filter: the pointer of the filter will be removed.
5849 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5850 struct ixgbe_5tuple_filter *filter)
5852 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5853 struct ixgbe_filter_info *filter_info =
5854 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5855 uint16_t index = filter->index;
5857 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5858 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5859 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5862 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5863 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5864 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5865 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5866 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5870 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5872 struct ixgbe_hw *hw;
5873 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5874 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
5876 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5878 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5881 /* refuse mtu that requires the support of scattered packets when this
5882 * feature has not been enabled before.
5884 if (!rx_conf->enable_scatter &&
5885 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5886 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5890 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5891 * request of the version 2.0 of the mailbox API.
5892 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5893 * of the mailbox API.
5894 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5895 * prior to 3.11.33 which contains the following change:
5896 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5898 ixgbevf_rlpml_set_vf(hw, max_frame);
5900 /* update max frame size */
5901 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5905 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5906 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5910 static inline struct ixgbe_5tuple_filter *
5911 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5912 struct ixgbe_5tuple_filter_info *key)
5914 struct ixgbe_5tuple_filter *it;
5916 TAILQ_FOREACH(it, filter_list, entries) {
5917 if (memcmp(key, &it->filter_info,
5918 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5925 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5927 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5928 struct ixgbe_5tuple_filter_info *filter_info)
5930 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5931 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5932 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5935 switch (filter->dst_ip_mask) {
5937 filter_info->dst_ip_mask = 0;
5938 filter_info->dst_ip = filter->dst_ip;
5941 filter_info->dst_ip_mask = 1;
5944 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5948 switch (filter->src_ip_mask) {
5950 filter_info->src_ip_mask = 0;
5951 filter_info->src_ip = filter->src_ip;
5954 filter_info->src_ip_mask = 1;
5957 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5961 switch (filter->dst_port_mask) {
5963 filter_info->dst_port_mask = 0;
5964 filter_info->dst_port = filter->dst_port;
5967 filter_info->dst_port_mask = 1;
5970 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5974 switch (filter->src_port_mask) {
5976 filter_info->src_port_mask = 0;
5977 filter_info->src_port = filter->src_port;
5980 filter_info->src_port_mask = 1;
5983 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5987 switch (filter->proto_mask) {
5989 filter_info->proto_mask = 0;
5990 filter_info->proto =
5991 convert_protocol_type(filter->proto);
5994 filter_info->proto_mask = 1;
5997 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6001 filter_info->priority = (uint8_t)filter->priority;
6006 * add or delete a ntuple filter
6009 * dev: Pointer to struct rte_eth_dev.
6010 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6011 * add: if true, add filter, if false, remove filter
6014 * - On success, zero.
6015 * - On failure, a negative value.
6018 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6019 struct rte_eth_ntuple_filter *ntuple_filter,
6022 struct ixgbe_filter_info *filter_info =
6023 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6024 struct ixgbe_5tuple_filter_info filter_5tuple;
6025 struct ixgbe_5tuple_filter *filter;
6028 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6029 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6033 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6034 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6038 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6040 if (filter != NULL && add) {
6041 PMD_DRV_LOG(ERR, "filter exists.");
6044 if (filter == NULL && !add) {
6045 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6050 filter = rte_zmalloc("ixgbe_5tuple_filter",
6051 sizeof(struct ixgbe_5tuple_filter), 0);
6054 (void)rte_memcpy(&filter->filter_info,
6056 sizeof(struct ixgbe_5tuple_filter_info));
6057 filter->queue = ntuple_filter->queue;
6058 ret = ixgbe_add_5tuple_filter(dev, filter);
6064 ixgbe_remove_5tuple_filter(dev, filter);
6070 * get a ntuple filter
6073 * dev: Pointer to struct rte_eth_dev.
6074 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6077 * - On success, zero.
6078 * - On failure, a negative value.
6081 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6082 struct rte_eth_ntuple_filter *ntuple_filter)
6084 struct ixgbe_filter_info *filter_info =
6085 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6086 struct ixgbe_5tuple_filter_info filter_5tuple;
6087 struct ixgbe_5tuple_filter *filter;
6090 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6091 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6095 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6096 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6100 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6102 if (filter == NULL) {
6103 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6106 ntuple_filter->queue = filter->queue;
6111 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6112 * @dev: pointer to rte_eth_dev structure
6113 * @filter_op:operation will be taken.
6114 * @arg: a pointer to specific structure corresponding to the filter_op
6117 * - On success, zero.
6118 * - On failure, a negative value.
6121 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6122 enum rte_filter_op filter_op,
6125 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6128 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6130 if (filter_op == RTE_ETH_FILTER_NOP)
6134 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6139 switch (filter_op) {
6140 case RTE_ETH_FILTER_ADD:
6141 ret = ixgbe_add_del_ntuple_filter(dev,
6142 (struct rte_eth_ntuple_filter *)arg,
6145 case RTE_ETH_FILTER_DELETE:
6146 ret = ixgbe_add_del_ntuple_filter(dev,
6147 (struct rte_eth_ntuple_filter *)arg,
6150 case RTE_ETH_FILTER_GET:
6151 ret = ixgbe_get_ntuple_filter(dev,
6152 (struct rte_eth_ntuple_filter *)arg);
6155 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6163 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6168 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6169 if (filter_info->ethertype_filters[i] == ethertype &&
6170 (filter_info->ethertype_mask & (1 << i)))
6177 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6182 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6183 if (!(filter_info->ethertype_mask & (1 << i))) {
6184 filter_info->ethertype_mask |= 1 << i;
6185 filter_info->ethertype_filters[i] = ethertype;
6193 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6196 if (idx >= IXGBE_MAX_ETQF_FILTERS)
6198 filter_info->ethertype_mask &= ~(1 << idx);
6199 filter_info->ethertype_filters[idx] = 0;
6204 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6205 struct rte_eth_ethertype_filter *filter,
6208 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6209 struct ixgbe_filter_info *filter_info =
6210 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6215 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6218 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6219 filter->ether_type == ETHER_TYPE_IPv6) {
6220 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6221 " ethertype filter.", filter->ether_type);
6225 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6226 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6229 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6230 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6234 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6235 if (ret >= 0 && add) {
6236 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6237 filter->ether_type);
6240 if (ret < 0 && !add) {
6241 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6242 filter->ether_type);
6247 ret = ixgbe_ethertype_filter_insert(filter_info,
6248 filter->ether_type);
6250 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6253 etqf = IXGBE_ETQF_FILTER_EN;
6254 etqf |= (uint32_t)filter->ether_type;
6255 etqs |= (uint32_t)((filter->queue <<
6256 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6257 IXGBE_ETQS_RX_QUEUE);
6258 etqs |= IXGBE_ETQS_QUEUE_EN;
6260 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6264 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6265 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6266 IXGBE_WRITE_FLUSH(hw);
6272 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6273 struct rte_eth_ethertype_filter *filter)
6275 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6276 struct ixgbe_filter_info *filter_info =
6277 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6278 uint32_t etqf, etqs;
6281 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6283 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6284 filter->ether_type);
6288 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6289 if (etqf & IXGBE_ETQF_FILTER_EN) {
6290 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6291 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6293 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6294 IXGBE_ETQS_RX_QUEUE_SHIFT;
6301 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6302 * @dev: pointer to rte_eth_dev structure
6303 * @filter_op:operation will be taken.
6304 * @arg: a pointer to specific structure corresponding to the filter_op
6307 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6308 enum rte_filter_op filter_op,
6311 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6314 MAC_TYPE_FILTER_SUP(hw->mac.type);
6316 if (filter_op == RTE_ETH_FILTER_NOP)
6320 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6325 switch (filter_op) {
6326 case RTE_ETH_FILTER_ADD:
6327 ret = ixgbe_add_del_ethertype_filter(dev,
6328 (struct rte_eth_ethertype_filter *)arg,
6331 case RTE_ETH_FILTER_DELETE:
6332 ret = ixgbe_add_del_ethertype_filter(dev,
6333 (struct rte_eth_ethertype_filter *)arg,
6336 case RTE_ETH_FILTER_GET:
6337 ret = ixgbe_get_ethertype_filter(dev,
6338 (struct rte_eth_ethertype_filter *)arg);
6341 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6349 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6350 enum rte_filter_type filter_type,
6351 enum rte_filter_op filter_op,
6356 switch (filter_type) {
6357 case RTE_ETH_FILTER_NTUPLE:
6358 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6360 case RTE_ETH_FILTER_ETHERTYPE:
6361 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6363 case RTE_ETH_FILTER_SYN:
6364 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6366 case RTE_ETH_FILTER_FDIR:
6367 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6369 case RTE_ETH_FILTER_L2_TUNNEL:
6370 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6373 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6382 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6383 u8 **mc_addr_ptr, u32 *vmdq)
6388 mc_addr = *mc_addr_ptr;
6389 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6394 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6395 struct ether_addr *mc_addr_set,
6396 uint32_t nb_mc_addr)
6398 struct ixgbe_hw *hw;
6401 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6402 mc_addr_list = (u8 *)mc_addr_set;
6403 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6404 ixgbe_dev_addr_list_itr, TRUE);
6408 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6410 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6411 uint64_t systime_cycles;
6413 switch (hw->mac.type) {
6414 case ixgbe_mac_X550:
6415 case ixgbe_mac_X550EM_x:
6416 case ixgbe_mac_X550EM_a:
6417 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6418 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6419 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6423 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6424 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6428 return systime_cycles;
6432 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6434 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6435 uint64_t rx_tstamp_cycles;
6437 switch (hw->mac.type) {
6438 case ixgbe_mac_X550:
6439 case ixgbe_mac_X550EM_x:
6440 case ixgbe_mac_X550EM_a:
6441 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6442 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6443 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6447 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6448 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6449 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6453 return rx_tstamp_cycles;
6457 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6459 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6460 uint64_t tx_tstamp_cycles;
6462 switch (hw->mac.type) {
6463 case ixgbe_mac_X550:
6464 case ixgbe_mac_X550EM_x:
6465 case ixgbe_mac_X550EM_a:
6466 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6467 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6468 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6472 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6473 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6474 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6478 return tx_tstamp_cycles;
6482 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6484 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6485 struct ixgbe_adapter *adapter =
6486 (struct ixgbe_adapter *)dev->data->dev_private;
6487 struct rte_eth_link link;
6488 uint32_t incval = 0;
6491 /* Get current link speed. */
6492 memset(&link, 0, sizeof(link));
6493 ixgbe_dev_link_update(dev, 1);
6494 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6496 switch (link.link_speed) {
6497 case ETH_SPEED_NUM_100M:
6498 incval = IXGBE_INCVAL_100;
6499 shift = IXGBE_INCVAL_SHIFT_100;
6501 case ETH_SPEED_NUM_1G:
6502 incval = IXGBE_INCVAL_1GB;
6503 shift = IXGBE_INCVAL_SHIFT_1GB;
6505 case ETH_SPEED_NUM_10G:
6507 incval = IXGBE_INCVAL_10GB;
6508 shift = IXGBE_INCVAL_SHIFT_10GB;
6512 switch (hw->mac.type) {
6513 case ixgbe_mac_X550:
6514 case ixgbe_mac_X550EM_x:
6515 case ixgbe_mac_X550EM_a:
6516 /* Independent of link speed. */
6518 /* Cycles read will be interpreted as ns. */
6521 case ixgbe_mac_X540:
6522 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6524 case ixgbe_mac_82599EB:
6525 incval >>= IXGBE_INCVAL_SHIFT_82599;
6526 shift -= IXGBE_INCVAL_SHIFT_82599;
6527 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6528 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6531 /* Not supported. */
6535 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6536 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6537 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6539 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6540 adapter->systime_tc.cc_shift = shift;
6541 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6543 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6544 adapter->rx_tstamp_tc.cc_shift = shift;
6545 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6547 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6548 adapter->tx_tstamp_tc.cc_shift = shift;
6549 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6553 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6555 struct ixgbe_adapter *adapter =
6556 (struct ixgbe_adapter *)dev->data->dev_private;
6558 adapter->systime_tc.nsec += delta;
6559 adapter->rx_tstamp_tc.nsec += delta;
6560 adapter->tx_tstamp_tc.nsec += delta;
6566 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6569 struct ixgbe_adapter *adapter =
6570 (struct ixgbe_adapter *)dev->data->dev_private;
6572 ns = rte_timespec_to_ns(ts);
6573 /* Set the timecounters to a new value. */
6574 adapter->systime_tc.nsec = ns;
6575 adapter->rx_tstamp_tc.nsec = ns;
6576 adapter->tx_tstamp_tc.nsec = ns;
6582 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6584 uint64_t ns, systime_cycles;
6585 struct ixgbe_adapter *adapter =
6586 (struct ixgbe_adapter *)dev->data->dev_private;
6588 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6589 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6590 *ts = rte_ns_to_timespec(ns);
6596 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6598 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6602 /* Stop the timesync system time. */
6603 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6604 /* Reset the timesync system time value. */
6605 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6606 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6608 /* Enable system time for platforms where it isn't on by default. */
6609 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6610 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6611 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6613 ixgbe_start_timecounters(dev);
6615 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6616 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6618 IXGBE_ETQF_FILTER_EN |
6621 /* Enable timestamping of received PTP packets. */
6622 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6623 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6624 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6626 /* Enable timestamping of transmitted PTP packets. */
6627 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6628 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6629 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6631 IXGBE_WRITE_FLUSH(hw);
6637 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6639 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6642 /* Disable timestamping of transmitted PTP packets. */
6643 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6644 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6645 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6647 /* Disable timestamping of received PTP packets. */
6648 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6649 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6650 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6652 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6653 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6655 /* Stop incrementating the System Time registers. */
6656 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6662 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6663 struct timespec *timestamp,
6664 uint32_t flags __rte_unused)
6666 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6667 struct ixgbe_adapter *adapter =
6668 (struct ixgbe_adapter *)dev->data->dev_private;
6669 uint32_t tsync_rxctl;
6670 uint64_t rx_tstamp_cycles;
6673 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6674 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6677 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6678 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6679 *timestamp = rte_ns_to_timespec(ns);
6685 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6686 struct timespec *timestamp)
6688 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6689 struct ixgbe_adapter *adapter =
6690 (struct ixgbe_adapter *)dev->data->dev_private;
6691 uint32_t tsync_txctl;
6692 uint64_t tx_tstamp_cycles;
6695 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6696 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6699 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6700 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6701 *timestamp = rte_ns_to_timespec(ns);
6707 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6709 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6712 const struct reg_info *reg_group;
6713 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6714 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6716 while ((reg_group = reg_set[g_ind++]))
6717 count += ixgbe_regs_group_count(reg_group);
6723 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6727 const struct reg_info *reg_group;
6729 while ((reg_group = ixgbevf_regs[g_ind++]))
6730 count += ixgbe_regs_group_count(reg_group);
6736 ixgbe_get_regs(struct rte_eth_dev *dev,
6737 struct rte_dev_reg_info *regs)
6739 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6740 uint32_t *data = regs->data;
6743 const struct reg_info *reg_group;
6744 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6745 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6748 regs->length = ixgbe_get_reg_length(dev);
6749 regs->width = sizeof(uint32_t);
6753 /* Support only full register dump */
6754 if ((regs->length == 0) ||
6755 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6756 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6758 while ((reg_group = reg_set[g_ind++]))
6759 count += ixgbe_read_regs_group(dev, &data[count],
6768 ixgbevf_get_regs(struct rte_eth_dev *dev,
6769 struct rte_dev_reg_info *regs)
6771 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6772 uint32_t *data = regs->data;
6775 const struct reg_info *reg_group;
6778 regs->length = ixgbevf_get_reg_length(dev);
6779 regs->width = sizeof(uint32_t);
6783 /* Support only full register dump */
6784 if ((regs->length == 0) ||
6785 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6786 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6788 while ((reg_group = ixgbevf_regs[g_ind++]))
6789 count += ixgbe_read_regs_group(dev, &data[count],
6798 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6800 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6802 /* Return unit is byte count */
6803 return hw->eeprom.word_size * 2;
6807 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6808 struct rte_dev_eeprom_info *in_eeprom)
6810 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6811 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6812 uint16_t *data = in_eeprom->data;
6815 first = in_eeprom->offset >> 1;
6816 length = in_eeprom->length >> 1;
6817 if ((first > hw->eeprom.word_size) ||
6818 ((first + length) > hw->eeprom.word_size))
6821 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6823 return eeprom->ops.read_buffer(hw, first, length, data);
6827 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6828 struct rte_dev_eeprom_info *in_eeprom)
6830 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6831 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6832 uint16_t *data = in_eeprom->data;
6835 first = in_eeprom->offset >> 1;
6836 length = in_eeprom->length >> 1;
6837 if ((first > hw->eeprom.word_size) ||
6838 ((first + length) > hw->eeprom.word_size))
6841 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6843 return eeprom->ops.write_buffer(hw, first, length, data);
6847 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6849 case ixgbe_mac_X550:
6850 case ixgbe_mac_X550EM_x:
6851 case ixgbe_mac_X550EM_a:
6852 return ETH_RSS_RETA_SIZE_512;
6853 case ixgbe_mac_X550_vf:
6854 case ixgbe_mac_X550EM_x_vf:
6855 case ixgbe_mac_X550EM_a_vf:
6856 return ETH_RSS_RETA_SIZE_64;
6858 return ETH_RSS_RETA_SIZE_128;
6863 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6865 case ixgbe_mac_X550:
6866 case ixgbe_mac_X550EM_x:
6867 case ixgbe_mac_X550EM_a:
6868 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6869 return IXGBE_RETA(reta_idx >> 2);
6871 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6872 case ixgbe_mac_X550_vf:
6873 case ixgbe_mac_X550EM_x_vf:
6874 case ixgbe_mac_X550EM_a_vf:
6875 return IXGBE_VFRETA(reta_idx >> 2);
6877 return IXGBE_RETA(reta_idx >> 2);
6882 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6884 case ixgbe_mac_X550_vf:
6885 case ixgbe_mac_X550EM_x_vf:
6886 case ixgbe_mac_X550EM_a_vf:
6887 return IXGBE_VFMRQC;
6894 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6896 case ixgbe_mac_X550_vf:
6897 case ixgbe_mac_X550EM_x_vf:
6898 case ixgbe_mac_X550EM_a_vf:
6899 return IXGBE_VFRSSRK(i);
6901 return IXGBE_RSSRK(i);
6906 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6908 case ixgbe_mac_82599_vf:
6909 case ixgbe_mac_X540_vf:
6917 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6918 struct rte_eth_dcb_info *dcb_info)
6920 struct ixgbe_dcb_config *dcb_config =
6921 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6922 struct ixgbe_dcb_tc_config *tc;
6923 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
6927 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6928 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6930 dcb_info->nb_tcs = 1;
6932 tc_queue = &dcb_info->tc_queue;
6933 nb_tcs = dcb_info->nb_tcs;
6935 if (dcb_config->vt_mode) { /* vt is enabled*/
6936 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6937 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6938 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6939 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6940 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
6941 for (j = 0; j < nb_tcs; j++) {
6942 tc_queue->tc_rxq[0][j].base = j;
6943 tc_queue->tc_rxq[0][j].nb_queue = 1;
6944 tc_queue->tc_txq[0][j].base = j;
6945 tc_queue->tc_txq[0][j].nb_queue = 1;
6948 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6949 for (j = 0; j < nb_tcs; j++) {
6950 tc_queue->tc_rxq[i][j].base =
6952 tc_queue->tc_rxq[i][j].nb_queue = 1;
6953 tc_queue->tc_txq[i][j].base =
6955 tc_queue->tc_txq[i][j].nb_queue = 1;
6959 } else { /* vt is disabled*/
6960 struct rte_eth_dcb_rx_conf *rx_conf =
6961 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6962 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6963 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6964 if (dcb_info->nb_tcs == ETH_4_TCS) {
6965 for (i = 0; i < dcb_info->nb_tcs; i++) {
6966 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6967 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6969 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6970 dcb_info->tc_queue.tc_txq[0][1].base = 64;
6971 dcb_info->tc_queue.tc_txq[0][2].base = 96;
6972 dcb_info->tc_queue.tc_txq[0][3].base = 112;
6973 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6974 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6975 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6976 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6977 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6978 for (i = 0; i < dcb_info->nb_tcs; i++) {
6979 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6980 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6982 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6983 dcb_info->tc_queue.tc_txq[0][1].base = 32;
6984 dcb_info->tc_queue.tc_txq[0][2].base = 64;
6985 dcb_info->tc_queue.tc_txq[0][3].base = 80;
6986 dcb_info->tc_queue.tc_txq[0][4].base = 96;
6987 dcb_info->tc_queue.tc_txq[0][5].base = 104;
6988 dcb_info->tc_queue.tc_txq[0][6].base = 112;
6989 dcb_info->tc_queue.tc_txq[0][7].base = 120;
6990 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6991 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6992 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6993 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6994 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6995 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6996 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6997 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7000 for (i = 0; i < dcb_info->nb_tcs; i++) {
7001 tc = &dcb_config->tc_config[i];
7002 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7007 /* Update e-tag ether type */
7009 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7010 uint16_t ether_type)
7012 uint32_t etag_etype;
7014 if (hw->mac.type != ixgbe_mac_X550 &&
7015 hw->mac.type != ixgbe_mac_X550EM_x &&
7016 hw->mac.type != ixgbe_mac_X550EM_a) {
7020 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7021 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7022 etag_etype |= ether_type;
7023 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7024 IXGBE_WRITE_FLUSH(hw);
7029 /* Config l2 tunnel ether type */
7031 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7032 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7035 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7037 if (l2_tunnel == NULL)
7040 switch (l2_tunnel->l2_tunnel_type) {
7041 case RTE_L2_TUNNEL_TYPE_E_TAG:
7042 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7045 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7053 /* Enable e-tag tunnel */
7055 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7057 uint32_t etag_etype;
7059 if (hw->mac.type != ixgbe_mac_X550 &&
7060 hw->mac.type != ixgbe_mac_X550EM_x &&
7061 hw->mac.type != ixgbe_mac_X550EM_a) {
7065 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7066 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7067 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7068 IXGBE_WRITE_FLUSH(hw);
7073 /* Enable l2 tunnel */
7075 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7076 enum rte_eth_tunnel_type l2_tunnel_type)
7079 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7081 switch (l2_tunnel_type) {
7082 case RTE_L2_TUNNEL_TYPE_E_TAG:
7083 ret = ixgbe_e_tag_enable(hw);
7086 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7094 /* Disable e-tag tunnel */
7096 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7098 uint32_t etag_etype;
7100 if (hw->mac.type != ixgbe_mac_X550 &&
7101 hw->mac.type != ixgbe_mac_X550EM_x &&
7102 hw->mac.type != ixgbe_mac_X550EM_a) {
7106 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7107 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7108 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7109 IXGBE_WRITE_FLUSH(hw);
7114 /* Disable l2 tunnel */
7116 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7117 enum rte_eth_tunnel_type l2_tunnel_type)
7120 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7122 switch (l2_tunnel_type) {
7123 case RTE_L2_TUNNEL_TYPE_E_TAG:
7124 ret = ixgbe_e_tag_disable(hw);
7127 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7136 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7137 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7140 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7141 uint32_t i, rar_entries;
7142 uint32_t rar_low, rar_high;
7144 if (hw->mac.type != ixgbe_mac_X550 &&
7145 hw->mac.type != ixgbe_mac_X550EM_x &&
7146 hw->mac.type != ixgbe_mac_X550EM_a) {
7150 rar_entries = ixgbe_get_num_rx_addrs(hw);
7152 for (i = 1; i < rar_entries; i++) {
7153 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7154 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7155 if ((rar_high & IXGBE_RAH_AV) &&
7156 (rar_high & IXGBE_RAH_ADTYPE) &&
7157 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7158 l2_tunnel->tunnel_id)) {
7159 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7160 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7162 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7172 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7173 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7176 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7177 uint32_t i, rar_entries;
7178 uint32_t rar_low, rar_high;
7180 if (hw->mac.type != ixgbe_mac_X550 &&
7181 hw->mac.type != ixgbe_mac_X550EM_x &&
7182 hw->mac.type != ixgbe_mac_X550EM_a) {
7186 /* One entry for one tunnel. Try to remove potential existing entry. */
7187 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7189 rar_entries = ixgbe_get_num_rx_addrs(hw);
7191 for (i = 1; i < rar_entries; i++) {
7192 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7193 if (rar_high & IXGBE_RAH_AV) {
7196 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7197 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7198 rar_low = l2_tunnel->tunnel_id;
7200 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7201 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7207 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7208 " Please remove a rule before adding a new one.");
7212 /* Add l2 tunnel filter */
7214 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7215 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7219 switch (l2_tunnel->l2_tunnel_type) {
7220 case RTE_L2_TUNNEL_TYPE_E_TAG:
7221 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7224 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7232 /* Delete l2 tunnel filter */
7234 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7235 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7239 switch (l2_tunnel->l2_tunnel_type) {
7240 case RTE_L2_TUNNEL_TYPE_E_TAG:
7241 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7244 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7253 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7254 * @dev: pointer to rte_eth_dev structure
7255 * @filter_op:operation will be taken.
7256 * @arg: a pointer to specific structure corresponding to the filter_op
7259 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7260 enum rte_filter_op filter_op,
7265 if (filter_op == RTE_ETH_FILTER_NOP)
7269 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7274 switch (filter_op) {
7275 case RTE_ETH_FILTER_ADD:
7276 ret = ixgbe_dev_l2_tunnel_filter_add
7278 (struct rte_eth_l2_tunnel_conf *)arg);
7280 case RTE_ETH_FILTER_DELETE:
7281 ret = ixgbe_dev_l2_tunnel_filter_del
7283 (struct rte_eth_l2_tunnel_conf *)arg);
7286 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7294 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7298 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7300 if (hw->mac.type != ixgbe_mac_X550 &&
7301 hw->mac.type != ixgbe_mac_X550EM_x &&
7302 hw->mac.type != ixgbe_mac_X550EM_a) {
7306 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7307 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7309 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7310 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7315 /* Enable l2 tunnel forwarding */
7317 ixgbe_dev_l2_tunnel_forwarding_enable
7318 (struct rte_eth_dev *dev,
7319 enum rte_eth_tunnel_type l2_tunnel_type)
7323 switch (l2_tunnel_type) {
7324 case RTE_L2_TUNNEL_TYPE_E_TAG:
7325 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7328 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7336 /* Disable l2 tunnel forwarding */
7338 ixgbe_dev_l2_tunnel_forwarding_disable
7339 (struct rte_eth_dev *dev,
7340 enum rte_eth_tunnel_type l2_tunnel_type)
7344 switch (l2_tunnel_type) {
7345 case RTE_L2_TUNNEL_TYPE_E_TAG:
7346 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7349 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7358 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7359 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7363 uint32_t vmtir, vmvir;
7364 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7366 if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
7368 "VF id %u should be less than %u",
7370 dev->pci_dev->max_vfs);
7374 if (hw->mac.type != ixgbe_mac_X550 &&
7375 hw->mac.type != ixgbe_mac_X550EM_x &&
7376 hw->mac.type != ixgbe_mac_X550EM_a) {
7381 vmtir = l2_tunnel->tunnel_id;
7385 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7387 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7388 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7390 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7391 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7396 /* Enable l2 tunnel tag insertion */
7398 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7399 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7403 switch (l2_tunnel->l2_tunnel_type) {
7404 case RTE_L2_TUNNEL_TYPE_E_TAG:
7405 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7408 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7416 /* Disable l2 tunnel tag insertion */
7418 ixgbe_dev_l2_tunnel_insertion_disable
7419 (struct rte_eth_dev *dev,
7420 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7424 switch (l2_tunnel->l2_tunnel_type) {
7425 case RTE_L2_TUNNEL_TYPE_E_TAG:
7426 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7429 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7438 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7443 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7445 if (hw->mac.type != ixgbe_mac_X550 &&
7446 hw->mac.type != ixgbe_mac_X550EM_x &&
7447 hw->mac.type != ixgbe_mac_X550EM_a) {
7451 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7453 qde |= IXGBE_QDE_STRIP_TAG;
7455 qde &= ~IXGBE_QDE_STRIP_TAG;
7456 qde &= ~IXGBE_QDE_READ;
7457 qde |= IXGBE_QDE_WRITE;
7458 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7463 /* Enable l2 tunnel tag stripping */
7465 ixgbe_dev_l2_tunnel_stripping_enable
7466 (struct rte_eth_dev *dev,
7467 enum rte_eth_tunnel_type l2_tunnel_type)
7471 switch (l2_tunnel_type) {
7472 case RTE_L2_TUNNEL_TYPE_E_TAG:
7473 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7476 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7484 /* Disable l2 tunnel tag stripping */
7486 ixgbe_dev_l2_tunnel_stripping_disable
7487 (struct rte_eth_dev *dev,
7488 enum rte_eth_tunnel_type l2_tunnel_type)
7492 switch (l2_tunnel_type) {
7493 case RTE_L2_TUNNEL_TYPE_E_TAG:
7494 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7497 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7505 /* Enable/disable l2 tunnel offload functions */
7507 ixgbe_dev_l2_tunnel_offload_set
7508 (struct rte_eth_dev *dev,
7509 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7515 if (l2_tunnel == NULL)
7519 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7521 ret = ixgbe_dev_l2_tunnel_enable(
7523 l2_tunnel->l2_tunnel_type);
7525 ret = ixgbe_dev_l2_tunnel_disable(
7527 l2_tunnel->l2_tunnel_type);
7530 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7532 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7536 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7541 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7543 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7545 l2_tunnel->l2_tunnel_type);
7547 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7549 l2_tunnel->l2_tunnel_type);
7552 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7554 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7556 l2_tunnel->l2_tunnel_type);
7558 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7560 l2_tunnel->l2_tunnel_type);
7567 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7570 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7571 IXGBE_WRITE_FLUSH(hw);
7576 /* There's only one register for VxLAN UDP port.
7577 * So, we cannot add several ports. Will update it.
7580 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7584 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7588 return ixgbe_update_vxlan_port(hw, port);
7591 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7592 * UDP port, it must have a value.
7593 * So, will reset it to the original value 0.
7596 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7601 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7603 if (cur_port != port) {
7604 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7608 return ixgbe_update_vxlan_port(hw, 0);
7611 /* Add UDP tunneling port */
7613 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7614 struct rte_eth_udp_tunnel *udp_tunnel)
7617 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7619 if (hw->mac.type != ixgbe_mac_X550 &&
7620 hw->mac.type != ixgbe_mac_X550EM_x &&
7621 hw->mac.type != ixgbe_mac_X550EM_a) {
7625 if (udp_tunnel == NULL)
7628 switch (udp_tunnel->prot_type) {
7629 case RTE_TUNNEL_TYPE_VXLAN:
7630 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7633 case RTE_TUNNEL_TYPE_GENEVE:
7634 case RTE_TUNNEL_TYPE_TEREDO:
7635 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7640 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7648 /* Remove UDP tunneling port */
7650 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7651 struct rte_eth_udp_tunnel *udp_tunnel)
7654 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7656 if (hw->mac.type != ixgbe_mac_X550 &&
7657 hw->mac.type != ixgbe_mac_X550EM_x &&
7658 hw->mac.type != ixgbe_mac_X550EM_a) {
7662 if (udp_tunnel == NULL)
7665 switch (udp_tunnel->prot_type) {
7666 case RTE_TUNNEL_TYPE_VXLAN:
7667 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7669 case RTE_TUNNEL_TYPE_GENEVE:
7670 case RTE_TUNNEL_TYPE_TEREDO:
7671 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7675 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7684 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7686 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7688 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7692 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7694 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7696 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
7699 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7701 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7704 /* peek the message first */
7705 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
7707 /* PF reset VF event */
7708 if (in_msg == IXGBE_PF_CONTROL_MSG) {
7709 /* dummy mbx read to ack pf */
7710 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7712 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
7718 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7721 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7722 struct ixgbe_interrupt *intr =
7723 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7724 ixgbevf_intr_disable(hw);
7726 /* read-on-clear nic registers here */
7727 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7730 /* only one misc vector supported - mailbox */
7731 eicr &= IXGBE_VTEICR_MASK;
7732 if (eicr == IXGBE_MISC_VEC_ID)
7733 intr->flags |= IXGBE_FLAG_MAILBOX;
7739 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7741 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7742 struct ixgbe_interrupt *intr =
7743 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7745 if (intr->flags & IXGBE_FLAG_MAILBOX) {
7746 ixgbevf_mbx_process(dev);
7747 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7750 ixgbevf_intr_enable(hw);
7756 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7759 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7761 ixgbevf_dev_interrupt_get_status(dev);
7762 ixgbevf_dev_interrupt_action(dev);
7765 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
7766 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
7767 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
7768 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);