4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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19 * from this software without specific prior written permission.
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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define NSEC_PER_SEC 1000000000L
130 #define IXGBE_INCVAL_10GB 0x66666666
131 #define IXGBE_INCVAL_1GB 0x40000000
132 #define IXGBE_INCVAL_100 0x50000000
133 #define IXGBE_INCVAL_SHIFT_10GB 28
134 #define IXGBE_INCVAL_SHIFT_1GB 24
135 #define IXGBE_INCVAL_SHIFT_100 21
136 #define IXGBE_INCVAL_SHIFT_82599 7
137 #define IXGBE_INCPER_SHIFT_82599 24
139 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
141 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
143 #define DEFAULT_ETAG_ETYPE 0x893f
144 #define IXGBE_ETAG_ETYPE 0x00005084
145 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
146 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
147 #define IXGBE_RAH_ADTYPE 0x40000000
148 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
149 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
152 #define IXGBE_QDE_STRIP_TAG 0x00000004
154 enum ixgbevf_xcast_modes {
155 IXGBEVF_XCAST_MODE_NONE = 0,
156 IXGBEVF_XCAST_MODE_MULTI,
157 IXGBEVF_XCAST_MODE_ALLMULTI,
160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
162 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
163 static int ixgbe_dev_start(struct rte_eth_dev *dev);
164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
165 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
166 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
173 int wait_to_complete);
174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
175 struct rte_eth_stats *stats);
176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
177 struct rte_eth_xstats *xstats, unsigned n);
178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
179 struct rte_eth_xstats *xstats, unsigned n);
180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
187 struct rte_eth_dev_info *dev_info);
188 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
189 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
190 struct rte_eth_dev_info *dev_info);
191 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
193 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
194 uint16_t vlan_id, int on);
195 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
196 enum rte_vlan_type vlan_type,
198 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
199 uint16_t queue, bool on);
200 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
202 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
203 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
204 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
205 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
206 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
208 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
209 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
210 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
211 struct rte_eth_fc_conf *fc_conf);
212 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
213 struct rte_eth_fc_conf *fc_conf);
214 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
215 struct rte_eth_pfc_conf *pfc_conf);
216 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
217 struct rte_eth_rss_reta_entry64 *reta_conf,
219 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
220 struct rte_eth_rss_reta_entry64 *reta_conf,
222 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
223 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
224 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
225 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
226 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
227 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
229 static void ixgbe_dev_interrupt_delayed_handler(void *param);
230 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
231 uint32_t index, uint32_t pool);
232 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
233 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
234 struct ether_addr *mac_addr);
235 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
237 /* For Virtual Function support */
238 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
239 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
240 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
241 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
242 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
243 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
244 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
245 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
246 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
247 struct rte_eth_stats *stats);
248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
250 uint16_t vlan_id, int on);
251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
252 uint16_t queue, int on);
253 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
260 uint8_t queue, uint8_t msix_vector);
261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
265 /* For Eth VMDQ APIs support */
266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
267 ether_addr* mac_addr,uint8_t on);
268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
269 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
270 uint16_t rx_mask, uint8_t on);
271 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
272 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
273 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
274 uint64_t pool_mask,uint8_t vlan_on);
275 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
276 struct rte_eth_mirror_conf *mirror_conf,
277 uint8_t rule_id, uint8_t on);
278 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
280 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
282 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
284 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
285 uint8_t queue, uint8_t msix_vector);
286 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
288 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
289 uint16_t queue_idx, uint16_t tx_rate);
290 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
291 uint16_t tx_rate, uint64_t q_msk);
293 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
294 struct ether_addr *mac_addr,
295 uint32_t index, uint32_t pool);
296 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
297 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
298 struct ether_addr *mac_addr);
299 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
300 struct rte_eth_syn_filter *filter,
302 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
303 struct rte_eth_syn_filter *filter);
304 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
305 enum rte_filter_op filter_op,
307 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
308 struct ixgbe_5tuple_filter *filter);
309 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
310 struct ixgbe_5tuple_filter *filter);
311 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
312 struct rte_eth_ntuple_filter *filter,
314 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
315 enum rte_filter_op filter_op,
317 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
318 struct rte_eth_ntuple_filter *filter);
319 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
320 struct rte_eth_ethertype_filter *filter,
322 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
323 enum rte_filter_op filter_op,
325 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
326 struct rte_eth_ethertype_filter *filter);
327 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
328 enum rte_filter_type filter_type,
329 enum rte_filter_op filter_op,
331 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
333 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
334 struct ether_addr *mc_addr_set,
335 uint32_t nb_mc_addr);
336 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
337 struct rte_eth_dcb_info *dcb_info);
339 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
340 static int ixgbe_get_regs(struct rte_eth_dev *dev,
341 struct rte_dev_reg_info *regs);
342 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
343 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
344 struct rte_dev_eeprom_info *eeprom);
345 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
346 struct rte_dev_eeprom_info *eeprom);
348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
350 struct rte_dev_reg_info *regs);
352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
355 struct timespec *timestamp,
357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
358 struct timespec *timestamp);
359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
361 struct timespec *timestamp);
362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
363 const struct timespec *timestamp);
365 static int ixgbe_dev_l2_tunnel_eth_type_conf
366 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
367 static int ixgbe_dev_l2_tunnel_offload_set
368 (struct rte_eth_dev *dev,
369 struct rte_eth_l2_tunnel_conf *l2_tunnel,
372 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
373 enum rte_filter_op filter_op,
376 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
377 struct rte_eth_udp_tunnel *udp_tunnel);
378 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
379 struct rte_eth_udp_tunnel *udp_tunnel);
382 * Define VF Stats MACRO for Non "cleared on read" register
384 #define UPDATE_VF_STAT(reg, last, cur) \
386 uint32_t latest = IXGBE_READ_REG(hw, reg); \
387 cur += (latest - last) & UINT_MAX; \
391 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
393 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
394 u64 new_msb = IXGBE_READ_REG(hw, msb); \
395 u64 latest = ((new_msb << 32) | new_lsb); \
396 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
400 #define IXGBE_SET_HWSTRIP(h, q) do{\
401 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
402 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
403 (h)->bitmap[idx] |= 1 << bit;\
406 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
407 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
408 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
409 (h)->bitmap[idx] &= ~(1 << bit);\
412 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
413 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
414 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
415 (r) = (h)->bitmap[idx] >> bit & 1;\
419 * The set of PCI devices this driver supports
421 static const struct rte_pci_id pci_id_ixgbe_map[] = {
423 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
424 #include "rte_pci_dev_ids.h"
426 { .vendor_id = 0, /* sentinel */ },
431 * The set of PCI devices this driver supports (for 82599 VF)
433 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
435 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
436 #include "rte_pci_dev_ids.h"
437 { .vendor_id = 0, /* sentinel */ },
441 static const struct rte_eth_desc_lim rx_desc_lim = {
442 .nb_max = IXGBE_MAX_RING_DESC,
443 .nb_min = IXGBE_MIN_RING_DESC,
444 .nb_align = IXGBE_RXD_ALIGN,
447 static const struct rte_eth_desc_lim tx_desc_lim = {
448 .nb_max = IXGBE_MAX_RING_DESC,
449 .nb_min = IXGBE_MIN_RING_DESC,
450 .nb_align = IXGBE_TXD_ALIGN,
453 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
454 .dev_configure = ixgbe_dev_configure,
455 .dev_start = ixgbe_dev_start,
456 .dev_stop = ixgbe_dev_stop,
457 .dev_set_link_up = ixgbe_dev_set_link_up,
458 .dev_set_link_down = ixgbe_dev_set_link_down,
459 .dev_close = ixgbe_dev_close,
460 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
461 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
462 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
463 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
464 .link_update = ixgbe_dev_link_update,
465 .stats_get = ixgbe_dev_stats_get,
466 .xstats_get = ixgbe_dev_xstats_get,
467 .stats_reset = ixgbe_dev_stats_reset,
468 .xstats_reset = ixgbe_dev_xstats_reset,
469 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
470 .dev_infos_get = ixgbe_dev_info_get,
471 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
472 .mtu_set = ixgbe_dev_mtu_set,
473 .vlan_filter_set = ixgbe_vlan_filter_set,
474 .vlan_tpid_set = ixgbe_vlan_tpid_set,
475 .vlan_offload_set = ixgbe_vlan_offload_set,
476 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
477 .rx_queue_start = ixgbe_dev_rx_queue_start,
478 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
479 .tx_queue_start = ixgbe_dev_tx_queue_start,
480 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
481 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
482 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
483 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
484 .rx_queue_release = ixgbe_dev_rx_queue_release,
485 .rx_queue_count = ixgbe_dev_rx_queue_count,
486 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
487 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
488 .tx_queue_release = ixgbe_dev_tx_queue_release,
489 .dev_led_on = ixgbe_dev_led_on,
490 .dev_led_off = ixgbe_dev_led_off,
491 .flow_ctrl_get = ixgbe_flow_ctrl_get,
492 .flow_ctrl_set = ixgbe_flow_ctrl_set,
493 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
494 .mac_addr_add = ixgbe_add_rar,
495 .mac_addr_remove = ixgbe_remove_rar,
496 .mac_addr_set = ixgbe_set_default_mac_addr,
497 .uc_hash_table_set = ixgbe_uc_hash_table_set,
498 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
499 .mirror_rule_set = ixgbe_mirror_rule_set,
500 .mirror_rule_reset = ixgbe_mirror_rule_reset,
501 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
502 .set_vf_rx = ixgbe_set_pool_rx,
503 .set_vf_tx = ixgbe_set_pool_tx,
504 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
505 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
506 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
507 .reta_update = ixgbe_dev_rss_reta_update,
508 .reta_query = ixgbe_dev_rss_reta_query,
509 #ifdef RTE_NIC_BYPASS
510 .bypass_init = ixgbe_bypass_init,
511 .bypass_state_set = ixgbe_bypass_state_store,
512 .bypass_state_show = ixgbe_bypass_state_show,
513 .bypass_event_set = ixgbe_bypass_event_store,
514 .bypass_event_show = ixgbe_bypass_event_show,
515 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
516 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
517 .bypass_ver_show = ixgbe_bypass_ver_show,
518 .bypass_wd_reset = ixgbe_bypass_wd_reset,
519 #endif /* RTE_NIC_BYPASS */
520 .rss_hash_update = ixgbe_dev_rss_hash_update,
521 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
522 .filter_ctrl = ixgbe_dev_filter_ctrl,
523 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
524 .rxq_info_get = ixgbe_rxq_info_get,
525 .txq_info_get = ixgbe_txq_info_get,
526 .timesync_enable = ixgbe_timesync_enable,
527 .timesync_disable = ixgbe_timesync_disable,
528 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
529 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
530 .get_reg_length = ixgbe_get_reg_length,
531 .get_reg = ixgbe_get_regs,
532 .get_eeprom_length = ixgbe_get_eeprom_length,
533 .get_eeprom = ixgbe_get_eeprom,
534 .set_eeprom = ixgbe_set_eeprom,
535 .get_dcb_info = ixgbe_dev_get_dcb_info,
536 .timesync_adjust_time = ixgbe_timesync_adjust_time,
537 .timesync_read_time = ixgbe_timesync_read_time,
538 .timesync_write_time = ixgbe_timesync_write_time,
539 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
540 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
541 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
542 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
546 * dev_ops for virtual function, bare necessities for basic vf
547 * operation have been implemented
549 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
550 .dev_configure = ixgbevf_dev_configure,
551 .dev_start = ixgbevf_dev_start,
552 .dev_stop = ixgbevf_dev_stop,
553 .link_update = ixgbe_dev_link_update,
554 .stats_get = ixgbevf_dev_stats_get,
555 .xstats_get = ixgbevf_dev_xstats_get,
556 .stats_reset = ixgbevf_dev_stats_reset,
557 .xstats_reset = ixgbevf_dev_stats_reset,
558 .dev_close = ixgbevf_dev_close,
559 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
560 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
561 .dev_infos_get = ixgbevf_dev_info_get,
562 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
563 .mtu_set = ixgbevf_dev_set_mtu,
564 .vlan_filter_set = ixgbevf_vlan_filter_set,
565 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
566 .vlan_offload_set = ixgbevf_vlan_offload_set,
567 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
568 .rx_queue_release = ixgbe_dev_rx_queue_release,
569 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
570 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
571 .tx_queue_release = ixgbe_dev_tx_queue_release,
572 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
573 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
574 .mac_addr_add = ixgbevf_add_mac_addr,
575 .mac_addr_remove = ixgbevf_remove_mac_addr,
576 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
577 .rxq_info_get = ixgbe_rxq_info_get,
578 .txq_info_get = ixgbe_txq_info_get,
579 .mac_addr_set = ixgbevf_set_default_mac_addr,
580 .get_reg_length = ixgbevf_get_reg_length,
581 .get_reg = ixgbevf_get_regs,
582 .reta_update = ixgbe_dev_rss_reta_update,
583 .reta_query = ixgbe_dev_rss_reta_query,
584 .rss_hash_update = ixgbe_dev_rss_hash_update,
585 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
588 /* store statistics names and its offset in stats structure */
589 struct rte_ixgbe_xstats_name_off {
590 char name[RTE_ETH_XSTATS_NAME_SIZE];
594 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
595 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
596 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
597 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
598 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
599 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
600 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
601 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
602 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
603 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
604 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
605 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
606 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
607 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
608 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
609 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
611 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
613 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
614 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
615 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
616 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
617 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
618 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
619 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
620 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
621 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
622 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
623 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
624 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
625 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
626 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
627 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
628 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
629 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
631 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
633 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
634 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
635 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
636 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
638 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
640 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
642 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
644 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
646 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
648 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
651 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
652 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
653 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
655 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
656 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
657 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
658 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
659 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
661 {"rx_fcoe_no_direct_data_placement_ext_buff",
662 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
664 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
666 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
668 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
670 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
672 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
675 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
676 sizeof(rte_ixgbe_stats_strings[0]))
678 /* Per-queue statistics */
679 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
680 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
681 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
682 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
683 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
686 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
687 sizeof(rte_ixgbe_rxq_strings[0]))
689 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
690 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
691 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
692 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
696 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
697 sizeof(rte_ixgbe_txq_strings[0]))
699 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
700 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
703 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
704 sizeof(rte_ixgbevf_stats_strings[0]))
707 * Atomically reads the link status information from global
708 * structure rte_eth_dev.
711 * - Pointer to the structure rte_eth_dev to read from.
712 * - Pointer to the buffer to be saved with the link status.
715 * - On success, zero.
716 * - On failure, negative value.
719 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
720 struct rte_eth_link *link)
722 struct rte_eth_link *dst = link;
723 struct rte_eth_link *src = &(dev->data->dev_link);
725 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
726 *(uint64_t *)src) == 0)
733 * Atomically writes the link status information into global
734 * structure rte_eth_dev.
737 * - Pointer to the structure rte_eth_dev to read from.
738 * - Pointer to the buffer to be saved with the link status.
741 * - On success, zero.
742 * - On failure, negative value.
745 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
746 struct rte_eth_link *link)
748 struct rte_eth_link *dst = &(dev->data->dev_link);
749 struct rte_eth_link *src = link;
751 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
752 *(uint64_t *)src) == 0)
759 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
762 ixgbe_is_sfp(struct ixgbe_hw *hw)
764 switch (hw->phy.type) {
765 case ixgbe_phy_sfp_avago:
766 case ixgbe_phy_sfp_ftl:
767 case ixgbe_phy_sfp_intel:
768 case ixgbe_phy_sfp_unknown:
769 case ixgbe_phy_sfp_passive_tyco:
770 case ixgbe_phy_sfp_passive_unknown:
777 static inline int32_t
778 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
783 status = ixgbe_reset_hw(hw);
785 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
786 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
787 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
788 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
789 IXGBE_WRITE_FLUSH(hw);
795 ixgbe_enable_intr(struct rte_eth_dev *dev)
797 struct ixgbe_interrupt *intr =
798 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
799 struct ixgbe_hw *hw =
800 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
802 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
803 IXGBE_WRITE_FLUSH(hw);
807 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
810 ixgbe_disable_intr(struct ixgbe_hw *hw)
812 PMD_INIT_FUNC_TRACE();
814 if (hw->mac.type == ixgbe_mac_82598EB) {
815 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
817 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
818 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
819 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
821 IXGBE_WRITE_FLUSH(hw);
825 * This function resets queue statistics mapping registers.
826 * From Niantic datasheet, Initialization of Statistics section:
827 * "...if software requires the queue counters, the RQSMR and TQSM registers
828 * must be re-programmed following a device reset.
831 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
835 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
836 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
837 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
843 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
848 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
849 #define NB_QMAP_FIELDS_PER_QSM_REG 4
850 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
852 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
853 struct ixgbe_stat_mapping_registers *stat_mappings =
854 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
855 uint32_t qsmr_mask = 0;
856 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
860 if ((hw->mac.type != ixgbe_mac_82599EB) &&
861 (hw->mac.type != ixgbe_mac_X540) &&
862 (hw->mac.type != ixgbe_mac_X550) &&
863 (hw->mac.type != ixgbe_mac_X550EM_x) &&
864 (hw->mac.type != ixgbe_mac_X550EM_a))
867 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
868 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
871 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
872 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
873 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
876 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
878 /* Now clear any previous stat_idx set */
879 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
881 stat_mappings->tqsm[n] &= ~clearing_mask;
883 stat_mappings->rqsmr[n] &= ~clearing_mask;
885 q_map = (uint32_t)stat_idx;
886 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
887 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
889 stat_mappings->tqsm[n] |= qsmr_mask;
891 stat_mappings->rqsmr[n] |= qsmr_mask;
893 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
894 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
896 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
897 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
899 /* Now write the mapping in the appropriate register */
901 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
902 stat_mappings->rqsmr[n], n);
903 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
906 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
907 stat_mappings->tqsm[n], n);
908 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
914 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
916 struct ixgbe_stat_mapping_registers *stat_mappings =
917 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
918 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
921 /* write whatever was in stat mapping table to the NIC */
922 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
924 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
927 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
932 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
935 struct ixgbe_dcb_tc_config *tc;
936 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
938 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
939 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
940 for (i = 0; i < dcb_max_tc; i++) {
941 tc = &dcb_config->tc_config[i];
942 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
943 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
944 (uint8_t)(100/dcb_max_tc + (i & 1));
945 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
946 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
947 (uint8_t)(100/dcb_max_tc + (i & 1));
948 tc->pfc = ixgbe_dcb_pfc_disabled;
951 /* Initialize default user to priority mapping, UPx->TC0 */
952 tc = &dcb_config->tc_config[0];
953 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
954 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
955 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
956 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
957 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
959 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
960 dcb_config->pfc_mode_enable = false;
961 dcb_config->vt_mode = true;
962 dcb_config->round_robin_enable = false;
963 /* support all DCB capabilities in 82599 */
964 dcb_config->support.capabilities = 0xFF;
966 /*we only support 4 Tcs for X540, X550 */
967 if (hw->mac.type == ixgbe_mac_X540 ||
968 hw->mac.type == ixgbe_mac_X550 ||
969 hw->mac.type == ixgbe_mac_X550EM_x ||
970 hw->mac.type == ixgbe_mac_X550EM_a) {
971 dcb_config->num_tcs.pg_tcs = 4;
972 dcb_config->num_tcs.pfc_tcs = 4;
977 * Ensure that all locks are released before first NVM or PHY access
980 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
985 * Phy lock should not fail in this early stage. If this is the case,
986 * it is due to an improper exit of the application.
987 * So force the release of the faulty lock. Release of common lock
988 * is done automatically by swfw_sync function.
990 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
991 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
992 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
994 ixgbe_release_swfw_semaphore(hw, mask);
997 * These ones are more tricky since they are common to all ports; but
998 * swfw_sync retries last long enough (1s) to be almost sure that if
999 * lock can not be taken it is due to an improper lock of the
1002 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1003 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1004 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1006 ixgbe_release_swfw_semaphore(hw, mask);
1010 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1011 * It returns 0 on success.
1014 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1016 struct rte_pci_device *pci_dev;
1017 struct ixgbe_hw *hw =
1018 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1019 struct ixgbe_vfta * shadow_vfta =
1020 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1021 struct ixgbe_hwstrip *hwstrip =
1022 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1023 struct ixgbe_dcb_config *dcb_config =
1024 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1025 struct ixgbe_filter_info *filter_info =
1026 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1031 PMD_INIT_FUNC_TRACE();
1033 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1034 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1035 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1038 * For secondary processes, we don't initialise any further as primary
1039 * has already done this work. Only check we don't need a different
1040 * RX and TX function.
1042 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1043 struct ixgbe_tx_queue *txq;
1044 /* TX queue function in primary, set by last queue initialized
1045 * Tx queue may not initialized by primary process */
1046 if (eth_dev->data->tx_queues) {
1047 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1048 ixgbe_set_tx_function(eth_dev, txq);
1050 /* Use default TX function if we get here */
1051 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1052 "Using default TX function.");
1055 ixgbe_set_rx_function(eth_dev);
1059 pci_dev = eth_dev->pci_dev;
1061 rte_eth_copy_pci_info(eth_dev, pci_dev);
1063 /* Vendor and Device ID need to be set before init of shared code */
1064 hw->device_id = pci_dev->id.device_id;
1065 hw->vendor_id = pci_dev->id.vendor_id;
1066 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1067 hw->allow_unsupported_sfp = 1;
1069 /* Initialize the shared code (base driver) */
1070 #ifdef RTE_NIC_BYPASS
1071 diag = ixgbe_bypass_init_shared_code(hw);
1073 diag = ixgbe_init_shared_code(hw);
1074 #endif /* RTE_NIC_BYPASS */
1076 if (diag != IXGBE_SUCCESS) {
1077 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1081 /* pick up the PCI bus settings for reporting later */
1082 ixgbe_get_bus_info(hw);
1084 /* Unlock any pending hardware semaphore */
1085 ixgbe_swfw_lock_reset(hw);
1087 /* Initialize DCB configuration*/
1088 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1089 ixgbe_dcb_init(hw,dcb_config);
1090 /* Get Hardware Flow Control setting */
1091 hw->fc.requested_mode = ixgbe_fc_full;
1092 hw->fc.current_mode = ixgbe_fc_full;
1093 hw->fc.pause_time = IXGBE_FC_PAUSE;
1094 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1095 hw->fc.low_water[i] = IXGBE_FC_LO;
1096 hw->fc.high_water[i] = IXGBE_FC_HI;
1098 hw->fc.send_xon = 1;
1100 /* Make sure we have a good EEPROM before we read from it */
1101 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1102 if (diag != IXGBE_SUCCESS) {
1103 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1107 #ifdef RTE_NIC_BYPASS
1108 diag = ixgbe_bypass_init_hw(hw);
1110 diag = ixgbe_init_hw(hw);
1111 #endif /* RTE_NIC_BYPASS */
1114 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1115 * is called too soon after the kernel driver unbinding/binding occurs.
1116 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1117 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1118 * also called. See ixgbe_identify_phy_82599(). The reason for the
1119 * failure is not known, and only occuts when virtualisation features
1120 * are disabled in the bios. A delay of 100ms was found to be enough by
1121 * trial-and-error, and is doubled to be safe.
1123 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1125 diag = ixgbe_init_hw(hw);
1128 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1129 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1130 "LOM. Please be aware there may be issues associated "
1131 "with your hardware.");
1132 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1133 "please contact your Intel or hardware representative "
1134 "who provided you with this hardware.");
1135 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1136 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1138 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1142 /* Reset the hw statistics */
1143 ixgbe_dev_stats_reset(eth_dev);
1145 /* disable interrupt */
1146 ixgbe_disable_intr(hw);
1148 /* reset mappings for queue statistics hw counters*/
1149 ixgbe_reset_qstat_mappings(hw);
1151 /* Allocate memory for storing MAC addresses */
1152 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1153 hw->mac.num_rar_entries, 0);
1154 if (eth_dev->data->mac_addrs == NULL) {
1156 "Failed to allocate %u bytes needed to store "
1158 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1161 /* Copy the permanent MAC address */
1162 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1163 ð_dev->data->mac_addrs[0]);
1165 /* Allocate memory for storing hash filter MAC addresses */
1166 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1167 IXGBE_VMDQ_NUM_UC_MAC, 0);
1168 if (eth_dev->data->hash_mac_addrs == NULL) {
1170 "Failed to allocate %d bytes needed to store MAC addresses",
1171 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1175 /* initialize the vfta */
1176 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1178 /* initialize the hw strip bitmap*/
1179 memset(hwstrip, 0, sizeof(*hwstrip));
1181 /* initialize PF if max_vfs not zero */
1182 ixgbe_pf_host_init(eth_dev);
1184 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1185 /* let hardware know driver is loaded */
1186 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1187 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1188 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1189 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1190 IXGBE_WRITE_FLUSH(hw);
1192 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1193 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1194 (int) hw->mac.type, (int) hw->phy.type,
1195 (int) hw->phy.sfp_type);
1197 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1198 (int) hw->mac.type, (int) hw->phy.type);
1200 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1201 eth_dev->data->port_id, pci_dev->id.vendor_id,
1202 pci_dev->id.device_id);
1204 rte_intr_callback_register(&pci_dev->intr_handle,
1205 ixgbe_dev_interrupt_handler,
1208 /* enable uio/vfio intr/eventfd mapping */
1209 rte_intr_enable(&pci_dev->intr_handle);
1211 /* enable support intr */
1212 ixgbe_enable_intr(eth_dev);
1214 /* initialize 5tuple filter list */
1215 TAILQ_INIT(&filter_info->fivetuple_list);
1216 memset(filter_info->fivetuple_mask, 0,
1217 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1223 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1225 struct rte_pci_device *pci_dev;
1226 struct ixgbe_hw *hw;
1228 PMD_INIT_FUNC_TRACE();
1230 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1233 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1234 pci_dev = eth_dev->pci_dev;
1236 if (hw->adapter_stopped == 0)
1237 ixgbe_dev_close(eth_dev);
1239 eth_dev->dev_ops = NULL;
1240 eth_dev->rx_pkt_burst = NULL;
1241 eth_dev->tx_pkt_burst = NULL;
1243 /* Unlock any pending hardware semaphore */
1244 ixgbe_swfw_lock_reset(hw);
1246 /* disable uio intr before callback unregister */
1247 rte_intr_disable(&(pci_dev->intr_handle));
1248 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1249 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1251 /* uninitialize PF if max_vfs not zero */
1252 ixgbe_pf_host_uninit(eth_dev);
1254 rte_free(eth_dev->data->mac_addrs);
1255 eth_dev->data->mac_addrs = NULL;
1257 rte_free(eth_dev->data->hash_mac_addrs);
1258 eth_dev->data->hash_mac_addrs = NULL;
1264 * Negotiate mailbox API version with the PF.
1265 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1266 * Then we try to negotiate starting with the most recent one.
1267 * If all negotiation attempts fail, then we will proceed with
1268 * the default one (ixgbe_mbox_api_10).
1271 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1275 /* start with highest supported, proceed down */
1276 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1283 i != RTE_DIM(sup_ver) &&
1284 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1290 generate_random_mac_addr(struct ether_addr *mac_addr)
1294 /* Set Organizationally Unique Identifier (OUI) prefix. */
1295 mac_addr->addr_bytes[0] = 0x00;
1296 mac_addr->addr_bytes[1] = 0x09;
1297 mac_addr->addr_bytes[2] = 0xC0;
1298 /* Force indication of locally assigned MAC address. */
1299 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1300 /* Generate the last 3 bytes of the MAC address with a random number. */
1301 random = rte_rand();
1302 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1306 * Virtual Function device init
1309 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1313 struct rte_pci_device *pci_dev;
1314 struct ixgbe_hw *hw =
1315 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1316 struct ixgbe_vfta * shadow_vfta =
1317 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1318 struct ixgbe_hwstrip *hwstrip =
1319 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1320 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1322 PMD_INIT_FUNC_TRACE();
1324 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1325 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1326 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1328 /* for secondary processes, we don't initialise any further as primary
1329 * has already done this work. Only check we don't need a different
1331 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1332 struct ixgbe_tx_queue *txq;
1333 /* TX queue function in primary, set by last queue initialized
1334 * Tx queue may not initialized by primary process
1336 if (eth_dev->data->tx_queues) {
1337 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1338 ixgbe_set_tx_function(eth_dev, txq);
1340 /* Use default TX function if we get here */
1341 PMD_INIT_LOG(NOTICE,
1342 "No TX queues configured yet. Using default TX function.");
1345 ixgbe_set_rx_function(eth_dev);
1350 pci_dev = eth_dev->pci_dev;
1352 rte_eth_copy_pci_info(eth_dev, pci_dev);
1354 hw->device_id = pci_dev->id.device_id;
1355 hw->vendor_id = pci_dev->id.vendor_id;
1356 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1358 /* initialize the vfta */
1359 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1361 /* initialize the hw strip bitmap*/
1362 memset(hwstrip, 0, sizeof(*hwstrip));
1364 /* Initialize the shared code (base driver) */
1365 diag = ixgbe_init_shared_code(hw);
1366 if (diag != IXGBE_SUCCESS) {
1367 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1371 /* init_mailbox_params */
1372 hw->mbx.ops.init_params(hw);
1374 /* Reset the hw statistics */
1375 ixgbevf_dev_stats_reset(eth_dev);
1377 /* Disable the interrupts for VF */
1378 ixgbevf_intr_disable(hw);
1380 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1381 diag = hw->mac.ops.reset_hw(hw);
1384 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1385 * the underlying PF driver has not assigned a MAC address to the VF.
1386 * In this case, assign a random MAC address.
1388 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1389 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1393 /* negotiate mailbox API version to use with the PF. */
1394 ixgbevf_negotiate_api(hw);
1396 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1397 ixgbevf_get_queues(hw, &tcs, &tc);
1399 /* Allocate memory for storing MAC addresses */
1400 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1401 hw->mac.num_rar_entries, 0);
1402 if (eth_dev->data->mac_addrs == NULL) {
1404 "Failed to allocate %u bytes needed to store "
1406 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1410 /* Generate a random MAC address, if none was assigned by PF. */
1411 if (is_zero_ether_addr(perm_addr)) {
1412 generate_random_mac_addr(perm_addr);
1413 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1415 rte_free(eth_dev->data->mac_addrs);
1416 eth_dev->data->mac_addrs = NULL;
1419 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1420 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1421 "%02x:%02x:%02x:%02x:%02x:%02x",
1422 perm_addr->addr_bytes[0],
1423 perm_addr->addr_bytes[1],
1424 perm_addr->addr_bytes[2],
1425 perm_addr->addr_bytes[3],
1426 perm_addr->addr_bytes[4],
1427 perm_addr->addr_bytes[5]);
1430 /* Copy the permanent MAC address */
1431 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1433 /* reset the hardware with the new settings */
1434 diag = hw->mac.ops.start_hw(hw);
1440 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1444 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1445 eth_dev->data->port_id, pci_dev->id.vendor_id,
1446 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1451 /* Virtual Function device uninit */
1454 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1456 struct ixgbe_hw *hw;
1458 PMD_INIT_FUNC_TRACE();
1460 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1463 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1465 if (hw->adapter_stopped == 0)
1466 ixgbevf_dev_close(eth_dev);
1468 eth_dev->dev_ops = NULL;
1469 eth_dev->rx_pkt_burst = NULL;
1470 eth_dev->tx_pkt_burst = NULL;
1472 /* Disable the interrupts for VF */
1473 ixgbevf_intr_disable(hw);
1475 rte_free(eth_dev->data->mac_addrs);
1476 eth_dev->data->mac_addrs = NULL;
1481 static struct eth_driver rte_ixgbe_pmd = {
1483 .name = "rte_ixgbe_pmd",
1484 .id_table = pci_id_ixgbe_map,
1485 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1486 RTE_PCI_DRV_DETACHABLE,
1488 .eth_dev_init = eth_ixgbe_dev_init,
1489 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1490 .dev_private_size = sizeof(struct ixgbe_adapter),
1494 * virtual function driver struct
1496 static struct eth_driver rte_ixgbevf_pmd = {
1498 .name = "rte_ixgbevf_pmd",
1499 .id_table = pci_id_ixgbevf_map,
1500 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1502 .eth_dev_init = eth_ixgbevf_dev_init,
1503 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1504 .dev_private_size = sizeof(struct ixgbe_adapter),
1508 * Driver initialization routine.
1509 * Invoked once at EAL init time.
1510 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1513 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1515 PMD_INIT_FUNC_TRACE();
1517 rte_eth_driver_register(&rte_ixgbe_pmd);
1522 * VF Driver initialization routine.
1523 * Invoked one at EAL init time.
1524 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1527 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1529 PMD_INIT_FUNC_TRACE();
1531 rte_eth_driver_register(&rte_ixgbevf_pmd);
1536 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1538 struct ixgbe_hw *hw =
1539 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1540 struct ixgbe_vfta * shadow_vfta =
1541 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1546 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1547 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1548 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1553 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1555 /* update local VFTA copy */
1556 shadow_vfta->vfta[vid_idx] = vfta;
1562 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1565 ixgbe_vlan_hw_strip_enable(dev, queue);
1567 ixgbe_vlan_hw_strip_disable(dev, queue);
1571 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1572 enum rte_vlan_type vlan_type,
1575 struct ixgbe_hw *hw =
1576 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1579 switch (vlan_type) {
1580 case ETH_VLAN_TYPE_INNER:
1581 /* Only the high 16-bits is valid */
1582 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1586 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1594 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1596 struct ixgbe_hw *hw =
1597 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1600 PMD_INIT_FUNC_TRACE();
1602 /* Filter Table Disable */
1603 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1604 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1606 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1610 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1612 struct ixgbe_hw *hw =
1613 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614 struct ixgbe_vfta * shadow_vfta =
1615 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1619 PMD_INIT_FUNC_TRACE();
1621 /* Filter Table Enable */
1622 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1623 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1624 vlnctrl |= IXGBE_VLNCTRL_VFE;
1626 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1628 /* write whatever is in local vfta copy */
1629 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1630 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1634 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1636 struct ixgbe_hwstrip *hwstrip =
1637 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1639 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1643 IXGBE_SET_HWSTRIP(hwstrip, queue);
1645 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1649 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1651 struct ixgbe_hw *hw =
1652 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655 PMD_INIT_FUNC_TRACE();
1657 if (hw->mac.type == ixgbe_mac_82598EB) {
1658 /* No queue level support */
1659 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1663 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1664 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1665 ctrl &= ~IXGBE_RXDCTL_VME;
1666 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1668 /* record those setting for HW strip per queue */
1669 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1673 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1675 struct ixgbe_hw *hw =
1676 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1679 PMD_INIT_FUNC_TRACE();
1681 if (hw->mac.type == ixgbe_mac_82598EB) {
1682 /* No queue level supported */
1683 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1687 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1688 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1689 ctrl |= IXGBE_RXDCTL_VME;
1690 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1692 /* record those setting for HW strip per queue */
1693 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1697 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1699 struct ixgbe_hw *hw =
1700 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704 PMD_INIT_FUNC_TRACE();
1706 if (hw->mac.type == ixgbe_mac_82598EB) {
1707 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1708 ctrl &= ~IXGBE_VLNCTRL_VME;
1709 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1712 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1713 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1714 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1715 ctrl &= ~IXGBE_RXDCTL_VME;
1716 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1718 /* record those setting for HW strip per queue */
1719 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1725 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1727 struct ixgbe_hw *hw =
1728 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1732 PMD_INIT_FUNC_TRACE();
1734 if (hw->mac.type == ixgbe_mac_82598EB) {
1735 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1736 ctrl |= IXGBE_VLNCTRL_VME;
1737 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1740 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1741 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1742 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1743 ctrl |= IXGBE_RXDCTL_VME;
1744 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1746 /* record those setting for HW strip per queue */
1747 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1753 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1755 struct ixgbe_hw *hw =
1756 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1759 PMD_INIT_FUNC_TRACE();
1761 /* DMATXCTRL: Geric Double VLAN Disable */
1762 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1763 ctrl &= ~IXGBE_DMATXCTL_GDV;
1764 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1766 /* CTRL_EXT: Global Double VLAN Disable */
1767 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1768 ctrl &= ~IXGBE_EXTENDED_VLAN;
1769 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1774 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1776 struct ixgbe_hw *hw =
1777 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1780 PMD_INIT_FUNC_TRACE();
1782 /* DMATXCTRL: Geric Double VLAN Enable */
1783 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1784 ctrl |= IXGBE_DMATXCTL_GDV;
1785 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1787 /* CTRL_EXT: Global Double VLAN Enable */
1788 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1789 ctrl |= IXGBE_EXTENDED_VLAN;
1790 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1792 /* Clear pooling mode of PFVTCTL. It's required by X550. */
1793 if (hw->mac.type == ixgbe_mac_X550 ||
1794 hw->mac.type == ixgbe_mac_X550EM_x ||
1795 hw->mac.type == ixgbe_mac_X550EM_a) {
1796 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1797 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1798 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1802 * VET EXT field in the EXVET register = 0x8100 by default
1803 * So no need to change. Same to VT field of DMATXCTL register
1808 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1810 if (mask & ETH_VLAN_STRIP_MASK) {
1811 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1812 ixgbe_vlan_hw_strip_enable_all(dev);
1814 ixgbe_vlan_hw_strip_disable_all(dev);
1817 if (mask & ETH_VLAN_FILTER_MASK) {
1818 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1819 ixgbe_vlan_hw_filter_enable(dev);
1821 ixgbe_vlan_hw_filter_disable(dev);
1824 if (mask & ETH_VLAN_EXTEND_MASK) {
1825 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1826 ixgbe_vlan_hw_extend_enable(dev);
1828 ixgbe_vlan_hw_extend_disable(dev);
1833 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1835 struct ixgbe_hw *hw =
1836 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1838 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1839 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1840 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1844 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1849 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1852 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1858 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1859 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1865 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1867 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1868 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1870 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1872 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1873 /* check multi-queue mode */
1874 switch (dev_conf->rxmode.mq_mode) {
1875 case ETH_MQ_RX_VMDQ_DCB:
1876 case ETH_MQ_RX_VMDQ_DCB_RSS:
1877 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1878 PMD_INIT_LOG(ERR, "SRIOV active,"
1879 " unsupported mq_mode rx %d.",
1880 dev_conf->rxmode.mq_mode);
1883 case ETH_MQ_RX_VMDQ_RSS:
1884 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1885 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1886 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1887 PMD_INIT_LOG(ERR, "SRIOV is active,"
1888 " invalid queue number"
1889 " for VMDQ RSS, allowed"
1890 " value are 1, 2 or 4.");
1894 case ETH_MQ_RX_VMDQ_ONLY:
1895 case ETH_MQ_RX_NONE:
1896 /* if nothing mq mode configure, use default scheme */
1897 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1898 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1899 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1901 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1902 /* SRIOV only works in VMDq enable mode */
1903 PMD_INIT_LOG(ERR, "SRIOV is active,"
1904 " wrong mq_mode rx %d.",
1905 dev_conf->rxmode.mq_mode);
1909 switch (dev_conf->txmode.mq_mode) {
1910 case ETH_MQ_TX_VMDQ_DCB:
1911 /* DCB VMDQ in SRIOV mode, not implement yet */
1912 PMD_INIT_LOG(ERR, "SRIOV is active,"
1913 " unsupported VMDQ mq_mode tx %d.",
1914 dev_conf->txmode.mq_mode);
1916 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1917 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1921 /* check valid queue number */
1922 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1923 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1924 PMD_INIT_LOG(ERR, "SRIOV is active,"
1925 " nb_rx_q=%d nb_tx_q=%d queue number"
1926 " must be less than or equal to %d.",
1928 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1932 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1933 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1937 /* check configuration for vmdb+dcb mode */
1938 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1939 const struct rte_eth_vmdq_dcb_conf *conf;
1941 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1942 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1943 IXGBE_VMDQ_DCB_NB_QUEUES);
1946 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1947 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1948 conf->nb_queue_pools == ETH_32_POOLS)) {
1949 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1950 " nb_queue_pools must be %d or %d.",
1951 ETH_16_POOLS, ETH_32_POOLS);
1955 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1956 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1958 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1959 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1960 IXGBE_VMDQ_DCB_NB_QUEUES);
1963 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1964 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1965 conf->nb_queue_pools == ETH_32_POOLS)) {
1966 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1967 " nb_queue_pools != %d and"
1968 " nb_queue_pools != %d.",
1969 ETH_16_POOLS, ETH_32_POOLS);
1974 /* For DCB mode check our configuration before we go further */
1975 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1976 const struct rte_eth_dcb_rx_conf *conf;
1978 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1979 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1980 IXGBE_DCB_NB_QUEUES);
1983 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1984 if (!(conf->nb_tcs == ETH_4_TCS ||
1985 conf->nb_tcs == ETH_8_TCS)) {
1986 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1987 " and nb_tcs != %d.",
1988 ETH_4_TCS, ETH_8_TCS);
1993 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1994 const struct rte_eth_dcb_tx_conf *conf;
1996 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1997 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1998 IXGBE_DCB_NB_QUEUES);
2001 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2002 if (!(conf->nb_tcs == ETH_4_TCS ||
2003 conf->nb_tcs == ETH_8_TCS)) {
2004 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2005 " and nb_tcs != %d.",
2006 ETH_4_TCS, ETH_8_TCS);
2012 * When DCB/VT is off, maximum number of queues changes,
2013 * except for 82598EB, which remains constant.
2015 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2016 hw->mac.type != ixgbe_mac_82598EB) {
2017 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2019 "Neither VT nor DCB are enabled, "
2021 IXGBE_NONE_MODE_TX_NB_QUEUES);
2030 ixgbe_dev_configure(struct rte_eth_dev *dev)
2032 struct ixgbe_interrupt *intr =
2033 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2034 struct ixgbe_adapter *adapter =
2035 (struct ixgbe_adapter *)dev->data->dev_private;
2038 PMD_INIT_FUNC_TRACE();
2039 /* multipe queue mode checking */
2040 ret = ixgbe_check_mq_mode(dev);
2042 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2047 /* set flag to update link status after init */
2048 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2051 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2052 * allocation or vector Rx preconditions we will reset it.
2054 adapter->rx_bulk_alloc_allowed = true;
2055 adapter->rx_vec_allowed = true;
2061 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2063 struct ixgbe_hw *hw =
2064 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065 struct ixgbe_interrupt *intr =
2066 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2069 /* only set up it on X550EM_X */
2070 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2071 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2072 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2073 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2074 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2075 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2080 * Configure device link speed and setup link.
2081 * It returns 0 on success.
2084 ixgbe_dev_start(struct rte_eth_dev *dev)
2086 struct ixgbe_hw *hw =
2087 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088 struct ixgbe_vf_info *vfinfo =
2089 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2090 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2091 uint32_t intr_vector = 0;
2092 int err, link_up = 0, negotiate = 0;
2097 uint32_t *link_speeds;
2099 PMD_INIT_FUNC_TRACE();
2101 /* IXGBE devices don't support:
2102 * - half duplex (checked afterwards for valid speeds)
2103 * - fixed speed: TODO implement
2105 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2106 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2107 dev->data->port_id);
2111 /* disable uio/vfio intr/eventfd mapping */
2112 rte_intr_disable(intr_handle);
2115 hw->adapter_stopped = 0;
2116 ixgbe_stop_adapter(hw);
2118 /* reinitialize adapter
2119 * this calls reset and start */
2120 status = ixgbe_pf_reset_hw(hw);
2123 hw->mac.ops.start_hw(hw);
2124 hw->mac.get_link_status = true;
2126 /* configure PF module if SRIOV enabled */
2127 ixgbe_pf_host_configure(dev);
2129 ixgbe_dev_phy_intr_setup(dev);
2131 /* check and configure queue intr-vector mapping */
2132 if ((rte_intr_cap_multiple(intr_handle) ||
2133 !RTE_ETH_DEV_SRIOV(dev).active) &&
2134 dev->data->dev_conf.intr_conf.rxq != 0) {
2135 intr_vector = dev->data->nb_rx_queues;
2136 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2137 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2138 IXGBE_MAX_INTR_QUEUE_NUM);
2141 if (rte_intr_efd_enable(intr_handle, intr_vector))
2145 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2146 intr_handle->intr_vec =
2147 rte_zmalloc("intr_vec",
2148 dev->data->nb_rx_queues * sizeof(int), 0);
2149 if (intr_handle->intr_vec == NULL) {
2150 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2151 " intr_vec\n", dev->data->nb_rx_queues);
2156 /* confiugre msix for sleep until rx interrupt */
2157 ixgbe_configure_msix(dev);
2159 /* initialize transmission unit */
2160 ixgbe_dev_tx_init(dev);
2162 /* This can fail when allocating mbufs for descriptor rings */
2163 err = ixgbe_dev_rx_init(dev);
2165 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2169 err = ixgbe_dev_rxtx_start(dev);
2171 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2175 /* Skip link setup if loopback mode is enabled for 82599. */
2176 if (hw->mac.type == ixgbe_mac_82599EB &&
2177 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2178 goto skip_link_setup;
2180 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2181 err = hw->mac.ops.setup_sfp(hw);
2186 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2187 /* Turn on the copper */
2188 ixgbe_set_phy_power(hw, true);
2190 /* Turn on the laser */
2191 ixgbe_enable_tx_laser(hw);
2194 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2197 dev->data->dev_link.link_status = link_up;
2199 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2203 link_speeds = &dev->data->dev_conf.link_speeds;
2204 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2205 ETH_LINK_SPEED_10G)) {
2206 PMD_INIT_LOG(ERR, "Invalid link setting");
2211 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2212 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2213 IXGBE_LINK_SPEED_82599_AUTONEG :
2214 IXGBE_LINK_SPEED_82598_AUTONEG;
2216 if (*link_speeds & ETH_LINK_SPEED_10G)
2217 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2218 if (*link_speeds & ETH_LINK_SPEED_1G)
2219 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2220 if (*link_speeds & ETH_LINK_SPEED_100M)
2221 speed |= IXGBE_LINK_SPEED_100_FULL;
2224 err = ixgbe_setup_link(hw, speed, link_up);
2230 if (rte_intr_allow_others(intr_handle)) {
2231 /* check if lsc interrupt is enabled */
2232 if (dev->data->dev_conf.intr_conf.lsc != 0)
2233 ixgbe_dev_lsc_interrupt_setup(dev);
2235 rte_intr_callback_unregister(intr_handle,
2236 ixgbe_dev_interrupt_handler,
2238 if (dev->data->dev_conf.intr_conf.lsc != 0)
2239 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2240 " no intr multiplex\n");
2243 /* check if rxq interrupt is enabled */
2244 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2245 rte_intr_dp_is_en(intr_handle))
2246 ixgbe_dev_rxq_interrupt_setup(dev);
2248 /* enable uio/vfio intr/eventfd mapping */
2249 rte_intr_enable(intr_handle);
2251 /* resume enabled intr since hw reset */
2252 ixgbe_enable_intr(dev);
2254 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2255 ETH_VLAN_EXTEND_MASK;
2256 ixgbe_vlan_offload_set(dev, mask);
2258 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2259 /* Enable vlan filtering for VMDq */
2260 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2263 /* Configure DCB hw */
2264 ixgbe_configure_dcb(dev);
2266 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2267 err = ixgbe_fdir_configure(dev);
2272 /* Restore vf rate limit */
2273 if (vfinfo != NULL) {
2274 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2275 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2276 if (vfinfo[vf].tx_rate[idx] != 0)
2277 ixgbe_set_vf_rate_limit(dev, vf,
2278 vfinfo[vf].tx_rate[idx],
2282 ixgbe_restore_statistics_mapping(dev);
2287 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2288 ixgbe_dev_clear_queues(dev);
2293 * Stop device: disable rx and tx functions to allow for reconfiguring.
2296 ixgbe_dev_stop(struct rte_eth_dev *dev)
2298 struct rte_eth_link link;
2299 struct ixgbe_hw *hw =
2300 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2301 struct ixgbe_vf_info *vfinfo =
2302 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2303 struct ixgbe_filter_info *filter_info =
2304 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2305 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2306 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2309 PMD_INIT_FUNC_TRACE();
2311 /* disable interrupts */
2312 ixgbe_disable_intr(hw);
2315 ixgbe_pf_reset_hw(hw);
2316 hw->adapter_stopped = 0;
2319 ixgbe_stop_adapter(hw);
2321 for (vf = 0; vfinfo != NULL &&
2322 vf < dev->pci_dev->max_vfs; vf++)
2323 vfinfo[vf].clear_to_send = false;
2325 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2326 /* Turn off the copper */
2327 ixgbe_set_phy_power(hw, false);
2329 /* Turn off the laser */
2330 ixgbe_disable_tx_laser(hw);
2333 ixgbe_dev_clear_queues(dev);
2335 /* Clear stored conf */
2336 dev->data->scattered_rx = 0;
2339 /* Clear recorded link status */
2340 memset(&link, 0, sizeof(link));
2341 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2343 /* Remove all ntuple filters of the device */
2344 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2345 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2346 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2347 TAILQ_REMOVE(&filter_info->fivetuple_list,
2351 memset(filter_info->fivetuple_mask, 0,
2352 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2354 if (!rte_intr_allow_others(intr_handle))
2355 /* resume to the default handler */
2356 rte_intr_callback_register(intr_handle,
2357 ixgbe_dev_interrupt_handler,
2360 /* Clean datapath event and queue/vec mapping */
2361 rte_intr_efd_disable(intr_handle);
2362 if (intr_handle->intr_vec != NULL) {
2363 rte_free(intr_handle->intr_vec);
2364 intr_handle->intr_vec = NULL;
2369 * Set device link up: enable tx.
2372 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2374 struct ixgbe_hw *hw =
2375 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2376 if (hw->mac.type == ixgbe_mac_82599EB) {
2377 #ifdef RTE_NIC_BYPASS
2378 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2379 /* Not suported in bypass mode */
2380 PMD_INIT_LOG(ERR, "Set link up is not supported "
2381 "by device id 0x%x", hw->device_id);
2387 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2388 /* Turn on the copper */
2389 ixgbe_set_phy_power(hw, true);
2391 /* Turn on the laser */
2392 ixgbe_enable_tx_laser(hw);
2399 * Set device link down: disable tx.
2402 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2404 struct ixgbe_hw *hw =
2405 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2406 if (hw->mac.type == ixgbe_mac_82599EB) {
2407 #ifdef RTE_NIC_BYPASS
2408 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2409 /* Not suported in bypass mode */
2410 PMD_INIT_LOG(ERR, "Set link down is not supported "
2411 "by device id 0x%x", hw->device_id);
2417 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2418 /* Turn off the copper */
2419 ixgbe_set_phy_power(hw, false);
2421 /* Turn off the laser */
2422 ixgbe_disable_tx_laser(hw);
2429 * Reest and stop device.
2432 ixgbe_dev_close(struct rte_eth_dev *dev)
2434 struct ixgbe_hw *hw =
2435 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2437 PMD_INIT_FUNC_TRACE();
2439 ixgbe_pf_reset_hw(hw);
2441 ixgbe_dev_stop(dev);
2442 hw->adapter_stopped = 1;
2444 ixgbe_dev_free_queues(dev);
2446 ixgbe_disable_pcie_master(hw);
2448 /* reprogram the RAR[0] in case user changed it. */
2449 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2453 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2454 struct ixgbe_hw_stats *hw_stats,
2455 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2456 uint64_t *total_qprc, uint64_t *total_qprdc)
2458 uint32_t bprc, lxon, lxoff, total;
2459 uint32_t delta_gprc = 0;
2461 /* Workaround for RX byte count not including CRC bytes when CRC
2462 + * strip is enabled. CRC bytes are removed from counters when crc_strip
2465 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2466 IXGBE_HLREG0_RXCRCSTRP);
2468 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2469 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2470 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2471 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2473 for (i = 0; i < 8; i++) {
2475 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2476 /* global total per queue */
2477 hw_stats->mpc[i] += mp;
2478 /* Running comprehensive total for stats display */
2479 *total_missed_rx += hw_stats->mpc[i];
2480 if (hw->mac.type == ixgbe_mac_82598EB) {
2481 hw_stats->rnbc[i] +=
2482 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2483 hw_stats->pxonrxc[i] +=
2484 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2485 hw_stats->pxoffrxc[i] +=
2486 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2488 hw_stats->pxonrxc[i] +=
2489 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2490 hw_stats->pxoffrxc[i] +=
2491 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2492 hw_stats->pxon2offc[i] +=
2493 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2495 hw_stats->pxontxc[i] +=
2496 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2497 hw_stats->pxofftxc[i] +=
2498 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2500 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2501 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2502 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2503 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2505 delta_gprc += delta_qprc;
2507 hw_stats->qprc[i] += delta_qprc;
2508 hw_stats->qptc[i] += delta_qptc;
2510 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2511 hw_stats->qbrc[i] +=
2512 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2514 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2516 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2517 hw_stats->qbtc[i] +=
2518 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2520 hw_stats->qprdc[i] += delta_qprdc;
2521 *total_qprdc += hw_stats->qprdc[i];
2523 *total_qprc += hw_stats->qprc[i];
2524 *total_qbrc += hw_stats->qbrc[i];
2526 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2527 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2528 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2531 * An errata states that gprc actually counts good + missed packets:
2532 * Workaround to set gprc to summated queue packet receives
2534 hw_stats->gprc = *total_qprc;
2536 if (hw->mac.type != ixgbe_mac_82598EB) {
2537 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2538 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2539 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2540 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2541 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2542 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2543 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2544 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2546 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2547 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2548 /* 82598 only has a counter in the high register */
2549 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2550 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2551 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2553 uint64_t old_tpr = hw_stats->tpr;
2555 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2556 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2559 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2561 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2562 hw_stats->gptc += delta_gptc;
2563 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2564 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2567 * Workaround: mprc hardware is incorrectly counting
2568 * broadcasts, so for now we subtract those.
2570 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2571 hw_stats->bprc += bprc;
2572 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2573 if (hw->mac.type == ixgbe_mac_82598EB)
2574 hw_stats->mprc -= bprc;
2576 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2577 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2578 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2579 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2580 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2581 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2583 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2584 hw_stats->lxontxc += lxon;
2585 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2586 hw_stats->lxofftxc += lxoff;
2587 total = lxon + lxoff;
2589 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2590 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2591 hw_stats->gptc -= total;
2592 hw_stats->mptc -= total;
2593 hw_stats->ptc64 -= total;
2594 hw_stats->gotc -= total * ETHER_MIN_LEN;
2596 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2597 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2598 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2599 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2600 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2601 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2602 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2603 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2604 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2605 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2606 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2607 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2608 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2609 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2610 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2611 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2612 /* Only read FCOE on 82599 */
2613 if (hw->mac.type != ixgbe_mac_82598EB) {
2614 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2615 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2616 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2617 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2618 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2621 /* Flow Director Stats registers */
2622 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2623 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2627 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2630 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2632 struct ixgbe_hw *hw =
2633 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2634 struct ixgbe_hw_stats *hw_stats =
2635 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2636 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2639 total_missed_rx = 0;
2644 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2645 &total_qprc, &total_qprdc);
2650 /* Fill out the rte_eth_stats statistics structure */
2651 stats->ipackets = total_qprc;
2652 stats->ibytes = total_qbrc;
2653 stats->opackets = hw_stats->gptc;
2654 stats->obytes = hw_stats->gotc;
2656 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2657 stats->q_ipackets[i] = hw_stats->qprc[i];
2658 stats->q_opackets[i] = hw_stats->qptc[i];
2659 stats->q_ibytes[i] = hw_stats->qbrc[i];
2660 stats->q_obytes[i] = hw_stats->qbtc[i];
2661 stats->q_errors[i] = hw_stats->qprdc[i];
2665 stats->imissed = total_missed_rx;
2666 stats->ierrors = hw_stats->crcerrs +
2682 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2684 struct ixgbe_hw_stats *stats =
2685 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2687 /* HW registers are cleared on read */
2688 ixgbe_dev_stats_get(dev, NULL);
2690 /* Reset software totals */
2691 memset(stats, 0, sizeof(*stats));
2694 /* This function calculates the number of xstats based on the current config */
2696 ixgbe_xstats_calc_num(void) {
2697 return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2698 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2702 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2705 struct ixgbe_hw *hw =
2706 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2707 struct ixgbe_hw_stats *hw_stats =
2708 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2709 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2710 unsigned i, stat, count = 0;
2712 count = ixgbe_xstats_calc_num();
2717 total_missed_rx = 0;
2722 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2723 &total_qprc, &total_qprdc);
2725 /* If this is a reset xstats is NULL, and we have cleared the
2726 * registers by reading them.
2731 /* Extended stats from ixgbe_hw_stats */
2733 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2734 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2735 rte_ixgbe_stats_strings[i].name);
2736 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2737 rte_ixgbe_stats_strings[i].offset);
2741 /* RX Priority Stats */
2742 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2743 for (i = 0; i < 8; i++) {
2744 snprintf(xstats[count].name, sizeof(xstats[count].name),
2745 "rx_priority%u_%s", i,
2746 rte_ixgbe_rxq_strings[stat].name);
2747 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2748 rte_ixgbe_rxq_strings[stat].offset +
2749 (sizeof(uint64_t) * i));
2754 /* TX Priority Stats */
2755 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2756 for (i = 0; i < 8; i++) {
2757 snprintf(xstats[count].name, sizeof(xstats[count].name),
2758 "tx_priority%u_%s", i,
2759 rte_ixgbe_txq_strings[stat].name);
2760 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2761 rte_ixgbe_txq_strings[stat].offset +
2762 (sizeof(uint64_t) * i));
2771 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2773 struct ixgbe_hw_stats *stats =
2774 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2776 unsigned count = ixgbe_xstats_calc_num();
2778 /* HW registers are cleared on read */
2779 ixgbe_dev_xstats_get(dev, NULL, count);
2781 /* Reset software totals */
2782 memset(stats, 0, sizeof(*stats));
2786 ixgbevf_update_stats(struct rte_eth_dev *dev)
2788 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2789 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2790 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2792 /* Good Rx packet, include VF loopback */
2793 UPDATE_VF_STAT(IXGBE_VFGPRC,
2794 hw_stats->last_vfgprc, hw_stats->vfgprc);
2796 /* Good Rx octets, include VF loopback */
2797 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2798 hw_stats->last_vfgorc, hw_stats->vfgorc);
2800 /* Good Tx packet, include VF loopback */
2801 UPDATE_VF_STAT(IXGBE_VFGPTC,
2802 hw_stats->last_vfgptc, hw_stats->vfgptc);
2804 /* Good Tx octets, include VF loopback */
2805 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2806 hw_stats->last_vfgotc, hw_stats->vfgotc);
2808 /* Rx Multicst Packet */
2809 UPDATE_VF_STAT(IXGBE_VFMPRC,
2810 hw_stats->last_vfmprc, hw_stats->vfmprc);
2814 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2817 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2818 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2821 if (n < IXGBEVF_NB_XSTATS)
2822 return IXGBEVF_NB_XSTATS;
2824 ixgbevf_update_stats(dev);
2829 /* Extended stats */
2830 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2831 snprintf(xstats[i].name, sizeof(xstats[i].name),
2832 "%s", rte_ixgbevf_stats_strings[i].name);
2833 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2834 rte_ixgbevf_stats_strings[i].offset);
2837 return IXGBEVF_NB_XSTATS;
2841 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2843 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2844 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2846 ixgbevf_update_stats(dev);
2851 stats->ipackets = hw_stats->vfgprc;
2852 stats->ibytes = hw_stats->vfgorc;
2853 stats->opackets = hw_stats->vfgptc;
2854 stats->obytes = hw_stats->vfgotc;
2855 stats->imcasts = hw_stats->vfmprc;
2856 /* stats->imcasts should be removed as imcasts is deprecated */
2860 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2862 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2863 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2865 /* Sync HW register to the last stats */
2866 ixgbevf_dev_stats_get(dev, NULL);
2868 /* reset HW current stats*/
2869 hw_stats->vfgprc = 0;
2870 hw_stats->vfgorc = 0;
2871 hw_stats->vfgptc = 0;
2872 hw_stats->vfgotc = 0;
2873 hw_stats->vfmprc = 0;
2878 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2880 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2881 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2883 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2884 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2885 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
2887 * When DCB/VT is off, maximum number of queues changes,
2888 * except for 82598EB, which remains constant.
2890 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2891 hw->mac.type != ixgbe_mac_82598EB)
2892 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
2894 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2895 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2896 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2897 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2898 dev_info->max_vfs = dev->pci_dev->max_vfs;
2899 if (hw->mac.type == ixgbe_mac_82598EB)
2900 dev_info->max_vmdq_pools = ETH_16_POOLS;
2902 dev_info->max_vmdq_pools = ETH_64_POOLS;
2903 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2904 dev_info->rx_offload_capa =
2905 DEV_RX_OFFLOAD_VLAN_STRIP |
2906 DEV_RX_OFFLOAD_IPV4_CKSUM |
2907 DEV_RX_OFFLOAD_UDP_CKSUM |
2908 DEV_RX_OFFLOAD_TCP_CKSUM;
2911 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2914 if ((hw->mac.type == ixgbe_mac_82599EB ||
2915 hw->mac.type == ixgbe_mac_X540) &&
2916 !RTE_ETH_DEV_SRIOV(dev).active)
2917 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2919 if (hw->mac.type == ixgbe_mac_X550 ||
2920 hw->mac.type == ixgbe_mac_X550EM_x ||
2921 hw->mac.type == ixgbe_mac_X550EM_a)
2922 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2924 dev_info->tx_offload_capa =
2925 DEV_TX_OFFLOAD_VLAN_INSERT |
2926 DEV_TX_OFFLOAD_IPV4_CKSUM |
2927 DEV_TX_OFFLOAD_UDP_CKSUM |
2928 DEV_TX_OFFLOAD_TCP_CKSUM |
2929 DEV_TX_OFFLOAD_SCTP_CKSUM |
2930 DEV_TX_OFFLOAD_TCP_TSO;
2932 if (hw->mac.type == ixgbe_mac_X550 ||
2933 hw->mac.type == ixgbe_mac_X550EM_x ||
2934 hw->mac.type == ixgbe_mac_X550EM_a)
2935 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2937 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2939 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2940 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2941 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2943 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2947 dev_info->default_txconf = (struct rte_eth_txconf) {
2949 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2950 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2951 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2953 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2954 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2955 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2956 ETH_TXQ_FLAGS_NOOFFLOADS,
2959 dev_info->rx_desc_lim = rx_desc_lim;
2960 dev_info->tx_desc_lim = tx_desc_lim;
2962 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2963 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2964 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2966 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2967 if (hw->mac.type == ixgbe_mac_X540 ||
2968 hw->mac.type == ixgbe_mac_X540_vf ||
2969 hw->mac.type == ixgbe_mac_X550 ||
2970 hw->mac.type == ixgbe_mac_X550_vf) {
2971 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2975 static const uint32_t *
2976 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2978 static const uint32_t ptypes[] = {
2979 /* For non-vec functions,
2980 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
2981 * for vec functions,
2982 * refers to _recv_raw_pkts_vec().
2986 RTE_PTYPE_L3_IPV4_EXT,
2988 RTE_PTYPE_L3_IPV6_EXT,
2992 RTE_PTYPE_TUNNEL_IP,
2993 RTE_PTYPE_INNER_L3_IPV6,
2994 RTE_PTYPE_INNER_L3_IPV6_EXT,
2995 RTE_PTYPE_INNER_L4_TCP,
2996 RTE_PTYPE_INNER_L4_UDP,
3000 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3001 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3002 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3003 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3009 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3010 struct rte_eth_dev_info *dev_info)
3012 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3014 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3015 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3016 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3017 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3018 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3019 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3020 dev_info->max_vfs = dev->pci_dev->max_vfs;
3021 if (hw->mac.type == ixgbe_mac_82598EB)
3022 dev_info->max_vmdq_pools = ETH_16_POOLS;
3024 dev_info->max_vmdq_pools = ETH_64_POOLS;
3025 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3026 DEV_RX_OFFLOAD_IPV4_CKSUM |
3027 DEV_RX_OFFLOAD_UDP_CKSUM |
3028 DEV_RX_OFFLOAD_TCP_CKSUM;
3029 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3030 DEV_TX_OFFLOAD_IPV4_CKSUM |
3031 DEV_TX_OFFLOAD_UDP_CKSUM |
3032 DEV_TX_OFFLOAD_TCP_CKSUM |
3033 DEV_TX_OFFLOAD_SCTP_CKSUM |
3034 DEV_TX_OFFLOAD_TCP_TSO;
3036 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3038 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3039 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3040 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3042 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3046 dev_info->default_txconf = (struct rte_eth_txconf) {
3048 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3049 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3050 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3052 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3053 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3054 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3055 ETH_TXQ_FLAGS_NOOFFLOADS,
3058 dev_info->rx_desc_lim = rx_desc_lim;
3059 dev_info->tx_desc_lim = tx_desc_lim;
3062 /* return 0 means link status changed, -1 means not changed */
3064 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3066 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3067 struct rte_eth_link link, old;
3068 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3072 link.link_status = ETH_LINK_DOWN;
3073 link.link_speed = 0;
3074 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3075 memset(&old, 0, sizeof(old));
3076 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3078 hw->mac.get_link_status = true;
3080 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3081 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3082 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3084 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3087 link.link_speed = ETH_SPEED_NUM_100M;
3088 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3089 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3090 if (link.link_status == old.link_status)
3096 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3097 if (link.link_status == old.link_status)
3101 link.link_status = ETH_LINK_UP;
3102 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3104 switch (link_speed) {
3106 case IXGBE_LINK_SPEED_UNKNOWN:
3107 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3108 link.link_speed = ETH_SPEED_NUM_100M;
3111 case IXGBE_LINK_SPEED_100_FULL:
3112 link.link_speed = ETH_SPEED_NUM_100M;
3115 case IXGBE_LINK_SPEED_1GB_FULL:
3116 link.link_speed = ETH_SPEED_NUM_1G;
3119 case IXGBE_LINK_SPEED_10GB_FULL:
3120 link.link_speed = ETH_SPEED_NUM_10G;
3123 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3125 if (link.link_status == old.link_status)
3132 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3134 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3137 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3138 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3139 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3143 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3145 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3148 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3149 fctrl &= (~IXGBE_FCTRL_UPE);
3150 if (dev->data->all_multicast == 1)
3151 fctrl |= IXGBE_FCTRL_MPE;
3153 fctrl &= (~IXGBE_FCTRL_MPE);
3154 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3158 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3160 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3163 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3164 fctrl |= IXGBE_FCTRL_MPE;
3165 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3169 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3171 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3174 if (dev->data->promiscuous == 1)
3175 return; /* must remain in all_multicast mode */
3177 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3178 fctrl &= (~IXGBE_FCTRL_MPE);
3179 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3183 * It clears the interrupt causes and enables the interrupt.
3184 * It will be called once only during nic initialized.
3187 * Pointer to struct rte_eth_dev.
3190 * - On success, zero.
3191 * - On failure, a negative value.
3194 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3196 struct ixgbe_interrupt *intr =
3197 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3199 ixgbe_dev_link_status_print(dev);
3200 intr->mask |= IXGBE_EICR_LSC;
3206 * It clears the interrupt causes and enables the interrupt.
3207 * It will be called once only during nic initialized.
3210 * Pointer to struct rte_eth_dev.
3213 * - On success, zero.
3214 * - On failure, a negative value.
3217 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3219 struct ixgbe_interrupt *intr =
3220 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3222 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3228 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3231 * Pointer to struct rte_eth_dev.
3234 * - On success, zero.
3235 * - On failure, a negative value.
3238 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3241 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3242 struct ixgbe_interrupt *intr =
3243 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3245 /* clear all cause mask */
3246 ixgbe_disable_intr(hw);
3248 /* read-on-clear nic registers here */
3249 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3250 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3254 /* set flag for async link update */
3255 if (eicr & IXGBE_EICR_LSC)
3256 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3258 if (eicr & IXGBE_EICR_MAILBOX)
3259 intr->flags |= IXGBE_FLAG_MAILBOX;
3261 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3262 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3263 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3264 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3270 * It gets and then prints the link status.
3273 * Pointer to struct rte_eth_dev.
3276 * - On success, zero.
3277 * - On failure, a negative value.
3280 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3282 struct rte_eth_link link;
3284 memset(&link, 0, sizeof(link));
3285 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3286 if (link.link_status) {
3287 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3288 (int)(dev->data->port_id),
3289 (unsigned)link.link_speed,
3290 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3291 "full-duplex" : "half-duplex");
3293 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3294 (int)(dev->data->port_id));
3296 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3297 dev->pci_dev->addr.domain,
3298 dev->pci_dev->addr.bus,
3299 dev->pci_dev->addr.devid,
3300 dev->pci_dev->addr.function);
3304 * It executes link_update after knowing an interrupt occurred.
3307 * Pointer to struct rte_eth_dev.
3310 * - On success, zero.
3311 * - On failure, a negative value.
3314 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3316 struct ixgbe_interrupt *intr =
3317 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3319 struct rte_eth_link link;
3320 int intr_enable_delay = false;
3321 struct ixgbe_hw *hw =
3322 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3324 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3326 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3327 ixgbe_pf_mbx_process(dev);
3328 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3331 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3332 ixgbe_handle_lasi(hw);
3333 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3336 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3337 /* get the link status before link update, for predicting later */
3338 memset(&link, 0, sizeof(link));
3339 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3341 ixgbe_dev_link_update(dev, 0);
3344 if (!link.link_status)
3345 /* handle it 1 sec later, wait it being stable */
3346 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3347 /* likely to down */
3349 /* handle it 4 sec later, wait it being stable */
3350 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3352 ixgbe_dev_link_status_print(dev);
3354 intr_enable_delay = true;
3357 if (intr_enable_delay) {
3358 if (rte_eal_alarm_set(timeout * 1000,
3359 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3360 PMD_DRV_LOG(ERR, "Error setting alarm");
3362 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3363 ixgbe_enable_intr(dev);
3364 rte_intr_enable(&(dev->pci_dev->intr_handle));
3372 * Interrupt handler which shall be registered for alarm callback for delayed
3373 * handling specific interrupt to wait for the stable nic state. As the
3374 * NIC interrupt state is not stable for ixgbe after link is just down,
3375 * it needs to wait 4 seconds to get the stable status.
3378 * Pointer to interrupt handle.
3380 * The address of parameter (struct rte_eth_dev *) regsitered before.
3386 ixgbe_dev_interrupt_delayed_handler(void *param)
3388 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3389 struct ixgbe_interrupt *intr =
3390 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3391 struct ixgbe_hw *hw =
3392 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3395 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3396 if (eicr & IXGBE_EICR_MAILBOX)
3397 ixgbe_pf_mbx_process(dev);
3399 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3400 ixgbe_handle_lasi(hw);
3401 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3404 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3405 ixgbe_dev_link_update(dev, 0);
3406 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3407 ixgbe_dev_link_status_print(dev);
3408 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3411 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3412 ixgbe_enable_intr(dev);
3413 rte_intr_enable(&(dev->pci_dev->intr_handle));
3417 * Interrupt handler triggered by NIC for handling
3418 * specific interrupt.
3421 * Pointer to interrupt handle.
3423 * The address of parameter (struct rte_eth_dev *) regsitered before.
3429 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3432 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3434 ixgbe_dev_interrupt_get_status(dev);
3435 ixgbe_dev_interrupt_action(dev);
3439 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3441 struct ixgbe_hw *hw;
3443 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3444 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3448 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3450 struct ixgbe_hw *hw;
3452 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3453 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3457 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3459 struct ixgbe_hw *hw;
3465 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3467 fc_conf->pause_time = hw->fc.pause_time;
3468 fc_conf->high_water = hw->fc.high_water[0];
3469 fc_conf->low_water = hw->fc.low_water[0];
3470 fc_conf->send_xon = hw->fc.send_xon;
3471 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3474 * Return rx_pause status according to actual setting of
3477 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3478 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3484 * Return tx_pause status according to actual setting of
3487 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3488 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3493 if (rx_pause && tx_pause)
3494 fc_conf->mode = RTE_FC_FULL;
3496 fc_conf->mode = RTE_FC_RX_PAUSE;
3498 fc_conf->mode = RTE_FC_TX_PAUSE;
3500 fc_conf->mode = RTE_FC_NONE;
3506 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3508 struct ixgbe_hw *hw;
3510 uint32_t rx_buf_size;
3511 uint32_t max_high_water;
3513 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3520 PMD_INIT_FUNC_TRACE();
3522 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3523 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3524 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3527 * At least reserve one Ethernet frame for watermark
3528 * high_water/low_water in kilo bytes for ixgbe
3530 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3531 if ((fc_conf->high_water > max_high_water) ||
3532 (fc_conf->high_water < fc_conf->low_water)) {
3533 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3534 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3538 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3539 hw->fc.pause_time = fc_conf->pause_time;
3540 hw->fc.high_water[0] = fc_conf->high_water;
3541 hw->fc.low_water[0] = fc_conf->low_water;
3542 hw->fc.send_xon = fc_conf->send_xon;
3543 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3545 err = ixgbe_fc_enable(hw);
3547 /* Not negotiated is not an error case */
3548 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3550 /* check if we want to forward MAC frames - driver doesn't have native
3551 * capability to do that, so we'll write the registers ourselves */
3553 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3555 /* set or clear MFLCN.PMCF bit depending on configuration */
3556 if (fc_conf->mac_ctrl_frame_fwd != 0)
3557 mflcn |= IXGBE_MFLCN_PMCF;
3559 mflcn &= ~IXGBE_MFLCN_PMCF;
3561 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3562 IXGBE_WRITE_FLUSH(hw);
3567 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3572 * ixgbe_pfc_enable_generic - Enable flow control
3573 * @hw: pointer to hardware structure
3574 * @tc_num: traffic class number
3575 * Enable flow control according to the current settings.
3578 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3581 uint32_t mflcn_reg, fccfg_reg;
3583 uint32_t fcrtl, fcrth;
3587 /* Validate the water mark configuration */
3588 if (!hw->fc.pause_time) {
3589 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3593 /* Low water mark of zero causes XOFF floods */
3594 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3595 /* High/Low water can not be 0 */
3596 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3597 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3598 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3602 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3603 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3604 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3608 /* Negotiate the fc mode to use */
3609 ixgbe_fc_autoneg(hw);
3611 /* Disable any previous flow control settings */
3612 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3613 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3615 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3616 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3618 switch (hw->fc.current_mode) {
3621 * If the count of enabled RX Priority Flow control >1,
3622 * and the TX pause can not be disabled
3625 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3626 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3627 if (reg & IXGBE_FCRTH_FCEN)
3631 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3633 case ixgbe_fc_rx_pause:
3635 * Rx Flow control is enabled and Tx Flow control is
3636 * disabled by software override. Since there really
3637 * isn't a way to advertise that we are capable of RX
3638 * Pause ONLY, we will advertise that we support both
3639 * symmetric and asymmetric Rx PAUSE. Later, we will
3640 * disable the adapter's ability to send PAUSE frames.
3642 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3644 * If the count of enabled RX Priority Flow control >1,
3645 * and the TX pause can not be disabled
3648 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3649 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3650 if (reg & IXGBE_FCRTH_FCEN)
3654 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3656 case ixgbe_fc_tx_pause:
3658 * Tx Flow control is enabled, and Rx Flow control is
3659 * disabled by software override.
3661 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3664 /* Flow control (both Rx and Tx) is enabled by SW override. */
3665 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3666 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3669 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3670 ret_val = IXGBE_ERR_CONFIG;
3675 /* Set 802.3x based flow control settings. */
3676 mflcn_reg |= IXGBE_MFLCN_DPF;
3677 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3678 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3680 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3681 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3682 hw->fc.high_water[tc_num]) {
3683 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3684 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3685 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3687 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3689 * In order to prevent Tx hangs when the internal Tx
3690 * switch is enabled we must set the high water mark
3691 * to the maximum FCRTH value. This allows the Tx
3692 * switch to function even under heavy Rx workloads.
3694 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3696 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3698 /* Configure pause time (2 TCs per register) */
3699 reg = hw->fc.pause_time * 0x00010001;
3700 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3701 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3703 /* Configure flow control refresh threshold value */
3704 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3711 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3713 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3714 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3716 if (hw->mac.type != ixgbe_mac_82598EB) {
3717 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3723 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3726 uint32_t rx_buf_size;
3727 uint32_t max_high_water;
3729 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3730 struct ixgbe_hw *hw =
3731 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3732 struct ixgbe_dcb_config *dcb_config =
3733 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3735 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3742 PMD_INIT_FUNC_TRACE();
3744 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3745 tc_num = map[pfc_conf->priority];
3746 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3747 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3749 * At least reserve one Ethernet frame for watermark
3750 * high_water/low_water in kilo bytes for ixgbe
3752 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3753 if ((pfc_conf->fc.high_water > max_high_water) ||
3754 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3755 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3756 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3760 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3761 hw->fc.pause_time = pfc_conf->fc.pause_time;
3762 hw->fc.send_xon = pfc_conf->fc.send_xon;
3763 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3764 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3766 err = ixgbe_dcb_pfc_enable(dev,tc_num);
3768 /* Not negotiated is not an error case */
3769 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3772 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3777 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3778 struct rte_eth_rss_reta_entry64 *reta_conf,
3781 uint16_t i, sp_reta_size;
3784 uint16_t idx, shift;
3785 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3788 PMD_INIT_FUNC_TRACE();
3790 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3791 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3796 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3797 if (reta_size != sp_reta_size) {
3798 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3799 "(%d) doesn't match the number hardware can supported "
3800 "(%d)\n", reta_size, sp_reta_size);
3804 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3805 idx = i / RTE_RETA_GROUP_SIZE;
3806 shift = i % RTE_RETA_GROUP_SIZE;
3807 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3811 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3812 if (mask == IXGBE_4_BIT_MASK)
3815 r = IXGBE_READ_REG(hw, reta_reg);
3816 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3817 if (mask & (0x1 << j))
3818 reta |= reta_conf[idx].reta[shift + j] <<
3821 reta |= r & (IXGBE_8_BIT_MASK <<
3824 IXGBE_WRITE_REG(hw, reta_reg, reta);
3831 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3832 struct rte_eth_rss_reta_entry64 *reta_conf,
3835 uint16_t i, sp_reta_size;
3838 uint16_t idx, shift;
3839 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3842 PMD_INIT_FUNC_TRACE();
3843 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3844 if (reta_size != sp_reta_size) {
3845 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3846 "(%d) doesn't match the number hardware can supported "
3847 "(%d)\n", reta_size, sp_reta_size);
3851 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3852 idx = i / RTE_RETA_GROUP_SIZE;
3853 shift = i % RTE_RETA_GROUP_SIZE;
3854 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3859 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3860 reta = IXGBE_READ_REG(hw, reta_reg);
3861 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3862 if (mask & (0x1 << j))
3863 reta_conf[idx].reta[shift + j] =
3864 ((reta >> (CHAR_BIT * j)) &
3873 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3874 uint32_t index, uint32_t pool)
3876 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3877 uint32_t enable_addr = 1;
3879 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3883 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3885 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3887 ixgbe_clear_rar(hw, index);
3891 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3893 ixgbe_remove_rar(dev, 0);
3895 ixgbe_add_rar(dev, addr, 0, 0);
3899 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3903 struct ixgbe_hw *hw;
3904 struct rte_eth_dev_info dev_info;
3905 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3907 ixgbe_dev_info_get(dev, &dev_info);
3909 /* check that mtu is within the allowed range */
3910 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3913 /* refuse mtu that requires the support of scattered packets when this
3914 * feature has not been enabled before. */
3915 if (!dev->data->scattered_rx &&
3916 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3917 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3920 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3921 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3923 /* switch to jumbo mode if needed */
3924 if (frame_size > ETHER_MAX_LEN) {
3925 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3926 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3928 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3929 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3931 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3933 /* update max frame size */
3934 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3936 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3937 maxfrs &= 0x0000FFFF;
3938 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3939 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3945 * Virtual Function operations
3948 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3950 PMD_INIT_FUNC_TRACE();
3952 /* Clear interrupt mask to stop from interrupts being generated */
3953 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3955 IXGBE_WRITE_FLUSH(hw);
3959 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3961 PMD_INIT_FUNC_TRACE();
3963 /* VF enable interrupt autoclean */
3964 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3965 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3966 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3968 IXGBE_WRITE_FLUSH(hw);
3972 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3974 struct rte_eth_conf* conf = &dev->data->dev_conf;
3975 struct ixgbe_adapter *adapter =
3976 (struct ixgbe_adapter *)dev->data->dev_private;
3978 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3979 dev->data->port_id);
3982 * VF has no ability to enable/disable HW CRC
3983 * Keep the persistent behavior the same as Host PF
3985 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3986 if (!conf->rxmode.hw_strip_crc) {
3987 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3988 conf->rxmode.hw_strip_crc = 1;
3991 if (conf->rxmode.hw_strip_crc) {
3992 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3993 conf->rxmode.hw_strip_crc = 0;
3998 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3999 * allocation or vector Rx preconditions we will reset it.
4001 adapter->rx_bulk_alloc_allowed = true;
4002 adapter->rx_vec_allowed = true;
4008 ixgbevf_dev_start(struct rte_eth_dev *dev)
4010 struct ixgbe_hw *hw =
4011 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4012 uint32_t intr_vector = 0;
4013 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4017 PMD_INIT_FUNC_TRACE();
4019 hw->mac.ops.reset_hw(hw);
4020 hw->mac.get_link_status = true;
4022 /* negotiate mailbox API version to use with the PF. */
4023 ixgbevf_negotiate_api(hw);
4025 ixgbevf_dev_tx_init(dev);
4027 /* This can fail when allocating mbufs for descriptor rings */
4028 err = ixgbevf_dev_rx_init(dev);
4030 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4031 ixgbe_dev_clear_queues(dev);
4036 ixgbevf_set_vfta_all(dev,1);
4039 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
4040 ETH_VLAN_EXTEND_MASK;
4041 ixgbevf_vlan_offload_set(dev, mask);
4043 ixgbevf_dev_rxtx_start(dev);
4045 /* check and configure queue intr-vector mapping */
4046 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4047 intr_vector = dev->data->nb_rx_queues;
4048 if (rte_intr_efd_enable(intr_handle, intr_vector))
4052 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4053 intr_handle->intr_vec =
4054 rte_zmalloc("intr_vec",
4055 dev->data->nb_rx_queues * sizeof(int), 0);
4056 if (intr_handle->intr_vec == NULL) {
4057 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4058 " intr_vec\n", dev->data->nb_rx_queues);
4062 ixgbevf_configure_msix(dev);
4064 rte_intr_enable(intr_handle);
4066 /* Re-enable interrupt for VF */
4067 ixgbevf_intr_enable(hw);
4073 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4075 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4076 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4078 PMD_INIT_FUNC_TRACE();
4080 hw->adapter_stopped = 1;
4081 ixgbe_stop_adapter(hw);
4084 * Clear what we set, but we still keep shadow_vfta to
4085 * restore after device starts
4087 ixgbevf_set_vfta_all(dev,0);
4089 /* Clear stored conf */
4090 dev->data->scattered_rx = 0;
4092 ixgbe_dev_clear_queues(dev);
4094 /* Clean datapath event and queue/vec mapping */
4095 rte_intr_efd_disable(intr_handle);
4096 if (intr_handle->intr_vec != NULL) {
4097 rte_free(intr_handle->intr_vec);
4098 intr_handle->intr_vec = NULL;
4103 ixgbevf_dev_close(struct rte_eth_dev *dev)
4105 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4107 PMD_INIT_FUNC_TRACE();
4111 ixgbevf_dev_stop(dev);
4113 ixgbe_dev_free_queues(dev);
4116 * Remove the VF MAC address ro ensure
4117 * that the VF traffic goes to the PF
4118 * after stop, close and detach of the VF
4120 ixgbevf_remove_mac_addr(dev, 0);
4123 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4125 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4126 struct ixgbe_vfta * shadow_vfta =
4127 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4128 int i = 0, j = 0, vfta = 0, mask = 1;
4130 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
4131 vfta = shadow_vfta->vfta[i];
4134 for (j = 0; j < 32; j++){
4136 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4145 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4147 struct ixgbe_hw *hw =
4148 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4149 struct ixgbe_vfta * shadow_vfta =
4150 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4151 uint32_t vid_idx = 0;
4152 uint32_t vid_bit = 0;
4155 PMD_INIT_FUNC_TRACE();
4157 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4158 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4160 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4163 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4164 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4166 /* Save what we set and retore it after device reset */
4168 shadow_vfta->vfta[vid_idx] |= vid_bit;
4170 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4176 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4178 struct ixgbe_hw *hw =
4179 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4182 PMD_INIT_FUNC_TRACE();
4184 if (queue >= hw->mac.max_rx_queues)
4187 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4189 ctrl |= IXGBE_RXDCTL_VME;
4191 ctrl &= ~IXGBE_RXDCTL_VME;
4192 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4194 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4198 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4200 struct ixgbe_hw *hw =
4201 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4205 /* VF function only support hw strip feature, others are not support */
4206 if (mask & ETH_VLAN_STRIP_MASK) {
4207 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4209 for (i = 0; i < hw->mac.max_rx_queues; i++)
4210 ixgbevf_vlan_strip_queue_set(dev,i,on);
4215 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4219 /* we only need to do this if VMDq is enabled */
4220 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4221 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4222 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4230 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4232 uint32_t vector = 0;
4233 switch (hw->mac.mc_filter_type) {
4234 case 0: /* use bits [47:36] of the address */
4235 vector = ((uc_addr->addr_bytes[4] >> 4) |
4236 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4238 case 1: /* use bits [46:35] of the address */
4239 vector = ((uc_addr->addr_bytes[4] >> 3) |
4240 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4242 case 2: /* use bits [45:34] of the address */
4243 vector = ((uc_addr->addr_bytes[4] >> 2) |
4244 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4246 case 3: /* use bits [43:32] of the address */
4247 vector = ((uc_addr->addr_bytes[4]) |
4248 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4250 default: /* Invalid mc_filter_type */
4254 /* vector can only be 12-bits or boundary will be exceeded */
4260 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4268 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4269 const uint32_t ixgbe_uta_bit_shift = 5;
4270 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4271 const uint32_t bit1 = 0x1;
4273 struct ixgbe_hw *hw =
4274 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4275 struct ixgbe_uta_info *uta_info =
4276 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4278 /* The UTA table only exists on 82599 hardware and newer */
4279 if (hw->mac.type < ixgbe_mac_82599EB)
4282 vector = ixgbe_uta_vector(hw,mac_addr);
4283 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4284 uta_shift = vector & ixgbe_uta_bit_mask;
4286 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4290 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4292 uta_info->uta_in_use++;
4293 reg_val |= (bit1 << uta_shift);
4294 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4296 uta_info->uta_in_use--;
4297 reg_val &= ~(bit1 << uta_shift);
4298 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4301 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4303 if (uta_info->uta_in_use > 0)
4304 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4305 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4307 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4313 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4316 struct ixgbe_hw *hw =
4317 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4318 struct ixgbe_uta_info *uta_info =
4319 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4321 /* The UTA table only exists on 82599 hardware and newer */
4322 if (hw->mac.type < ixgbe_mac_82599EB)
4326 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4327 uta_info->uta_shadow[i] = ~0;
4328 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4331 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4332 uta_info->uta_shadow[i] = 0;
4333 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4341 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4343 uint32_t new_val = orig_val;
4345 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4346 new_val |= IXGBE_VMOLR_AUPE;
4347 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4348 new_val |= IXGBE_VMOLR_ROMPE;
4349 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4350 new_val |= IXGBE_VMOLR_ROPE;
4351 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4352 new_val |= IXGBE_VMOLR_BAM;
4353 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4354 new_val |= IXGBE_VMOLR_MPE;
4360 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4361 uint16_t rx_mask, uint8_t on)
4365 struct ixgbe_hw *hw =
4366 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4367 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4369 if (hw->mac.type == ixgbe_mac_82598EB) {
4370 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4371 " on 82599 hardware and newer");
4374 if (ixgbe_vmdq_mode_check(hw) < 0)
4377 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4384 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4390 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4394 const uint8_t bit1 = 0x1;
4396 struct ixgbe_hw *hw =
4397 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4399 if (ixgbe_vmdq_mode_check(hw) < 0)
4402 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4403 reg = IXGBE_READ_REG(hw, addr);
4411 IXGBE_WRITE_REG(hw, addr,reg);
4417 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4421 const uint8_t bit1 = 0x1;
4423 struct ixgbe_hw *hw =
4424 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4426 if (ixgbe_vmdq_mode_check(hw) < 0)
4429 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4430 reg = IXGBE_READ_REG(hw, addr);
4438 IXGBE_WRITE_REG(hw, addr,reg);
4444 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4445 uint64_t pool_mask, uint8_t vlan_on)
4449 struct ixgbe_hw *hw =
4450 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4452 if (ixgbe_vmdq_mode_check(hw) < 0)
4454 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4455 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4456 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4465 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
4466 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
4467 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
4468 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
4469 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4470 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4471 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4474 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4475 struct rte_eth_mirror_conf *mirror_conf,
4476 uint8_t rule_id, uint8_t on)
4478 uint32_t mr_ctl,vlvf;
4479 uint32_t mp_lsb = 0;
4480 uint32_t mv_msb = 0;
4481 uint32_t mv_lsb = 0;
4482 uint32_t mp_msb = 0;
4485 uint64_t vlan_mask = 0;
4487 const uint8_t pool_mask_offset = 32;
4488 const uint8_t vlan_mask_offset = 32;
4489 const uint8_t dst_pool_offset = 8;
4490 const uint8_t rule_mr_offset = 4;
4491 const uint8_t mirror_rule_mask= 0x0F;
4493 struct ixgbe_mirror_info *mr_info =
4494 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4495 struct ixgbe_hw *hw =
4496 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4497 uint8_t mirror_type = 0;
4499 if (ixgbe_vmdq_mode_check(hw) < 0)
4502 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4505 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4506 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4507 mirror_conf->rule_type);
4511 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4512 mirror_type |= IXGBE_MRCTL_VLME;
4513 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4514 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4515 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4516 /* search vlan id related pool vlan filter index */
4517 reg_index = ixgbe_find_vlvf_slot(hw,
4518 mirror_conf->vlan.vlan_id[i]);
4521 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4522 if ((vlvf & IXGBE_VLVF_VIEN) &&
4523 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4524 mirror_conf->vlan.vlan_id[i]))
4525 vlan_mask |= (1ULL << reg_index);
4532 mv_lsb = vlan_mask & 0xFFFFFFFF;
4533 mv_msb = vlan_mask >> vlan_mask_offset;
4535 mr_info->mr_conf[rule_id].vlan.vlan_mask =
4536 mirror_conf->vlan.vlan_mask;
4537 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4538 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4539 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4540 mirror_conf->vlan.vlan_id[i];
4545 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4546 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4547 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4552 * if enable pool mirror, write related pool mask register,if disable
4553 * pool mirror, clear PFMRVM register
4555 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4556 mirror_type |= IXGBE_MRCTL_VPME;
4558 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4559 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4560 mr_info->mr_conf[rule_id].pool_mask =
4561 mirror_conf->pool_mask;
4566 mr_info->mr_conf[rule_id].pool_mask = 0;
4569 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4570 mirror_type |= IXGBE_MRCTL_UPME;
4571 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4572 mirror_type |= IXGBE_MRCTL_DPME;
4574 /* read mirror control register and recalculate it */
4575 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4578 mr_ctl |= mirror_type;
4579 mr_ctl &= mirror_rule_mask;
4580 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4582 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4584 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4585 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4587 /* write mirrror control register */
4588 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4590 /* write pool mirrror control register */
4591 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4592 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4593 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4596 /* write VLAN mirrror control register */
4597 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4598 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4599 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4607 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4610 uint32_t lsb_val = 0;
4611 uint32_t msb_val = 0;
4612 const uint8_t rule_mr_offset = 4;
4614 struct ixgbe_hw *hw =
4615 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4616 struct ixgbe_mirror_info *mr_info =
4617 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4619 if (ixgbe_vmdq_mode_check(hw) < 0)
4622 memset(&mr_info->mr_conf[rule_id], 0,
4623 sizeof(struct rte_eth_mirror_conf));
4625 /* clear PFVMCTL register */
4626 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4628 /* clear pool mask register */
4629 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4630 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4632 /* clear vlan mask register */
4633 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4634 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4640 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4643 struct ixgbe_hw *hw =
4644 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4646 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4647 mask |= (1 << IXGBE_MISC_VEC_ID);
4648 RTE_SET_USED(queue_id);
4649 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4651 rte_intr_enable(&dev->pci_dev->intr_handle);
4657 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4660 struct ixgbe_hw *hw =
4661 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4663 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4664 mask &= ~(1 << IXGBE_MISC_VEC_ID);
4665 RTE_SET_USED(queue_id);
4666 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4672 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4675 struct ixgbe_hw *hw =
4676 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4677 struct ixgbe_interrupt *intr =
4678 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4680 if (queue_id < 16) {
4681 ixgbe_disable_intr(hw);
4682 intr->mask |= (1 << queue_id);
4683 ixgbe_enable_intr(dev);
4684 } else if (queue_id < 32) {
4685 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4686 mask &= (1 << queue_id);
4687 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4688 } else if (queue_id < 64) {
4689 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4690 mask &= (1 << (queue_id - 32));
4691 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4693 rte_intr_enable(&dev->pci_dev->intr_handle);
4699 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4702 struct ixgbe_hw *hw =
4703 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4704 struct ixgbe_interrupt *intr =
4705 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4707 if (queue_id < 16) {
4708 ixgbe_disable_intr(hw);
4709 intr->mask &= ~(1 << queue_id);
4710 ixgbe_enable_intr(dev);
4711 } else if (queue_id < 32) {
4712 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4713 mask &= ~(1 << queue_id);
4714 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4715 } else if (queue_id < 64) {
4716 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4717 mask &= ~(1 << (queue_id - 32));
4718 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4725 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4726 uint8_t queue, uint8_t msix_vector)
4730 if (direction == -1) {
4732 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4733 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4736 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4738 /* rx or tx cause */
4739 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4740 idx = ((16 * (queue & 1)) + (8 * direction));
4741 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4742 tmp &= ~(0xFF << idx);
4743 tmp |= (msix_vector << idx);
4744 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4749 * set the IVAR registers, mapping interrupt causes to vectors
4751 * pointer to ixgbe_hw struct
4753 * 0 for Rx, 1 for Tx, -1 for other causes
4755 * queue to map the corresponding interrupt to
4757 * the vector to map to the corresponding queue
4760 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4761 uint8_t queue, uint8_t msix_vector)
4765 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4766 if (hw->mac.type == ixgbe_mac_82598EB) {
4767 if (direction == -1)
4769 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4770 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4771 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4772 tmp |= (msix_vector << (8 * (queue & 0x3)));
4773 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4774 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4775 (hw->mac.type == ixgbe_mac_X540)) {
4776 if (direction == -1) {
4778 idx = ((queue & 1) * 8);
4779 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4780 tmp &= ~(0xFF << idx);
4781 tmp |= (msix_vector << idx);
4782 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4784 /* rx or tx causes */
4785 idx = ((16 * (queue & 1)) + (8 * direction));
4786 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4787 tmp &= ~(0xFF << idx);
4788 tmp |= (msix_vector << idx);
4789 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4795 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4797 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4798 struct ixgbe_hw *hw =
4799 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4801 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4803 /* won't configure msix register if no mapping is done
4804 * between intr vector and event fd.
4806 if (!rte_intr_dp_is_en(intr_handle))
4809 /* Configure all RX queues of VF */
4810 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4811 /* Force all queue use vector 0,
4812 * as IXGBE_VF_MAXMSIVECOTR = 1
4814 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4815 intr_handle->intr_vec[q_idx] = vector_idx;
4818 /* Configure VF other cause ivar */
4819 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4823 * Sets up the hardware to properly generate MSI-X interrupts
4825 * board private structure
4828 ixgbe_configure_msix(struct rte_eth_dev *dev)
4830 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4831 struct ixgbe_hw *hw =
4832 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4833 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4834 uint32_t vec = IXGBE_MISC_VEC_ID;
4838 /* won't configure msix register if no mapping is done
4839 * between intr vector and event fd
4841 if (!rte_intr_dp_is_en(intr_handle))
4844 if (rte_intr_allow_others(intr_handle))
4845 vec = base = IXGBE_RX_VEC_START;
4847 /* setup GPIE for MSI-x mode */
4848 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4849 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4850 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4851 /* auto clearing and auto setting corresponding bits in EIMS
4852 * when MSI-X interrupt is triggered
4854 if (hw->mac.type == ixgbe_mac_82598EB) {
4855 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4857 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4858 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4860 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4862 /* Populate the IVAR table and set the ITR values to the
4863 * corresponding register.
4865 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4867 /* by default, 1:1 mapping */
4868 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4869 intr_handle->intr_vec[queue_id] = vec;
4870 if (vec < base + intr_handle->nb_efd - 1)
4874 switch (hw->mac.type) {
4875 case ixgbe_mac_82598EB:
4876 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4879 case ixgbe_mac_82599EB:
4880 case ixgbe_mac_X540:
4881 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4886 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4887 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4889 /* set up to autoclear timer, and the vectors */
4890 mask = IXGBE_EIMS_ENABLE_MASK;
4891 mask &= ~(IXGBE_EIMS_OTHER |
4892 IXGBE_EIMS_MAILBOX |
4895 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4898 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4899 uint16_t queue_idx, uint16_t tx_rate)
4901 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4902 uint32_t rf_dec, rf_int;
4904 uint16_t link_speed = dev->data->dev_link.link_speed;
4906 if (queue_idx >= hw->mac.max_tx_queues)
4910 /* Calculate the rate factor values to set */
4911 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4912 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4913 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4915 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4916 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4917 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4918 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4924 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4925 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4928 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4929 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4930 IXGBE_MAX_JUMBO_FRAME_SIZE))
4931 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4932 IXGBE_MMW_SIZE_JUMBO_FRAME);
4934 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4935 IXGBE_MMW_SIZE_DEFAULT);
4937 /* Set RTTBCNRC of queue X */
4938 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4939 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4940 IXGBE_WRITE_FLUSH(hw);
4945 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4946 uint16_t tx_rate, uint64_t q_msk)
4948 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4949 struct ixgbe_vf_info *vfinfo =
4950 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4951 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4952 uint32_t queue_stride =
4953 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4954 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4955 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4956 uint16_t total_rate = 0;
4958 if (queue_end >= hw->mac.max_tx_queues)
4961 if (vfinfo != NULL) {
4962 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4965 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4967 total_rate += vfinfo[vf_idx].tx_rate[idx];
4972 /* Store tx_rate for this vf. */
4973 for (idx = 0; idx < nb_q_per_pool; idx++) {
4974 if (((uint64_t)0x1 << idx) & q_msk) {
4975 if (vfinfo[vf].tx_rate[idx] != tx_rate)
4976 vfinfo[vf].tx_rate[idx] = tx_rate;
4977 total_rate += tx_rate;
4981 if (total_rate > dev->data->dev_link.link_speed) {
4983 * Reset stored TX rate of the VF if it causes exceed
4986 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4990 /* Set RTTBCNRC of each queue/pool for vf X */
4991 for (; queue_idx <= queue_end; queue_idx++) {
4993 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5001 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5002 __attribute__((unused)) uint32_t index,
5003 __attribute__((unused)) uint32_t pool)
5005 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5009 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5010 * operation. Trap this case to avoid exhausting the [very limited]
5011 * set of PF resources used to store VF MAC addresses.
5013 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5015 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5018 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5022 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5024 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5025 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5026 struct ether_addr *mac_addr;
5031 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5032 * not support the deletion of a given MAC address.
5033 * Instead, it imposes to delete all MAC addresses, then to add again
5034 * all MAC addresses with the exception of the one to be deleted.
5036 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5039 * Add again all MAC addresses, with the exception of the deleted one
5040 * and of the permanent MAC address.
5042 for (i = 0, mac_addr = dev->data->mac_addrs;
5043 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5044 /* Skip the deleted MAC address */
5047 /* Skip NULL MAC addresses */
5048 if (is_zero_ether_addr(mac_addr))
5050 /* Skip the permanent MAC address */
5051 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5053 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5056 "Adding again MAC address "
5057 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5059 mac_addr->addr_bytes[0],
5060 mac_addr->addr_bytes[1],
5061 mac_addr->addr_bytes[2],
5062 mac_addr->addr_bytes[3],
5063 mac_addr->addr_bytes[4],
5064 mac_addr->addr_bytes[5],
5070 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5072 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5074 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5077 #define MAC_TYPE_FILTER_SUP(type) do {\
5078 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5079 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5080 (type) != ixgbe_mac_X550EM_a)\
5085 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5086 struct rte_eth_syn_filter *filter,
5089 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5092 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5095 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5098 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5100 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5101 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5103 if (filter->hig_pri)
5104 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5106 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5108 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5110 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5112 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5113 IXGBE_WRITE_FLUSH(hw);
5118 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5119 struct rte_eth_syn_filter *filter)
5121 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5122 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5124 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5125 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5126 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5133 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5134 enum rte_filter_op filter_op,
5137 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5140 MAC_TYPE_FILTER_SUP(hw->mac.type);
5142 if (filter_op == RTE_ETH_FILTER_NOP)
5146 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5151 switch (filter_op) {
5152 case RTE_ETH_FILTER_ADD:
5153 ret = ixgbe_syn_filter_set(dev,
5154 (struct rte_eth_syn_filter *)arg,
5157 case RTE_ETH_FILTER_DELETE:
5158 ret = ixgbe_syn_filter_set(dev,
5159 (struct rte_eth_syn_filter *)arg,
5162 case RTE_ETH_FILTER_GET:
5163 ret = ixgbe_syn_filter_get(dev,
5164 (struct rte_eth_syn_filter *)arg);
5167 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5176 static inline enum ixgbe_5tuple_protocol
5177 convert_protocol_type(uint8_t protocol_value)
5179 if (protocol_value == IPPROTO_TCP)
5180 return IXGBE_FILTER_PROTOCOL_TCP;
5181 else if (protocol_value == IPPROTO_UDP)
5182 return IXGBE_FILTER_PROTOCOL_UDP;
5183 else if (protocol_value == IPPROTO_SCTP)
5184 return IXGBE_FILTER_PROTOCOL_SCTP;
5186 return IXGBE_FILTER_PROTOCOL_NONE;
5190 * add a 5tuple filter
5193 * dev: Pointer to struct rte_eth_dev.
5194 * index: the index the filter allocates.
5195 * filter: ponter to the filter that will be added.
5196 * rx_queue: the queue id the filter assigned to.
5199 * - On success, zero.
5200 * - On failure, a negative value.
5203 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5204 struct ixgbe_5tuple_filter *filter)
5206 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5207 struct ixgbe_filter_info *filter_info =
5208 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5210 uint32_t ftqf, sdpqf;
5211 uint32_t l34timir = 0;
5212 uint8_t mask = 0xff;
5215 * look for an unused 5tuple filter index,
5216 * and insert the filter to list.
5218 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5219 idx = i / (sizeof(uint32_t) * NBBY);
5220 shift = i % (sizeof(uint32_t) * NBBY);
5221 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5222 filter_info->fivetuple_mask[idx] |= 1 << shift;
5224 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5230 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5231 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5235 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5236 IXGBE_SDPQF_DSTPORT_SHIFT);
5237 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5239 ftqf = (uint32_t)(filter->filter_info.proto &
5240 IXGBE_FTQF_PROTOCOL_MASK);
5241 ftqf |= (uint32_t)((filter->filter_info.priority &
5242 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5243 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5244 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5245 if (filter->filter_info.dst_ip_mask == 0)
5246 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5247 if (filter->filter_info.src_port_mask == 0)
5248 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5249 if (filter->filter_info.dst_port_mask == 0)
5250 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5251 if (filter->filter_info.proto_mask == 0)
5252 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5253 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5254 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5255 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5257 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5258 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5259 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5260 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5262 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5263 l34timir |= (uint32_t)(filter->queue <<
5264 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5265 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5270 * remove a 5tuple filter
5273 * dev: Pointer to struct rte_eth_dev.
5274 * filter: the pointer of the filter will be removed.
5277 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5278 struct ixgbe_5tuple_filter *filter)
5280 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5281 struct ixgbe_filter_info *filter_info =
5282 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5283 uint16_t index = filter->index;
5285 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5286 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5287 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5290 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5291 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5292 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5293 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5294 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5298 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5300 struct ixgbe_hw *hw;
5301 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5303 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5305 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5308 /* refuse mtu that requires the support of scattered packets when this
5309 * feature has not been enabled before. */
5310 if (!dev->data->scattered_rx &&
5311 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5312 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5316 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5317 * request of the version 2.0 of the mailbox API.
5318 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5319 * of the mailbox API.
5320 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5321 * prior to 3.11.33 which contains the following change:
5322 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5324 ixgbevf_rlpml_set_vf(hw, max_frame);
5326 /* update max frame size */
5327 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5331 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5332 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5336 static inline struct ixgbe_5tuple_filter *
5337 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5338 struct ixgbe_5tuple_filter_info *key)
5340 struct ixgbe_5tuple_filter *it;
5342 TAILQ_FOREACH(it, filter_list, entries) {
5343 if (memcmp(key, &it->filter_info,
5344 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5351 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5353 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5354 struct ixgbe_5tuple_filter_info *filter_info)
5356 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5357 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5358 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5361 switch (filter->dst_ip_mask) {
5363 filter_info->dst_ip_mask = 0;
5364 filter_info->dst_ip = filter->dst_ip;
5367 filter_info->dst_ip_mask = 1;
5370 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5374 switch (filter->src_ip_mask) {
5376 filter_info->src_ip_mask = 0;
5377 filter_info->src_ip = filter->src_ip;
5380 filter_info->src_ip_mask = 1;
5383 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5387 switch (filter->dst_port_mask) {
5389 filter_info->dst_port_mask = 0;
5390 filter_info->dst_port = filter->dst_port;
5393 filter_info->dst_port_mask = 1;
5396 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5400 switch (filter->src_port_mask) {
5402 filter_info->src_port_mask = 0;
5403 filter_info->src_port = filter->src_port;
5406 filter_info->src_port_mask = 1;
5409 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5413 switch (filter->proto_mask) {
5415 filter_info->proto_mask = 0;
5416 filter_info->proto =
5417 convert_protocol_type(filter->proto);
5420 filter_info->proto_mask = 1;
5423 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5427 filter_info->priority = (uint8_t)filter->priority;
5432 * add or delete a ntuple filter
5435 * dev: Pointer to struct rte_eth_dev.
5436 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5437 * add: if true, add filter, if false, remove filter
5440 * - On success, zero.
5441 * - On failure, a negative value.
5444 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5445 struct rte_eth_ntuple_filter *ntuple_filter,
5448 struct ixgbe_filter_info *filter_info =
5449 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5450 struct ixgbe_5tuple_filter_info filter_5tuple;
5451 struct ixgbe_5tuple_filter *filter;
5454 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5455 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5459 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5460 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5464 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5466 if (filter != NULL && add) {
5467 PMD_DRV_LOG(ERR, "filter exists.");
5470 if (filter == NULL && !add) {
5471 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5476 filter = rte_zmalloc("ixgbe_5tuple_filter",
5477 sizeof(struct ixgbe_5tuple_filter), 0);
5480 (void)rte_memcpy(&filter->filter_info,
5482 sizeof(struct ixgbe_5tuple_filter_info));
5483 filter->queue = ntuple_filter->queue;
5484 ret = ixgbe_add_5tuple_filter(dev, filter);
5490 ixgbe_remove_5tuple_filter(dev, filter);
5496 * get a ntuple filter
5499 * dev: Pointer to struct rte_eth_dev.
5500 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5503 * - On success, zero.
5504 * - On failure, a negative value.
5507 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5508 struct rte_eth_ntuple_filter *ntuple_filter)
5510 struct ixgbe_filter_info *filter_info =
5511 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5512 struct ixgbe_5tuple_filter_info filter_5tuple;
5513 struct ixgbe_5tuple_filter *filter;
5516 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5517 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5521 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5522 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5526 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5528 if (filter == NULL) {
5529 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5532 ntuple_filter->queue = filter->queue;
5537 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5538 * @dev: pointer to rte_eth_dev structure
5539 * @filter_op:operation will be taken.
5540 * @arg: a pointer to specific structure corresponding to the filter_op
5543 * - On success, zero.
5544 * - On failure, a negative value.
5547 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5548 enum rte_filter_op filter_op,
5551 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5554 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5556 if (filter_op == RTE_ETH_FILTER_NOP)
5560 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5565 switch (filter_op) {
5566 case RTE_ETH_FILTER_ADD:
5567 ret = ixgbe_add_del_ntuple_filter(dev,
5568 (struct rte_eth_ntuple_filter *)arg,
5571 case RTE_ETH_FILTER_DELETE:
5572 ret = ixgbe_add_del_ntuple_filter(dev,
5573 (struct rte_eth_ntuple_filter *)arg,
5576 case RTE_ETH_FILTER_GET:
5577 ret = ixgbe_get_ntuple_filter(dev,
5578 (struct rte_eth_ntuple_filter *)arg);
5581 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5589 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5594 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5595 if (filter_info->ethertype_filters[i] == ethertype &&
5596 (filter_info->ethertype_mask & (1 << i)))
5603 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5608 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5609 if (!(filter_info->ethertype_mask & (1 << i))) {
5610 filter_info->ethertype_mask |= 1 << i;
5611 filter_info->ethertype_filters[i] = ethertype;
5619 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5622 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5624 filter_info->ethertype_mask &= ~(1 << idx);
5625 filter_info->ethertype_filters[idx] = 0;
5630 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5631 struct rte_eth_ethertype_filter *filter,
5634 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5635 struct ixgbe_filter_info *filter_info =
5636 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5641 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5644 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5645 filter->ether_type == ETHER_TYPE_IPv6) {
5646 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5647 " ethertype filter.", filter->ether_type);
5651 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5652 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5655 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5656 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5660 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5661 if (ret >= 0 && add) {
5662 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5663 filter->ether_type);
5666 if (ret < 0 && !add) {
5667 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5668 filter->ether_type);
5673 ret = ixgbe_ethertype_filter_insert(filter_info,
5674 filter->ether_type);
5676 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5679 etqf = IXGBE_ETQF_FILTER_EN;
5680 etqf |= (uint32_t)filter->ether_type;
5681 etqs |= (uint32_t)((filter->queue <<
5682 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5683 IXGBE_ETQS_RX_QUEUE);
5684 etqs |= IXGBE_ETQS_QUEUE_EN;
5686 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5690 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5691 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5692 IXGBE_WRITE_FLUSH(hw);
5698 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5699 struct rte_eth_ethertype_filter *filter)
5701 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5702 struct ixgbe_filter_info *filter_info =
5703 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5704 uint32_t etqf, etqs;
5707 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5709 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5710 filter->ether_type);
5714 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5715 if (etqf & IXGBE_ETQF_FILTER_EN) {
5716 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5717 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5719 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5720 IXGBE_ETQS_RX_QUEUE_SHIFT;
5727 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5728 * @dev: pointer to rte_eth_dev structure
5729 * @filter_op:operation will be taken.
5730 * @arg: a pointer to specific structure corresponding to the filter_op
5733 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5734 enum rte_filter_op filter_op,
5737 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5740 MAC_TYPE_FILTER_SUP(hw->mac.type);
5742 if (filter_op == RTE_ETH_FILTER_NOP)
5746 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5751 switch (filter_op) {
5752 case RTE_ETH_FILTER_ADD:
5753 ret = ixgbe_add_del_ethertype_filter(dev,
5754 (struct rte_eth_ethertype_filter *)arg,
5757 case RTE_ETH_FILTER_DELETE:
5758 ret = ixgbe_add_del_ethertype_filter(dev,
5759 (struct rte_eth_ethertype_filter *)arg,
5762 case RTE_ETH_FILTER_GET:
5763 ret = ixgbe_get_ethertype_filter(dev,
5764 (struct rte_eth_ethertype_filter *)arg);
5767 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5775 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5776 enum rte_filter_type filter_type,
5777 enum rte_filter_op filter_op,
5782 switch (filter_type) {
5783 case RTE_ETH_FILTER_NTUPLE:
5784 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5786 case RTE_ETH_FILTER_ETHERTYPE:
5787 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5789 case RTE_ETH_FILTER_SYN:
5790 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5792 case RTE_ETH_FILTER_FDIR:
5793 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5795 case RTE_ETH_FILTER_L2_TUNNEL:
5796 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5799 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5808 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5809 u8 **mc_addr_ptr, u32 *vmdq)
5814 mc_addr = *mc_addr_ptr;
5815 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5820 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5821 struct ether_addr *mc_addr_set,
5822 uint32_t nb_mc_addr)
5824 struct ixgbe_hw *hw;
5827 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5828 mc_addr_list = (u8 *)mc_addr_set;
5829 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5830 ixgbe_dev_addr_list_itr, TRUE);
5834 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5836 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5837 uint64_t systime_cycles;
5839 switch (hw->mac.type) {
5840 case ixgbe_mac_X550:
5841 case ixgbe_mac_X550EM_x:
5842 case ixgbe_mac_X550EM_a:
5843 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5844 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5845 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5849 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5850 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5854 return systime_cycles;
5858 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5860 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5861 uint64_t rx_tstamp_cycles;
5863 switch (hw->mac.type) {
5864 case ixgbe_mac_X550:
5865 case ixgbe_mac_X550EM_x:
5866 case ixgbe_mac_X550EM_a:
5867 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5868 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5869 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5873 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5874 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5875 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5879 return rx_tstamp_cycles;
5883 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5885 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5886 uint64_t tx_tstamp_cycles;
5888 switch (hw->mac.type) {
5889 case ixgbe_mac_X550:
5890 case ixgbe_mac_X550EM_x:
5891 case ixgbe_mac_X550EM_a:
5892 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5893 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5894 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5898 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5899 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5900 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5904 return tx_tstamp_cycles;
5908 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5910 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5911 struct ixgbe_adapter *adapter =
5912 (struct ixgbe_adapter *)dev->data->dev_private;
5913 struct rte_eth_link link;
5914 uint32_t incval = 0;
5917 /* Get current link speed. */
5918 memset(&link, 0, sizeof(link));
5919 ixgbe_dev_link_update(dev, 1);
5920 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5922 switch (link.link_speed) {
5923 case ETH_SPEED_NUM_100M:
5924 incval = IXGBE_INCVAL_100;
5925 shift = IXGBE_INCVAL_SHIFT_100;
5927 case ETH_SPEED_NUM_1G:
5928 incval = IXGBE_INCVAL_1GB;
5929 shift = IXGBE_INCVAL_SHIFT_1GB;
5931 case ETH_SPEED_NUM_10G:
5933 incval = IXGBE_INCVAL_10GB;
5934 shift = IXGBE_INCVAL_SHIFT_10GB;
5938 switch (hw->mac.type) {
5939 case ixgbe_mac_X550:
5940 case ixgbe_mac_X550EM_x:
5941 case ixgbe_mac_X550EM_a:
5942 /* Independent of link speed. */
5944 /* Cycles read will be interpreted as ns. */
5947 case ixgbe_mac_X540:
5948 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5950 case ixgbe_mac_82599EB:
5951 incval >>= IXGBE_INCVAL_SHIFT_82599;
5952 shift -= IXGBE_INCVAL_SHIFT_82599;
5953 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5954 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5957 /* Not supported. */
5961 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5962 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5963 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5965 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5966 adapter->systime_tc.cc_shift = shift;
5967 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5969 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5970 adapter->rx_tstamp_tc.cc_shift = shift;
5971 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5973 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5974 adapter->tx_tstamp_tc.cc_shift = shift;
5975 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5979 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5981 struct ixgbe_adapter *adapter =
5982 (struct ixgbe_adapter *)dev->data->dev_private;
5984 adapter->systime_tc.nsec += delta;
5985 adapter->rx_tstamp_tc.nsec += delta;
5986 adapter->tx_tstamp_tc.nsec += delta;
5992 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5995 struct ixgbe_adapter *adapter =
5996 (struct ixgbe_adapter *)dev->data->dev_private;
5998 ns = rte_timespec_to_ns(ts);
5999 /* Set the timecounters to a new value. */
6000 adapter->systime_tc.nsec = ns;
6001 adapter->rx_tstamp_tc.nsec = ns;
6002 adapter->tx_tstamp_tc.nsec = ns;
6008 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6010 uint64_t ns, systime_cycles;
6011 struct ixgbe_adapter *adapter =
6012 (struct ixgbe_adapter *)dev->data->dev_private;
6014 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6015 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6016 *ts = rte_ns_to_timespec(ns);
6022 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6024 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6028 /* Stop the timesync system time. */
6029 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6030 /* Reset the timesync system time value. */
6031 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6032 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6034 /* Enable system time for platforms where it isn't on by default. */
6035 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6036 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6037 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6039 ixgbe_start_timecounters(dev);
6041 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6042 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6044 IXGBE_ETQF_FILTER_EN |
6047 /* Enable timestamping of received PTP packets. */
6048 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6049 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6050 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6052 /* Enable timestamping of transmitted PTP packets. */
6053 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6054 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6055 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6057 IXGBE_WRITE_FLUSH(hw);
6063 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6065 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6068 /* Disable timestamping of transmitted PTP packets. */
6069 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6070 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6071 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6073 /* Disable timestamping of received PTP packets. */
6074 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6075 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6076 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6078 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6079 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6081 /* Stop incrementating the System Time registers. */
6082 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6088 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6089 struct timespec *timestamp,
6090 uint32_t flags __rte_unused)
6092 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6093 struct ixgbe_adapter *adapter =
6094 (struct ixgbe_adapter *)dev->data->dev_private;
6095 uint32_t tsync_rxctl;
6096 uint64_t rx_tstamp_cycles;
6099 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6100 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6103 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6104 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6105 *timestamp = rte_ns_to_timespec(ns);
6111 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6112 struct timespec *timestamp)
6114 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6115 struct ixgbe_adapter *adapter =
6116 (struct ixgbe_adapter *)dev->data->dev_private;
6117 uint32_t tsync_txctl;
6118 uint64_t tx_tstamp_cycles;
6121 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6122 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6125 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6126 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6127 *timestamp = rte_ns_to_timespec(ns);
6133 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6135 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6138 const struct reg_info *reg_group;
6139 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6140 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6142 while ((reg_group = reg_set[g_ind++]))
6143 count += ixgbe_regs_group_count(reg_group);
6149 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6153 const struct reg_info *reg_group;
6155 while ((reg_group = ixgbevf_regs[g_ind++]))
6156 count += ixgbe_regs_group_count(reg_group);
6162 ixgbe_get_regs(struct rte_eth_dev *dev,
6163 struct rte_dev_reg_info *regs)
6165 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6166 uint32_t *data = regs->data;
6169 const struct reg_info *reg_group;
6170 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6171 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6173 /* Support only full register dump */
6174 if ((regs->length == 0) ||
6175 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6176 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6178 while ((reg_group = reg_set[g_ind++]))
6179 count += ixgbe_read_regs_group(dev, &data[count],
6188 ixgbevf_get_regs(struct rte_eth_dev *dev,
6189 struct rte_dev_reg_info *regs)
6191 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6192 uint32_t *data = regs->data;
6195 const struct reg_info *reg_group;
6197 /* Support only full register dump */
6198 if ((regs->length == 0) ||
6199 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6200 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6202 while ((reg_group = ixgbevf_regs[g_ind++]))
6203 count += ixgbe_read_regs_group(dev, &data[count],
6212 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6214 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6216 /* Return unit is byte count */
6217 return hw->eeprom.word_size * 2;
6221 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6222 struct rte_dev_eeprom_info *in_eeprom)
6224 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6225 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6226 uint16_t *data = in_eeprom->data;
6229 first = in_eeprom->offset >> 1;
6230 length = in_eeprom->length >> 1;
6231 if ((first > hw->eeprom.word_size) ||
6232 ((first + length) > hw->eeprom.word_size))
6235 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6237 return eeprom->ops.read_buffer(hw, first, length, data);
6241 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6242 struct rte_dev_eeprom_info *in_eeprom)
6244 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6245 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6246 uint16_t *data = in_eeprom->data;
6249 first = in_eeprom->offset >> 1;
6250 length = in_eeprom->length >> 1;
6251 if ((first > hw->eeprom.word_size) ||
6252 ((first + length) > hw->eeprom.word_size))
6255 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6257 return eeprom->ops.write_buffer(hw, first, length, data);
6261 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6263 case ixgbe_mac_X550:
6264 case ixgbe_mac_X550EM_x:
6265 case ixgbe_mac_X550EM_a:
6266 return ETH_RSS_RETA_SIZE_512;
6267 case ixgbe_mac_X550_vf:
6268 case ixgbe_mac_X550EM_x_vf:
6269 case ixgbe_mac_X550EM_a_vf:
6270 return ETH_RSS_RETA_SIZE_64;
6272 return ETH_RSS_RETA_SIZE_128;
6277 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6279 case ixgbe_mac_X550:
6280 case ixgbe_mac_X550EM_x:
6281 case ixgbe_mac_X550EM_a:
6282 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6283 return IXGBE_RETA(reta_idx >> 2);
6285 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6286 case ixgbe_mac_X550_vf:
6287 case ixgbe_mac_X550EM_x_vf:
6288 case ixgbe_mac_X550EM_a_vf:
6289 return IXGBE_VFRETA(reta_idx >> 2);
6291 return IXGBE_RETA(reta_idx >> 2);
6296 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6298 case ixgbe_mac_X550_vf:
6299 case ixgbe_mac_X550EM_x_vf:
6300 case ixgbe_mac_X550EM_a_vf:
6301 return IXGBE_VFMRQC;
6308 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6310 case ixgbe_mac_X550_vf:
6311 case ixgbe_mac_X550EM_x_vf:
6312 case ixgbe_mac_X550EM_a_vf:
6313 return IXGBE_VFRSSRK(i);
6315 return IXGBE_RSSRK(i);
6320 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6322 case ixgbe_mac_82599_vf:
6323 case ixgbe_mac_X540_vf:
6331 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6332 struct rte_eth_dcb_info *dcb_info)
6334 struct ixgbe_dcb_config *dcb_config =
6335 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6336 struct ixgbe_dcb_tc_config *tc;
6339 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6340 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6342 dcb_info->nb_tcs = 1;
6344 if (dcb_config->vt_mode) { /* vt is enabled*/
6345 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6346 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6347 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6348 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6349 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6350 for (j = 0; j < dcb_info->nb_tcs; j++) {
6351 dcb_info->tc_queue.tc_rxq[i][j].base =
6352 i * dcb_info->nb_tcs + j;
6353 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6354 dcb_info->tc_queue.tc_txq[i][j].base =
6355 i * dcb_info->nb_tcs + j;
6356 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6359 } else { /* vt is disabled*/
6360 struct rte_eth_dcb_rx_conf *rx_conf =
6361 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6362 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6363 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6364 if (dcb_info->nb_tcs == ETH_4_TCS) {
6365 for (i = 0; i < dcb_info->nb_tcs; i++) {
6366 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6367 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6369 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6370 dcb_info->tc_queue.tc_txq[0][1].base = 64;
6371 dcb_info->tc_queue.tc_txq[0][2].base = 96;
6372 dcb_info->tc_queue.tc_txq[0][3].base = 112;
6373 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6374 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6375 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6376 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6377 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6378 for (i = 0; i < dcb_info->nb_tcs; i++) {
6379 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6380 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6382 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6383 dcb_info->tc_queue.tc_txq[0][1].base = 32;
6384 dcb_info->tc_queue.tc_txq[0][2].base = 64;
6385 dcb_info->tc_queue.tc_txq[0][3].base = 80;
6386 dcb_info->tc_queue.tc_txq[0][4].base = 96;
6387 dcb_info->tc_queue.tc_txq[0][5].base = 104;
6388 dcb_info->tc_queue.tc_txq[0][6].base = 112;
6389 dcb_info->tc_queue.tc_txq[0][7].base = 120;
6390 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6391 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6392 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6393 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6394 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6395 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6396 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6397 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6400 for (i = 0; i < dcb_info->nb_tcs; i++) {
6401 tc = &dcb_config->tc_config[i];
6402 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6407 /* Update e-tag ether type */
6409 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6410 uint16_t ether_type)
6412 uint32_t etag_etype;
6414 if (hw->mac.type != ixgbe_mac_X550 &&
6415 hw->mac.type != ixgbe_mac_X550EM_x &&
6416 hw->mac.type != ixgbe_mac_X550EM_a) {
6420 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6421 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6422 etag_etype |= ether_type;
6423 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6424 IXGBE_WRITE_FLUSH(hw);
6429 /* Config l2 tunnel ether type */
6431 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6432 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6435 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6437 if (l2_tunnel == NULL)
6440 switch (l2_tunnel->l2_tunnel_type) {
6441 case RTE_L2_TUNNEL_TYPE_E_TAG:
6442 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6445 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6453 /* Enable e-tag tunnel */
6455 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6457 uint32_t etag_etype;
6459 if (hw->mac.type != ixgbe_mac_X550 &&
6460 hw->mac.type != ixgbe_mac_X550EM_x &&
6461 hw->mac.type != ixgbe_mac_X550EM_a) {
6465 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6466 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6467 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6468 IXGBE_WRITE_FLUSH(hw);
6473 /* Enable l2 tunnel */
6475 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6476 enum rte_eth_tunnel_type l2_tunnel_type)
6479 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6481 switch (l2_tunnel_type) {
6482 case RTE_L2_TUNNEL_TYPE_E_TAG:
6483 ret = ixgbe_e_tag_enable(hw);
6486 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6494 /* Disable e-tag tunnel */
6496 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6498 uint32_t etag_etype;
6500 if (hw->mac.type != ixgbe_mac_X550 &&
6501 hw->mac.type != ixgbe_mac_X550EM_x &&
6502 hw->mac.type != ixgbe_mac_X550EM_a) {
6506 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6507 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6508 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6509 IXGBE_WRITE_FLUSH(hw);
6514 /* Disable l2 tunnel */
6516 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6517 enum rte_eth_tunnel_type l2_tunnel_type)
6520 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6522 switch (l2_tunnel_type) {
6523 case RTE_L2_TUNNEL_TYPE_E_TAG:
6524 ret = ixgbe_e_tag_disable(hw);
6527 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6536 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6537 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6540 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6541 uint32_t i, rar_entries;
6542 uint32_t rar_low, rar_high;
6544 if (hw->mac.type != ixgbe_mac_X550 &&
6545 hw->mac.type != ixgbe_mac_X550EM_x &&
6546 hw->mac.type != ixgbe_mac_X550EM_a) {
6550 rar_entries = ixgbe_get_num_rx_addrs(hw);
6552 for (i = 1; i < rar_entries; i++) {
6553 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6554 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6555 if ((rar_high & IXGBE_RAH_AV) &&
6556 (rar_high & IXGBE_RAH_ADTYPE) &&
6557 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6558 l2_tunnel->tunnel_id)) {
6559 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6560 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6562 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6572 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6573 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6576 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6577 uint32_t i, rar_entries;
6578 uint32_t rar_low, rar_high;
6580 if (hw->mac.type != ixgbe_mac_X550 &&
6581 hw->mac.type != ixgbe_mac_X550EM_x &&
6582 hw->mac.type != ixgbe_mac_X550EM_a) {
6586 /* One entry for one tunnel. Try to remove potential existing entry. */
6587 ixgbe_e_tag_filter_del(dev, l2_tunnel);
6589 rar_entries = ixgbe_get_num_rx_addrs(hw);
6591 for (i = 1; i < rar_entries; i++) {
6592 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6593 if (rar_high & IXGBE_RAH_AV) {
6596 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6597 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6598 rar_low = l2_tunnel->tunnel_id;
6600 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6601 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6607 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6608 " Please remove a rule before adding a new one.");
6612 /* Add l2 tunnel filter */
6614 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6615 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6619 switch (l2_tunnel->l2_tunnel_type) {
6620 case RTE_L2_TUNNEL_TYPE_E_TAG:
6621 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6624 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6632 /* Delete l2 tunnel filter */
6634 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6635 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6639 switch (l2_tunnel->l2_tunnel_type) {
6640 case RTE_L2_TUNNEL_TYPE_E_TAG:
6641 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6644 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6653 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6654 * @dev: pointer to rte_eth_dev structure
6655 * @filter_op:operation will be taken.
6656 * @arg: a pointer to specific structure corresponding to the filter_op
6659 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6660 enum rte_filter_op filter_op,
6665 if (filter_op == RTE_ETH_FILTER_NOP)
6669 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6674 switch (filter_op) {
6675 case RTE_ETH_FILTER_ADD:
6676 ret = ixgbe_dev_l2_tunnel_filter_add
6678 (struct rte_eth_l2_tunnel_conf *)arg);
6680 case RTE_ETH_FILTER_DELETE:
6681 ret = ixgbe_dev_l2_tunnel_filter_del
6683 (struct rte_eth_l2_tunnel_conf *)arg);
6686 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6694 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6698 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6700 if (hw->mac.type != ixgbe_mac_X550 &&
6701 hw->mac.type != ixgbe_mac_X550EM_x &&
6702 hw->mac.type != ixgbe_mac_X550EM_a) {
6706 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6707 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6709 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6710 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6715 /* Enable l2 tunnel forwarding */
6717 ixgbe_dev_l2_tunnel_forwarding_enable
6718 (struct rte_eth_dev *dev,
6719 enum rte_eth_tunnel_type l2_tunnel_type)
6723 switch (l2_tunnel_type) {
6724 case RTE_L2_TUNNEL_TYPE_E_TAG:
6725 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6728 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6736 /* Disable l2 tunnel forwarding */
6738 ixgbe_dev_l2_tunnel_forwarding_disable
6739 (struct rte_eth_dev *dev,
6740 enum rte_eth_tunnel_type l2_tunnel_type)
6744 switch (l2_tunnel_type) {
6745 case RTE_L2_TUNNEL_TYPE_E_TAG:
6746 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6749 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6758 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6759 struct rte_eth_l2_tunnel_conf *l2_tunnel,
6763 uint32_t vmtir, vmvir;
6764 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6766 if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6768 "VF id %u should be less than %u",
6770 dev->pci_dev->max_vfs);
6774 if (hw->mac.type != ixgbe_mac_X550 &&
6775 hw->mac.type != ixgbe_mac_X550EM_x &&
6776 hw->mac.type != ixgbe_mac_X550EM_a) {
6781 vmtir = l2_tunnel->tunnel_id;
6785 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6787 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6788 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6790 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6791 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6796 /* Enable l2 tunnel tag insertion */
6798 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6799 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6803 switch (l2_tunnel->l2_tunnel_type) {
6804 case RTE_L2_TUNNEL_TYPE_E_TAG:
6805 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6808 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6816 /* Disable l2 tunnel tag insertion */
6818 ixgbe_dev_l2_tunnel_insertion_disable
6819 (struct rte_eth_dev *dev,
6820 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6824 switch (l2_tunnel->l2_tunnel_type) {
6825 case RTE_L2_TUNNEL_TYPE_E_TAG:
6826 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6829 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6838 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6843 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6845 if (hw->mac.type != ixgbe_mac_X550 &&
6846 hw->mac.type != ixgbe_mac_X550EM_x &&
6847 hw->mac.type != ixgbe_mac_X550EM_a) {
6851 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6853 qde |= IXGBE_QDE_STRIP_TAG;
6855 qde &= ~IXGBE_QDE_STRIP_TAG;
6856 qde &= ~IXGBE_QDE_READ;
6857 qde |= IXGBE_QDE_WRITE;
6858 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6863 /* Enable l2 tunnel tag stripping */
6865 ixgbe_dev_l2_tunnel_stripping_enable
6866 (struct rte_eth_dev *dev,
6867 enum rte_eth_tunnel_type l2_tunnel_type)
6871 switch (l2_tunnel_type) {
6872 case RTE_L2_TUNNEL_TYPE_E_TAG:
6873 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6876 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6884 /* Disable l2 tunnel tag stripping */
6886 ixgbe_dev_l2_tunnel_stripping_disable
6887 (struct rte_eth_dev *dev,
6888 enum rte_eth_tunnel_type l2_tunnel_type)
6892 switch (l2_tunnel_type) {
6893 case RTE_L2_TUNNEL_TYPE_E_TAG:
6894 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6897 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6905 /* Enable/disable l2 tunnel offload functions */
6907 ixgbe_dev_l2_tunnel_offload_set
6908 (struct rte_eth_dev *dev,
6909 struct rte_eth_l2_tunnel_conf *l2_tunnel,
6915 if (l2_tunnel == NULL)
6919 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6921 ret = ixgbe_dev_l2_tunnel_enable(
6923 l2_tunnel->l2_tunnel_type);
6925 ret = ixgbe_dev_l2_tunnel_disable(
6927 l2_tunnel->l2_tunnel_type);
6930 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6932 ret = ixgbe_dev_l2_tunnel_insertion_enable(
6936 ret = ixgbe_dev_l2_tunnel_insertion_disable(
6941 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6943 ret = ixgbe_dev_l2_tunnel_stripping_enable(
6945 l2_tunnel->l2_tunnel_type);
6947 ret = ixgbe_dev_l2_tunnel_stripping_disable(
6949 l2_tunnel->l2_tunnel_type);
6952 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6954 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6956 l2_tunnel->l2_tunnel_type);
6958 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6960 l2_tunnel->l2_tunnel_type);
6967 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6970 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6971 IXGBE_WRITE_FLUSH(hw);
6976 /* There's only one register for VxLAN UDP port.
6977 * So, we cannot add several ports. Will update it.
6980 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6984 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6988 return ixgbe_update_vxlan_port(hw, port);
6991 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6992 * UDP port, it must have a value.
6993 * So, will reset it to the original value 0.
6996 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7001 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7003 if (cur_port != port) {
7004 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7008 return ixgbe_update_vxlan_port(hw, 0);
7011 /* Add UDP tunneling port */
7013 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7014 struct rte_eth_udp_tunnel *udp_tunnel)
7017 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7019 if (hw->mac.type != ixgbe_mac_X550 &&
7020 hw->mac.type != ixgbe_mac_X550EM_x &&
7021 hw->mac.type != ixgbe_mac_X550EM_a) {
7025 if (udp_tunnel == NULL)
7028 switch (udp_tunnel->prot_type) {
7029 case RTE_TUNNEL_TYPE_VXLAN:
7030 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7033 case RTE_TUNNEL_TYPE_GENEVE:
7034 case RTE_TUNNEL_TYPE_TEREDO:
7035 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7040 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7048 /* Remove UDP tunneling port */
7050 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7051 struct rte_eth_udp_tunnel *udp_tunnel)
7054 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7056 if (hw->mac.type != ixgbe_mac_X550 &&
7057 hw->mac.type != ixgbe_mac_X550EM_x &&
7058 hw->mac.type != ixgbe_mac_X550EM_a) {
7062 if (udp_tunnel == NULL)
7065 switch (udp_tunnel->prot_type) {
7066 case RTE_TUNNEL_TYPE_VXLAN:
7067 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7069 case RTE_TUNNEL_TYPE_GENEVE:
7070 case RTE_TUNNEL_TYPE_TEREDO:
7071 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7075 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7083 /* ixgbevf_update_xcast_mode - Update Multicast mode
7084 * @hw: pointer to the HW structure
7085 * @netdev: pointer to net device structure
7086 * @xcast_mode: new multicast mode
7088 * Updates the Multicast Mode of VF.
7090 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7093 struct ixgbe_mbx_info *mbx = &hw->mbx;
7097 switch (hw->api_version) {
7098 case ixgbe_mbox_api_12:
7104 msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7105 msgbuf[1] = xcast_mode;
7107 err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7111 err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7115 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7116 if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7123 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7125 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7127 ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7131 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7133 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7135 ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7138 static struct rte_driver rte_ixgbe_driver = {
7140 .init = rte_ixgbe_pmd_init,
7143 static struct rte_driver rte_ixgbevf_driver = {
7145 .init = rte_ixgbevf_pmd_init,
7148 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7149 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);