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34 #ifndef _IXGBE_ETHDEV_H_
35 #define _IXGBE_ETHDEV_H_
36 #include "base/ixgbe_type.h"
37 #include "base/ixgbe_dcb.h"
38 #include "base/ixgbe_dcb_82599.h"
39 #include "base/ixgbe_dcb_82598.h"
40 #include "ixgbe_bypass.h"
41 #ifdef RTE_LIBRTE_SECURITY
42 #include "ixgbe_ipsec.h"
47 #include <rte_bus_pci.h>
48 #include <rte_tm_driver.h>
50 /* need update link, bit flag */
51 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
52 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
53 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
54 #define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
55 #define IXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
58 * Defines that were not part of ixgbe_type.h as they are not used by the
61 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
62 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
63 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
64 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
65 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
66 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
67 #define IXGBE_NB_STAT_MAPPING_REGS 32
68 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
69 #define IXGBE_VFTA_SIZE 128
70 #define IXGBE_VLAN_TAG_SIZE 4
71 #define IXGBE_MAX_RX_QUEUE_NUM 128
72 #define IXGBE_MAX_INTR_QUEUE_NUM 15
73 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
74 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
75 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64
78 #define NBBY 8 /* number of bits in a byte */
80 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
82 /* EITR Interval is in 2048ns uinits for 1G and 10G link */
83 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
84 #define IXGBE_EITR_ITR_INT_SHIFT 3
85 #define IXGBE_EITR_INTERVAL_US(us) \
86 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
87 IXGBE_EITR_ITR_INT_MASK)
90 /* Loopback operation modes */
91 /* 82599 specific loopback operation types */
92 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
93 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
95 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
97 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
98 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
99 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
101 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
103 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
104 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
105 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
106 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
108 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
109 #define IXGBE_ETQF_SHIFT 16
110 #define IXGBE_ETQF_UP_EN 0x00080000
111 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
112 #define IXGBE_ETQF_MAX_PRI 7
114 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
115 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
116 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
118 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
119 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
120 #define IXGBE_L34T_IMIR_LLI 0x00100000
121 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
122 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
123 #define IXGBE_5TUPLE_MAX_PRI 7
124 #define IXGBE_5TUPLE_MIN_PRI 1
126 /* bit of VXLAN tunnel type | 7 bits of zeros | 8 bits of zeros*/
127 #define IXGBE_FDIR_VXLAN_TUNNEL_TYPE 0x8000
128 /* bit of NVGRE tunnel type | 7 bits of zeros | 8 bits of zeros*/
129 #define IXGBE_FDIR_NVGRE_TUNNEL_TYPE 0x0
131 #define IXGBE_RSS_OFFLOAD_ALL ( \
133 ETH_RSS_NONFRAG_IPV4_TCP | \
134 ETH_RSS_NONFRAG_IPV4_UDP | \
136 ETH_RSS_NONFRAG_IPV6_TCP | \
137 ETH_RSS_NONFRAG_IPV6_UDP | \
139 ETH_RSS_IPV6_TCP_EX | \
142 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
143 #define IXGBE_VF_MAXMSIVECTOR 1
145 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
146 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
148 #define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F
150 #define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00
152 #define IXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
153 #define IXGBE_MAX_L2_TN_FILTER_NUM 128
155 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
156 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
160 #define MAC_TYPE_FILTER_SUP(type) do {\
161 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
162 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
163 (type) != ixgbe_mac_X550EM_a)\
167 /* Link speed for X550 auto negotiation */
168 #define IXGBE_LINK_SPEED_X550_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
169 IXGBE_LINK_SPEED_1GB_FULL | \
170 IXGBE_LINK_SPEED_2_5GB_FULL | \
171 IXGBE_LINK_SPEED_5GB_FULL | \
172 IXGBE_LINK_SPEED_10GB_FULL)
175 * Information about the fdir mode.
177 struct ixgbe_hw_fdir_mask {
178 uint16_t vlan_tci_mask;
179 uint32_t src_ipv4_mask;
180 uint32_t dst_ipv4_mask;
181 uint16_t src_ipv6_mask;
182 uint16_t dst_ipv6_mask;
183 uint16_t src_port_mask;
184 uint16_t dst_port_mask;
185 uint16_t flex_bytes_mask;
186 uint8_t mac_addr_byte_mask;
187 uint32_t tunnel_id_mask;
188 uint8_t tunnel_type_mask;
191 struct ixgbe_fdir_filter {
192 TAILQ_ENTRY(ixgbe_fdir_filter) entries;
193 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
194 uint32_t fdirflags; /* drop or forward */
195 uint32_t fdirhash; /* hash value for fdir */
196 uint8_t queue; /* assigned rx queue */
199 /* list of fdir filters */
200 TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter);
202 struct ixgbe_fdir_rule {
203 struct ixgbe_hw_fdir_mask mask;
204 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
205 bool b_spec; /* If TRUE, ixgbe_fdir, fdirflags, queue have meaning. */
206 bool b_mask; /* If TRUE, mask has meaning. */
207 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
208 uint32_t fdirflags; /* drop or forward */
209 uint32_t soft_id; /* an unique value for this rule */
210 uint8_t queue; /* assigned rx queue */
211 uint8_t flex_bytes_offset;
214 struct ixgbe_hw_fdir_info {
215 struct ixgbe_hw_fdir_mask mask;
216 uint8_t flex_bytes_offset;
225 struct ixgbe_fdir_filter_list fdir_list; /* filter list*/
226 /* store the pointers of the filters, index is the hash value. */
227 struct ixgbe_fdir_filter **hash_map;
228 struct rte_hash *hash_handle; /* cuckoo hash handler */
229 bool mask_added; /* If already got mask from consistent filter */
232 /* structure for interrupt relative data */
233 struct ixgbe_interrupt {
236 /*to save original mask during delayed handler */
237 uint32_t mask_original;
240 struct ixgbe_stat_mapping_registers {
241 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
242 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
246 uint32_t vfta[IXGBE_VFTA_SIZE];
249 struct ixgbe_hwstrip {
250 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
254 * VF data which used by PF host only
256 #define IXGBE_MAX_VF_MC_ENTRIES 30
257 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
258 #define IXGBE_MAX_UTA 128
260 struct ixgbe_uta_info {
261 uint8_t uc_filter_type;
263 uint32_t uta_shadow[IXGBE_MAX_UTA];
266 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
268 struct ixgbe_mirror_info {
269 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
270 /**< store PF mirror rules configuration*/
273 struct ixgbe_vf_info {
274 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
275 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
276 uint16_t num_vf_mc_hashes;
277 uint16_t default_vf_vlan_id;
278 uint16_t vlans_enabled;
280 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
282 uint8_t spoofchk_enabled;
287 * Possible l4type of 5tuple filters.
289 enum ixgbe_5tuple_protocol {
290 IXGBE_FILTER_PROTOCOL_TCP = 0,
291 IXGBE_FILTER_PROTOCOL_UDP,
292 IXGBE_FILTER_PROTOCOL_SCTP,
293 IXGBE_FILTER_PROTOCOL_NONE,
296 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
298 struct ixgbe_5tuple_filter_info {
303 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
304 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
305 used when more than one filter matches. */
306 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
307 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
308 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
309 src_port_mask:1, /* if mask is 1b, do not compare src port. */
310 proto_mask:1; /* if mask is 1b, do not compare protocol. */
313 /* 5tuple filter structure */
314 struct ixgbe_5tuple_filter {
315 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
316 uint16_t index; /* the index of 5tuple filter */
317 struct ixgbe_5tuple_filter_info filter_info;
318 uint16_t queue; /* rx queue assigned to */
321 #define IXGBE_5TUPLE_ARRAY_SIZE \
322 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
323 (sizeof(uint32_t) * NBBY))
325 struct ixgbe_ethertype_filter {
330 * If this filter is added by configuration,
331 * it should not be removed.
337 * Structure to store filters' info.
339 struct ixgbe_filter_info {
340 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
341 /* store used ethertype filters*/
342 struct ixgbe_ethertype_filter ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
343 /* Bit mask for every used 5tuple filter */
344 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
345 struct ixgbe_5tuple_filter_list fivetuple_list;
346 /* store the SYN filter info */
350 struct ixgbe_l2_tn_key {
351 enum rte_eth_tunnel_type l2_tn_type;
355 struct ixgbe_l2_tn_filter {
356 TAILQ_ENTRY(ixgbe_l2_tn_filter) entries;
357 struct ixgbe_l2_tn_key key;
361 TAILQ_HEAD(ixgbe_l2_tn_filter_list, ixgbe_l2_tn_filter);
363 struct ixgbe_l2_tn_info {
364 struct ixgbe_l2_tn_filter_list l2_tn_list;
365 struct ixgbe_l2_tn_filter **hash_map;
366 struct rte_hash *hash_handle;
367 bool e_tag_en; /* e-tag enabled */
368 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
369 bool e_tag_ether_type; /* ether type for e-tag */
373 enum rte_filter_type filter_type;
378 * Statistics counters collected by the MACsec
380 struct ixgbe_macsec_stats {
381 /* TX port statistics */
382 uint64_t out_pkts_untagged;
383 uint64_t out_pkts_encrypted;
384 uint64_t out_pkts_protected;
385 uint64_t out_octets_encrypted;
386 uint64_t out_octets_protected;
388 /* RX port statistics */
389 uint64_t in_pkts_untagged;
390 uint64_t in_pkts_badtag;
391 uint64_t in_pkts_nosci;
392 uint64_t in_pkts_unknownsci;
393 uint64_t in_octets_decrypted;
394 uint64_t in_octets_validated;
396 /* RX SC statistics */
397 uint64_t in_pkts_unchecked;
398 uint64_t in_pkts_delayed;
399 uint64_t in_pkts_late;
401 /* RX SA statistics */
403 uint64_t in_pkts_invalid;
404 uint64_t in_pkts_notvalid;
405 uint64_t in_pkts_unusedsa;
406 uint64_t in_pkts_notusingsa;
409 /* The configuration of bandwidth */
410 struct ixgbe_bw_conf {
411 uint8_t tc_num; /* Number of TCs. */
414 /* Struct to store Traffic Manager shaper profile. */
415 struct ixgbe_tm_shaper_profile {
416 TAILQ_ENTRY(ixgbe_tm_shaper_profile) node;
417 uint32_t shaper_profile_id;
418 uint32_t reference_count;
419 struct rte_tm_shaper_params profile;
422 TAILQ_HEAD(ixgbe_shaper_profile_list, ixgbe_tm_shaper_profile);
424 /* node type of Traffic Manager */
425 enum ixgbe_tm_node_type {
426 IXGBE_TM_NODE_TYPE_PORT,
427 IXGBE_TM_NODE_TYPE_TC,
428 IXGBE_TM_NODE_TYPE_QUEUE,
429 IXGBE_TM_NODE_TYPE_MAX,
432 /* Struct to store Traffic Manager node configuration. */
433 struct ixgbe_tm_node {
434 TAILQ_ENTRY(ixgbe_tm_node) node;
438 uint32_t reference_count;
440 struct ixgbe_tm_node *parent;
441 struct ixgbe_tm_shaper_profile *shaper_profile;
442 struct rte_tm_node_params params;
445 TAILQ_HEAD(ixgbe_tm_node_list, ixgbe_tm_node);
447 /* The configuration of Traffic Manager */
448 struct ixgbe_tm_conf {
449 struct ixgbe_shaper_profile_list shaper_profile_list;
450 struct ixgbe_tm_node *root; /* root node - port */
451 struct ixgbe_tm_node_list tc_list; /* node list for all the TCs */
452 struct ixgbe_tm_node_list queue_list; /* node list for all the queues */
454 * The number of added TC nodes.
455 * It should be no more than the TC number of this port.
459 * The number of added queue nodes.
460 * It should be no more than the queue number of this port.
462 uint32_t nb_queue_node;
464 * This flag is used to check if APP can change the TM node
466 * When it's true, means the configuration is applied to HW,
467 * APP should not change the configuration.
468 * As we don't support on-the-fly configuration, when starting
469 * the port, APP should call the hierarchy_commit API to set this
470 * flag to true. When stopping the port, this flag should be set
477 * Structure to store private data for each driver instance (for each port).
479 struct ixgbe_adapter {
481 struct ixgbe_hw_stats stats;
482 struct ixgbe_macsec_stats macsec_stats;
483 struct ixgbe_hw_fdir_info fdir;
484 struct ixgbe_interrupt intr;
485 struct ixgbe_stat_mapping_registers stat_mappings;
486 struct ixgbe_vfta shadow_vfta;
487 struct ixgbe_hwstrip hwstrip;
488 struct ixgbe_dcb_config dcb_config;
489 struct ixgbe_mirror_info mr_data;
490 struct ixgbe_vf_info *vfdata;
491 struct ixgbe_uta_info uta_info;
492 #ifdef RTE_LIBRTE_IXGBE_BYPASS
493 struct ixgbe_bypass_info bps;
494 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
495 struct ixgbe_filter_info filter;
496 struct ixgbe_l2_tn_info l2_tn;
497 struct ixgbe_bw_conf bw_conf;
498 #ifdef RTE_LIBRTE_SECURITY
499 struct ixgbe_ipsec ipsec;
501 bool rx_bulk_alloc_allowed;
503 struct rte_timecounter systime_tc;
504 struct rte_timecounter rx_tstamp_tc;
505 struct rte_timecounter tx_tstamp_tc;
506 struct ixgbe_tm_conf tm_conf;
509 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
510 (&((struct ixgbe_adapter *)adapter)->hw)
512 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
513 (&((struct ixgbe_adapter *)adapter)->stats)
515 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \
516 (&((struct ixgbe_adapter *)adapter)->macsec_stats)
518 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
519 (&((struct ixgbe_adapter *)adapter)->intr)
521 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
522 (&((struct ixgbe_adapter *)adapter)->fdir)
524 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
525 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
527 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
528 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
530 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
531 (&((struct ixgbe_adapter *)adapter)->hwstrip)
533 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
534 (&((struct ixgbe_adapter *)adapter)->dcb_config)
536 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
537 (&((struct ixgbe_adapter *)adapter)->vfdata)
539 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
540 (&((struct ixgbe_adapter *)adapter)->mr_data)
542 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
543 (&((struct ixgbe_adapter *)adapter)->uta_info)
545 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
546 (&((struct ixgbe_adapter *)adapter)->filter)
548 #define IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(adapter) \
549 (&((struct ixgbe_adapter *)adapter)->l2_tn)
551 #define IXGBE_DEV_PRIVATE_TO_BW_CONF(adapter) \
552 (&((struct ixgbe_adapter *)adapter)->bw_conf)
554 #define IXGBE_DEV_PRIVATE_TO_TM_CONF(adapter) \
555 (&((struct ixgbe_adapter *)adapter)->tm_conf)
557 #define IXGBE_DEV_PRIVATE_TO_IPSEC(adapter)\
558 (&((struct ixgbe_adapter *)adapter)->ipsec)
561 * RX/TX function prototypes
563 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
565 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
567 void ixgbe_dev_rx_queue_release(void *rxq);
569 void ixgbe_dev_tx_queue_release(void *txq);
571 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
572 uint16_t nb_rx_desc, unsigned int socket_id,
573 const struct rte_eth_rxconf *rx_conf,
574 struct rte_mempool *mb_pool);
576 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
577 uint16_t nb_tx_desc, unsigned int socket_id,
578 const struct rte_eth_txconf *tx_conf);
580 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
581 uint16_t rx_queue_id);
583 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
585 int ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
586 int ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
588 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
590 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
592 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
594 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
596 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
598 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
600 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
602 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
603 struct rte_eth_rxq_info *qinfo);
605 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
606 struct rte_eth_txq_info *qinfo);
608 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
610 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
612 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
614 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
617 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
620 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
621 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
622 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
623 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
625 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
628 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
631 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
634 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
635 struct rte_eth_rss_conf *rss_conf);
637 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
638 struct rte_eth_rss_conf *rss_conf);
640 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
642 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
644 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
646 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
648 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
650 int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
651 struct rte_eth_ntuple_filter *filter,
653 int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
654 struct rte_eth_ethertype_filter *filter,
656 int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
657 struct rte_eth_syn_filter *filter,
660 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
661 struct rte_eth_l2_tunnel_conf *l2_tunnel,
664 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
665 struct rte_eth_l2_tunnel_conf *l2_tunnel);
666 void ixgbe_filterlist_init(void);
667 void ixgbe_filterlist_flush(void);
669 * Flow director function prototypes
671 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
672 int ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
673 int ixgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
675 int ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
676 struct ixgbe_fdir_rule *rule,
677 bool del, bool update);
679 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
682 * misc function prototypes
684 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
686 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
688 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
690 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
692 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
694 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
696 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
698 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
700 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
702 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
703 enum rte_filter_op filter_op, void *arg);
704 void ixgbe_fdir_filter_restore(struct rte_eth_dev *dev);
705 int ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
707 extern const struct rte_flow_ops ixgbe_flow_ops;
709 void ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
710 void ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
711 void ixgbe_clear_syn_filter(struct rte_eth_dev *dev);
712 int ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
714 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw);
716 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw);
718 int ixgbe_vt_check(struct ixgbe_hw *hw);
719 int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
720 uint16_t tx_rate, uint64_t q_msk);
721 bool is_ixgbe_supported(struct rte_eth_dev *dev);
722 int ixgbe_tm_ops_get(struct rte_eth_dev *dev, void *ops);
723 void ixgbe_tm_conf_init(struct rte_eth_dev *dev);
724 void ixgbe_tm_conf_uninit(struct rte_eth_dev *dev);
725 int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
729 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
734 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
735 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
736 (filter_info->ethertype_mask & (1 << i)))
743 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
744 struct ixgbe_ethertype_filter *ethertype_filter)
748 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
749 if (!(filter_info->ethertype_mask & (1 << i))) {
750 filter_info->ethertype_mask |= 1 << i;
751 filter_info->ethertype_filters[i].ethertype =
752 ethertype_filter->ethertype;
753 filter_info->ethertype_filters[i].etqf =
754 ethertype_filter->etqf;
755 filter_info->ethertype_filters[i].etqs =
756 ethertype_filter->etqs;
757 filter_info->ethertype_filters[i].conf =
758 ethertype_filter->conf;
766 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
769 if (idx >= IXGBE_MAX_ETQF_FILTERS)
771 filter_info->ethertype_mask &= ~(1 << idx);
772 filter_info->ethertype_filters[idx].ethertype = 0;
773 filter_info->ethertype_filters[idx].etqf = 0;
774 filter_info->ethertype_filters[idx].etqs = 0;
775 filter_info->ethertype_filters[idx].etqs = FALSE;
779 #endif /* _IXGBE_ETHDEV_H_ */