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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <rte_ethdev.h>
36 #include <rte_malloc.h>
38 #include "ixgbe_ethdev.h"
39 #include "ixgbe_rxtx.h"
41 #include <tmmintrin.h>
43 #ifndef __INTEL_COMPILER
44 #pragma GCC diagnostic ignored "-Wcast-qual"
48 ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)
52 volatile union ixgbe_adv_rx_desc *rxdp;
53 struct ixgbe_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
54 struct rte_mbuf *mb0, *mb1;
55 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
56 RTE_PKTMBUF_HEADROOM);
57 __m128i dma_addr0, dma_addr1;
59 const __m128i hba_msk = _mm_set_epi64x(0, UINT64_MAX);
61 rxdp = rxq->rx_ring + rxq->rxrearm_start;
63 /* Pull 'n' more MBUFs into the software ring */
64 if (rte_mempool_get_bulk(rxq->mb_pool,
66 RTE_IXGBE_RXQ_REARM_THRESH) < 0) {
67 if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=
69 dma_addr0 = _mm_setzero_si128();
70 for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {
71 rxep[i].mbuf = &rxq->fake_mbuf;
72 _mm_store_si128((__m128i *)&rxdp[i].read,
76 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
77 RTE_IXGBE_RXQ_REARM_THRESH;
81 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
82 for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
83 __m128i vaddr0, vaddr1;
90 * Flush mbuf with pkt template.
91 * Data to be rearmed is 6 bytes long.
92 * Though, RX will overwrite ol_flags that are coming next
93 * anyway. So overwrite whole 8 bytes with one load:
94 * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
96 p0 = (uintptr_t)&mb0->rearm_data;
97 *(uint64_t *)p0 = rxq->mbuf_initializer;
98 p1 = (uintptr_t)&mb1->rearm_data;
99 *(uint64_t *)p1 = rxq->mbuf_initializer;
101 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
102 vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));
103 vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));
105 /* convert pa to dma_addr hdr/data */
106 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
107 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
109 /* add headroom to pa values */
110 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
111 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
113 /* set Header Buffer Address to zero */
114 dma_addr0 = _mm_and_si128(dma_addr0, hba_msk);
115 dma_addr1 = _mm_and_si128(dma_addr1, hba_msk);
117 /* flush desc with pa dma_addr */
118 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
119 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
122 rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;
123 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
124 rxq->rxrearm_start = 0;
126 rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;
128 rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?
129 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
131 /* Update the tail pointer on the NIC */
132 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
135 /* Handling the offload flags (olflags) field takes computation
136 * time when receiving packets. Therefore we provide a flag to disable
137 * the processing of the olflags field when they are not needed. This
138 * gives improved performance, at the cost of losing the offload info
139 * in the received packet
141 #ifdef RTE_IXGBE_RX_OLFLAGS_ENABLE
143 #define VTAG_SHIFT (3)
146 desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
148 __m128i ptype0, ptype1, vtag0, vtag1;
154 /* pkt type + vlan olflags mask */
155 const __m128i pkttype_msk = _mm_set_epi16(
156 0x0000, 0x0000, 0x0000, 0x0000,
157 PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT);
159 /* mask everything except rss type */
160 const __m128i rsstype_msk = _mm_set_epi16(
161 0x0000, 0x0000, 0x0000, 0x0000,
162 0x000F, 0x000F, 0x000F, 0x000F);
164 /* map rss type to rss hash flag */
165 const __m128i rss_flags = _mm_set_epi8(PKT_RX_FDIR, 0, 0, 0,
166 0, 0, 0, PKT_RX_RSS_HASH,
167 PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
168 PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
170 ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
171 ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
172 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
173 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
175 ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
176 ptype0 = _mm_and_si128(ptype0, rsstype_msk);
177 ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
179 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
180 vtag1 = _mm_srli_epi16(vtag1, VTAG_SHIFT);
181 vtag1 = _mm_and_si128(vtag1, pkttype_msk);
183 vtag1 = _mm_or_si128(ptype0, vtag1);
184 vol.dword = _mm_cvtsi128_si64(vtag1);
186 rx_pkts[0]->ol_flags = vol.e[0];
187 rx_pkts[1]->ol_flags = vol.e[1];
188 rx_pkts[2]->ol_flags = vol.e[2];
189 rx_pkts[3]->ol_flags = vol.e[3];
192 #define desc_to_olflags_v(desc, rx_pkts) do {} while (0)
196 * vPMD raw receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
199 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
200 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
202 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
203 * - don't support ol_flags for rss and csum err
205 static inline uint16_t
206 _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
207 uint16_t nb_pkts, uint8_t *split_packet)
209 volatile union ixgbe_adv_rx_desc *rxdp;
210 struct ixgbe_rx_entry *sw_ring;
211 uint16_t nb_pkts_recd;
215 __m128i crc_adjust = _mm_set_epi16(
216 0, 0, 0, /* ignore non-length fields */
217 -rxq->crc_len, /* sub crc on data_len */
218 0, /* ignore high-16bits of pkt_len */
219 -rxq->crc_len, /* sub crc on pkt_len */
220 0, 0 /* ignore pkt_type field */
222 __m128i dd_check, eop_check;
224 /* nb_pkts shall be less equal than RTE_IXGBE_MAX_RX_BURST */
225 nb_pkts = RTE_MIN(nb_pkts, RTE_IXGBE_MAX_RX_BURST);
227 /* nb_pkts has to be floor-aligned to RTE_IXGBE_DESCS_PER_LOOP */
228 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_IXGBE_DESCS_PER_LOOP);
230 /* Just the act of getting into the function from the application is
231 * going to cost about 7 cycles */
232 rxdp = rxq->rx_ring + rxq->rx_tail;
234 _mm_prefetch((const void *)rxdp, _MM_HINT_T0);
236 /* See if we need to rearm the RX queue - gives the prefetch a bit
238 if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)
239 ixgbe_rxq_rearm(rxq);
241 /* Before we start moving massive data around, check to see if
242 * there is actually a packet available */
243 if (!(rxdp->wb.upper.status_error &
244 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
247 /* 4 packets DD mask */
248 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
250 /* 4 packets EOP mask */
251 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
253 /* mask to shuffle from desc. to mbuf */
254 shuf_msk = _mm_set_epi8(
255 7, 6, 5, 4, /* octet 4~7, 32bits rss */
256 15, 14, /* octet 14~15, low 16 bits vlan_macip */
257 13, 12, /* octet 12~13, 16 bits data_len */
258 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
259 13, 12, /* octet 12~13, low 16 bits pkt_len */
260 0xFF, 0xFF, /* skip 32 bit pkt_type */
264 /* Cache is empty -> need to scan the buffer rings, but first move
265 * the next 'n' mbufs into the cache */
266 sw_ring = &rxq->sw_ring[rxq->rx_tail];
268 /* A. load 4 packet in one loop
269 * [A*. mask out 4 unused dirty field in desc]
270 * B. copy 4 mbuf point from swring to rx_pkts
271 * C. calc the number of DD bits among the 4 packets
272 * [C*. extract the end-of-packet bit, if requested]
273 * D. fill info. from desc to mbuf
275 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
276 pos += RTE_IXGBE_DESCS_PER_LOOP,
277 rxdp += RTE_IXGBE_DESCS_PER_LOOP) {
278 __m128i descs[RTE_IXGBE_DESCS_PER_LOOP];
279 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
280 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
281 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
283 /* B.1 load 1 mbuf point */
284 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
286 /* Read desc statuses backwards to avoid race condition */
287 /* A.1 load 4 pkts desc */
288 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
290 /* B.2 copy 2 mbuf point into rx_pkts */
291 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
293 /* B.1 load 1 mbuf point */
294 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
296 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
297 /* B.1 load 2 mbuf point */
298 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
299 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
301 /* B.2 copy 2 mbuf point into rx_pkts */
302 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
305 rte_prefetch0(&rx_pkts[pos]->cacheline1);
306 rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
307 rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
308 rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
311 /* avoid compiler reorder optimization */
312 rte_compiler_barrier();
314 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
315 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
316 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
318 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
319 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
320 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
322 /* C.1 4=>2 filter staterr info only */
323 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
324 /* C.1 4=>2 filter staterr info only */
325 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
327 /* set ol_flags with vlan packet type */
328 desc_to_olflags_v(descs, &rx_pkts[pos]);
330 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
331 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
332 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
334 /* C.2 get 4 pkts staterr value */
335 zero = _mm_xor_si128(dd_check, dd_check);
336 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
338 /* D.3 copy final 3,4 data to rx_pkts */
339 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
341 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
344 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
345 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
346 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
348 /* C* extract and record EOP bit */
350 __m128i eop_shuf_mask = _mm_set_epi8(
351 0xFF, 0xFF, 0xFF, 0xFF,
352 0xFF, 0xFF, 0xFF, 0xFF,
353 0xFF, 0xFF, 0xFF, 0xFF,
354 0x04, 0x0C, 0x00, 0x08
357 /* and with mask to extract bits, flipping 1-0 */
358 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
359 /* the staterr values are not in order, as the count
360 * count of dd bits doesn't care. However, for end of
361 * packet tracking, we do care, so shuffle. This also
362 * compresses the 32-bit values to 8-bit */
363 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
364 /* store the resulting 32-bit value */
365 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
366 split_packet += RTE_IXGBE_DESCS_PER_LOOP;
368 /* zero-out next pointers */
369 rx_pkts[pos]->next = NULL;
370 rx_pkts[pos + 1]->next = NULL;
371 rx_pkts[pos + 2]->next = NULL;
372 rx_pkts[pos + 3]->next = NULL;
375 /* C.3 calc available number of desc */
376 staterr = _mm_and_si128(staterr, dd_check);
377 staterr = _mm_packs_epi32(staterr, zero);
379 /* D.3 copy final 1,2 data to rx_pkts */
380 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
382 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
385 /* C.4 calc avaialbe number of desc */
386 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
388 if (likely(var != RTE_IXGBE_DESCS_PER_LOOP))
392 /* Update our internal tail pointer */
393 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
394 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
395 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
401 * vPMD receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
404 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
405 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
407 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
408 * - don't support ol_flags for rss and csum err
411 ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
414 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
417 static inline uint16_t
418 reassemble_packets(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_bufs,
419 uint16_t nb_bufs, uint8_t *split_flags)
421 struct rte_mbuf *pkts[nb_bufs]; /*finished pkts*/
422 struct rte_mbuf *start = rxq->pkt_first_seg;
423 struct rte_mbuf *end = rxq->pkt_last_seg;
424 unsigned pkt_idx, buf_idx;
426 for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
428 /* processing a split packet */
429 end->next = rx_bufs[buf_idx];
430 rx_bufs[buf_idx]->data_len += rxq->crc_len;
433 start->pkt_len += rx_bufs[buf_idx]->data_len;
436 if (!split_flags[buf_idx]) {
437 /* it's the last packet of the set */
438 start->hash = end->hash;
439 start->ol_flags = end->ol_flags;
440 /* we need to strip crc for the whole packet */
441 start->pkt_len -= rxq->crc_len;
442 if (end->data_len > rxq->crc_len)
443 end->data_len -= rxq->crc_len;
445 /* free up last mbuf */
446 struct rte_mbuf *secondlast = start;
449 while (secondlast->next != end)
450 secondlast = secondlast->next;
451 secondlast->data_len -= (rxq->crc_len -
453 secondlast->next = NULL;
454 rte_pktmbuf_free_seg(end);
457 pkts[pkt_idx++] = start;
461 /* not processing a split packet */
462 if (!split_flags[buf_idx]) {
463 /* not a split packet, save and skip */
464 pkts[pkt_idx++] = rx_bufs[buf_idx];
467 end = start = rx_bufs[buf_idx];
468 rx_bufs[buf_idx]->data_len += rxq->crc_len;
469 rx_bufs[buf_idx]->pkt_len += rxq->crc_len;
473 /* save the partial packet for next time */
474 rxq->pkt_first_seg = start;
475 rxq->pkt_last_seg = end;
476 memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
481 * vPMD receive routine that reassembles scattered packets
484 * - don't support ol_flags for rss and csum err
485 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
486 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
488 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
491 ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
494 struct ixgbe_rx_queue *rxq = rx_queue;
495 uint8_t split_flags[RTE_IXGBE_MAX_RX_BURST] = {0};
497 /* get some new buffers */
498 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
503 /* happy day case, full burst + no packets to be joined */
504 const uint64_t *split_fl64 = (uint64_t *)split_flags;
505 if (rxq->pkt_first_seg == NULL &&
506 split_fl64[0] == 0 && split_fl64[1] == 0 &&
507 split_fl64[2] == 0 && split_fl64[3] == 0)
510 /* reassemble any packets that need reassembly*/
512 if (rxq->pkt_first_seg == NULL) {
513 /* find the first split flag, and only reassemble then*/
514 while (i < nb_bufs && !split_flags[i])
519 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
524 vtx1(volatile union ixgbe_adv_tx_desc *txdp,
525 struct rte_mbuf *pkt, uint64_t flags)
527 __m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |
528 flags | pkt->data_len,
529 pkt->buf_physaddr + pkt->data_off);
530 _mm_store_si128((__m128i *)&txdp->read, descriptor);
534 vtx(volatile union ixgbe_adv_tx_desc *txdp,
535 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
538 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
539 vtx1(txdp, *pkt, flags);
542 static inline int __attribute__((always_inline))
543 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
545 struct ixgbe_tx_entry_v *txep;
550 struct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];
552 /* check DD bit on threshold descriptor */
553 status = txq->tx_ring[txq->tx_next_dd].wb.status;
554 if (!(status & IXGBE_ADVTXD_STAT_DD))
557 n = txq->tx_rs_thresh;
560 * first buffer to free from S/W ring is at index
561 * tx_next_dd - (tx_rs_thresh-1)
563 txep = &txq->sw_ring_v[txq->tx_next_dd - (n - 1)];
564 m = __rte_pktmbuf_prefree_seg(txep[0].mbuf);
565 if (likely(m != NULL)) {
568 for (i = 1; i < n; i++) {
569 m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
570 if (likely(m != NULL)) {
571 if (likely(m->pool == free[0]->pool))
574 rte_mempool_put_bulk(free[0]->pool,
575 (void *)free, nb_free);
581 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
583 for (i = 1; i < n; i++) {
584 m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
586 rte_mempool_put(m->pool, m);
590 /* buffers were freed, update counters */
591 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
592 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
593 if (txq->tx_next_dd >= txq->nb_tx_desc)
594 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
596 return txq->tx_rs_thresh;
599 static inline void __attribute__((always_inline))
600 tx_backlog_entry(struct ixgbe_tx_entry_v *txep,
601 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
604 for (i = 0; i < (int)nb_pkts; ++i)
605 txep[i].mbuf = tx_pkts[i];
609 ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
612 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
613 volatile union ixgbe_adv_tx_desc *txdp;
614 struct ixgbe_tx_entry_v *txep;
615 uint16_t n, nb_commit, tx_id;
616 uint64_t flags = DCMD_DTYP_FLAGS;
617 uint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;
620 /* cross rx_thresh boundary is not allowed */
621 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
623 if (txq->nb_tx_free < txq->tx_free_thresh)
624 ixgbe_tx_free_bufs(txq);
626 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
627 if (unlikely(nb_pkts == 0))
630 tx_id = txq->tx_tail;
631 txdp = &txq->tx_ring[tx_id];
632 txep = &txq->sw_ring_v[tx_id];
634 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
636 n = (uint16_t)(txq->nb_tx_desc - tx_id);
637 if (nb_commit >= n) {
639 tx_backlog_entry(txep, tx_pkts, n);
641 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
642 vtx1(txdp, *tx_pkts, flags);
644 vtx1(txdp, *tx_pkts++, rs);
646 nb_commit = (uint16_t)(nb_commit - n);
649 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
651 /* avoid reach the end of ring */
652 txdp = &(txq->tx_ring[tx_id]);
653 txep = &txq->sw_ring_v[tx_id];
656 tx_backlog_entry(txep, tx_pkts, nb_commit);
658 vtx(txdp, tx_pkts, nb_commit, flags);
660 tx_id = (uint16_t)(tx_id + nb_commit);
661 if (tx_id > txq->tx_next_rs) {
662 txq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=
663 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
664 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
668 txq->tx_tail = tx_id;
670 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
675 static void __attribute__((cold))
676 ixgbe_tx_queue_release_mbufs_vec(struct ixgbe_tx_queue *txq)
679 struct ixgbe_tx_entry_v *txe;
680 const uint16_t max_desc = (uint16_t)(txq->nb_tx_desc - 1);
682 if (txq->sw_ring == NULL || txq->nb_tx_free == max_desc)
685 /* release the used mbufs in sw_ring */
686 for (i = txq->tx_next_dd - (txq->tx_rs_thresh - 1);
688 i = (i + 1) & max_desc) {
689 txe = &txq->sw_ring_v[i];
690 rte_pktmbuf_free_seg(txe->mbuf);
692 txq->nb_tx_free = max_desc;
695 for (i = 0; i < txq->nb_tx_desc; i++) {
696 txe = &txq->sw_ring_v[i];
701 void __attribute__((cold))
702 ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq)
704 const unsigned mask = rxq->nb_rx_desc - 1;
707 if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_rx_desc)
710 /* free all mbufs that are valid in the ring */
711 for (i = rxq->rx_tail; i != rxq->rxrearm_start; i = (i + 1) & mask)
712 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
713 rxq->rxrearm_nb = rxq->nb_rx_desc;
715 /* set all entries to NULL */
716 memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);
719 static void __attribute__((cold))
720 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
725 if (txq->sw_ring != NULL) {
726 rte_free(txq->sw_ring_v - 1);
727 txq->sw_ring_v = NULL;
731 static void __attribute__((cold))
732 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
734 static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
735 struct ixgbe_tx_entry_v *txe = txq->sw_ring_v;
738 /* Zero out HW ring memory */
739 for (i = 0; i < txq->nb_tx_desc; i++)
740 txq->tx_ring[i] = zeroed_desc;
742 /* Initialize SW ring entries */
743 for (i = 0; i < txq->nb_tx_desc; i++) {
744 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
745 txd->wb.status = IXGBE_TXD_STAT_DD;
749 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
750 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
755 * Always allow 1 descriptor to be un-allocated to avoid
756 * a H/W race condition
758 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
759 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
761 memset((void *)&txq->ctx_cache, 0,
762 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
765 static const struct ixgbe_txq_ops vec_txq_ops = {
766 .release_mbufs = ixgbe_tx_queue_release_mbufs_vec,
767 .free_swring = ixgbe_tx_free_swring,
768 .reset = ixgbe_reset_tx_queue,
771 int __attribute__((cold))
772 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq)
775 struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
778 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
779 mb_def.port = rxq->port_id;
780 rte_mbuf_refcnt_set(&mb_def, 1);
782 /* prevent compiler reordering: rearm_data covers previous fields */
783 rte_compiler_barrier();
784 p = (uintptr_t)&mb_def.rearm_data;
785 rxq->mbuf_initializer = *(uint64_t *)p;
789 int __attribute__((cold))
790 ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq)
792 if (txq->sw_ring_v == NULL)
795 /* leave the first one for overflow */
796 txq->sw_ring_v = txq->sw_ring_v + 1;
797 txq->ops = &vec_txq_ops;
802 int __attribute__((cold))
803 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
805 #ifndef RTE_LIBRTE_IEEE1588
806 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
807 struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
809 #ifndef RTE_IXGBE_RX_OLFLAGS_ENABLE
810 /* whithout rx ol_flags, no VP flag report */
811 if (rxmode->hw_vlan_strip != 0 ||
812 rxmode->hw_vlan_extend != 0)
816 /* no fdir support */
817 if (fconf->mode != RTE_FDIR_MODE_NONE)
821 * - no csum error report support
822 * - no header split support
824 if (rxmode->hw_ip_checksum == 1 ||
825 rxmode->header_split == 1)