4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <rte_ethdev.h>
36 #include <rte_malloc.h>
38 #include "ixgbe_ethdev.h"
39 #include "ixgbe_rxtx.h"
40 #include "ixgbe_rxtx_vec_common.h"
42 #include <tmmintrin.h>
44 #ifndef __INTEL_COMPILER
45 #pragma GCC diagnostic ignored "-Wcast-qual"
49 ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)
53 volatile union ixgbe_adv_rx_desc *rxdp;
54 struct ixgbe_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
55 struct rte_mbuf *mb0, *mb1;
56 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
57 RTE_PKTMBUF_HEADROOM);
58 __m128i dma_addr0, dma_addr1;
60 const __m128i hba_msk = _mm_set_epi64x(0, UINT64_MAX);
62 rxdp = rxq->rx_ring + rxq->rxrearm_start;
64 /* Pull 'n' more MBUFs into the software ring */
65 if (rte_mempool_get_bulk(rxq->mb_pool,
67 RTE_IXGBE_RXQ_REARM_THRESH) < 0) {
68 if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=
70 dma_addr0 = _mm_setzero_si128();
71 for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {
72 rxep[i].mbuf = &rxq->fake_mbuf;
73 _mm_store_si128((__m128i *)&rxdp[i].read,
77 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
78 RTE_IXGBE_RXQ_REARM_THRESH;
82 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
83 for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
84 __m128i vaddr0, vaddr1;
89 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
90 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
91 offsetof(struct rte_mbuf, buf_addr) + 8);
92 vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));
93 vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));
95 /* convert pa to dma_addr hdr/data */
96 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
97 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
99 /* add headroom to pa values */
100 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
101 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
103 /* set Header Buffer Address to zero */
104 dma_addr0 = _mm_and_si128(dma_addr0, hba_msk);
105 dma_addr1 = _mm_and_si128(dma_addr1, hba_msk);
107 /* flush desc with pa dma_addr */
108 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
109 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
112 rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;
113 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
114 rxq->rxrearm_start = 0;
116 rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;
118 rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?
119 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
121 /* Update the tail pointer on the NIC */
122 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
125 #ifdef RTE_LIBRTE_SECURITY
127 desc_to_olflags_v_ipsec(__m128i descs[4], struct rte_mbuf **rx_pkts)
129 __m128i sterr, rearm, tmp_e, tmp_p;
130 uint32_t *rearm0 = (uint32_t *)rx_pkts[0]->rearm_data + 2;
131 uint32_t *rearm1 = (uint32_t *)rx_pkts[1]->rearm_data + 2;
132 uint32_t *rearm2 = (uint32_t *)rx_pkts[2]->rearm_data + 2;
133 uint32_t *rearm3 = (uint32_t *)rx_pkts[3]->rearm_data + 2;
134 const __m128i ipsec_sterr_msk =
135 _mm_set1_epi32(IXGBE_RXDADV_IPSEC_STATUS_SECP |
136 IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED);
137 const __m128i ipsec_proc_msk =
138 _mm_set1_epi32(IXGBE_RXDADV_IPSEC_STATUS_SECP);
139 const __m128i ipsec_err_flag =
140 _mm_set1_epi32(PKT_RX_SEC_OFFLOAD_FAILED |
142 const __m128i ipsec_proc_flag = _mm_set1_epi32(PKT_RX_SEC_OFFLOAD);
144 rearm = _mm_set_epi32(*rearm3, *rearm2, *rearm1, *rearm0);
145 sterr = _mm_set_epi32(_mm_extract_epi32(descs[3], 2),
146 _mm_extract_epi32(descs[2], 2),
147 _mm_extract_epi32(descs[1], 2),
148 _mm_extract_epi32(descs[0], 2));
149 sterr = _mm_and_si128(sterr, ipsec_sterr_msk);
150 tmp_e = _mm_cmpeq_epi32(sterr, ipsec_sterr_msk);
151 tmp_p = _mm_cmpeq_epi32(sterr, ipsec_proc_msk);
152 sterr = _mm_or_si128(_mm_and_si128(tmp_e, ipsec_err_flag),
153 _mm_and_si128(tmp_p, ipsec_proc_flag));
154 rearm = _mm_or_si128(rearm, sterr);
155 *rearm0 = _mm_extract_epi32(rearm, 0);
156 *rearm1 = _mm_extract_epi32(rearm, 1);
157 *rearm2 = _mm_extract_epi32(rearm, 2);
158 *rearm3 = _mm_extract_epi32(rearm, 3);
163 desc_to_olflags_v(__m128i descs[4], __m128i mbuf_init, uint8_t vlan_flags,
164 struct rte_mbuf **rx_pkts)
166 __m128i ptype0, ptype1, vtag0, vtag1, csum;
167 __m128i rearm0, rearm1, rearm2, rearm3;
169 /* mask everything except rss type */
170 const __m128i rsstype_msk = _mm_set_epi16(
171 0x0000, 0x0000, 0x0000, 0x0000,
172 0x000F, 0x000F, 0x000F, 0x000F);
174 /* mask the lower byte of ol_flags */
175 const __m128i ol_flags_msk = _mm_set_epi16(
176 0x0000, 0x0000, 0x0000, 0x0000,
177 0x00FF, 0x00FF, 0x00FF, 0x00FF);
179 /* map rss type to rss hash flag */
180 const __m128i rss_flags = _mm_set_epi8(PKT_RX_FDIR, 0, 0, 0,
181 0, 0, 0, PKT_RX_RSS_HASH,
182 PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
183 PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
185 /* mask everything except vlan present and l4/ip csum error */
186 const __m128i vlan_csum_msk = _mm_set_epi16(
187 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
188 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
189 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
190 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
191 IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP,
192 IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP);
193 /* map vlan present (0x8), IPE (0x2), L4E (0x1) to ol_flags */
194 const __m128i vlan_csum_map_lo = _mm_set_epi8(
196 vlan_flags | PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
197 vlan_flags | PKT_RX_IP_CKSUM_BAD,
198 vlan_flags | PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
199 vlan_flags | PKT_RX_IP_CKSUM_GOOD,
201 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
203 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
204 PKT_RX_IP_CKSUM_GOOD);
206 const __m128i vlan_csum_map_hi = _mm_set_epi8(
208 0, PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t), 0,
209 PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t),
211 0, PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t), 0,
212 PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t));
214 ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
215 ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
216 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
217 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
219 ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
220 ptype0 = _mm_and_si128(ptype0, rsstype_msk);
221 ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
223 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
224 vtag1 = _mm_and_si128(vtag1, vlan_csum_msk);
226 /* csum bits are in the most significant, to use shuffle we need to
227 * shift them. Change mask to 0xc000 to 0x0003.
229 csum = _mm_srli_epi16(vtag1, 14);
231 /* now or the most significant 64 bits containing the checksum
232 * flags with the vlan present flags.
234 csum = _mm_srli_si128(csum, 8);
235 vtag1 = _mm_or_si128(csum, vtag1);
237 /* convert VP, IPE, L4E to ol_flags */
238 vtag0 = _mm_shuffle_epi8(vlan_csum_map_hi, vtag1);
239 vtag0 = _mm_slli_epi16(vtag0, sizeof(uint8_t));
241 vtag1 = _mm_shuffle_epi8(vlan_csum_map_lo, vtag1);
242 vtag1 = _mm_and_si128(vtag1, ol_flags_msk);
243 vtag1 = _mm_or_si128(vtag0, vtag1);
245 vtag1 = _mm_or_si128(ptype0, vtag1);
248 * At this point, we have the 4 sets of flags in the low 64-bits
250 * We want to extract these, and merge them with the mbuf init data
251 * so we can do a single 16-byte write to the mbuf to set the flags
252 * and all the other initialization fields. Extracting the
253 * appropriate flags means that we have to do a shift and blend for
254 * each mbuf before we do the write.
256 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 8), 0x10);
257 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 6), 0x10);
258 rearm2 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 4), 0x10);
259 rearm3 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 2), 0x10);
261 /* write the rearm data and the olflags in one write */
262 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
263 offsetof(struct rte_mbuf, rearm_data) + 8);
264 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
265 RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
266 _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
267 _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
268 _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
269 _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
272 static inline uint32_t get_packet_type(int index,
275 uint32_t tunnel_check)
277 if (etqf_check & (0x02 << (index * RTE_IXGBE_DESCS_PER_LOOP)))
278 return RTE_PTYPE_UNKNOWN;
280 if (tunnel_check & (0x02 << (index * RTE_IXGBE_DESCS_PER_LOOP))) {
281 pkt_info &= IXGBE_PACKET_TYPE_MASK_TUNNEL;
282 return ptype_table_tn[pkt_info];
285 pkt_info &= IXGBE_PACKET_TYPE_MASK_82599;
286 return ptype_table[pkt_info];
290 desc_to_ptype_v(__m128i descs[4], uint16_t pkt_type_mask,
291 struct rte_mbuf **rx_pkts)
293 __m128i etqf_mask = _mm_set_epi64x(0x800000008000LL, 0x800000008000LL);
294 __m128i ptype_mask = _mm_set_epi32(
295 pkt_type_mask, pkt_type_mask, pkt_type_mask, pkt_type_mask);
296 __m128i tunnel_mask =
297 _mm_set_epi64x(0x100000001000LL, 0x100000001000LL);
299 uint32_t etqf_check, tunnel_check, pkt_info;
301 __m128i ptype0 = _mm_unpacklo_epi32(descs[0], descs[2]);
302 __m128i ptype1 = _mm_unpacklo_epi32(descs[1], descs[3]);
304 /* interleave low 32 bits,
305 * now we have 4 ptypes in a XMM register
307 ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
309 /* create a etqf bitmask based on the etqf bit. */
310 etqf_check = _mm_movemask_epi8(_mm_and_si128(ptype0, etqf_mask));
312 /* shift left by IXGBE_PACKET_TYPE_SHIFT, and apply ptype mask */
313 ptype0 = _mm_and_si128(_mm_srli_epi32(ptype0, IXGBE_PACKET_TYPE_SHIFT),
316 /* create a tunnel bitmask based on the tunnel bit */
317 tunnel_check = _mm_movemask_epi8(
318 _mm_slli_epi32(_mm_and_si128(ptype0, tunnel_mask), 0x3));
320 pkt_info = _mm_extract_epi32(ptype0, 0);
321 rx_pkts[0]->packet_type =
322 get_packet_type(0, pkt_info, etqf_check, tunnel_check);
323 pkt_info = _mm_extract_epi32(ptype0, 1);
324 rx_pkts[1]->packet_type =
325 get_packet_type(1, pkt_info, etqf_check, tunnel_check);
326 pkt_info = _mm_extract_epi32(ptype0, 2);
327 rx_pkts[2]->packet_type =
328 get_packet_type(2, pkt_info, etqf_check, tunnel_check);
329 pkt_info = _mm_extract_epi32(ptype0, 3);
330 rx_pkts[3]->packet_type =
331 get_packet_type(3, pkt_info, etqf_check, tunnel_check);
335 * vPMD raw receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
338 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
339 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
341 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
343 static inline uint16_t
344 _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
345 uint16_t nb_pkts, uint8_t *split_packet)
347 volatile union ixgbe_adv_rx_desc *rxdp;
348 struct ixgbe_rx_entry *sw_ring;
349 uint16_t nb_pkts_recd;
350 #ifdef RTE_LIBRTE_SECURITY
351 uint8_t use_ipsec = rxq->using_ipsec;
356 __m128i crc_adjust = _mm_set_epi16(
357 0, 0, 0, /* ignore non-length fields */
358 -rxq->crc_len, /* sub crc on data_len */
359 0, /* ignore high-16bits of pkt_len */
360 -rxq->crc_len, /* sub crc on pkt_len */
361 0, 0 /* ignore pkt_type field */
364 * compile-time check the above crc_adjust layout is correct.
365 * NOTE: the first field (lowest address) is given last in set_epi16
368 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
369 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
370 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
371 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
372 __m128i dd_check, eop_check;
376 /* nb_pkts shall be less equal than RTE_IXGBE_MAX_RX_BURST */
377 nb_pkts = RTE_MIN(nb_pkts, RTE_IXGBE_MAX_RX_BURST);
379 /* nb_pkts has to be floor-aligned to RTE_IXGBE_DESCS_PER_LOOP */
380 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_IXGBE_DESCS_PER_LOOP);
382 /* Just the act of getting into the function from the application is
383 * going to cost about 7 cycles
385 rxdp = rxq->rx_ring + rxq->rx_tail;
389 /* See if we need to rearm the RX queue - gives the prefetch a bit
392 if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)
393 ixgbe_rxq_rearm(rxq);
395 /* Before we start moving massive data around, check to see if
396 * there is actually a packet available
398 if (!(rxdp->wb.upper.status_error &
399 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
402 /* 4 packets DD mask */
403 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
405 /* 4 packets EOP mask */
406 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
408 /* mask to shuffle from desc. to mbuf */
409 shuf_msk = _mm_set_epi8(
410 7, 6, 5, 4, /* octet 4~7, 32bits rss */
411 15, 14, /* octet 14~15, low 16 bits vlan_macip */
412 13, 12, /* octet 12~13, 16 bits data_len */
413 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
414 13, 12, /* octet 12~13, low 16 bits pkt_len */
415 0xFF, 0xFF, /* skip 32 bit pkt_type */
419 * Compile-time verify the shuffle mask
420 * NOTE: some field positions already verified above, but duplicated
421 * here for completeness in case of future modifications.
423 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
424 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
425 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
426 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
427 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
428 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
429 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
430 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
432 mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
434 /* Cache is empty -> need to scan the buffer rings, but first move
435 * the next 'n' mbufs into the cache
437 sw_ring = &rxq->sw_ring[rxq->rx_tail];
439 /* ensure these 2 flags are in the lower 8 bits */
440 RTE_BUILD_BUG_ON((PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED) > UINT8_MAX);
441 vlan_flags = rxq->vlan_flags & UINT8_MAX;
443 /* A. load 4 packet in one loop
444 * [A*. mask out 4 unused dirty field in desc]
445 * B. copy 4 mbuf point from swring to rx_pkts
446 * C. calc the number of DD bits among the 4 packets
447 * [C*. extract the end-of-packet bit, if requested]
448 * D. fill info. from desc to mbuf
450 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
451 pos += RTE_IXGBE_DESCS_PER_LOOP,
452 rxdp += RTE_IXGBE_DESCS_PER_LOOP) {
453 __m128i descs[RTE_IXGBE_DESCS_PER_LOOP];
454 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
455 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
456 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
458 #if defined(RTE_ARCH_X86_64)
462 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
463 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
465 /* Read desc statuses backwards to avoid race condition */
466 /* A.1 load 4 pkts desc */
467 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
468 rte_compiler_barrier();
470 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
471 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
473 #if defined(RTE_ARCH_X86_64)
474 /* B.1 load 2 64 bit mbuf points */
475 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
478 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
479 rte_compiler_barrier();
480 /* B.1 load 2 mbuf point */
481 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
482 rte_compiler_barrier();
483 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
485 #if defined(RTE_ARCH_X86_64)
486 /* B.2 copy 2 mbuf point into rx_pkts */
487 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
491 rte_mbuf_prefetch_part2(rx_pkts[pos]);
492 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
493 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
494 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
497 /* avoid compiler reorder optimization */
498 rte_compiler_barrier();
500 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
501 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
502 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
504 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
505 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
506 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
508 /* C.1 4=>2 filter staterr info only */
509 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
510 /* C.1 4=>2 filter staterr info only */
511 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
513 /* set ol_flags with vlan packet type */
514 desc_to_olflags_v(descs, mbuf_init, vlan_flags, &rx_pkts[pos]);
516 #ifdef RTE_LIBRTE_SECURITY
517 if (unlikely(use_ipsec))
518 desc_to_olflags_v_ipsec(descs, &rx_pkts[pos]);
521 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
522 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
523 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
525 /* C.2 get 4 pkts staterr value */
526 zero = _mm_xor_si128(dd_check, dd_check);
527 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
529 /* D.3 copy final 3,4 data to rx_pkts */
530 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
532 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
535 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
536 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
537 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
539 /* C* extract and record EOP bit */
541 __m128i eop_shuf_mask = _mm_set_epi8(
542 0xFF, 0xFF, 0xFF, 0xFF,
543 0xFF, 0xFF, 0xFF, 0xFF,
544 0xFF, 0xFF, 0xFF, 0xFF,
545 0x04, 0x0C, 0x00, 0x08
548 /* and with mask to extract bits, flipping 1-0 */
549 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
550 /* the staterr values are not in order, as the count
551 * count of dd bits doesn't care. However, for end of
552 * packet tracking, we do care, so shuffle. This also
553 * compresses the 32-bit values to 8-bit
555 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
556 /* store the resulting 32-bit value */
557 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
558 split_packet += RTE_IXGBE_DESCS_PER_LOOP;
561 /* C.3 calc available number of desc */
562 staterr = _mm_and_si128(staterr, dd_check);
563 staterr = _mm_packs_epi32(staterr, zero);
565 /* D.3 copy final 1,2 data to rx_pkts */
566 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
568 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
571 desc_to_ptype_v(descs, rxq->pkt_type_mask, &rx_pkts[pos]);
573 /* C.4 calc avaialbe number of desc */
574 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
576 if (likely(var != RTE_IXGBE_DESCS_PER_LOOP))
580 /* Update our internal tail pointer */
581 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
582 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
583 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
589 * vPMD receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
592 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
593 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
595 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
598 ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
601 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
605 * vPMD receive routine that reassembles scattered packets
608 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
609 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
611 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
614 ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
617 struct ixgbe_rx_queue *rxq = rx_queue;
618 uint8_t split_flags[RTE_IXGBE_MAX_RX_BURST] = {0};
620 /* get some new buffers */
621 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
626 /* happy day case, full burst + no packets to be joined */
627 const uint64_t *split_fl64 = (uint64_t *)split_flags;
628 if (rxq->pkt_first_seg == NULL &&
629 split_fl64[0] == 0 && split_fl64[1] == 0 &&
630 split_fl64[2] == 0 && split_fl64[3] == 0)
633 /* reassemble any packets that need reassembly*/
635 if (rxq->pkt_first_seg == NULL) {
636 /* find the first split flag, and only reassemble then*/
637 while (i < nb_bufs && !split_flags[i])
642 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
647 vtx1(volatile union ixgbe_adv_tx_desc *txdp,
648 struct rte_mbuf *pkt, uint64_t flags)
650 __m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |
651 flags | pkt->data_len,
652 pkt->buf_iova + pkt->data_off);
653 _mm_store_si128((__m128i *)&txdp->read, descriptor);
657 vtx(volatile union ixgbe_adv_tx_desc *txdp,
658 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
662 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
663 vtx1(txdp, *pkt, flags);
667 ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
670 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
671 volatile union ixgbe_adv_tx_desc *txdp;
672 struct ixgbe_tx_entry_v *txep;
673 uint16_t n, nb_commit, tx_id;
674 uint64_t flags = DCMD_DTYP_FLAGS;
675 uint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;
678 /* cross rx_thresh boundary is not allowed */
679 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
681 if (txq->nb_tx_free < txq->tx_free_thresh)
682 ixgbe_tx_free_bufs(txq);
684 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
685 if (unlikely(nb_pkts == 0))
688 tx_id = txq->tx_tail;
689 txdp = &txq->tx_ring[tx_id];
690 txep = &txq->sw_ring_v[tx_id];
692 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
694 n = (uint16_t)(txq->nb_tx_desc - tx_id);
695 if (nb_commit >= n) {
697 tx_backlog_entry(txep, tx_pkts, n);
699 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
700 vtx1(txdp, *tx_pkts, flags);
702 vtx1(txdp, *tx_pkts++, rs);
704 nb_commit = (uint16_t)(nb_commit - n);
707 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
709 /* avoid reach the end of ring */
710 txdp = &(txq->tx_ring[tx_id]);
711 txep = &txq->sw_ring_v[tx_id];
714 tx_backlog_entry(txep, tx_pkts, nb_commit);
716 vtx(txdp, tx_pkts, nb_commit, flags);
718 tx_id = (uint16_t)(tx_id + nb_commit);
719 if (tx_id > txq->tx_next_rs) {
720 txq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=
721 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
722 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
726 txq->tx_tail = tx_id;
728 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
733 static void __attribute__((cold))
734 ixgbe_tx_queue_release_mbufs_vec(struct ixgbe_tx_queue *txq)
736 _ixgbe_tx_queue_release_mbufs_vec(txq);
739 void __attribute__((cold))
740 ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq)
742 _ixgbe_rx_queue_release_mbufs_vec(rxq);
745 static void __attribute__((cold))
746 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
748 _ixgbe_tx_free_swring_vec(txq);
751 static void __attribute__((cold))
752 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
754 _ixgbe_reset_tx_queue_vec(txq);
757 static const struct ixgbe_txq_ops vec_txq_ops = {
758 .release_mbufs = ixgbe_tx_queue_release_mbufs_vec,
759 .free_swring = ixgbe_tx_free_swring,
760 .reset = ixgbe_reset_tx_queue,
763 int __attribute__((cold))
764 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq)
766 return ixgbe_rxq_vec_setup_default(rxq);
769 int __attribute__((cold))
770 ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq)
772 return ixgbe_txq_vec_setup_default(txq, &vec_txq_ops);
775 int __attribute__((cold))
776 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
778 return ixgbe_rx_vec_dev_conf_condition_check_default(dev);