4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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45 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
47 #pragma GCC diagnostic ignored "-Wpedantic"
49 #include <infiniband/verbs.h>
51 #pragma GCC diagnostic error "-Wpedantic"
54 #include <rte_malloc.h>
55 #include <rte_ethdev.h>
56 #include <rte_ethdev_pci.h>
58 #include <rte_bus_pci.h>
59 #include <rte_common.h>
60 #include <rte_eal_memconfig.h>
61 #include <rte_kvargs.h>
64 #include "mlx5_utils.h"
65 #include "mlx5_rxtx.h"
66 #include "mlx5_autoconf.h"
67 #include "mlx5_defs.h"
69 /* Device parameter to enable RX completion queue compression. */
70 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
72 /* Device parameter to configure inline send. */
73 #define MLX5_TXQ_INLINE "txq_inline"
76 * Device parameter to configure the number of TX queues threshold for
77 * enabling inline send.
79 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
81 /* Device parameter to enable multi-packet send WQEs. */
82 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
84 /* Device parameter to include 2 dsegs in the title WQEBB. */
85 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
87 /* Device parameter to limit the size of inlining packet. */
88 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
90 /* Device parameter to enable hardware TSO offload. */
91 #define MLX5_TSO "tso"
93 /* Device parameter to enable hardware Tx vector. */
94 #define MLX5_TX_VEC_EN "tx_vec_en"
96 /* Device parameter to enable hardware Rx vector. */
97 #define MLX5_RX_VEC_EN "rx_vec_en"
99 /* Default PMD specific parameter value. */
100 #define MLX5_ARG_UNSET (-1)
102 #ifndef HAVE_IBV_MLX5_MOD_MPW
103 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
104 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
107 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
108 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
117 int inline_max_packet_sz;
123 /** Driver-specific log messages type. */
127 * Retrieve integer value from environment variable.
130 * Environment variable name.
133 * Integer value, 0 if the variable is not set.
136 mlx5_getenv_int(const char *name)
138 const char *val = getenv(name);
146 * Verbs callback to allocate a memory. This function should allocate the space
147 * according to the size provided residing inside a huge page.
148 * Please note that all allocation must respect the alignment from libmlx5
149 * (i.e. currently sysconf(_SC_PAGESIZE)).
152 * The size in bytes of the memory to allocate.
154 * A pointer to the callback data.
157 * Allocated buffer, NULL otherwise and rte_errno is set.
160 mlx5_alloc_verbs_buf(size_t size, void *data)
162 struct priv *priv = data;
164 size_t alignment = sysconf(_SC_PAGESIZE);
165 unsigned int socket = SOCKET_ID_ANY;
167 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
168 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
170 socket = ctrl->socket;
171 } else if (priv->verbs_alloc_ctx.type ==
172 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
173 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
175 socket = ctrl->socket;
177 assert(data != NULL);
178 ret = rte_malloc_socket(__func__, size, alignment, socket);
185 * Verbs callback to free a memory.
188 * A pointer to the memory to free.
190 * A pointer to the callback data.
193 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
195 assert(data != NULL);
200 * DPDK callback to close the device.
202 * Destroy all queues and objects, free memory.
205 * Pointer to Ethernet device structure.
208 mlx5_dev_close(struct rte_eth_dev *dev)
210 struct priv *priv = dev->data->dev_private;
214 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
216 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
217 /* In case mlx5_dev_stop() has not been called. */
218 mlx5_dev_interrupt_handler_uninstall(dev);
219 mlx5_traffic_disable(dev);
220 /* Prevent crashes when queues are still in use. */
221 dev->rx_pkt_burst = removed_rx_burst;
222 dev->tx_pkt_burst = removed_tx_burst;
223 if (priv->rxqs != NULL) {
224 /* XXX race condition if mlx5_rx_burst() is still running. */
226 for (i = 0; (i != priv->rxqs_n); ++i)
227 mlx5_rxq_release(dev, i);
231 if (priv->txqs != NULL) {
232 /* XXX race condition if mlx5_tx_burst() is still running. */
234 for (i = 0; (i != priv->txqs_n); ++i)
235 mlx5_txq_release(dev, i);
239 if (priv->pd != NULL) {
240 assert(priv->ctx != NULL);
241 claim_zero(ibv_dealloc_pd(priv->pd));
242 claim_zero(ibv_close_device(priv->ctx));
244 assert(priv->ctx == NULL);
245 if (priv->rss_conf.rss_key != NULL)
246 rte_free(priv->rss_conf.rss_key);
247 if (priv->reta_idx != NULL)
248 rte_free(priv->reta_idx);
249 if (priv->primary_socket)
250 mlx5_socket_uninit(dev);
251 ret = mlx5_hrxq_ibv_verify(dev);
253 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
255 ret = mlx5_ind_table_ibv_verify(dev);
257 DRV_LOG(WARNING, "port %u some indirection table still remain",
259 ret = mlx5_rxq_ibv_verify(dev);
261 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
263 ret = mlx5_rxq_verify(dev);
265 DRV_LOG(WARNING, "port %u some Rx queues still remain",
267 ret = mlx5_txq_ibv_verify(dev);
269 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
271 ret = mlx5_txq_verify(dev);
273 DRV_LOG(WARNING, "port %u some Tx queues still remain",
275 ret = mlx5_flow_verify(dev);
277 DRV_LOG(WARNING, "port %u some flows still remain",
279 ret = mlx5_mr_verify(dev);
281 DRV_LOG(WARNING, "port %u some memory region still remain",
283 memset(priv, 0, sizeof(*priv));
286 const struct eth_dev_ops mlx5_dev_ops = {
287 .dev_configure = mlx5_dev_configure,
288 .dev_start = mlx5_dev_start,
289 .dev_stop = mlx5_dev_stop,
290 .dev_set_link_down = mlx5_set_link_down,
291 .dev_set_link_up = mlx5_set_link_up,
292 .dev_close = mlx5_dev_close,
293 .promiscuous_enable = mlx5_promiscuous_enable,
294 .promiscuous_disable = mlx5_promiscuous_disable,
295 .allmulticast_enable = mlx5_allmulticast_enable,
296 .allmulticast_disable = mlx5_allmulticast_disable,
297 .link_update = mlx5_link_update,
298 .stats_get = mlx5_stats_get,
299 .stats_reset = mlx5_stats_reset,
300 .xstats_get = mlx5_xstats_get,
301 .xstats_reset = mlx5_xstats_reset,
302 .xstats_get_names = mlx5_xstats_get_names,
303 .dev_infos_get = mlx5_dev_infos_get,
304 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
305 .vlan_filter_set = mlx5_vlan_filter_set,
306 .rx_queue_setup = mlx5_rx_queue_setup,
307 .tx_queue_setup = mlx5_tx_queue_setup,
308 .rx_queue_release = mlx5_rx_queue_release,
309 .tx_queue_release = mlx5_tx_queue_release,
310 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
311 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
312 .mac_addr_remove = mlx5_mac_addr_remove,
313 .mac_addr_add = mlx5_mac_addr_add,
314 .mac_addr_set = mlx5_mac_addr_set,
315 .mtu_set = mlx5_dev_set_mtu,
316 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
317 .vlan_offload_set = mlx5_vlan_offload_set,
318 .reta_update = mlx5_dev_rss_reta_update,
319 .reta_query = mlx5_dev_rss_reta_query,
320 .rss_hash_update = mlx5_rss_hash_update,
321 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
322 .filter_ctrl = mlx5_dev_filter_ctrl,
323 .rx_descriptor_status = mlx5_rx_descriptor_status,
324 .tx_descriptor_status = mlx5_tx_descriptor_status,
325 .rx_queue_intr_enable = mlx5_rx_intr_enable,
326 .rx_queue_intr_disable = mlx5_rx_intr_disable,
329 static const struct eth_dev_ops mlx5_dev_sec_ops = {
330 .stats_get = mlx5_stats_get,
331 .stats_reset = mlx5_stats_reset,
332 .xstats_get = mlx5_xstats_get,
333 .xstats_reset = mlx5_xstats_reset,
334 .xstats_get_names = mlx5_xstats_get_names,
335 .dev_infos_get = mlx5_dev_infos_get,
336 .rx_descriptor_status = mlx5_rx_descriptor_status,
337 .tx_descriptor_status = mlx5_tx_descriptor_status,
340 /* Available operators in flow isolated mode. */
341 const struct eth_dev_ops mlx5_dev_ops_isolate = {
342 .dev_configure = mlx5_dev_configure,
343 .dev_start = mlx5_dev_start,
344 .dev_stop = mlx5_dev_stop,
345 .dev_set_link_down = mlx5_set_link_down,
346 .dev_set_link_up = mlx5_set_link_up,
347 .dev_close = mlx5_dev_close,
348 .link_update = mlx5_link_update,
349 .stats_get = mlx5_stats_get,
350 .stats_reset = mlx5_stats_reset,
351 .xstats_get = mlx5_xstats_get,
352 .xstats_reset = mlx5_xstats_reset,
353 .xstats_get_names = mlx5_xstats_get_names,
354 .dev_infos_get = mlx5_dev_infos_get,
355 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
356 .vlan_filter_set = mlx5_vlan_filter_set,
357 .rx_queue_setup = mlx5_rx_queue_setup,
358 .tx_queue_setup = mlx5_tx_queue_setup,
359 .rx_queue_release = mlx5_rx_queue_release,
360 .tx_queue_release = mlx5_tx_queue_release,
361 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
362 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
363 .mac_addr_remove = mlx5_mac_addr_remove,
364 .mac_addr_add = mlx5_mac_addr_add,
365 .mac_addr_set = mlx5_mac_addr_set,
366 .mtu_set = mlx5_dev_set_mtu,
367 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
368 .vlan_offload_set = mlx5_vlan_offload_set,
369 .filter_ctrl = mlx5_dev_filter_ctrl,
370 .rx_descriptor_status = mlx5_rx_descriptor_status,
371 .tx_descriptor_status = mlx5_tx_descriptor_status,
372 .rx_queue_intr_enable = mlx5_rx_intr_enable,
373 .rx_queue_intr_disable = mlx5_rx_intr_disable,
377 struct rte_pci_addr pci_addr; /* associated PCI address */
378 uint32_t ports; /* physical ports bitfield. */
382 * Get device index in mlx5_dev[] from PCI bus address.
384 * @param[in] pci_addr
385 * PCI bus address to look for.
388 * mlx5_dev[] index on success, -1 on failure.
391 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
396 assert(pci_addr != NULL);
397 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
398 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
399 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
400 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
401 (mlx5_dev[i].pci_addr.function == pci_addr->function))
403 if ((mlx5_dev[i].ports == 0) && (ret == -1))
410 * Verify and store value for device argument.
413 * Key argument to verify.
415 * Value associated with key.
420 * 0 on success, a negative errno value otherwise and rte_errno is set.
423 mlx5_args_check(const char *key, const char *val, void *opaque)
425 struct mlx5_args *args = opaque;
429 tmp = strtoul(val, NULL, 0);
432 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
435 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
436 args->cqe_comp = !!tmp;
437 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
438 args->txq_inline = tmp;
439 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
440 args->txqs_inline = tmp;
441 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
443 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
444 args->mpw_hdr_dseg = !!tmp;
445 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
446 args->inline_max_packet_sz = tmp;
447 } else if (strcmp(MLX5_TSO, key) == 0) {
449 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
450 args->tx_vec_en = !!tmp;
451 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
452 args->rx_vec_en = !!tmp;
454 DRV_LOG(WARNING, "%s: unknown parameter", key);
462 * Parse device parameters.
465 * Pointer to private structure.
467 * Device arguments structure.
470 * 0 on success, a negative errno value otherwise and rte_errno is set.
473 mlx5_args(struct mlx5_args *args, struct rte_devargs *devargs)
475 const char **params = (const char *[]){
476 MLX5_RXQ_CQE_COMP_EN,
478 MLX5_TXQS_MIN_INLINE,
480 MLX5_TXQ_MPW_HDR_DSEG_EN,
481 MLX5_TXQ_MAX_INLINE_LEN,
487 struct rte_kvargs *kvlist;
493 /* Following UGLY cast is done to pass checkpatch. */
494 kvlist = rte_kvargs_parse(devargs->args, params);
497 /* Process parameters. */
498 for (i = 0; (params[i] != NULL); ++i) {
499 if (rte_kvargs_count(kvlist, params[i])) {
500 ret = rte_kvargs_process(kvlist, params[i],
501 mlx5_args_check, args);
504 rte_kvargs_free(kvlist);
509 rte_kvargs_free(kvlist);
513 static struct rte_pci_driver mlx5_driver;
516 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
517 * local resource used by both primary and secondary to avoid duplicate
519 * The space has to be available on both primary and secondary process,
520 * TXQ UAR maps to this area using fixed mmap w/o double check.
522 static void *uar_base;
525 * Reserve UAR address space for primary process.
528 * Pointer to Ethernet device.
531 * 0 on success, a negative errno value otherwise and rte_errno is set.
534 mlx5_uar_init_primary(struct rte_eth_dev *dev)
536 struct priv *priv = dev->data->dev_private;
537 void *addr = (void *)0;
539 const struct rte_mem_config *mcfg;
541 if (uar_base) { /* UAR address space mapped. */
542 priv->uar_base = uar_base;
545 /* find out lower bound of hugepage segments */
546 mcfg = rte_eal_get_configuration()->mem_config;
547 for (i = 0; i < RTE_MAX_MEMSEG && mcfg->memseg[i].addr; i++) {
549 addr = RTE_MIN(addr, mcfg->memseg[i].addr);
551 addr = mcfg->memseg[i].addr;
553 /* keep distance to hugepages to minimize potential conflicts. */
554 addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
555 /* anonymous mmap, no real memory consumption. */
556 addr = mmap(addr, MLX5_UAR_SIZE,
557 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
558 if (addr == MAP_FAILED) {
560 "port %u failed to reserve UAR address space, please"
561 " adjust MLX5_UAR_SIZE or try --base-virtaddr",
566 /* Accept either same addr or a new addr returned from mmap if target
569 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
570 dev->data->port_id, addr);
571 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
572 uar_base = addr; /* process local, don't reserve again. */
577 * Reserve UAR address space for secondary process, align with
581 * Pointer to Ethernet device.
584 * 0 on success, a negative errno value otherwise and rte_errno is set.
587 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
589 struct priv *priv = dev->data->dev_private;
592 assert(priv->uar_base);
593 if (uar_base) { /* already reserved. */
594 assert(uar_base == priv->uar_base);
597 /* anonymous mmap, no real memory consumption. */
598 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
599 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
600 if (addr == MAP_FAILED) {
601 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
602 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
606 if (priv->uar_base != addr) {
608 "port %u UAR address %p size %llu occupied, please"
609 " adjust MLX5_UAR_OFFSET or try EAL parameter"
611 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
615 uar_base = addr; /* process local, don't reserve again */
616 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
617 dev->data->port_id, addr);
622 * Assign parameters from args into priv, only non default
623 * values are considered.
626 * Pointer to private structure.
628 * Pointer to args values.
631 mlx5_args_assign(struct priv *priv, struct mlx5_args *args)
633 if (args->cqe_comp != MLX5_ARG_UNSET)
634 priv->cqe_comp = args->cqe_comp;
635 if (args->txq_inline != MLX5_ARG_UNSET)
636 priv->txq_inline = args->txq_inline;
637 if (args->txqs_inline != MLX5_ARG_UNSET)
638 priv->txqs_inline = args->txqs_inline;
639 if (args->mps != MLX5_ARG_UNSET)
640 priv->mps = args->mps ? priv->mps : 0;
641 if (args->mpw_hdr_dseg != MLX5_ARG_UNSET)
642 priv->mpw_hdr_dseg = args->mpw_hdr_dseg;
643 if (args->inline_max_packet_sz != MLX5_ARG_UNSET)
644 priv->inline_max_packet_sz = args->inline_max_packet_sz;
645 if (args->tso != MLX5_ARG_UNSET)
646 priv->tso = args->tso;
647 if (args->tx_vec_en != MLX5_ARG_UNSET)
648 priv->tx_vec_en = args->tx_vec_en;
649 if (args->rx_vec_en != MLX5_ARG_UNSET)
650 priv->rx_vec_en = args->rx_vec_en;
654 * DPDK callback to register a PCI device.
656 * This function creates an Ethernet device for each port of a given
660 * PCI driver structure (mlx5_driver).
662 * PCI device information.
665 * 0 on success, a negative errno value otherwise and rte_errno is set.
668 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
669 struct rte_pci_device *pci_dev)
671 struct ibv_device **list = NULL;
672 struct ibv_device *ibv_dev;
674 struct ibv_context *attr_ctx = NULL;
675 struct ibv_device_attr_ex device_attr;
677 unsigned int cqe_comp;
678 unsigned int tunnel_en = 0;
681 struct mlx5dv_context attrs_out;
682 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
683 struct ibv_counter_set_description cs_desc;
686 assert(pci_drv == &mlx5_driver);
687 /* Get mlx5_dev[] index. */
688 idx = mlx5_dev_idx(&pci_dev->addr);
690 DRV_LOG(ERR, "this driver cannot support any more adapters");
694 DRV_LOG(DEBUG, "using driver device index %d", idx);
695 /* Save PCI address. */
696 mlx5_dev[idx].pci_addr = pci_dev->addr;
697 list = ibv_get_device_list(&i);
703 "cannot list devices, is ib_uverbs loaded?");
708 * For each listed device, check related sysfs entry against
709 * the provided PCI ID.
712 struct rte_pci_addr pci_addr;
715 DRV_LOG(DEBUG, "checking device \"%s\"", list[i]->name);
716 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
718 if ((pci_dev->addr.domain != pci_addr.domain) ||
719 (pci_dev->addr.bus != pci_addr.bus) ||
720 (pci_dev->addr.devid != pci_addr.devid) ||
721 (pci_dev->addr.function != pci_addr.function))
723 switch (pci_dev->id.device_id) {
724 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
727 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
728 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
729 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
730 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
731 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
737 DRV_LOG(INFO, "PCI information matches, using device \"%s\"",
739 attr_ctx = ibv_open_device(list[i]);
744 if (attr_ctx == NULL) {
748 "cannot access device, is mlx5_ib loaded?");
753 "cannot use device, are drivers up to date?");
759 DRV_LOG(DEBUG, "device opened");
761 * Multi-packet send is supported by ConnectX-4 Lx PF as well
762 * as all ConnectX-5 devices.
764 mlx5dv_query_device(attr_ctx, &attrs_out);
765 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
766 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
767 DRV_LOG(DEBUG, "enhanced MPW is supported");
768 mps = MLX5_MPW_ENHANCED;
770 DRV_LOG(DEBUG, "MPW is supported");
774 DRV_LOG(DEBUG, "MPW isn't supported");
775 mps = MLX5_MPW_DISABLED;
777 if (RTE_CACHE_LINE_SIZE == 128 &&
778 !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
782 err = ibv_query_device_ex(attr_ctx, NULL, &device_attr);
784 DEBUG("ibv_query_device_ex() failed");
787 DRV_LOG(INFO, "%u port(s) detected",
788 device_attr.orig_attr.phys_port_cnt);
789 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
790 char name[RTE_ETH_NAME_MAX_LEN];
791 uint32_t port = i + 1; /* ports are indexed from one */
792 uint32_t test = (1 << i);
793 struct ibv_context *ctx = NULL;
794 struct ibv_port_attr port_attr;
795 struct ibv_pd *pd = NULL;
796 struct priv *priv = NULL;
797 struct rte_eth_dev *eth_dev = NULL;
798 struct ibv_device_attr_ex device_attr_ex;
799 struct ether_addr mac;
800 struct mlx5_args args = {
801 .cqe_comp = MLX5_ARG_UNSET,
802 .txq_inline = MLX5_ARG_UNSET,
803 .txqs_inline = MLX5_ARG_UNSET,
804 .mps = MLX5_ARG_UNSET,
805 .mpw_hdr_dseg = MLX5_ARG_UNSET,
806 .inline_max_packet_sz = MLX5_ARG_UNSET,
807 .tso = MLX5_ARG_UNSET,
808 .tx_vec_en = MLX5_ARG_UNSET,
809 .rx_vec_en = MLX5_ARG_UNSET,
812 snprintf(name, sizeof(name), PCI_PRI_FMT,
813 pci_dev->addr.domain, pci_dev->addr.bus,
814 pci_dev->addr.devid, pci_dev->addr.function);
815 mlx5_dev[idx].ports |= test;
816 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
817 eth_dev = rte_eth_dev_attach_secondary(name);
818 if (eth_dev == NULL) {
819 DRV_LOG(ERR, "can not attach rte ethdev");
824 eth_dev->device = &pci_dev->device;
825 eth_dev->dev_ops = &mlx5_dev_sec_ops;
826 err = mlx5_uar_init_secondary(eth_dev);
831 /* Receive command fd from primary process */
832 err = mlx5_socket_connect(eth_dev);
837 /* Remap UAR for Tx queues. */
838 err = mlx5_tx_uar_remap(eth_dev, err);
844 * Ethdev pointer is still required as input since
845 * the primary device is not accessible from the
848 eth_dev->rx_pkt_burst =
849 mlx5_select_rx_function(eth_dev);
850 eth_dev->tx_pkt_burst =
851 mlx5_select_tx_function(eth_dev);
854 DRV_LOG(DEBUG, "using port %u (%08" PRIx32 ")", port, test);
855 ctx = ibv_open_device(ibv_dev);
860 /* Check port status. */
861 err = ibv_query_port(ctx, port, &port_attr);
863 DRV_LOG(ERR, "port query failed: %s", strerror(err));
866 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
868 "port %d is not configured in Ethernet mode",
873 if (port_attr.state != IBV_PORT_ACTIVE)
874 DRV_LOG(DEBUG, "port %d is not active: \"%s\" (%d)",
875 port, ibv_port_state_str(port_attr.state),
877 /* Allocate protection domain. */
878 pd = ibv_alloc_pd(ctx);
880 DRV_LOG(ERR, "PD allocation failure");
884 mlx5_dev[idx].ports |= test;
885 /* from rte_ethdev.c */
886 priv = rte_zmalloc("ethdev private structure",
888 RTE_CACHE_LINE_SIZE);
890 DRV_LOG(ERR, "priv allocation failure");
895 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
896 sizeof(priv->ibdev_path));
897 priv->device_attr = device_attr;
900 priv->mtu = ETHER_MTU;
901 priv->mps = mps; /* Enable MPW by default if supported. */
902 priv->cqe_comp = cqe_comp;
903 priv->tunnel_en = tunnel_en;
904 /* Enable vector by default if supported. */
907 err = mlx5_args(&args, pci_dev->device.devargs);
909 DRV_LOG(ERR, "failed to process device arguments: %s",
914 mlx5_args_assign(priv, &args);
915 err = ibv_query_device_ex(ctx, NULL, &device_attr_ex);
917 DRV_LOG(ERR, "ibv_query_device_ex() failed");
921 !!(device_attr_ex.device_cap_flags_ex &
922 IBV_DEVICE_RAW_IP_CSUM);
923 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
924 (priv->hw_csum ? "" : "not "));
926 #ifdef HAVE_IBV_DEVICE_VXLAN_SUPPORT
927 priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags &
928 IBV_DEVICE_VXLAN_SUPPORT);
930 DRV_LOG(DEBUG, "Rx L2 tunnel checksum offloads are %ssupported",
931 (priv->hw_csum_l2tun ? "" : "not "));
933 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
934 priv->counter_set_supported = !!(device_attr.max_counter_sets);
935 ibv_describe_counter_set(ctx, 0, &cs_desc);
937 "counter type = %d, num of cs = %ld, attributes = %d",
938 cs_desc.counter_type, cs_desc.num_of_cs,
941 priv->ind_table_max_size =
942 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
943 /* Remove this check once DPDK supports larger/variable
944 * indirection tables. */
945 if (priv->ind_table_max_size >
946 (unsigned int)ETH_RSS_RETA_SIZE_512)
947 priv->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
948 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
949 priv->ind_table_max_size);
950 priv->hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
951 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
952 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
953 (priv->hw_vlan_strip ? "" : "not "));
955 priv->hw_fcs_strip = !!(device_attr_ex.raw_packet_caps &
956 IBV_RAW_PACKET_CAP_SCATTER_FCS);
957 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
958 (priv->hw_fcs_strip ? "" : "not "));
960 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
961 priv->hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
964 "hardware Rx end alignment padding is %ssupported",
965 (priv->hw_padding ? "" : "not "));
966 priv->tso = ((priv->tso) &&
967 (device_attr_ex.tso_caps.max_tso > 0) &&
968 (device_attr_ex.tso_caps.supported_qpts &
969 (1 << IBV_QPT_RAW_PACKET)));
971 priv->max_tso_payload_sz =
972 device_attr_ex.tso_caps.max_tso;
973 if (priv->mps && !mps) {
975 "multi-packet send not supported on this device"
976 " (" MLX5_TXQ_MPW_EN ")");
979 } else if (priv->mps && priv->tso) {
981 "multi-packet send not supported in conjunction"
982 " with TSO. MPS disabled");
985 DRV_LOG(INFO, "%s MPS is %s",
986 priv->mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
987 priv->mps != MLX5_MPW_DISABLED ? "enabled" :
989 /* Set default values for Enhanced MPW, a.k.a MPWv2. */
990 if (priv->mps == MLX5_MPW_ENHANCED) {
991 if (args.txqs_inline == MLX5_ARG_UNSET)
992 priv->txqs_inline = MLX5_EMPW_MIN_TXQS;
993 if (args.inline_max_packet_sz == MLX5_ARG_UNSET)
994 priv->inline_max_packet_sz =
995 MLX5_EMPW_MAX_INLINE_LEN;
996 if (args.txq_inline == MLX5_ARG_UNSET)
997 priv->txq_inline = MLX5_WQE_SIZE_MAX -
1000 if (priv->cqe_comp && !cqe_comp) {
1001 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1004 eth_dev = rte_eth_dev_allocate(name);
1005 if (eth_dev == NULL) {
1006 DRV_LOG(ERR, "can not allocate rte ethdev");
1010 eth_dev->data->dev_private = priv;
1011 priv->dev_data = eth_dev->data;
1012 eth_dev->data->mac_addrs = priv->mac;
1013 eth_dev->device = &pci_dev->device;
1014 rte_eth_copy_pci_info(eth_dev, pci_dev);
1015 eth_dev->device->driver = &mlx5_driver.driver;
1016 err = mlx5_uar_init_primary(eth_dev);
1021 /* Configure the first MAC address by default. */
1022 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1024 "port %u cannot get MAC address, is mlx5_en"
1025 " loaded? (errno: %s)",
1026 eth_dev->data->port_id, strerror(errno));
1031 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1032 eth_dev->data->port_id,
1033 mac.addr_bytes[0], mac.addr_bytes[1],
1034 mac.addr_bytes[2], mac.addr_bytes[3],
1035 mac.addr_bytes[4], mac.addr_bytes[5]);
1038 char ifname[IF_NAMESIZE];
1040 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1041 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1042 eth_dev->data->port_id, ifname);
1044 DRV_LOG(DEBUG, "port %u ifname is unknown",
1045 eth_dev->data->port_id);
1048 /* Get actual MTU if possible. */
1049 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1054 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1057 * Initialize burst functions to prevent crashes before link-up.
1059 eth_dev->rx_pkt_burst = removed_rx_burst;
1060 eth_dev->tx_pkt_burst = removed_tx_burst;
1061 eth_dev->dev_ops = &mlx5_dev_ops;
1062 /* Register MAC address. */
1063 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1064 TAILQ_INIT(&priv->flows);
1065 TAILQ_INIT(&priv->ctrl_flows);
1066 /* Hint libmlx5 to use PMD allocator for data plane resources */
1067 struct mlx5dv_ctx_allocators alctr = {
1068 .alloc = &mlx5_alloc_verbs_buf,
1069 .free = &mlx5_free_verbs_buf,
1072 mlx5dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1073 (void *)((uintptr_t)&alctr));
1074 /* Bring Ethernet device up. */
1075 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1076 eth_dev->data->port_id);
1077 mlx5_set_link_up(eth_dev);
1079 * Even though the interrupt handler is not installed yet,
1080 * interrupts will still trigger on the asyn_fd from
1081 * Verbs context returned by ibv_open_device().
1083 mlx5_link_update(eth_dev, 0);
1089 claim_zero(ibv_dealloc_pd(pd));
1091 claim_zero(ibv_close_device(ctx));
1092 if (eth_dev && rte_eal_process_type() == RTE_PROC_PRIMARY)
1093 rte_eth_dev_release_port(eth_dev);
1097 * XXX if something went wrong in the loop above, there is a resource
1098 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
1099 * long as the dpdk does not provide a way to deallocate a ethdev and a
1100 * way to enumerate the registered ethdevs to free the previous ones.
1102 /* no port found, complain */
1103 if (!mlx5_dev[idx].ports) {
1109 claim_zero(ibv_close_device(attr_ctx));
1111 ibv_free_device_list(list);
1119 static const struct rte_pci_id mlx5_pci_id_map[] = {
1121 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1122 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1125 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1126 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1129 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1130 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1133 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1134 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1137 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1138 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1141 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1142 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1145 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1146 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1149 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1150 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1157 static struct rte_pci_driver mlx5_driver = {
1159 .name = MLX5_DRIVER_NAME
1161 .id_table = mlx5_pci_id_map,
1162 .probe = mlx5_pci_probe,
1163 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1167 * Driver initialization routine.
1169 RTE_INIT(rte_mlx5_pmd_init);
1171 rte_mlx5_pmd_init(void)
1173 /* Build the static table for ptype conversion. */
1174 mlx5_set_ptype_table();
1176 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1177 * huge pages. Calling ibv_fork_init() during init allows
1178 * applications to use fork() safely for purposes other than
1179 * using this PMD, which is not supported in forked processes.
1181 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1182 /* Match the size of Rx completion entry to the size of a cacheline. */
1183 if (RTE_CACHE_LINE_SIZE == 128)
1184 setenv("MLX5_CQE_SIZE", "128", 0);
1186 rte_pci_register(&mlx5_driver);
1189 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1190 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1191 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
1193 /** Initialize driver log type. */
1194 RTE_INIT(vdev_netvsc_init_log)
1196 mlx5_logtype = rte_log_register("pmd.net.mlx5");
1197 if (mlx5_logtype >= 0)
1198 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);