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34 #ifndef RTE_PMD_MLX5_DEFS_H_
35 #define RTE_PMD_MLX5_DEFS_H_
37 #include <rte_ethdev.h>
39 #include "mlx5_autoconf.h"
41 /* Reported driver name. */
42 #define MLX5_DRIVER_NAME "net_mlx5"
44 /* Maximum number of simultaneous MAC addresses. */
45 #define MLX5_MAX_MAC_ADDRESSES 128
47 /* Maximum number of simultaneous VLAN filters. */
48 #define MLX5_MAX_VLAN_IDS 128
51 * Request TX completion every time descriptors reach this threshold since
52 * the previous request. Must be a power of two for performance reasons.
54 #define MLX5_TX_COMP_THRESH 32
57 * Request TX completion every time the total number of WQEBBs used for inlining
58 * packets exceeds the size of WQ divided by this divisor. Better to be power of
59 * two for performance.
61 #define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3)
64 * Maximum number of cached Memory Pools (MPs) per TX queue. Each RTE MP
65 * from which buffers are to be transmitted will have to be mapped by this
66 * driver to their own Memory Region (MR). This is a slow operation.
68 * This value is always 1 for RX queues.
70 #ifndef MLX5_PMD_TX_MP_CACHE
71 #define MLX5_PMD_TX_MP_CACHE 8
75 * If defined, only use software counters. The PMD will never ask the hardware
76 * for these, and many of them won't be available.
78 #ifndef MLX5_PMD_SOFT_COUNTERS
79 #define MLX5_PMD_SOFT_COUNTERS 1
83 #define MLX5_ALARM_TIMEOUT_US 100000
85 /* Maximum number of extended statistics counters. */
86 #define MLX5_MAX_XSTATS 32
88 /* Maximum Packet headers size (L2+L3+L4) for TSO. */
89 #define MLX5_MAX_TSO_HEADER 128
91 /* Default maximum number of Tx queues for vectorized Tx. */
92 #if defined(RTE_ARCH_ARM64)
93 #define MLX5_VPMD_MAX_TXQS 8
95 #define MLX5_VPMD_MAX_TXQS 4
97 #define MLX5_VPMD_MAX_TXQS_BLUEFIELD 16
99 /* Threshold of buffer replenishment for vectorized Rx. */
100 #define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \
101 (RTE_MIN(MLX5_VPMD_RX_MAX_BURST, (unsigned int)(n) >> 2))
103 /* Maximum size of burst for vectorized Rx. */
104 #define MLX5_VPMD_RX_MAX_BURST 64U
107 * Maximum size of burst for vectorized Tx. This is related to the maximum size
108 * of Enhanced MPW (eMPW) WQE as vectorized Tx is supported with eMPW.
109 * Careful when changing, large value can cause WQE DS to overlap.
111 #define MLX5_VPMD_TX_MAX_BURST 32U
113 /* Number of packets vectorized Rx can simultaneously process in a loop. */
114 #define MLX5_VPMD_DESCS_PER_LOOP 4
117 #define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP))
119 /* Timeout in seconds to get a valid link status. */
120 #define MLX5_LINK_STATUS_TIMEOUT 10
122 /* Reserved address space for UAR mapping. */
123 #define MLX5_UAR_SIZE (1ULL << 32)
125 /* Offset of reserved UAR address space to hugepage memory. Offset is used here
126 * to minimize possibility of address next to hugepage being used by other code
127 * in either primary or secondary process, failing to map TX UAR would make TX
128 * packets invisible to HW.
130 #define MLX5_UAR_OFFSET (1ULL << 32)
132 /* Size of per-queue MR cache table. */
133 #define MLX5_MR_CACHE_N 8
135 /* First entry must be NULL for comparison. */
136 #define MLX5_MR_LOOKUP_TABLE_PAD 1
138 /* Definition of static_assert found in /usr/include/assert.h */
139 #ifndef HAVE_STATIC_ASSERT
140 #define static_assert _Static_assert
143 #endif /* RTE_PMD_MLX5_DEFS_H_ */