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34 #ifndef RTE_PMD_MLX5_PRM_H_
35 #define RTE_PMD_MLX5_PRM_H_
38 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
40 #pragma GCC diagnostic ignored "-Wpedantic"
42 #include <infiniband/mlx5_hw.h>
44 #pragma GCC diagnostic error "-Wpedantic"
47 #include "mlx5_autoconf.h"
49 /* Get CQE owner bit. */
50 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
53 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
56 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
58 /* Get CQE solicited event. */
59 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
61 /* Invalidate a CQE. */
62 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
64 /* Maximum number of packets a multi-packet WQE can handle. */
65 #define MLX5_MPW_DSEG_MAX 5
68 #define MLX5_WQE_DWORD_SIZE 16
71 #define MLX5_WQE_SIZE (4 * MLX5_WQE_DWORD_SIZE)
73 /* Compute the number of DS. */
74 #define MLX5_WQE_DS(n) \
75 (((n) + MLX5_WQE_DWORD_SIZE - 1) / MLX5_WQE_DWORD_SIZE)
77 /* Room for inline data in multi-packet WQE. */
78 #define MLX5_MWQE64_INL_DATA 28
80 #ifndef HAVE_VERBS_MLX5_OPCODE_TSO
81 #define MLX5_OPCODE_TSO MLX5_OPCODE_LSO_MPW /* Compat with OFED 3.3. */
84 /* CQE value to inform that VLAN is stripped. */
85 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
88 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
91 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
94 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
97 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
100 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
102 /* IP is fragmented. */
103 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
105 /* L2 header is valid. */
106 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
108 /* L3 header is valid. */
109 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
111 /* L4 header is valid. */
112 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
114 /* Outer packet, 0 IPv4, 1 IPv6. */
115 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
117 /* Tunnel packet bit in the CQE. */
118 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
120 /* Subset of struct mlx5_wqe_eth_seg. */
121 struct mlx5_wqe_eth_seg_small {
127 uint16_t inline_hdr_sz;
128 uint8_t inline_hdr[2];
131 struct mlx5_wqe_inl_small {
136 /* Small common part of the WQE. */
139 struct mlx5_wqe_eth_seg_small eseg;
148 /* MPW session status. */
149 enum mlx5_mpw_state {
150 MLX5_MPW_STATE_OPENED,
151 MLX5_MPW_INL_STATE_OPENED,
152 MLX5_MPW_STATE_CLOSED,
155 /* MPW session descriptor. */
157 enum mlx5_mpw_state state;
160 unsigned int total_len;
161 volatile struct mlx5_wqe *wqe;
163 volatile struct mlx5_wqe_data_seg *dseg[MLX5_MPW_DSEG_MAX];
164 volatile uint8_t *raw;
168 /* CQ element structure - should be equal to the cache line size */
170 #if (RTE_CACHE_LINE_SIZE == 128)
175 uint32_t rx_hash_res;
176 uint8_t rx_hash_type;
178 uint16_t hdr_type_etc;
184 uint16_t wqe_counter;
189 #endif /* RTE_PMD_MLX5_PRM_H_ */