4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5dv.h>
47 #pragma GCC diagnostic error "-Wpedantic"
51 #include <rte_mempool.h>
52 #include <rte_prefetch.h>
53 #include <rte_common.h>
54 #include <rte_branch_prediction.h>
55 #include <rte_ether.h>
58 #include "mlx5_utils.h"
59 #include "mlx5_rxtx.h"
60 #include "mlx5_autoconf.h"
61 #include "mlx5_defs.h"
64 static __rte_always_inline uint32_t
65 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
67 static __rte_always_inline int
68 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
69 uint16_t cqe_cnt, uint32_t *rss_hash);
71 static __rte_always_inline uint32_t
72 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
74 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
75 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
79 * Build a table to translate Rx completion flags to packet type.
81 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
84 mlx5_set_ptype_table(void)
87 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
89 /* Last entry must not be overwritten, reserved for errored packet. */
90 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
91 (*p)[i] = RTE_PTYPE_UNKNOWN;
93 * The index to the array should have:
94 * bit[1:0] = l3_hdr_type
95 * bit[4:2] = l4_hdr_type
98 * bit[7] = outer_l3_type
101 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
103 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
104 RTE_PTYPE_L4_NONFRAG;
105 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
106 RTE_PTYPE_L4_NONFRAG;
108 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
110 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
113 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
115 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
118 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
120 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
122 /* Repeat with outer_l3_type being set. Just in case. */
123 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
124 RTE_PTYPE_L4_NONFRAG;
125 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
126 RTE_PTYPE_L4_NONFRAG;
127 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
129 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
131 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
133 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
135 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
137 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
140 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
141 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
142 RTE_PTYPE_INNER_L4_NONFRAG;
143 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
144 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
145 RTE_PTYPE_INNER_L4_NONFRAG;
146 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
147 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L4_NONFRAG;
149 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
150 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
151 RTE_PTYPE_INNER_L4_NONFRAG;
152 /* Tunneled - Fragmented */
153 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
154 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L4_FRAG;
156 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
157 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L4_FRAG;
159 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
160 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L4_FRAG;
162 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
163 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
164 RTE_PTYPE_INNER_L4_FRAG;
166 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L4_TCP;
169 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L4_TCP;
172 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L4_TCP;
175 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_TCP;
179 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
181 RTE_PTYPE_INNER_L4_UDP;
182 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
183 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
184 RTE_PTYPE_INNER_L4_UDP;
185 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
186 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
187 RTE_PTYPE_INNER_L4_UDP;
188 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
189 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
190 RTE_PTYPE_INNER_L4_UDP;
194 * Return the size of tailroom of WQ.
197 * Pointer to TX queue structure.
199 * Pointer to tail of WQ.
205 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
208 tailroom = (uintptr_t)(txq->wqes) +
209 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
215 * Copy data to tailroom of circular queue.
218 * Pointer to destination.
222 * Number of bytes to copy.
224 * Pointer to head of queue.
226 * Size of tailroom from dst.
229 * Pointer after copied data.
232 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
233 void *base, size_t tailroom)
238 rte_memcpy(dst, src, tailroom);
239 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
241 ret = (uint8_t *)base + n - tailroom;
243 rte_memcpy(dst, src, n);
244 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
250 * DPDK callback to check the status of a tx descriptor.
255 * The index of the descriptor in the ring.
258 * The status of the tx descriptor.
261 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
263 struct mlx5_txq_data *txq = tx_queue;
266 mlx5_tx_complete(txq);
267 used = txq->elts_head - txq->elts_tail;
269 return RTE_ETH_TX_DESC_FULL;
270 return RTE_ETH_TX_DESC_DONE;
274 * DPDK callback to check the status of a rx descriptor.
279 * The index of the descriptor in the ring.
282 * The status of the tx descriptor.
285 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
287 struct mlx5_rxq_data *rxq = rx_queue;
288 struct rxq_zip *zip = &rxq->zip;
289 volatile struct mlx5_cqe *cqe;
290 const unsigned int cqe_n = (1 << rxq->cqe_n);
291 const unsigned int cqe_cnt = cqe_n - 1;
295 /* if we are processing a compressed cqe */
297 used = zip->cqe_cnt - zip->ca;
303 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
304 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
308 op_own = cqe->op_own;
309 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
310 n = rte_be_to_cpu_32(cqe->byte_cnt);
315 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
317 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
319 return RTE_ETH_RX_DESC_DONE;
320 return RTE_ETH_RX_DESC_AVAIL;
324 * DPDK callback for TX.
327 * Generic pointer to TX queue structure.
329 * Packets to transmit.
331 * Number of packets in array.
334 * Number of packets successfully transmitted (<= pkts_n).
337 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
339 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
340 uint16_t elts_head = txq->elts_head;
341 const uint16_t elts_n = 1 << txq->elts_n;
342 const uint16_t elts_m = elts_n - 1;
347 unsigned int max_inline = txq->max_inline;
348 const unsigned int inline_en = !!max_inline && txq->inline_en;
351 volatile struct mlx5_wqe_v *wqe = NULL;
352 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
353 unsigned int segs_n = 0;
354 struct rte_mbuf *buf = NULL;
357 if (unlikely(!pkts_n))
359 /* Prefetch first packet cacheline. */
360 rte_prefetch0(*pkts);
361 /* Start processing. */
362 mlx5_tx_complete(txq);
363 max_elts = (elts_n - (elts_head - txq->elts_tail));
364 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
365 if (unlikely(!max_wqe))
368 volatile rte_v128u32_t *dseg = NULL;
371 unsigned int sg = 0; /* counter of additional segs attached. */
374 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
375 uint16_t tso_header_sz = 0;
379 uint16_t tso_segsz = 0;
380 #ifdef MLX5_PMD_SOFT_COUNTERS
381 uint32_t total_length = 0;
386 segs_n = buf->nb_segs;
388 * Make sure there is enough room to store this packet and
389 * that one ring entry remains unused.
392 if (max_elts < segs_n)
396 if (unlikely(--max_wqe == 0))
398 wqe = (volatile struct mlx5_wqe_v *)
399 tx_mlx5_wqe(txq, txq->wqe_ci);
400 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
402 rte_prefetch0(*(pkts + 1));
403 addr = rte_pktmbuf_mtod(buf, uintptr_t);
404 length = DATA_LEN(buf);
405 ehdr = (((uint8_t *)addr)[1] << 8) |
406 ((uint8_t *)addr)[0];
407 #ifdef MLX5_PMD_SOFT_COUNTERS
408 total_length = length;
410 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
411 txq->stats.oerrors++;
414 /* Update element. */
415 (*txq->elts)[elts_head & elts_m] = buf;
416 /* Prefetch next buffer data. */
419 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
420 cs_flags = txq_ol_cksum_to_cs(txq, buf);
421 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
422 /* Replace the Ethernet type by the VLAN if necessary. */
423 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
424 uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
426 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
430 /* Copy Destination and source mac address. */
431 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
433 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
434 /* Copy missing two bytes to end the DSeg. */
435 memcpy((uint8_t *)raw + len + sizeof(vlan),
436 ((uint8_t *)addr) + len, 2);
440 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
441 MLX5_WQE_DWORD_SIZE);
442 length -= pkt_inline_sz;
443 addr += pkt_inline_sz;
445 raw += MLX5_WQE_DWORD_SIZE;
447 tso = buf->ol_flags & PKT_TX_TCP_SEG;
449 uintptr_t end = (uintptr_t)
450 (((uintptr_t)txq->wqes) +
454 uint8_t vlan_sz = (buf->ol_flags &
455 PKT_TX_VLAN_PKT) ? 4 : 0;
456 const uint64_t is_tunneled =
459 PKT_TX_TUNNEL_VXLAN);
461 tso_header_sz = buf->l2_len + vlan_sz +
462 buf->l3_len + buf->l4_len;
463 tso_segsz = buf->tso_segsz;
464 if (unlikely(tso_segsz == 0)) {
465 txq->stats.oerrors++;
468 if (is_tunneled && txq->tunnel_en) {
469 tso_header_sz += buf->outer_l2_len +
471 cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
473 cs_flags |= MLX5_ETH_WQE_L4_CSUM;
475 if (unlikely(tso_header_sz >
476 MLX5_MAX_TSO_HEADER)) {
477 txq->stats.oerrors++;
480 copy_b = tso_header_sz - pkt_inline_sz;
481 /* First seg must contain all headers. */
482 assert(copy_b <= length);
484 ((end - (uintptr_t)raw) > copy_b)) {
485 uint16_t n = (MLX5_WQE_DS(copy_b) -
488 if (unlikely(max_wqe < n))
491 rte_memcpy((void *)raw,
492 (void *)addr, copy_b);
495 /* Include padding for TSO header. */
496 copy_b = MLX5_WQE_DS(copy_b) *
498 pkt_inline_sz += copy_b;
502 wqe->ctrl = (rte_v128u32_t){
511 #ifdef MLX5_PMD_SOFT_COUNTERS
519 /* Inline if enough room. */
520 if (inline_en || tso) {
522 uintptr_t end = (uintptr_t)
523 (((uintptr_t)txq->wqes) +
524 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
525 unsigned int inline_room = max_inline *
526 RTE_CACHE_LINE_SIZE -
527 (pkt_inline_sz - 2) -
529 uintptr_t addr_end = (addr + inline_room) &
530 ~(RTE_CACHE_LINE_SIZE - 1);
531 unsigned int copy_b = (addr_end > addr) ?
532 RTE_MIN((addr_end - addr), length) :
535 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
537 * One Dseg remains in the current WQE. To
538 * keep the computation positive, it is
539 * removed after the bytes to Dseg conversion.
541 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
543 if (unlikely(max_wqe < n))
547 inl = rte_cpu_to_be_32(copy_b |
549 rte_memcpy((void *)raw,
550 (void *)&inl, sizeof(inl));
552 pkt_inline_sz += sizeof(inl);
554 rte_memcpy((void *)raw, (void *)addr, copy_b);
557 pkt_inline_sz += copy_b;
560 * 2 DWORDs consumed by the WQE header + ETH segment +
561 * the size of the inline part of the packet.
563 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
565 if (ds % (MLX5_WQE_SIZE /
566 MLX5_WQE_DWORD_SIZE) == 0) {
567 if (unlikely(--max_wqe == 0))
569 dseg = (volatile rte_v128u32_t *)
570 tx_mlx5_wqe(txq, txq->wqe_ci +
573 dseg = (volatile rte_v128u32_t *)
575 (ds * MLX5_WQE_DWORD_SIZE));
578 } else if (!segs_n) {
581 /* dseg will be advance as part of next_seg */
582 dseg = (volatile rte_v128u32_t *)
584 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
589 * No inline has been done in the packet, only the
590 * Ethernet Header as been stored.
592 dseg = (volatile rte_v128u32_t *)
593 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
596 /* Add the remaining packet as a simple ds. */
597 naddr = rte_cpu_to_be_64(addr);
598 *dseg = (rte_v128u32_t){
599 rte_cpu_to_be_32(length),
600 mlx5_tx_mb2mr(txq, buf),
613 * Spill on next WQE when the current one does not have
614 * enough room left. Size of WQE must a be a multiple
615 * of data segment size.
617 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
618 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
619 if (unlikely(--max_wqe == 0))
621 dseg = (volatile rte_v128u32_t *)
622 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
623 rte_prefetch0(tx_mlx5_wqe(txq,
624 txq->wqe_ci + ds / 4 + 1));
631 length = DATA_LEN(buf);
632 #ifdef MLX5_PMD_SOFT_COUNTERS
633 total_length += length;
635 /* Store segment information. */
636 naddr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
637 *dseg = (rte_v128u32_t){
638 rte_cpu_to_be_32(length),
639 mlx5_tx_mb2mr(txq, buf),
643 (*txq->elts)[++elts_head & elts_m] = buf;
645 /* Advance counter only if all segs are successfully posted. */
651 if (ds > MLX5_DSEG_MAX) {
652 txq->stats.oerrors++;
658 /* Initialize known and common part of the WQE structure. */
660 wqe->ctrl = (rte_v128u32_t){
661 rte_cpu_to_be_32((txq->wqe_ci << 8) |
663 rte_cpu_to_be_32(txq->qp_num_8s | ds),
667 wqe->eseg = (rte_v128u32_t){
669 cs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),
671 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
674 wqe->ctrl = (rte_v128u32_t){
675 rte_cpu_to_be_32((txq->wqe_ci << 8) |
677 rte_cpu_to_be_32(txq->qp_num_8s | ds),
681 wqe->eseg = (rte_v128u32_t){
685 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
689 txq->wqe_ci += (ds + 3) / 4;
690 /* Save the last successful WQE for completion request */
691 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
692 #ifdef MLX5_PMD_SOFT_COUNTERS
693 /* Increment sent bytes counter. */
694 txq->stats.obytes += total_length;
696 } while (i < pkts_n);
697 /* Take a shortcut if nothing must be sent. */
698 if (unlikely((i + k) == 0))
700 txq->elts_head += (i + j);
701 /* Check whether completion threshold has been reached. */
702 comp = txq->elts_comp + i + j + k;
703 if (comp >= MLX5_TX_COMP_THRESH) {
704 /* Request completion on last WQE. */
705 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
706 /* Save elts_head in unused "immediate" field of WQE. */
707 last_wqe->ctrl3 = txq->elts_head;
710 txq->elts_comp = comp;
712 #ifdef MLX5_PMD_SOFT_COUNTERS
713 /* Increment sent packets counter. */
714 txq->stats.opackets += i;
716 /* Ring QP doorbell. */
717 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
722 * Open a MPW session.
725 * Pointer to TX queue structure.
727 * Pointer to MPW session structure.
732 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
734 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
735 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
736 (volatile struct mlx5_wqe_data_seg (*)[])
737 tx_mlx5_wqe(txq, idx + 1);
739 mpw->state = MLX5_MPW_STATE_OPENED;
743 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
744 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
745 mpw->wqe->eseg.inline_hdr_sz = 0;
746 mpw->wqe->eseg.rsvd0 = 0;
747 mpw->wqe->eseg.rsvd1 = 0;
748 mpw->wqe->eseg.rsvd2 = 0;
749 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
752 mpw->wqe->ctrl[2] = 0;
753 mpw->wqe->ctrl[3] = 0;
754 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
755 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
756 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
757 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
758 mpw->data.dseg[2] = &(*dseg)[0];
759 mpw->data.dseg[3] = &(*dseg)[1];
760 mpw->data.dseg[4] = &(*dseg)[2];
764 * Close a MPW session.
767 * Pointer to TX queue structure.
769 * Pointer to MPW session structure.
772 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
774 unsigned int num = mpw->pkts_n;
777 * Store size in multiple of 16 bytes. Control and Ethernet segments
780 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
781 mpw->state = MLX5_MPW_STATE_CLOSED;
786 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
787 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
791 * DPDK callback for TX with MPW support.
794 * Generic pointer to TX queue structure.
796 * Packets to transmit.
798 * Number of packets in array.
801 * Number of packets successfully transmitted (<= pkts_n).
804 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
806 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
807 uint16_t elts_head = txq->elts_head;
808 const uint16_t elts_n = 1 << txq->elts_n;
809 const uint16_t elts_m = elts_n - 1;
815 struct mlx5_mpw mpw = {
816 .state = MLX5_MPW_STATE_CLOSED,
819 if (unlikely(!pkts_n))
821 /* Prefetch first packet cacheline. */
822 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
823 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
824 /* Start processing. */
825 mlx5_tx_complete(txq);
826 max_elts = (elts_n - (elts_head - txq->elts_tail));
827 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
828 if (unlikely(!max_wqe))
831 struct rte_mbuf *buf = *(pkts++);
833 unsigned int segs_n = buf->nb_segs;
837 * Make sure there is enough room to store this packet and
838 * that one ring entry remains unused.
841 if (max_elts < segs_n)
843 /* Do not bother with large packets MPW cannot handle. */
844 if (segs_n > MLX5_MPW_DSEG_MAX) {
845 txq->stats.oerrors++;
850 cs_flags = txq_ol_cksum_to_cs(txq, buf);
851 /* Retrieve packet information. */
852 length = PKT_LEN(buf);
854 /* Start new session if packet differs. */
855 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
856 ((mpw.len != length) ||
858 (mpw.wqe->eseg.cs_flags != cs_flags)))
859 mlx5_mpw_close(txq, &mpw);
860 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
862 * Multi-Packet WQE consumes at most two WQE.
863 * mlx5_mpw_new() expects to be able to use such
866 if (unlikely(max_wqe < 2))
869 mlx5_mpw_new(txq, &mpw, length);
870 mpw.wqe->eseg.cs_flags = cs_flags;
872 /* Multi-segment packets must be alone in their MPW. */
873 assert((segs_n == 1) || (mpw.pkts_n == 0));
874 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
878 volatile struct mlx5_wqe_data_seg *dseg;
882 (*txq->elts)[elts_head++ & elts_m] = buf;
883 dseg = mpw.data.dseg[mpw.pkts_n];
884 addr = rte_pktmbuf_mtod(buf, uintptr_t);
885 *dseg = (struct mlx5_wqe_data_seg){
886 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
887 .lkey = mlx5_tx_mb2mr(txq, buf),
888 .addr = rte_cpu_to_be_64(addr),
890 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
891 length += DATA_LEN(buf);
897 assert(length == mpw.len);
898 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
899 mlx5_mpw_close(txq, &mpw);
900 #ifdef MLX5_PMD_SOFT_COUNTERS
901 /* Increment sent bytes counter. */
902 txq->stats.obytes += length;
906 /* Take a shortcut if nothing must be sent. */
907 if (unlikely(i == 0))
909 /* Check whether completion threshold has been reached. */
910 /* "j" includes both packets and segments. */
911 comp = txq->elts_comp + j;
912 if (comp >= MLX5_TX_COMP_THRESH) {
913 volatile struct mlx5_wqe *wqe = mpw.wqe;
915 /* Request completion on last WQE. */
916 wqe->ctrl[2] = rte_cpu_to_be_32(8);
917 /* Save elts_head in unused "immediate" field of WQE. */
918 wqe->ctrl[3] = elts_head;
921 txq->elts_comp = comp;
923 #ifdef MLX5_PMD_SOFT_COUNTERS
924 /* Increment sent packets counter. */
925 txq->stats.opackets += i;
927 /* Ring QP doorbell. */
928 if (mpw.state == MLX5_MPW_STATE_OPENED)
929 mlx5_mpw_close(txq, &mpw);
930 mlx5_tx_dbrec(txq, mpw.wqe);
931 txq->elts_head = elts_head;
936 * Open a MPW inline session.
939 * Pointer to TX queue structure.
941 * Pointer to MPW session structure.
946 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
949 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
950 struct mlx5_wqe_inl_small *inl;
952 mpw->state = MLX5_MPW_INL_STATE_OPENED;
956 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
957 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
960 mpw->wqe->ctrl[2] = 0;
961 mpw->wqe->ctrl[3] = 0;
962 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
963 mpw->wqe->eseg.inline_hdr_sz = 0;
964 mpw->wqe->eseg.cs_flags = 0;
965 mpw->wqe->eseg.rsvd0 = 0;
966 mpw->wqe->eseg.rsvd1 = 0;
967 mpw->wqe->eseg.rsvd2 = 0;
968 inl = (struct mlx5_wqe_inl_small *)
969 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
970 mpw->data.raw = (uint8_t *)&inl->raw;
974 * Close a MPW inline session.
977 * Pointer to TX queue structure.
979 * Pointer to MPW session structure.
982 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
985 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
986 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
988 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
990 * Store size in multiple of 16 bytes. Control and Ethernet segments
993 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
995 mpw->state = MLX5_MPW_STATE_CLOSED;
996 inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
997 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1001 * DPDK callback for TX with MPW inline support.
1004 * Generic pointer to TX queue structure.
1006 * Packets to transmit.
1008 * Number of packets in array.
1011 * Number of packets successfully transmitted (<= pkts_n).
1014 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1017 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1018 uint16_t elts_head = txq->elts_head;
1019 const uint16_t elts_n = 1 << txq->elts_n;
1020 const uint16_t elts_m = elts_n - 1;
1026 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1027 struct mlx5_mpw mpw = {
1028 .state = MLX5_MPW_STATE_CLOSED,
1031 * Compute the maximum number of WQE which can be consumed by inline
1034 * - 1 control segment,
1035 * - 1 Ethernet segment,
1036 * - N Dseg from the inline request.
1038 const unsigned int wqe_inl_n =
1039 ((2 * MLX5_WQE_DWORD_SIZE +
1040 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1041 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1043 if (unlikely(!pkts_n))
1045 /* Prefetch first packet cacheline. */
1046 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1047 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1048 /* Start processing. */
1049 mlx5_tx_complete(txq);
1050 max_elts = (elts_n - (elts_head - txq->elts_tail));
1052 struct rte_mbuf *buf = *(pkts++);
1055 unsigned int segs_n = buf->nb_segs;
1059 * Make sure there is enough room to store this packet and
1060 * that one ring entry remains unused.
1063 if (max_elts < segs_n)
1065 /* Do not bother with large packets MPW cannot handle. */
1066 if (segs_n > MLX5_MPW_DSEG_MAX) {
1067 txq->stats.oerrors++;
1073 * Compute max_wqe in case less WQE were consumed in previous
1076 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1077 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1078 /* Retrieve packet information. */
1079 length = PKT_LEN(buf);
1080 /* Start new session if packet differs. */
1081 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1082 if ((mpw.len != length) ||
1084 (mpw.wqe->eseg.cs_flags != cs_flags))
1085 mlx5_mpw_close(txq, &mpw);
1086 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1087 if ((mpw.len != length) ||
1089 (length > inline_room) ||
1090 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1091 mlx5_mpw_inline_close(txq, &mpw);
1093 txq->max_inline * RTE_CACHE_LINE_SIZE;
1096 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1097 if ((segs_n != 1) ||
1098 (length > inline_room)) {
1100 * Multi-Packet WQE consumes at most two WQE.
1101 * mlx5_mpw_new() expects to be able to use
1104 if (unlikely(max_wqe < 2))
1107 mlx5_mpw_new(txq, &mpw, length);
1108 mpw.wqe->eseg.cs_flags = cs_flags;
1110 if (unlikely(max_wqe < wqe_inl_n))
1112 max_wqe -= wqe_inl_n;
1113 mlx5_mpw_inline_new(txq, &mpw, length);
1114 mpw.wqe->eseg.cs_flags = cs_flags;
1117 /* Multi-segment packets must be alone in their MPW. */
1118 assert((segs_n == 1) || (mpw.pkts_n == 0));
1119 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1120 assert(inline_room ==
1121 txq->max_inline * RTE_CACHE_LINE_SIZE);
1122 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1126 volatile struct mlx5_wqe_data_seg *dseg;
1129 (*txq->elts)[elts_head++ & elts_m] = buf;
1130 dseg = mpw.data.dseg[mpw.pkts_n];
1131 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1132 *dseg = (struct mlx5_wqe_data_seg){
1134 rte_cpu_to_be_32(DATA_LEN(buf)),
1135 .lkey = mlx5_tx_mb2mr(txq, buf),
1136 .addr = rte_cpu_to_be_64(addr),
1138 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1139 length += DATA_LEN(buf);
1145 assert(length == mpw.len);
1146 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1147 mlx5_mpw_close(txq, &mpw);
1151 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1152 assert(length <= inline_room);
1153 assert(length == DATA_LEN(buf));
1154 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1155 (*txq->elts)[elts_head++ & elts_m] = buf;
1156 /* Maximum number of bytes before wrapping. */
1157 max = ((((uintptr_t)(txq->wqes)) +
1160 (uintptr_t)mpw.data.raw);
1162 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1165 mpw.data.raw = (volatile void *)txq->wqes;
1166 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1167 (void *)(addr + max),
1169 mpw.data.raw += length - max;
1171 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1177 (volatile void *)txq->wqes;
1179 mpw.data.raw += length;
1182 mpw.total_len += length;
1184 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1185 mlx5_mpw_inline_close(txq, &mpw);
1187 txq->max_inline * RTE_CACHE_LINE_SIZE;
1189 inline_room -= length;
1192 #ifdef MLX5_PMD_SOFT_COUNTERS
1193 /* Increment sent bytes counter. */
1194 txq->stats.obytes += length;
1198 /* Take a shortcut if nothing must be sent. */
1199 if (unlikely(i == 0))
1201 /* Check whether completion threshold has been reached. */
1202 /* "j" includes both packets and segments. */
1203 comp = txq->elts_comp + j;
1204 if (comp >= MLX5_TX_COMP_THRESH) {
1205 volatile struct mlx5_wqe *wqe = mpw.wqe;
1207 /* Request completion on last WQE. */
1208 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1209 /* Save elts_head in unused "immediate" field of WQE. */
1210 wqe->ctrl[3] = elts_head;
1213 txq->elts_comp = comp;
1215 #ifdef MLX5_PMD_SOFT_COUNTERS
1216 /* Increment sent packets counter. */
1217 txq->stats.opackets += i;
1219 /* Ring QP doorbell. */
1220 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1221 mlx5_mpw_inline_close(txq, &mpw);
1222 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1223 mlx5_mpw_close(txq, &mpw);
1224 mlx5_tx_dbrec(txq, mpw.wqe);
1225 txq->elts_head = elts_head;
1230 * Open an Enhanced MPW session.
1233 * Pointer to TX queue structure.
1235 * Pointer to MPW session structure.
1240 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1242 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1244 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1246 mpw->total_len = sizeof(struct mlx5_wqe);
1247 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1249 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1250 (txq->wqe_ci << 8) |
1251 MLX5_OPCODE_ENHANCED_MPSW);
1252 mpw->wqe->ctrl[2] = 0;
1253 mpw->wqe->ctrl[3] = 0;
1254 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1255 if (unlikely(padding)) {
1256 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1258 /* Pad the first 2 DWORDs with zero-length inline header. */
1259 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1260 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1261 rte_cpu_to_be_32(MLX5_INLINE_SEG);
1262 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1263 /* Start from the next WQEBB. */
1264 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1266 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1271 * Close an Enhanced MPW session.
1274 * Pointer to TX queue structure.
1276 * Pointer to MPW session structure.
1279 * Number of consumed WQEs.
1281 static inline uint16_t
1282 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1286 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1289 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1290 MLX5_WQE_DS(mpw->total_len));
1291 mpw->state = MLX5_MPW_STATE_CLOSED;
1292 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1298 * DPDK callback for TX with Enhanced MPW support.
1301 * Generic pointer to TX queue structure.
1303 * Packets to transmit.
1305 * Number of packets in array.
1308 * Number of packets successfully transmitted (<= pkts_n).
1311 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1313 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1314 uint16_t elts_head = txq->elts_head;
1315 const uint16_t elts_n = 1 << txq->elts_n;
1316 const uint16_t elts_m = elts_n - 1;
1321 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1322 unsigned int mpw_room = 0;
1323 unsigned int inl_pad = 0;
1325 struct mlx5_mpw mpw = {
1326 .state = MLX5_MPW_STATE_CLOSED,
1329 if (unlikely(!pkts_n))
1331 /* Start processing. */
1332 mlx5_tx_complete(txq);
1333 max_elts = (elts_n - (elts_head - txq->elts_tail));
1334 /* A CQE slot must always be available. */
1335 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1336 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1337 if (unlikely(!max_wqe))
1340 struct rte_mbuf *buf = *(pkts++);
1344 unsigned int do_inline = 0; /* Whether inline is possible. */
1346 unsigned int segs_n = buf->nb_segs;
1350 * Make sure there is enough room to store this packet and
1351 * that one ring entry remains unused.
1354 if (max_elts - j < segs_n)
1356 /* Do not bother with large packets MPW cannot handle. */
1357 if (segs_n > MLX5_MPW_DSEG_MAX) {
1358 txq->stats.oerrors++;
1361 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1362 /* Retrieve packet information. */
1363 length = PKT_LEN(buf);
1364 /* Start new session if:
1365 * - multi-segment packet
1366 * - no space left even for a dseg
1367 * - next packet can be inlined with a new WQE
1369 * It can't be MLX5_MPW_STATE_OPENED as always have a single
1372 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1373 if ((segs_n != 1) ||
1374 (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1376 (length <= txq->inline_max_packet_sz &&
1377 inl_pad + sizeof(inl_hdr) + length >
1379 (mpw.wqe->eseg.cs_flags != cs_flags))
1380 max_wqe -= mlx5_empw_close(txq, &mpw);
1382 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1383 if (unlikely(segs_n != 1)) {
1384 /* Fall back to legacy MPW.
1385 * A MPW session consumes 2 WQEs at most to
1386 * include MLX5_MPW_DSEG_MAX pointers.
1388 if (unlikely(max_wqe < 2))
1390 mlx5_mpw_new(txq, &mpw, length);
1392 /* In Enhanced MPW, inline as much as the budget
1393 * is allowed. The remaining space is to be
1394 * filled with dsegs. If the title WQEBB isn't
1395 * padded, it will have 2 dsegs there.
1397 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1398 (max_inline ? max_inline :
1399 pkts_n * MLX5_WQE_DWORD_SIZE) +
1401 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1404 /* Don't pad the title WQEBB to not waste WQ. */
1405 mlx5_empw_new(txq, &mpw, 0);
1406 mpw_room -= mpw.total_len;
1409 length <= txq->inline_max_packet_sz &&
1410 sizeof(inl_hdr) + length <= mpw_room &&
1413 mpw.wqe->eseg.cs_flags = cs_flags;
1415 /* Evaluate whether the next packet can be inlined.
1416 * Inlininig is possible when:
1417 * - length is less than configured value
1418 * - length fits for remaining space
1419 * - not required to fill the title WQEBB with dsegs
1422 length <= txq->inline_max_packet_sz &&
1423 inl_pad + sizeof(inl_hdr) + length <=
1425 (!txq->mpw_hdr_dseg ||
1426 mpw.total_len >= MLX5_WQE_SIZE);
1428 /* Multi-segment packets must be alone in their MPW. */
1429 assert((segs_n == 1) || (mpw.pkts_n == 0));
1430 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1431 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1435 volatile struct mlx5_wqe_data_seg *dseg;
1438 (*txq->elts)[elts_head++ & elts_m] = buf;
1439 dseg = mpw.data.dseg[mpw.pkts_n];
1440 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1441 *dseg = (struct mlx5_wqe_data_seg){
1442 .byte_count = rte_cpu_to_be_32(
1444 .lkey = mlx5_tx_mb2mr(txq, buf),
1445 .addr = rte_cpu_to_be_64(addr),
1447 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1448 length += DATA_LEN(buf);
1454 /* A multi-segmented packet takes one MPW session.
1455 * TODO: Pack more multi-segmented packets if possible.
1457 mlx5_mpw_close(txq, &mpw);
1462 } else if (do_inline) {
1463 /* Inline packet into WQE. */
1466 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1467 assert(length == DATA_LEN(buf));
1468 inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1469 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1470 mpw.data.raw = (volatile void *)
1471 ((uintptr_t)mpw.data.raw + inl_pad);
1472 max = tx_mlx5_wq_tailroom(txq,
1473 (void *)(uintptr_t)mpw.data.raw);
1474 /* Copy inline header. */
1475 mpw.data.raw = (volatile void *)
1477 (void *)(uintptr_t)mpw.data.raw,
1480 (void *)(uintptr_t)txq->wqes,
1482 max = tx_mlx5_wq_tailroom(txq,
1483 (void *)(uintptr_t)mpw.data.raw);
1484 /* Copy packet data. */
1485 mpw.data.raw = (volatile void *)
1487 (void *)(uintptr_t)mpw.data.raw,
1490 (void *)(uintptr_t)txq->wqes,
1493 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1494 /* No need to get completion as the entire packet is
1495 * copied to WQ. Free the buf right away.
1497 rte_pktmbuf_free_seg(buf);
1498 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1499 /* Add pad in the next packet if any. */
1500 inl_pad = (((uintptr_t)mpw.data.raw +
1501 (MLX5_WQE_DWORD_SIZE - 1)) &
1502 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1503 (uintptr_t)mpw.data.raw;
1505 /* No inline. Load a dseg of packet pointer. */
1506 volatile rte_v128u32_t *dseg;
1508 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1509 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1510 assert(length == DATA_LEN(buf));
1511 if (!tx_mlx5_wq_tailroom(txq,
1512 (void *)((uintptr_t)mpw.data.raw
1514 dseg = (volatile void *)txq->wqes;
1516 dseg = (volatile void *)
1517 ((uintptr_t)mpw.data.raw +
1519 (*txq->elts)[elts_head++ & elts_m] = buf;
1520 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1521 for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1522 rte_prefetch2((void *)(addr +
1523 n * RTE_CACHE_LINE_SIZE));
1524 naddr = rte_cpu_to_be_64(addr);
1525 *dseg = (rte_v128u32_t) {
1526 rte_cpu_to_be_32(length),
1527 mlx5_tx_mb2mr(txq, buf),
1531 mpw.data.raw = (volatile void *)(dseg + 1);
1532 mpw.total_len += (inl_pad + sizeof(*dseg));
1535 mpw_room -= (inl_pad + sizeof(*dseg));
1538 #ifdef MLX5_PMD_SOFT_COUNTERS
1539 /* Increment sent bytes counter. */
1540 txq->stats.obytes += length;
1543 } while (i < pkts_n);
1544 /* Take a shortcut if nothing must be sent. */
1545 if (unlikely(i == 0))
1547 /* Check whether completion threshold has been reached. */
1548 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1549 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1550 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1551 volatile struct mlx5_wqe *wqe = mpw.wqe;
1553 /* Request completion on last WQE. */
1554 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1555 /* Save elts_head in unused "immediate" field of WQE. */
1556 wqe->ctrl[3] = elts_head;
1558 txq->mpw_comp = txq->wqe_ci;
1561 txq->elts_comp += j;
1563 #ifdef MLX5_PMD_SOFT_COUNTERS
1564 /* Increment sent packets counter. */
1565 txq->stats.opackets += i;
1567 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1568 mlx5_empw_close(txq, &mpw);
1569 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1570 mlx5_mpw_close(txq, &mpw);
1571 /* Ring QP doorbell. */
1572 mlx5_tx_dbrec(txq, mpw.wqe);
1573 txq->elts_head = elts_head;
1578 * Translate RX completion flags to packet type.
1583 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1586 * Packet type for struct rte_mbuf.
1588 static inline uint32_t
1589 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1592 uint8_t pinfo = cqe->pkt_info;
1593 uint16_t ptype = cqe->hdr_type_etc;
1596 * The index to the array should have:
1597 * bit[1:0] = l3_hdr_type
1598 * bit[4:2] = l4_hdr_type
1601 * bit[7] = outer_l3_type
1603 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1604 return mlx5_ptype_table[idx];
1608 * Get size of the next packet for a given CQE. For compressed CQEs, the
1609 * consumer index is updated only once all packets of the current one have
1613 * Pointer to RX queue.
1616 * @param[out] rss_hash
1617 * Packet RSS Hash result.
1620 * Packet size in bytes (0 if there is none), -1 in case of completion
1624 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1625 uint16_t cqe_cnt, uint32_t *rss_hash)
1627 struct rxq_zip *zip = &rxq->zip;
1628 uint16_t cqe_n = cqe_cnt + 1;
1632 /* Process compressed data in the CQE and mini arrays. */
1634 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1635 (volatile struct mlx5_mini_cqe8 (*)[8])
1636 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1638 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1639 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1640 if ((++zip->ai & 7) == 0) {
1641 /* Invalidate consumed CQEs */
1644 while (idx != end) {
1645 (*rxq->cqes)[idx & cqe_cnt].op_own =
1646 MLX5_CQE_INVALIDATE;
1650 * Increment consumer index to skip the number of
1651 * CQEs consumed. Hardware leaves holes in the CQ
1652 * ring for software use.
1657 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1658 /* Invalidate the rest */
1662 while (idx != end) {
1663 (*rxq->cqes)[idx & cqe_cnt].op_own =
1664 MLX5_CQE_INVALIDATE;
1667 rxq->cq_ci = zip->cq_ci;
1670 /* No compressed data, get next CQE and verify if it is compressed. */
1675 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1676 if (unlikely(ret == 1))
1679 op_own = cqe->op_own;
1680 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1681 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1682 (volatile struct mlx5_mini_cqe8 (*)[8])
1683 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1686 /* Fix endianness. */
1687 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1689 * Current mini array position is the one returned by
1692 * If completion comprises several mini arrays, as a
1693 * special case the second one is located 7 CQEs after
1694 * the initial CQE instead of 8 for subsequent ones.
1696 zip->ca = rxq->cq_ci;
1697 zip->na = zip->ca + 7;
1698 /* Compute the next non compressed CQE. */
1700 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1701 /* Get packet size to return. */
1702 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1703 *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1705 /* Prefetch all the entries to be invalidated */
1708 while (idx != end) {
1709 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1713 len = rte_be_to_cpu_32(cqe->byte_cnt);
1714 *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1716 /* Error while receiving packet. */
1717 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1724 * Translate RX completion flags to offload flags.
1727 * Pointer to RX queue structure.
1732 * Offload flags (ol_flags) for struct rte_mbuf.
1734 static inline uint32_t
1735 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1737 uint32_t ol_flags = 0;
1738 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1742 MLX5_CQE_RX_L3_HDR_VALID,
1743 PKT_RX_IP_CKSUM_GOOD) |
1745 MLX5_CQE_RX_L4_HDR_VALID,
1746 PKT_RX_L4_CKSUM_GOOD);
1747 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1750 MLX5_CQE_RX_L3_HDR_VALID,
1751 PKT_RX_IP_CKSUM_GOOD) |
1753 MLX5_CQE_RX_L4_HDR_VALID,
1754 PKT_RX_L4_CKSUM_GOOD);
1759 * DPDK callback for RX.
1762 * Generic pointer to RX queue structure.
1764 * Array to store received packets.
1766 * Maximum number of packets in array.
1769 * Number of packets successfully received (<= pkts_n).
1772 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1774 struct mlx5_rxq_data *rxq = dpdk_rxq;
1775 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1776 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1777 const unsigned int sges_n = rxq->sges_n;
1778 struct rte_mbuf *pkt = NULL;
1779 struct rte_mbuf *seg = NULL;
1780 volatile struct mlx5_cqe *cqe =
1781 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1783 unsigned int rq_ci = rxq->rq_ci << sges_n;
1784 int len = 0; /* keep its value across iterations. */
1787 unsigned int idx = rq_ci & wqe_cnt;
1788 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1789 struct rte_mbuf *rep = (*rxq->elts)[idx];
1790 uint32_t rss_hash_res = 0;
1798 rep = rte_mbuf_raw_alloc(rxq->mp);
1799 if (unlikely(rep == NULL)) {
1800 ++rxq->stats.rx_nombuf;
1803 * no buffers before we even started,
1804 * bail out silently.
1808 while (pkt != seg) {
1809 assert(pkt != (*rxq->elts)[idx]);
1813 rte_mbuf_raw_free(pkt);
1819 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1820 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1823 rte_mbuf_raw_free(rep);
1826 if (unlikely(len == -1)) {
1827 /* RX error, packet is likely too large. */
1828 rte_mbuf_raw_free(rep);
1829 ++rxq->stats.idropped;
1833 assert(len >= (rxq->crc_present << 2));
1834 /* Update packet information. */
1835 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1837 if (rss_hash_res && rxq->rss_hash) {
1838 pkt->hash.rss = rss_hash_res;
1839 pkt->ol_flags = PKT_RX_RSS_HASH;
1842 MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1843 pkt->ol_flags |= PKT_RX_FDIR;
1844 if (cqe->sop_drop_qpn !=
1845 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1846 uint32_t mark = cqe->sop_drop_qpn;
1848 pkt->ol_flags |= PKT_RX_FDIR_ID;
1850 mlx5_flow_mark_get(mark);
1853 if (rxq->csum | rxq->csum_l2tun)
1854 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1855 if (rxq->vlan_strip &&
1856 (cqe->hdr_type_etc &
1857 rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1858 pkt->ol_flags |= PKT_RX_VLAN |
1859 PKT_RX_VLAN_STRIPPED;
1861 rte_be_to_cpu_16(cqe->vlan_info);
1863 if (rxq->hw_timestamp) {
1865 rte_be_to_cpu_64(cqe->timestamp);
1866 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1868 if (rxq->crc_present)
1869 len -= ETHER_CRC_LEN;
1872 DATA_LEN(rep) = DATA_LEN(seg);
1873 PKT_LEN(rep) = PKT_LEN(seg);
1874 SET_DATA_OFF(rep, DATA_OFF(seg));
1875 PORT(rep) = PORT(seg);
1876 (*rxq->elts)[idx] = rep;
1878 * Fill NIC descriptor with the new buffer. The lkey and size
1879 * of the buffers are already known, only the buffer address
1882 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1883 if (len > DATA_LEN(seg)) {
1884 len -= DATA_LEN(seg);
1889 DATA_LEN(seg) = len;
1890 #ifdef MLX5_PMD_SOFT_COUNTERS
1891 /* Increment bytes counter. */
1892 rxq->stats.ibytes += PKT_LEN(pkt);
1894 /* Return packet. */
1900 /* Align consumer index to the next stride. */
1905 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1907 /* Update the consumer index. */
1908 rxq->rq_ci = rq_ci >> sges_n;
1910 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1912 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1913 #ifdef MLX5_PMD_SOFT_COUNTERS
1914 /* Increment packets counter. */
1915 rxq->stats.ipackets += i;
1921 * Dummy DPDK callback for TX.
1923 * This function is used to temporarily replace the real callback during
1924 * unsafe control operations on the queue, or in case of error.
1927 * Generic pointer to TX queue structure.
1929 * Packets to transmit.
1931 * Number of packets in array.
1934 * Number of packets successfully transmitted (<= pkts_n).
1937 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1946 * Dummy DPDK callback for RX.
1948 * This function is used to temporarily replace the real callback during
1949 * unsafe control operations on the queue, or in case of error.
1952 * Generic pointer to RX queue structure.
1954 * Array to store received packets.
1956 * Maximum number of packets in array.
1959 * Number of packets successfully received (<= pkts_n).
1962 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1971 * Vectorized Rx/Tx routines are not compiled in when required vector
1972 * instructions are not supported on a target architecture. The following null
1973 * stubs are needed for linkage when those are not included outside of this file
1974 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1977 uint16_t __attribute__((weak))
1978 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1986 uint16_t __attribute__((weak))
1987 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1995 uint16_t __attribute__((weak))
1996 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2004 int __attribute__((weak))
2005 priv_check_raw_vec_tx_support(struct priv *priv)
2011 int __attribute__((weak))
2012 priv_check_vec_tx_support(struct priv *priv)
2018 int __attribute__((weak))
2019 rxq_check_vec_support(struct mlx5_rxq_data *rxq)
2025 int __attribute__((weak))
2026 priv_check_vec_rx_support(struct priv *priv)