4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci)
75 __attribute__((always_inline));
77 static inline uint32_t
78 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
79 __attribute__((always_inline));
82 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
83 __attribute__((always_inline));
85 static inline uint32_t
86 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
87 __attribute__((always_inline));
90 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
91 uint16_t cqe_cnt, uint32_t *rss_hash)
92 __attribute__((always_inline));
94 static inline uint32_t
95 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
96 __attribute__((always_inline));
101 * Verify or set magic value in CQE.
110 check_cqe_seen(volatile struct mlx5_cqe *cqe)
112 static const uint8_t magic[] = "seen";
113 volatile uint8_t (*buf)[sizeof(cqe->rsvd3)] = &cqe->rsvd3;
117 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
118 if (!ret || (*buf)[i] != magic[i]) {
120 (*buf)[i] = magic[i];
128 * Check whether CQE is valid.
133 * Size of completion queue.
138 * 0 on success, 1 on failure.
141 check_cqe(volatile struct mlx5_cqe *cqe,
142 unsigned int cqes_n, const uint16_t ci)
144 uint16_t idx = ci & cqes_n;
145 uint8_t op_own = cqe->op_own;
146 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
147 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
149 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
150 return 1; /* No CQE. */
152 if ((op_code == MLX5_CQE_RESP_ERR) ||
153 (op_code == MLX5_CQE_REQ_ERR)) {
154 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
155 uint8_t syndrome = err_cqe->syndrome;
157 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
158 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
160 if (!check_cqe_seen(cqe))
161 ERROR("unexpected CQE error %u (0x%02x)"
163 op_code, op_code, syndrome);
165 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
166 (op_code != MLX5_CQE_REQ)) {
167 if (!check_cqe_seen(cqe))
168 ERROR("unexpected CQE opcode %u (0x%02x)",
177 txq_complete(struct txq *txq) __attribute__((always_inline));
180 * Manage TX completions.
182 * When sending a burst, mlx5_tx_burst() posts several WRs.
185 * Pointer to TX queue structure.
188 txq_complete(struct txq *txq)
190 const unsigned int elts_n = 1 << txq->elts_n;
191 const unsigned int cqe_n = 1 << txq->cqe_n;
192 const unsigned int cqe_cnt = cqe_n - 1;
193 uint16_t elts_free = txq->elts_tail;
195 uint16_t cq_ci = txq->cq_ci;
196 volatile struct mlx5_cqe *cqe = NULL;
197 volatile struct mlx5_wqe *wqe;
200 volatile struct mlx5_cqe *tmp;
202 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
203 if (check_cqe(tmp, cqe_n, cq_ci))
207 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
208 if (!check_cqe_seen(cqe))
209 ERROR("unexpected compressed CQE, TX stopped");
212 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
213 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
214 if (!check_cqe_seen(cqe))
215 ERROR("unexpected error CQE, TX stopped");
221 if (unlikely(cqe == NULL))
223 wqe = &(*txq->wqes)[ntohs(cqe->wqe_counter) &
224 ((1 << txq->wqe_n) - 1)].hdr;
225 elts_tail = wqe->ctrl[3];
226 assert(elts_tail < (1 << txq->wqe_n));
228 while (elts_free != elts_tail) {
229 struct rte_mbuf *elt = (*txq->elts)[elts_free];
230 unsigned int elts_free_next =
231 (elts_free + 1) & (elts_n - 1);
232 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
236 memset(&(*txq->elts)[elts_free],
238 sizeof((*txq->elts)[elts_free]));
240 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
241 /* Only one segment needs to be freed. */
242 rte_pktmbuf_free_seg(elt);
243 elts_free = elts_free_next;
246 txq->elts_tail = elts_tail;
247 /* Update the consumer index. */
249 *txq->cq_db = htonl(cq_ci);
253 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
254 * the cloned mbuf is allocated is returned instead.
260 * Memory pool where data is located for given mbuf.
262 static struct rte_mempool *
263 txq_mb2mp(struct rte_mbuf *buf)
265 if (unlikely(RTE_MBUF_INDIRECT(buf)))
266 return rte_mbuf_from_indirect(buf)->pool;
271 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
272 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
273 * remove an entry first.
276 * Pointer to TX queue structure.
278 * Memory Pool for which a Memory Region lkey must be returned.
281 * mr->lkey on success, (uint32_t)-1 on failure.
283 static inline uint32_t
284 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
287 uint32_t lkey = (uint32_t)-1;
289 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
290 if (unlikely(txq->mp2mr[i].mp == NULL)) {
291 /* Unknown MP, add a new MR for it. */
294 if (txq->mp2mr[i].mp == mp) {
295 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
296 assert(htonl(txq->mp2mr[i].mr->lkey) ==
298 lkey = txq->mp2mr[i].lkey;
302 if (unlikely(lkey == (uint32_t)-1))
303 lkey = txq_mp2mr_reg(txq, mp, i);
308 * Ring TX queue doorbell.
311 * Pointer to TX queue structure.
313 * Pointer to the last WQE posted in the NIC.
316 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
318 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
319 volatile uint64_t *src = ((volatile uint64_t *)wqe);
322 *txq->qp_db = htonl(txq->wqe_ci);
323 /* Ensure ordering between DB record and BF copy. */
332 * Pointer to TX queue structure.
334 * CQE consumer index.
337 tx_prefetch_cqe(struct txq *txq, uint16_t ci)
339 volatile struct mlx5_cqe *cqe;
341 cqe = &(*txq->cqes)[ci & ((1 << txq->cqe_n) - 1)];
349 * Pointer to TX queue structure.
351 * WQE consumer index.
354 tx_prefetch_wqe(struct txq *txq, uint16_t ci)
356 volatile struct mlx5_wqe64 *wqe;
358 wqe = &(*txq->wqes)[ci & ((1 << txq->wqe_n) - 1)];
363 * DPDK callback for TX.
366 * Generic pointer to TX queue structure.
368 * Packets to transmit.
370 * Number of packets in array.
373 * Number of packets successfully transmitted (<= pkts_n).
376 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
378 struct txq *txq = (struct txq *)dpdk_txq;
379 uint16_t elts_head = txq->elts_head;
380 const unsigned int elts_n = 1 << txq->elts_n;
385 volatile struct mlx5_wqe *wqe = NULL;
386 unsigned int segs_n = 0;
387 struct rte_mbuf *buf = NULL;
390 if (unlikely(!pkts_n))
392 /* Prefetch first packet cacheline. */
393 tx_prefetch_cqe(txq, txq->cq_ci);
394 tx_prefetch_cqe(txq, txq->cq_ci + 1);
395 rte_prefetch0(*pkts);
396 /* Start processing. */
398 max = (elts_n - (elts_head - txq->elts_tail));
402 volatile struct mlx5_wqe_data_seg *dseg = NULL;
406 #ifdef MLX5_PMD_SOFT_COUNTERS
407 uint32_t total_length = 0;
412 segs_n = buf->nb_segs;
414 * Make sure there is enough room to store this packet and
415 * that one ring entry remains unused.
418 if (max < segs_n + 1)
424 wqe = &(*txq->wqes)[txq->wqe_ci &
425 ((1 << txq->wqe_n) - 1)].hdr;
426 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
428 rte_prefetch0(*pkts);
429 addr = rte_pktmbuf_mtod(buf, uintptr_t);
430 length = DATA_LEN(buf);
431 #ifdef MLX5_PMD_SOFT_COUNTERS
432 total_length = length;
434 assert(length >= MLX5_WQE_DWORD_SIZE);
435 /* Update element. */
436 (*txq->elts)[elts_head] = buf;
437 elts_head = (elts_head + 1) & (elts_n - 1);
438 /* Prefetch next buffer data. */
440 volatile void *pkt_addr;
442 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
443 rte_prefetch0(pkt_addr);
445 /* Should we enable HW CKSUM offload */
447 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
449 MLX5_ETH_WQE_L3_CSUM |
450 MLX5_ETH_WQE_L4_CSUM;
452 wqe->eseg.cs_flags = 0;
454 raw = (uint8_t *)(uintptr_t)&wqe->eseg.inline_hdr[0];
455 /* Start the know and common part of the WQE structure. */
456 wqe->ctrl[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
463 /* Start by copying the Ethernet Header. */
464 memcpy((uint8_t *)raw, ((uint8_t *)addr), 16);
465 length -= MLX5_WQE_DWORD_SIZE;
466 addr += MLX5_WQE_DWORD_SIZE;
467 /* Replace the Ethernet type by the VLAN if necessary. */
468 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
469 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
471 memcpy((uint8_t *)(raw + MLX5_WQE_DWORD_SIZE -
473 &vlan, sizeof(vlan));
474 addr -= sizeof(vlan);
475 length += sizeof(vlan);
477 /* Inline if enough room. */
478 if (txq->max_inline != 0) {
480 (uintptr_t)&(*txq->wqes)[1 << txq->wqe_n];
481 uint16_t max_inline =
482 txq->max_inline * RTE_CACHE_LINE_SIZE;
483 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE;
486 raw += MLX5_WQE_DWORD_SIZE;
487 room = end - (uintptr_t)raw;
488 if (room > max_inline) {
489 uintptr_t addr_end = (addr + max_inline) &
490 ~(RTE_CACHE_LINE_SIZE - 1);
491 uint16_t copy_b = ((addr_end - addr) > length) ?
495 rte_memcpy((void *)raw, (void *)addr, copy_b);
498 pkt_inline_sz += copy_b;
500 assert(addr <= addr_end);
502 /* Store the inlined packet size in the WQE. */
503 wqe->eseg.inline_hdr_sz = htons(pkt_inline_sz);
505 * 2 DWORDs consumed by the WQE header + 1 DSEG +
506 * the size of the inline part of the packet.
508 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
510 dseg = (struct mlx5_wqe_data_seg *)
512 (ds * MLX5_WQE_DWORD_SIZE));
513 if ((uintptr_t)dseg >= end)
514 dseg = (struct mlx5_wqe_data_seg *)
515 ((uintptr_t)&(*txq->wqes)[0]);
517 } else if (!segs_n) {
524 * No inline has been done in the packet, only the
525 * Ethernet Header as been stored.
527 wqe->eseg.inline_hdr_sz = htons(MLX5_WQE_DWORD_SIZE);
528 dseg = (struct mlx5_wqe_data_seg *)
529 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
532 /* Add the remaining packet as a simple ds. */
533 *dseg = (struct mlx5_wqe_data_seg) {
534 .addr = htonll(addr),
535 .byte_count = htonl(length),
536 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
547 * Spill on next WQE when the current one does not have
548 * enough room left. Size of WQE must a be a multiple
549 * of data segment size.
551 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
552 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
553 unsigned int n = (txq->wqe_ci + ((ds + 3) / 4)) &
554 ((1 << txq->wqe_n) - 1);
556 dseg = (struct mlx5_wqe_data_seg *)
557 ((uintptr_t)&(*txq->wqes)[n]);
558 tx_prefetch_wqe(txq, n + 1);
565 length = DATA_LEN(buf);
566 #ifdef MLX5_PMD_SOFT_COUNTERS
567 total_length += length;
569 /* Store segment information. */
570 *dseg = (struct mlx5_wqe_data_seg) {
571 .addr = htonll(rte_pktmbuf_mtod(buf, uintptr_t)),
572 .byte_count = htonl(length),
573 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
575 (*txq->elts)[elts_head] = buf;
576 elts_head = (elts_head + 1) & (elts_n - 1);
585 wqe->ctrl[1] = htonl(txq->qp_num_8s | ds);
586 txq->wqe_ci += (ds + 3) / 4;
587 #ifdef MLX5_PMD_SOFT_COUNTERS
588 /* Increment sent bytes counter. */
589 txq->stats.obytes += total_length;
592 /* Take a shortcut if nothing must be sent. */
593 if (unlikely(i == 0))
595 /* Check whether completion threshold has been reached. */
596 comp = txq->elts_comp + i + j;
597 if (comp >= MLX5_TX_COMP_THRESH) {
598 /* Request completion on last WQE. */
599 wqe->ctrl[2] = htonl(8);
600 /* Save elts_head in unused "immediate" field of WQE. */
601 wqe->ctrl[3] = elts_head;
604 txq->elts_comp = comp;
606 #ifdef MLX5_PMD_SOFT_COUNTERS
607 /* Increment sent packets counter. */
608 txq->stats.opackets += i;
610 /* Ring QP doorbell. */
611 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
612 txq->elts_head = elts_head;
617 * Open a MPW session.
620 * Pointer to TX queue structure.
622 * Pointer to MPW session structure.
627 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
629 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
630 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
631 (volatile struct mlx5_wqe_data_seg (*)[])
632 (uintptr_t)&(*txq->wqes)[(idx + 1) & ((1 << txq->wqe_n) - 1)];
634 mpw->state = MLX5_MPW_STATE_OPENED;
638 mpw->wqe = (volatile struct mlx5_wqe *)&(*txq->wqes)[idx].hdr;
639 mpw->wqe->eseg.mss = htons(length);
640 mpw->wqe->eseg.inline_hdr_sz = 0;
641 mpw->wqe->eseg.rsvd0 = 0;
642 mpw->wqe->eseg.rsvd1 = 0;
643 mpw->wqe->eseg.rsvd2 = 0;
644 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
645 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
646 mpw->wqe->ctrl[2] = 0;
647 mpw->wqe->ctrl[3] = 0;
648 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
649 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
650 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
651 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
652 mpw->data.dseg[2] = &(*dseg)[0];
653 mpw->data.dseg[3] = &(*dseg)[1];
654 mpw->data.dseg[4] = &(*dseg)[2];
658 * Close a MPW session.
661 * Pointer to TX queue structure.
663 * Pointer to MPW session structure.
666 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
668 unsigned int num = mpw->pkts_n;
671 * Store size in multiple of 16 bytes. Control and Ethernet segments
674 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
675 mpw->state = MLX5_MPW_STATE_CLOSED;
680 tx_prefetch_wqe(txq, txq->wqe_ci);
681 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
685 * DPDK callback for TX with MPW support.
688 * Generic pointer to TX queue structure.
690 * Packets to transmit.
692 * Number of packets in array.
695 * Number of packets successfully transmitted (<= pkts_n).
698 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
700 struct txq *txq = (struct txq *)dpdk_txq;
701 uint16_t elts_head = txq->elts_head;
702 const unsigned int elts_n = 1 << txq->elts_n;
707 struct mlx5_mpw mpw = {
708 .state = MLX5_MPW_STATE_CLOSED,
711 if (unlikely(!pkts_n))
713 /* Prefetch first packet cacheline. */
714 tx_prefetch_cqe(txq, txq->cq_ci);
715 tx_prefetch_wqe(txq, txq->wqe_ci);
716 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
717 /* Start processing. */
719 max = (elts_n - (elts_head - txq->elts_tail));
723 struct rte_mbuf *buf = *(pkts++);
724 unsigned int elts_head_next;
726 unsigned int segs_n = buf->nb_segs;
727 uint32_t cs_flags = 0;
730 * Make sure there is enough room to store this packet and
731 * that one ring entry remains unused.
734 if (max < segs_n + 1)
736 /* Do not bother with large packets MPW cannot handle. */
737 if (segs_n > MLX5_MPW_DSEG_MAX)
741 /* Should we enable HW CKSUM offload */
743 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
744 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
745 /* Retrieve packet information. */
746 length = PKT_LEN(buf);
748 /* Start new session if packet differs. */
749 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
750 ((mpw.len != length) ||
752 (mpw.wqe->eseg.cs_flags != cs_flags)))
753 mlx5_mpw_close(txq, &mpw);
754 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
755 mlx5_mpw_new(txq, &mpw, length);
756 mpw.wqe->eseg.cs_flags = cs_flags;
758 /* Multi-segment packets must be alone in their MPW. */
759 assert((segs_n == 1) || (mpw.pkts_n == 0));
760 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
764 volatile struct mlx5_wqe_data_seg *dseg;
767 elts_head_next = (elts_head + 1) & (elts_n - 1);
769 (*txq->elts)[elts_head] = buf;
770 dseg = mpw.data.dseg[mpw.pkts_n];
771 addr = rte_pktmbuf_mtod(buf, uintptr_t);
772 *dseg = (struct mlx5_wqe_data_seg){
773 .byte_count = htonl(DATA_LEN(buf)),
774 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
775 .addr = htonll(addr),
777 elts_head = elts_head_next;
778 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
779 length += DATA_LEN(buf);
785 assert(length == mpw.len);
786 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
787 mlx5_mpw_close(txq, &mpw);
788 elts_head = elts_head_next;
789 #ifdef MLX5_PMD_SOFT_COUNTERS
790 /* Increment sent bytes counter. */
791 txq->stats.obytes += length;
795 /* Take a shortcut if nothing must be sent. */
796 if (unlikely(i == 0))
798 /* Check whether completion threshold has been reached. */
799 /* "j" includes both packets and segments. */
800 comp = txq->elts_comp + j;
801 if (comp >= MLX5_TX_COMP_THRESH) {
802 volatile struct mlx5_wqe *wqe = mpw.wqe;
804 /* Request completion on last WQE. */
805 wqe->ctrl[2] = htonl(8);
806 /* Save elts_head in unused "immediate" field of WQE. */
807 wqe->ctrl[3] = elts_head;
810 txq->elts_comp = comp;
812 #ifdef MLX5_PMD_SOFT_COUNTERS
813 /* Increment sent packets counter. */
814 txq->stats.opackets += i;
816 /* Ring QP doorbell. */
817 if (mpw.state == MLX5_MPW_STATE_OPENED)
818 mlx5_mpw_close(txq, &mpw);
819 mlx5_tx_dbrec(txq, mpw.wqe);
820 txq->elts_head = elts_head;
825 * Open a MPW inline session.
828 * Pointer to TX queue structure.
830 * Pointer to MPW session structure.
835 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
837 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
838 struct mlx5_wqe_inl_small *inl;
840 mpw->state = MLX5_MPW_INL_STATE_OPENED;
844 mpw->wqe = (volatile struct mlx5_wqe *)&(*txq->wqes)[idx].hdr;
845 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
848 mpw->wqe->ctrl[2] = 0;
849 mpw->wqe->ctrl[3] = 0;
850 mpw->wqe->eseg.mss = htons(length);
851 mpw->wqe->eseg.inline_hdr_sz = 0;
852 mpw->wqe->eseg.cs_flags = 0;
853 mpw->wqe->eseg.rsvd0 = 0;
854 mpw->wqe->eseg.rsvd1 = 0;
855 mpw->wqe->eseg.rsvd2 = 0;
856 inl = (struct mlx5_wqe_inl_small *)
857 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
858 mpw->data.raw = (uint8_t *)&inl->raw;
862 * Close a MPW inline session.
865 * Pointer to TX queue structure.
867 * Pointer to MPW session structure.
870 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
873 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
874 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
876 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
878 * Store size in multiple of 16 bytes. Control and Ethernet segments
881 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
882 mpw->state = MLX5_MPW_STATE_CLOSED;
883 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
884 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
888 * DPDK callback for TX with MPW inline support.
891 * Generic pointer to TX queue structure.
893 * Packets to transmit.
895 * Number of packets in array.
898 * Number of packets successfully transmitted (<= pkts_n).
901 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
904 struct txq *txq = (struct txq *)dpdk_txq;
905 uint16_t elts_head = txq->elts_head;
906 const unsigned int elts_n = 1 << txq->elts_n;
911 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
912 struct mlx5_mpw mpw = {
913 .state = MLX5_MPW_STATE_CLOSED,
916 if (unlikely(!pkts_n))
918 /* Prefetch first packet cacheline. */
919 tx_prefetch_cqe(txq, txq->cq_ci);
920 tx_prefetch_wqe(txq, txq->wqe_ci);
921 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
922 /* Start processing. */
924 max = (elts_n - (elts_head - txq->elts_tail));
928 struct rte_mbuf *buf = *(pkts++);
929 unsigned int elts_head_next;
932 unsigned int segs_n = buf->nb_segs;
933 uint32_t cs_flags = 0;
936 * Make sure there is enough room to store this packet and
937 * that one ring entry remains unused.
940 if (max < segs_n + 1)
942 /* Do not bother with large packets MPW cannot handle. */
943 if (segs_n > MLX5_MPW_DSEG_MAX)
947 /* Should we enable HW CKSUM offload */
949 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
950 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
951 /* Retrieve packet information. */
952 length = PKT_LEN(buf);
953 /* Start new session if packet differs. */
954 if (mpw.state == MLX5_MPW_STATE_OPENED) {
955 if ((mpw.len != length) ||
957 (mpw.wqe->eseg.cs_flags != cs_flags))
958 mlx5_mpw_close(txq, &mpw);
959 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
960 if ((mpw.len != length) ||
962 (length > inline_room) ||
963 (mpw.wqe->eseg.cs_flags != cs_flags)) {
964 mlx5_mpw_inline_close(txq, &mpw);
966 txq->max_inline * RTE_CACHE_LINE_SIZE;
969 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
971 (length > inline_room)) {
972 mlx5_mpw_new(txq, &mpw, length);
973 mpw.wqe->eseg.cs_flags = cs_flags;
975 mlx5_mpw_inline_new(txq, &mpw, length);
976 mpw.wqe->eseg.cs_flags = cs_flags;
979 /* Multi-segment packets must be alone in their MPW. */
980 assert((segs_n == 1) || (mpw.pkts_n == 0));
981 if (mpw.state == MLX5_MPW_STATE_OPENED) {
982 assert(inline_room ==
983 txq->max_inline * RTE_CACHE_LINE_SIZE);
984 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
988 volatile struct mlx5_wqe_data_seg *dseg;
991 (elts_head + 1) & (elts_n - 1);
993 (*txq->elts)[elts_head] = buf;
994 dseg = mpw.data.dseg[mpw.pkts_n];
995 addr = rte_pktmbuf_mtod(buf, uintptr_t);
996 *dseg = (struct mlx5_wqe_data_seg){
997 .byte_count = htonl(DATA_LEN(buf)),
998 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
999 .addr = htonll(addr),
1001 elts_head = elts_head_next;
1002 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1003 length += DATA_LEN(buf);
1009 assert(length == mpw.len);
1010 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1011 mlx5_mpw_close(txq, &mpw);
1015 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1016 assert(length <= inline_room);
1017 assert(length == DATA_LEN(buf));
1018 elts_head_next = (elts_head + 1) & (elts_n - 1);
1019 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1020 (*txq->elts)[elts_head] = buf;
1021 /* Maximum number of bytes before wrapping. */
1022 max = ((uintptr_t)&(*txq->wqes)[1 << txq->wqe_n] -
1023 (uintptr_t)mpw.data.raw);
1025 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1029 (volatile void *)&(*txq->wqes)[0];
1030 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1031 (void *)(addr + max),
1033 mpw.data.raw += length - max;
1035 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1038 mpw.data.raw += length;
1040 if ((uintptr_t)mpw.data.raw ==
1041 (uintptr_t)&(*txq->wqes)[1 << txq->wqe_n])
1043 (volatile void *)&(*txq->wqes)[0];
1045 mpw.total_len += length;
1047 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1048 mlx5_mpw_inline_close(txq, &mpw);
1050 txq->max_inline * RTE_CACHE_LINE_SIZE;
1052 inline_room -= length;
1055 elts_head = elts_head_next;
1056 #ifdef MLX5_PMD_SOFT_COUNTERS
1057 /* Increment sent bytes counter. */
1058 txq->stats.obytes += length;
1062 /* Take a shortcut if nothing must be sent. */
1063 if (unlikely(i == 0))
1065 /* Check whether completion threshold has been reached. */
1066 /* "j" includes both packets and segments. */
1067 comp = txq->elts_comp + j;
1068 if (comp >= MLX5_TX_COMP_THRESH) {
1069 volatile struct mlx5_wqe *wqe = mpw.wqe;
1071 /* Request completion on last WQE. */
1072 wqe->ctrl[2] = htonl(8);
1073 /* Save elts_head in unused "immediate" field of WQE. */
1074 wqe->ctrl[3] = elts_head;
1077 txq->elts_comp = comp;
1079 #ifdef MLX5_PMD_SOFT_COUNTERS
1080 /* Increment sent packets counter. */
1081 txq->stats.opackets += i;
1083 /* Ring QP doorbell. */
1084 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1085 mlx5_mpw_inline_close(txq, &mpw);
1086 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1087 mlx5_mpw_close(txq, &mpw);
1088 mlx5_tx_dbrec(txq, mpw.wqe);
1089 txq->elts_head = elts_head;
1094 * Translate RX completion flags to packet type.
1099 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1102 * Packet type for struct rte_mbuf.
1104 static inline uint32_t
1105 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1108 uint16_t flags = ntohs(cqe->hdr_type_etc);
1110 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1113 MLX5_CQE_RX_IPV4_PACKET,
1114 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1116 MLX5_CQE_RX_IPV6_PACKET,
1117 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1118 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1119 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1120 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1124 MLX5_CQE_L3_HDR_TYPE_IPV6,
1125 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1127 MLX5_CQE_L3_HDR_TYPE_IPV4,
1128 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1134 * Get size of the next packet for a given CQE. For compressed CQEs, the
1135 * consumer index is updated only once all packets of the current one have
1139 * Pointer to RX queue.
1142 * @param[out] rss_hash
1143 * Packet RSS Hash result.
1146 * Packet size in bytes (0 if there is none), -1 in case of completion
1150 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1151 uint16_t cqe_cnt, uint32_t *rss_hash)
1153 struct rxq_zip *zip = &rxq->zip;
1154 uint16_t cqe_n = cqe_cnt + 1;
1157 /* Process compressed data in the CQE and mini arrays. */
1159 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1160 (volatile struct mlx5_mini_cqe8 (*)[8])
1161 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1163 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1164 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1165 if ((++zip->ai & 7) == 0) {
1167 * Increment consumer index to skip the number of
1168 * CQEs consumed. Hardware leaves holes in the CQ
1169 * ring for software use.
1174 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1175 uint16_t idx = rxq->cq_ci;
1176 uint16_t end = zip->cq_ci;
1178 while (idx != end) {
1179 (*rxq->cqes)[idx & cqe_cnt].op_own =
1180 MLX5_CQE_INVALIDATE;
1183 rxq->cq_ci = zip->cq_ci;
1186 /* No compressed data, get next CQE and verify if it is compressed. */
1191 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1192 if (unlikely(ret == 1))
1195 op_own = cqe->op_own;
1196 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1197 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1198 (volatile struct mlx5_mini_cqe8 (*)[8])
1199 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1202 /* Fix endianness. */
1203 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1205 * Current mini array position is the one returned by
1208 * If completion comprises several mini arrays, as a
1209 * special case the second one is located 7 CQEs after
1210 * the initial CQE instead of 8 for subsequent ones.
1212 zip->ca = rxq->cq_ci & cqe_cnt;
1213 zip->na = zip->ca + 7;
1214 /* Compute the next non compressed CQE. */
1216 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1217 /* Get packet size to return. */
1218 len = ntohl((*mc)[0].byte_cnt);
1219 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1222 len = ntohl(cqe->byte_cnt);
1223 *rss_hash = ntohl(cqe->rx_hash_res);
1225 /* Error while receiving packet. */
1226 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1233 * Translate RX completion flags to offload flags.
1236 * Pointer to RX queue structure.
1241 * Offload flags (ol_flags) for struct rte_mbuf.
1243 static inline uint32_t
1244 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1246 uint32_t ol_flags = 0;
1247 uint16_t flags = ntohs(cqe->hdr_type_etc);
1251 MLX5_CQE_RX_L3_HDR_VALID,
1252 PKT_RX_IP_CKSUM_GOOD) |
1254 MLX5_CQE_RX_L4_HDR_VALID,
1255 PKT_RX_L4_CKSUM_GOOD);
1256 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1259 MLX5_CQE_RX_L3_HDR_VALID,
1260 PKT_RX_IP_CKSUM_GOOD) |
1262 MLX5_CQE_RX_L4_HDR_VALID,
1263 PKT_RX_L4_CKSUM_GOOD);
1268 * DPDK callback for RX.
1271 * Generic pointer to RX queue structure.
1273 * Array to store received packets.
1275 * Maximum number of packets in array.
1278 * Number of packets successfully received (<= pkts_n).
1281 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1283 struct rxq *rxq = dpdk_rxq;
1284 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1285 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1286 const unsigned int sges_n = rxq->sges_n;
1287 struct rte_mbuf *pkt = NULL;
1288 struct rte_mbuf *seg = NULL;
1289 volatile struct mlx5_cqe *cqe =
1290 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1292 unsigned int rq_ci = rxq->rq_ci << sges_n;
1293 int len; /* keep its value across iterations. */
1296 unsigned int idx = rq_ci & wqe_cnt;
1297 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1298 struct rte_mbuf *rep = (*rxq->elts)[idx];
1299 uint32_t rss_hash_res = 0;
1307 rep = rte_mbuf_raw_alloc(rxq->mp);
1308 if (unlikely(rep == NULL)) {
1309 ++rxq->stats.rx_nombuf;
1312 * no buffers before we even started,
1313 * bail out silently.
1317 while (pkt != seg) {
1318 assert(pkt != (*rxq->elts)[idx]);
1320 rte_mbuf_refcnt_set(pkt, 0);
1321 __rte_mbuf_raw_free(pkt);
1327 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1328 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1331 rte_mbuf_refcnt_set(rep, 0);
1332 __rte_mbuf_raw_free(rep);
1335 if (unlikely(len == -1)) {
1336 /* RX error, packet is likely too large. */
1337 rte_mbuf_refcnt_set(rep, 0);
1338 __rte_mbuf_raw_free(rep);
1339 ++rxq->stats.idropped;
1343 assert(len >= (rxq->crc_present << 2));
1344 /* Update packet information. */
1345 pkt->packet_type = 0;
1347 if (rss_hash_res && rxq->rss_hash) {
1348 pkt->hash.rss = rss_hash_res;
1349 pkt->ol_flags = PKT_RX_RSS_HASH;
1351 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1355 rxq_cq_to_pkt_type(cqe);
1357 rxq_cq_to_ol_flags(rxq, cqe);
1359 if (cqe->hdr_type_etc &
1360 MLX5_CQE_VLAN_STRIPPED) {
1361 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1362 PKT_RX_VLAN_STRIPPED;
1363 pkt->vlan_tci = ntohs(cqe->vlan_info);
1365 if (rxq->crc_present)
1366 len -= ETHER_CRC_LEN;
1370 DATA_LEN(rep) = DATA_LEN(seg);
1371 PKT_LEN(rep) = PKT_LEN(seg);
1372 SET_DATA_OFF(rep, DATA_OFF(seg));
1373 NB_SEGS(rep) = NB_SEGS(seg);
1374 PORT(rep) = PORT(seg);
1376 (*rxq->elts)[idx] = rep;
1378 * Fill NIC descriptor with the new buffer. The lkey and size
1379 * of the buffers are already known, only the buffer address
1382 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1383 if (len > DATA_LEN(seg)) {
1384 len -= DATA_LEN(seg);
1389 DATA_LEN(seg) = len;
1390 #ifdef MLX5_PMD_SOFT_COUNTERS
1391 /* Increment bytes counter. */
1392 rxq->stats.ibytes += PKT_LEN(pkt);
1394 /* Return packet. */
1400 /* Align consumer index to the next stride. */
1405 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1407 /* Update the consumer index. */
1408 rxq->rq_ci = rq_ci >> sges_n;
1410 *rxq->cq_db = htonl(rxq->cq_ci);
1412 *rxq->rq_db = htonl(rxq->rq_ci);
1413 #ifdef MLX5_PMD_SOFT_COUNTERS
1414 /* Increment packets counter. */
1415 rxq->stats.ipackets += i;
1421 * Dummy DPDK callback for TX.
1423 * This function is used to temporarily replace the real callback during
1424 * unsafe control operations on the queue, or in case of error.
1427 * Generic pointer to TX queue structure.
1429 * Packets to transmit.
1431 * Number of packets in array.
1434 * Number of packets successfully transmitted (<= pkts_n).
1437 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1446 * Dummy DPDK callback for RX.
1448 * This function is used to temporarily replace the real callback during
1449 * unsafe control operations on the queue, or in case of error.
1452 * Generic pointer to RX queue structure.
1454 * Array to store received packets.
1456 * Maximum number of packets in array.
1459 * Number of packets successfully received (<= pkts_n).
1462 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)