4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci)
75 __attribute__((always_inline));
77 static inline uint32_t
78 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
79 __attribute__((always_inline));
82 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
83 __attribute__((always_inline));
85 static inline uint32_t
86 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
87 __attribute__((always_inline));
90 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
91 uint16_t cqe_cnt, uint32_t *rss_hash)
92 __attribute__((always_inline));
94 static inline uint32_t
95 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
96 __attribute__((always_inline));
101 * Verify or set magic value in CQE.
110 check_cqe_seen(volatile struct mlx5_cqe *cqe)
112 static const uint8_t magic[] = "seen";
113 volatile uint8_t (*buf)[sizeof(cqe->rsvd3)] = &cqe->rsvd3;
117 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
118 if (!ret || (*buf)[i] != magic[i]) {
120 (*buf)[i] = magic[i];
128 * Check whether CQE is valid.
133 * Size of completion queue.
138 * 0 on success, 1 on failure.
141 check_cqe(volatile struct mlx5_cqe *cqe,
142 unsigned int cqes_n, const uint16_t ci)
144 uint16_t idx = ci & cqes_n;
145 uint8_t op_own = cqe->op_own;
146 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
147 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
149 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
150 return 1; /* No CQE. */
152 if ((op_code == MLX5_CQE_RESP_ERR) ||
153 (op_code == MLX5_CQE_REQ_ERR)) {
154 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
155 uint8_t syndrome = err_cqe->syndrome;
157 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
158 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
160 if (!check_cqe_seen(cqe))
161 ERROR("unexpected CQE error %u (0x%02x)"
163 op_code, op_code, syndrome);
165 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
166 (op_code != MLX5_CQE_REQ)) {
167 if (!check_cqe_seen(cqe))
168 ERROR("unexpected CQE opcode %u (0x%02x)",
177 txq_complete(struct txq *txq) __attribute__((always_inline));
180 * Manage TX completions.
182 * When sending a burst, mlx5_tx_burst() posts several WRs.
185 * Pointer to TX queue structure.
188 txq_complete(struct txq *txq)
190 const unsigned int elts_n = 1 << txq->elts_n;
191 const unsigned int cqe_n = 1 << txq->cqe_n;
192 const unsigned int cqe_cnt = cqe_n - 1;
193 uint16_t elts_free = txq->elts_tail;
195 uint16_t cq_ci = txq->cq_ci;
196 volatile struct mlx5_cqe *cqe = NULL;
197 volatile struct mlx5_wqe *wqe;
200 volatile struct mlx5_cqe *tmp;
202 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
203 if (check_cqe(tmp, cqe_n, cq_ci))
207 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
208 if (!check_cqe_seen(cqe))
209 ERROR("unexpected compressed CQE, TX stopped");
212 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
213 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
214 if (!check_cqe_seen(cqe))
215 ERROR("unexpected error CQE, TX stopped");
221 if (unlikely(cqe == NULL))
223 wqe = &(*txq->wqes)[ntohs(cqe->wqe_counter) &
224 ((1 << txq->wqe_n) - 1)].hdr;
225 elts_tail = wqe->ctrl[3];
226 assert(elts_tail < (1 << txq->wqe_n));
228 while (elts_free != elts_tail) {
229 struct rte_mbuf *elt = (*txq->elts)[elts_free];
230 unsigned int elts_free_next =
231 (elts_free + 1) & (elts_n - 1);
232 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
236 memset(&(*txq->elts)[elts_free],
238 sizeof((*txq->elts)[elts_free]));
240 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
241 /* Only one segment needs to be freed. */
242 rte_pktmbuf_free_seg(elt);
243 elts_free = elts_free_next;
246 txq->elts_tail = elts_tail;
247 /* Update the consumer index. */
249 *txq->cq_db = htonl(cq_ci);
253 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
254 * the cloned mbuf is allocated is returned instead.
260 * Memory pool where data is located for given mbuf.
262 static struct rte_mempool *
263 txq_mb2mp(struct rte_mbuf *buf)
265 if (unlikely(RTE_MBUF_INDIRECT(buf)))
266 return rte_mbuf_from_indirect(buf)->pool;
271 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
272 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
273 * remove an entry first.
276 * Pointer to TX queue structure.
278 * Memory Pool for which a Memory Region lkey must be returned.
281 * mr->lkey on success, (uint32_t)-1 on failure.
283 static inline uint32_t
284 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
287 uint32_t lkey = (uint32_t)-1;
289 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
290 if (unlikely(txq->mp2mr[i].mp == NULL)) {
291 /* Unknown MP, add a new MR for it. */
294 if (txq->mp2mr[i].mp == mp) {
295 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
296 assert(htonl(txq->mp2mr[i].mr->lkey) ==
298 lkey = txq->mp2mr[i].lkey;
302 if (unlikely(lkey == (uint32_t)-1))
303 lkey = txq_mp2mr_reg(txq, mp, i);
308 * Ring TX queue doorbell.
311 * Pointer to TX queue structure.
313 * Pointer to the last WQE posted in the NIC.
316 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
318 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
319 volatile uint64_t *src = ((volatile uint64_t *)wqe);
322 *txq->qp_db = htonl(txq->wqe_ci);
323 /* Ensure ordering between DB record and BF copy. */
332 * Pointer to TX queue structure.
334 * CQE consumer index.
337 tx_prefetch_cqe(struct txq *txq, uint16_t ci)
339 volatile struct mlx5_cqe *cqe;
341 cqe = &(*txq->cqes)[ci & ((1 << txq->cqe_n) - 1)];
349 * Pointer to TX queue structure.
351 * WQE consumer index.
354 tx_prefetch_wqe(struct txq *txq, uint16_t ci)
356 volatile struct mlx5_wqe64 *wqe;
358 wqe = &(*txq->wqes)[ci & ((1 << txq->wqe_n) - 1)];
363 * DPDK callback for TX.
366 * Generic pointer to TX queue structure.
368 * Packets to transmit.
370 * Number of packets in array.
373 * Number of packets successfully transmitted (<= pkts_n).
376 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
378 struct txq *txq = (struct txq *)dpdk_txq;
379 uint16_t elts_head = txq->elts_head;
380 const unsigned int elts_n = 1 << txq->elts_n;
385 volatile struct mlx5_wqe *wqe = NULL;
386 unsigned int segs_n = 0;
387 struct rte_mbuf *buf = NULL;
390 if (unlikely(!pkts_n))
392 /* Prefetch first packet cacheline. */
393 tx_prefetch_cqe(txq, txq->cq_ci);
394 tx_prefetch_cqe(txq, txq->cq_ci + 1);
395 rte_prefetch0(*pkts);
396 /* Start processing. */
398 max = (elts_n - (elts_head - txq->elts_tail));
402 volatile struct mlx5_wqe_data_seg *dseg = NULL;
406 #ifdef MLX5_PMD_SOFT_COUNTERS
407 uint32_t total_length = 0;
412 segs_n = buf->nb_segs;
414 * Make sure there is enough room to store this packet and
415 * that one ring entry remains unused.
418 if (max < segs_n + 1)
424 wqe = &(*txq->wqes)[txq->wqe_ci &
425 ((1 << txq->wqe_n) - 1)].hdr;
426 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
428 rte_prefetch0(*pkts);
429 addr = rte_pktmbuf_mtod(buf, uintptr_t);
430 length = DATA_LEN(buf);
431 #ifdef MLX5_PMD_SOFT_COUNTERS
432 total_length = length;
434 if (length < (MLX5_WQE_DWORD_SIZE + 2))
436 /* Update element. */
437 (*txq->elts)[elts_head] = buf;
438 elts_head = (elts_head + 1) & (elts_n - 1);
439 /* Prefetch next buffer data. */
441 volatile void *pkt_addr;
443 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
444 rte_prefetch0(pkt_addr);
446 /* Should we enable HW CKSUM offload */
448 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
450 MLX5_ETH_WQE_L3_CSUM |
451 MLX5_ETH_WQE_L4_CSUM;
453 wqe->eseg.cs_flags = 0;
455 raw = (uint8_t *)(uintptr_t)&wqe->eseg.inline_hdr[0];
456 /* Start the know and common part of the WQE structure. */
457 wqe->ctrl[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
464 /* Start by copying the Ethernet Header. */
465 memcpy((uint8_t *)raw, ((uint8_t *)addr), 16);
466 length -= MLX5_WQE_DWORD_SIZE;
467 addr += MLX5_WQE_DWORD_SIZE;
468 /* Replace the Ethernet type by the VLAN if necessary. */
469 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
470 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
472 memcpy((uint8_t *)(raw + MLX5_WQE_DWORD_SIZE -
474 &vlan, sizeof(vlan));
475 addr -= sizeof(vlan);
476 length += sizeof(vlan);
478 /* Inline if enough room. */
479 if (txq->max_inline != 0) {
481 (uintptr_t)&(*txq->wqes)[1 << txq->wqe_n];
482 uint16_t max_inline =
483 txq->max_inline * RTE_CACHE_LINE_SIZE;
484 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE;
487 raw += MLX5_WQE_DWORD_SIZE;
488 room = end - (uintptr_t)raw;
489 if (room > max_inline) {
490 uintptr_t addr_end = (addr + max_inline) &
491 ~(RTE_CACHE_LINE_SIZE - 1);
492 uint16_t copy_b = ((addr_end - addr) > length) ?
496 rte_memcpy((void *)raw, (void *)addr, copy_b);
499 pkt_inline_sz += copy_b;
501 assert(addr <= addr_end);
503 /* Store the inlined packet size in the WQE. */
504 wqe->eseg.inline_hdr_sz = htons(pkt_inline_sz);
506 * 2 DWORDs consumed by the WQE header + 1 DSEG +
507 * the size of the inline part of the packet.
509 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
511 dseg = (struct mlx5_wqe_data_seg *)
513 (ds * MLX5_WQE_DWORD_SIZE));
514 if ((uintptr_t)dseg >= end)
515 dseg = (struct mlx5_wqe_data_seg *)
516 ((uintptr_t)&(*txq->wqes)[0]);
518 } else if (!segs_n) {
525 * No inline has been done in the packet, only the
526 * Ethernet Header as been stored.
528 wqe->eseg.inline_hdr_sz = htons(MLX5_WQE_DWORD_SIZE);
529 dseg = (struct mlx5_wqe_data_seg *)
530 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
533 /* Add the remaining packet as a simple ds. */
534 *dseg = (struct mlx5_wqe_data_seg) {
535 .addr = htonll(addr),
536 .byte_count = htonl(length),
537 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
548 * Spill on next WQE when the current one does not have
549 * enough room left. Size of WQE must a be a multiple
550 * of data segment size.
552 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
553 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
554 unsigned int n = (txq->wqe_ci + ((ds + 3) / 4)) &
555 ((1 << txq->wqe_n) - 1);
557 dseg = (struct mlx5_wqe_data_seg *)
558 ((uintptr_t)&(*txq->wqes)[n]);
559 tx_prefetch_wqe(txq, n + 1);
566 length = DATA_LEN(buf);
567 #ifdef MLX5_PMD_SOFT_COUNTERS
568 total_length += length;
570 /* Store segment information. */
571 *dseg = (struct mlx5_wqe_data_seg) {
572 .addr = htonll(rte_pktmbuf_mtod(buf, uintptr_t)),
573 .byte_count = htonl(length),
574 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
576 (*txq->elts)[elts_head] = buf;
577 elts_head = (elts_head + 1) & (elts_n - 1);
586 wqe->ctrl[1] = htonl(txq->qp_num_8s | ds);
587 txq->wqe_ci += (ds + 3) / 4;
588 #ifdef MLX5_PMD_SOFT_COUNTERS
589 /* Increment sent bytes counter. */
590 txq->stats.obytes += total_length;
593 /* Take a shortcut if nothing must be sent. */
594 if (unlikely(i == 0))
596 /* Check whether completion threshold has been reached. */
597 comp = txq->elts_comp + i + j;
598 if (comp >= MLX5_TX_COMP_THRESH) {
599 /* Request completion on last WQE. */
600 wqe->ctrl[2] = htonl(8);
601 /* Save elts_head in unused "immediate" field of WQE. */
602 wqe->ctrl[3] = elts_head;
605 txq->elts_comp = comp;
607 #ifdef MLX5_PMD_SOFT_COUNTERS
608 /* Increment sent packets counter. */
609 txq->stats.opackets += i;
611 /* Ring QP doorbell. */
612 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
613 txq->elts_head = elts_head;
618 * Open a MPW session.
621 * Pointer to TX queue structure.
623 * Pointer to MPW session structure.
628 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
630 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
631 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
632 (volatile struct mlx5_wqe_data_seg (*)[])
633 (uintptr_t)&(*txq->wqes)[(idx + 1) & ((1 << txq->wqe_n) - 1)];
635 mpw->state = MLX5_MPW_STATE_OPENED;
639 mpw->wqe = (volatile struct mlx5_wqe *)&(*txq->wqes)[idx].hdr;
640 mpw->wqe->eseg.mss = htons(length);
641 mpw->wqe->eseg.inline_hdr_sz = 0;
642 mpw->wqe->eseg.rsvd0 = 0;
643 mpw->wqe->eseg.rsvd1 = 0;
644 mpw->wqe->eseg.rsvd2 = 0;
645 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
646 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
647 mpw->wqe->ctrl[2] = 0;
648 mpw->wqe->ctrl[3] = 0;
649 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
650 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
651 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
652 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
653 mpw->data.dseg[2] = &(*dseg)[0];
654 mpw->data.dseg[3] = &(*dseg)[1];
655 mpw->data.dseg[4] = &(*dseg)[2];
659 * Close a MPW session.
662 * Pointer to TX queue structure.
664 * Pointer to MPW session structure.
667 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
669 unsigned int num = mpw->pkts_n;
672 * Store size in multiple of 16 bytes. Control and Ethernet segments
675 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
676 mpw->state = MLX5_MPW_STATE_CLOSED;
681 tx_prefetch_wqe(txq, txq->wqe_ci);
682 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
686 * DPDK callback for TX with MPW support.
689 * Generic pointer to TX queue structure.
691 * Packets to transmit.
693 * Number of packets in array.
696 * Number of packets successfully transmitted (<= pkts_n).
699 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
701 struct txq *txq = (struct txq *)dpdk_txq;
702 uint16_t elts_head = txq->elts_head;
703 const unsigned int elts_n = 1 << txq->elts_n;
708 struct mlx5_mpw mpw = {
709 .state = MLX5_MPW_STATE_CLOSED,
712 if (unlikely(!pkts_n))
714 /* Prefetch first packet cacheline. */
715 tx_prefetch_cqe(txq, txq->cq_ci);
716 tx_prefetch_wqe(txq, txq->wqe_ci);
717 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
718 /* Start processing. */
720 max = (elts_n - (elts_head - txq->elts_tail));
724 struct rte_mbuf *buf = *(pkts++);
725 unsigned int elts_head_next;
727 unsigned int segs_n = buf->nb_segs;
728 uint32_t cs_flags = 0;
731 * Make sure there is enough room to store this packet and
732 * that one ring entry remains unused.
735 if (max < segs_n + 1)
737 /* Do not bother with large packets MPW cannot handle. */
738 if (segs_n > MLX5_MPW_DSEG_MAX)
742 /* Should we enable HW CKSUM offload */
744 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
745 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
746 /* Retrieve packet information. */
747 length = PKT_LEN(buf);
749 /* Start new session if packet differs. */
750 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
751 ((mpw.len != length) ||
753 (mpw.wqe->eseg.cs_flags != cs_flags)))
754 mlx5_mpw_close(txq, &mpw);
755 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
756 mlx5_mpw_new(txq, &mpw, length);
757 mpw.wqe->eseg.cs_flags = cs_flags;
759 /* Multi-segment packets must be alone in their MPW. */
760 assert((segs_n == 1) || (mpw.pkts_n == 0));
761 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
765 volatile struct mlx5_wqe_data_seg *dseg;
768 elts_head_next = (elts_head + 1) & (elts_n - 1);
770 (*txq->elts)[elts_head] = buf;
771 dseg = mpw.data.dseg[mpw.pkts_n];
772 addr = rte_pktmbuf_mtod(buf, uintptr_t);
773 *dseg = (struct mlx5_wqe_data_seg){
774 .byte_count = htonl(DATA_LEN(buf)),
775 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
776 .addr = htonll(addr),
778 elts_head = elts_head_next;
779 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
780 length += DATA_LEN(buf);
786 assert(length == mpw.len);
787 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
788 mlx5_mpw_close(txq, &mpw);
789 elts_head = elts_head_next;
790 #ifdef MLX5_PMD_SOFT_COUNTERS
791 /* Increment sent bytes counter. */
792 txq->stats.obytes += length;
796 /* Take a shortcut if nothing must be sent. */
797 if (unlikely(i == 0))
799 /* Check whether completion threshold has been reached. */
800 /* "j" includes both packets and segments. */
801 comp = txq->elts_comp + j;
802 if (comp >= MLX5_TX_COMP_THRESH) {
803 volatile struct mlx5_wqe *wqe = mpw.wqe;
805 /* Request completion on last WQE. */
806 wqe->ctrl[2] = htonl(8);
807 /* Save elts_head in unused "immediate" field of WQE. */
808 wqe->ctrl[3] = elts_head;
811 txq->elts_comp = comp;
813 #ifdef MLX5_PMD_SOFT_COUNTERS
814 /* Increment sent packets counter. */
815 txq->stats.opackets += i;
817 /* Ring QP doorbell. */
818 if (mpw.state == MLX5_MPW_STATE_OPENED)
819 mlx5_mpw_close(txq, &mpw);
820 mlx5_tx_dbrec(txq, mpw.wqe);
821 txq->elts_head = elts_head;
826 * Open a MPW inline session.
829 * Pointer to TX queue structure.
831 * Pointer to MPW session structure.
836 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
838 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
839 struct mlx5_wqe_inl_small *inl;
841 mpw->state = MLX5_MPW_INL_STATE_OPENED;
845 mpw->wqe = (volatile struct mlx5_wqe *)&(*txq->wqes)[idx].hdr;
846 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
849 mpw->wqe->ctrl[2] = 0;
850 mpw->wqe->ctrl[3] = 0;
851 mpw->wqe->eseg.mss = htons(length);
852 mpw->wqe->eseg.inline_hdr_sz = 0;
853 mpw->wqe->eseg.cs_flags = 0;
854 mpw->wqe->eseg.rsvd0 = 0;
855 mpw->wqe->eseg.rsvd1 = 0;
856 mpw->wqe->eseg.rsvd2 = 0;
857 inl = (struct mlx5_wqe_inl_small *)
858 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
859 mpw->data.raw = (uint8_t *)&inl->raw;
863 * Close a MPW inline session.
866 * Pointer to TX queue structure.
868 * Pointer to MPW session structure.
871 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
874 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
875 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
877 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
879 * Store size in multiple of 16 bytes. Control and Ethernet segments
882 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
883 mpw->state = MLX5_MPW_STATE_CLOSED;
884 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
885 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
889 * DPDK callback for TX with MPW inline support.
892 * Generic pointer to TX queue structure.
894 * Packets to transmit.
896 * Number of packets in array.
899 * Number of packets successfully transmitted (<= pkts_n).
902 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
905 struct txq *txq = (struct txq *)dpdk_txq;
906 uint16_t elts_head = txq->elts_head;
907 const unsigned int elts_n = 1 << txq->elts_n;
912 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
913 struct mlx5_mpw mpw = {
914 .state = MLX5_MPW_STATE_CLOSED,
917 if (unlikely(!pkts_n))
919 /* Prefetch first packet cacheline. */
920 tx_prefetch_cqe(txq, txq->cq_ci);
921 tx_prefetch_wqe(txq, txq->wqe_ci);
922 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
923 /* Start processing. */
925 max = (elts_n - (elts_head - txq->elts_tail));
929 struct rte_mbuf *buf = *(pkts++);
930 unsigned int elts_head_next;
933 unsigned int segs_n = buf->nb_segs;
934 uint32_t cs_flags = 0;
937 * Make sure there is enough room to store this packet and
938 * that one ring entry remains unused.
941 if (max < segs_n + 1)
943 /* Do not bother with large packets MPW cannot handle. */
944 if (segs_n > MLX5_MPW_DSEG_MAX)
948 /* Should we enable HW CKSUM offload */
950 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
951 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
952 /* Retrieve packet information. */
953 length = PKT_LEN(buf);
954 /* Start new session if packet differs. */
955 if (mpw.state == MLX5_MPW_STATE_OPENED) {
956 if ((mpw.len != length) ||
958 (mpw.wqe->eseg.cs_flags != cs_flags))
959 mlx5_mpw_close(txq, &mpw);
960 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
961 if ((mpw.len != length) ||
963 (length > inline_room) ||
964 (mpw.wqe->eseg.cs_flags != cs_flags)) {
965 mlx5_mpw_inline_close(txq, &mpw);
967 txq->max_inline * RTE_CACHE_LINE_SIZE;
970 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
972 (length > inline_room)) {
973 mlx5_mpw_new(txq, &mpw, length);
974 mpw.wqe->eseg.cs_flags = cs_flags;
976 mlx5_mpw_inline_new(txq, &mpw, length);
977 mpw.wqe->eseg.cs_flags = cs_flags;
980 /* Multi-segment packets must be alone in their MPW. */
981 assert((segs_n == 1) || (mpw.pkts_n == 0));
982 if (mpw.state == MLX5_MPW_STATE_OPENED) {
983 assert(inline_room ==
984 txq->max_inline * RTE_CACHE_LINE_SIZE);
985 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
989 volatile struct mlx5_wqe_data_seg *dseg;
992 (elts_head + 1) & (elts_n - 1);
994 (*txq->elts)[elts_head] = buf;
995 dseg = mpw.data.dseg[mpw.pkts_n];
996 addr = rte_pktmbuf_mtod(buf, uintptr_t);
997 *dseg = (struct mlx5_wqe_data_seg){
998 .byte_count = htonl(DATA_LEN(buf)),
999 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1000 .addr = htonll(addr),
1002 elts_head = elts_head_next;
1003 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1004 length += DATA_LEN(buf);
1010 assert(length == mpw.len);
1011 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1012 mlx5_mpw_close(txq, &mpw);
1016 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1017 assert(length <= inline_room);
1018 assert(length == DATA_LEN(buf));
1019 elts_head_next = (elts_head + 1) & (elts_n - 1);
1020 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1021 (*txq->elts)[elts_head] = buf;
1022 /* Maximum number of bytes before wrapping. */
1023 max = ((uintptr_t)&(*txq->wqes)[1 << txq->wqe_n] -
1024 (uintptr_t)mpw.data.raw);
1026 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1030 (volatile void *)&(*txq->wqes)[0];
1031 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1032 (void *)(addr + max),
1034 mpw.data.raw += length - max;
1036 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1039 mpw.data.raw += length;
1041 if ((uintptr_t)mpw.data.raw ==
1042 (uintptr_t)&(*txq->wqes)[1 << txq->wqe_n])
1044 (volatile void *)&(*txq->wqes)[0];
1046 mpw.total_len += length;
1048 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1049 mlx5_mpw_inline_close(txq, &mpw);
1051 txq->max_inline * RTE_CACHE_LINE_SIZE;
1053 inline_room -= length;
1056 elts_head = elts_head_next;
1057 #ifdef MLX5_PMD_SOFT_COUNTERS
1058 /* Increment sent bytes counter. */
1059 txq->stats.obytes += length;
1063 /* Take a shortcut if nothing must be sent. */
1064 if (unlikely(i == 0))
1066 /* Check whether completion threshold has been reached. */
1067 /* "j" includes both packets and segments. */
1068 comp = txq->elts_comp + j;
1069 if (comp >= MLX5_TX_COMP_THRESH) {
1070 volatile struct mlx5_wqe *wqe = mpw.wqe;
1072 /* Request completion on last WQE. */
1073 wqe->ctrl[2] = htonl(8);
1074 /* Save elts_head in unused "immediate" field of WQE. */
1075 wqe->ctrl[3] = elts_head;
1078 txq->elts_comp = comp;
1080 #ifdef MLX5_PMD_SOFT_COUNTERS
1081 /* Increment sent packets counter. */
1082 txq->stats.opackets += i;
1084 /* Ring QP doorbell. */
1085 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1086 mlx5_mpw_inline_close(txq, &mpw);
1087 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1088 mlx5_mpw_close(txq, &mpw);
1089 mlx5_tx_dbrec(txq, mpw.wqe);
1090 txq->elts_head = elts_head;
1095 * Translate RX completion flags to packet type.
1100 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1103 * Packet type for struct rte_mbuf.
1105 static inline uint32_t
1106 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1109 uint16_t flags = ntohs(cqe->hdr_type_etc);
1111 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1114 MLX5_CQE_RX_IPV4_PACKET,
1115 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1117 MLX5_CQE_RX_IPV6_PACKET,
1118 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1119 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1120 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1121 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1125 MLX5_CQE_L3_HDR_TYPE_IPV6,
1126 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1128 MLX5_CQE_L3_HDR_TYPE_IPV4,
1129 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1135 * Get size of the next packet for a given CQE. For compressed CQEs, the
1136 * consumer index is updated only once all packets of the current one have
1140 * Pointer to RX queue.
1143 * @param[out] rss_hash
1144 * Packet RSS Hash result.
1147 * Packet size in bytes (0 if there is none), -1 in case of completion
1151 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1152 uint16_t cqe_cnt, uint32_t *rss_hash)
1154 struct rxq_zip *zip = &rxq->zip;
1155 uint16_t cqe_n = cqe_cnt + 1;
1158 /* Process compressed data in the CQE and mini arrays. */
1160 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1161 (volatile struct mlx5_mini_cqe8 (*)[8])
1162 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1164 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1165 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1166 if ((++zip->ai & 7) == 0) {
1168 * Increment consumer index to skip the number of
1169 * CQEs consumed. Hardware leaves holes in the CQ
1170 * ring for software use.
1175 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1176 uint16_t idx = rxq->cq_ci;
1177 uint16_t end = zip->cq_ci;
1179 while (idx != end) {
1180 (*rxq->cqes)[idx & cqe_cnt].op_own =
1181 MLX5_CQE_INVALIDATE;
1184 rxq->cq_ci = zip->cq_ci;
1187 /* No compressed data, get next CQE and verify if it is compressed. */
1192 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1193 if (unlikely(ret == 1))
1196 op_own = cqe->op_own;
1197 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1198 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1199 (volatile struct mlx5_mini_cqe8 (*)[8])
1200 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1203 /* Fix endianness. */
1204 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1206 * Current mini array position is the one returned by
1209 * If completion comprises several mini arrays, as a
1210 * special case the second one is located 7 CQEs after
1211 * the initial CQE instead of 8 for subsequent ones.
1213 zip->ca = rxq->cq_ci & cqe_cnt;
1214 zip->na = zip->ca + 7;
1215 /* Compute the next non compressed CQE. */
1217 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1218 /* Get packet size to return. */
1219 len = ntohl((*mc)[0].byte_cnt);
1220 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1223 len = ntohl(cqe->byte_cnt);
1224 *rss_hash = ntohl(cqe->rx_hash_res);
1226 /* Error while receiving packet. */
1227 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1234 * Translate RX completion flags to offload flags.
1237 * Pointer to RX queue structure.
1242 * Offload flags (ol_flags) for struct rte_mbuf.
1244 static inline uint32_t
1245 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1247 uint32_t ol_flags = 0;
1248 uint16_t flags = ntohs(cqe->hdr_type_etc);
1252 MLX5_CQE_RX_L3_HDR_VALID,
1253 PKT_RX_IP_CKSUM_GOOD) |
1255 MLX5_CQE_RX_L4_HDR_VALID,
1256 PKT_RX_L4_CKSUM_GOOD);
1257 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1260 MLX5_CQE_RX_L3_HDR_VALID,
1261 PKT_RX_IP_CKSUM_GOOD) |
1263 MLX5_CQE_RX_L4_HDR_VALID,
1264 PKT_RX_L4_CKSUM_GOOD);
1269 * DPDK callback for RX.
1272 * Generic pointer to RX queue structure.
1274 * Array to store received packets.
1276 * Maximum number of packets in array.
1279 * Number of packets successfully received (<= pkts_n).
1282 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1284 struct rxq *rxq = dpdk_rxq;
1285 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1286 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1287 const unsigned int sges_n = rxq->sges_n;
1288 struct rte_mbuf *pkt = NULL;
1289 struct rte_mbuf *seg = NULL;
1290 volatile struct mlx5_cqe *cqe =
1291 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1293 unsigned int rq_ci = rxq->rq_ci << sges_n;
1294 int len = 0; /* keep its value across iterations. */
1297 unsigned int idx = rq_ci & wqe_cnt;
1298 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1299 struct rte_mbuf *rep = (*rxq->elts)[idx];
1300 uint32_t rss_hash_res = 0;
1308 rep = rte_mbuf_raw_alloc(rxq->mp);
1309 if (unlikely(rep == NULL)) {
1310 ++rxq->stats.rx_nombuf;
1313 * no buffers before we even started,
1314 * bail out silently.
1318 while (pkt != seg) {
1319 assert(pkt != (*rxq->elts)[idx]);
1321 rte_mbuf_refcnt_set(pkt, 0);
1322 __rte_mbuf_raw_free(pkt);
1328 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1329 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1332 rte_mbuf_refcnt_set(rep, 0);
1333 __rte_mbuf_raw_free(rep);
1336 if (unlikely(len == -1)) {
1337 /* RX error, packet is likely too large. */
1338 rte_mbuf_refcnt_set(rep, 0);
1339 __rte_mbuf_raw_free(rep);
1340 ++rxq->stats.idropped;
1344 assert(len >= (rxq->crc_present << 2));
1345 /* Update packet information. */
1346 pkt->packet_type = 0;
1348 if (rss_hash_res && rxq->rss_hash) {
1349 pkt->hash.rss = rss_hash_res;
1350 pkt->ol_flags = PKT_RX_RSS_HASH;
1352 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1356 rxq_cq_to_pkt_type(cqe);
1358 rxq_cq_to_ol_flags(rxq, cqe);
1360 if (ntohs(cqe->hdr_type_etc) &
1361 MLX5_CQE_VLAN_STRIPPED) {
1362 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1363 PKT_RX_VLAN_STRIPPED;
1364 pkt->vlan_tci = ntohs(cqe->vlan_info);
1366 if (rxq->crc_present)
1367 len -= ETHER_CRC_LEN;
1371 DATA_LEN(rep) = DATA_LEN(seg);
1372 PKT_LEN(rep) = PKT_LEN(seg);
1373 SET_DATA_OFF(rep, DATA_OFF(seg));
1374 NB_SEGS(rep) = NB_SEGS(seg);
1375 PORT(rep) = PORT(seg);
1377 (*rxq->elts)[idx] = rep;
1379 * Fill NIC descriptor with the new buffer. The lkey and size
1380 * of the buffers are already known, only the buffer address
1383 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1384 if (len > DATA_LEN(seg)) {
1385 len -= DATA_LEN(seg);
1390 DATA_LEN(seg) = len;
1391 #ifdef MLX5_PMD_SOFT_COUNTERS
1392 /* Increment bytes counter. */
1393 rxq->stats.ibytes += PKT_LEN(pkt);
1395 /* Return packet. */
1401 /* Align consumer index to the next stride. */
1406 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1408 /* Update the consumer index. */
1409 rxq->rq_ci = rq_ci >> sges_n;
1411 *rxq->cq_db = htonl(rxq->cq_ci);
1413 *rxq->rq_db = htonl(rxq->rq_ci);
1414 #ifdef MLX5_PMD_SOFT_COUNTERS
1415 /* Increment packets counter. */
1416 rxq->stats.ipackets += i;
1422 * Dummy DPDK callback for TX.
1424 * This function is used to temporarily replace the real callback during
1425 * unsafe control operations on the queue, or in case of error.
1428 * Generic pointer to TX queue structure.
1430 * Packets to transmit.
1432 * Number of packets in array.
1435 * Number of packets successfully transmitted (<= pkts_n).
1438 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1447 * Dummy DPDK callback for RX.
1449 * This function is used to temporarily replace the real callback during
1450 * unsafe control operations on the queue, or in case of error.
1453 * Generic pointer to RX queue structure.
1455 * Array to store received packets.
1457 * Maximum number of packets in array.
1460 * Number of packets successfully received (<= pkts_n).
1463 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)