4 * Copyright 2017 6WIND S.A.
5 * Copyright 2017 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef RTE_PMD_MLX5_RXTX_VEC_SSE_H_
35 #define RTE_PMD_MLX5_RXTX_VEC_SSE_H_
41 #include <smmintrin.h>
44 #include <rte_mempool.h>
45 #include <rte_prefetch.h>
48 #include "mlx5_utils.h"
49 #include "mlx5_rxtx.h"
50 #include "mlx5_rxtx_vec.h"
51 #include "mlx5_autoconf.h"
52 #include "mlx5_defs.h"
55 #ifndef __INTEL_COMPILER
56 #pragma GCC diagnostic ignored "-Wcast-qual"
60 * Fill in buffer descriptors in a multi-packet send descriptor.
63 * Pointer to TX queue structure.
65 * Pointer to buffer descriptor to be written.
67 * Pointer to array of packets to be sent.
69 * Number of packets to be filled.
72 txq_wr_dseg_v(struct mlx5_txq_data *txq, __m128i *dseg,
73 struct rte_mbuf **pkts, unsigned int n)
77 const __m128i shuf_mask_dseg =
78 _mm_set_epi8(8, 9, 10, 11, /* addr, bswap64 */
80 7, 6, 5, 4, /* lkey */
81 0, 1, 2, 3 /* length, bswap32 */);
82 #ifdef MLX5_PMD_SOFT_COUNTERS
86 for (pos = 0; pos < n; ++pos, ++dseg) {
88 struct rte_mbuf *pkt = pkts[pos];
90 addr = rte_pktmbuf_mtod(pkt, uintptr_t);
91 desc = _mm_set_epi32(addr >> 32,
93 mlx5_tx_mb2mr(txq, pkt),
95 desc = _mm_shuffle_epi8(desc, shuf_mask_dseg);
96 _mm_store_si128(dseg, desc);
97 #ifdef MLX5_PMD_SOFT_COUNTERS
98 tx_byte += DATA_LEN(pkt);
101 #ifdef MLX5_PMD_SOFT_COUNTERS
102 txq->stats.obytes += tx_byte;
107 * Send multi-segmented packets until it encounters a single segment packet in
111 * Pointer to TX queue structure.
113 * Pointer to array of packets to be sent.
115 * Number of packets to be sent.
118 * Number of packets successfully transmitted (<= pkts_n).
121 txq_scatter_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
124 uint16_t elts_head = txq->elts_head;
125 const uint16_t elts_n = 1 << txq->elts_n;
126 const uint16_t elts_m = elts_n - 1;
127 const uint16_t wq_n = 1 << txq->wqe_n;
128 const uint16_t wq_mask = wq_n - 1;
129 const unsigned int nb_dword_per_wqebb =
130 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
131 const unsigned int nb_dword_in_hdr =
132 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
134 volatile struct mlx5_wqe *wqe = NULL;
136 assert(elts_n > pkts_n);
137 mlx5_tx_complete(txq);
138 if (unlikely(!pkts_n))
140 for (n = 0; n < pkts_n; ++n) {
141 struct rte_mbuf *buf = pkts[n];
142 unsigned int segs_n = buf->nb_segs;
143 unsigned int ds = nb_dword_in_hdr;
144 unsigned int len = PKT_LEN(buf);
145 uint16_t wqe_ci = txq->wqe_ci;
146 const __m128i shuf_mask_ctrl =
147 _mm_set_epi8(15, 14, 13, 12,
148 8, 9, 10, 11, /* bswap32 */
149 4, 5, 6, 7, /* bswap32 */
150 0, 1, 2, 3 /* bswap32 */);
154 __m128i *t_wqe, *dseg;
158 max_elts = elts_n - (elts_head - txq->elts_tail);
159 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi);
161 * A MPW session consumes 2 WQEs at most to
162 * include MLX5_MPW_DSEG_MAX pointers.
165 max_elts < segs_n || max_wqe < 2)
167 if (segs_n > MLX5_MPW_DSEG_MAX) {
168 txq->stats.oerrors++;
171 wqe = &((volatile struct mlx5_wqe64 *)
172 txq->wqes)[wqe_ci & wq_mask].hdr;
173 cs_flags = txq_ol_cksum_to_cs(txq, buf);
174 /* Title WQEBB pointer. */
175 t_wqe = (__m128i *)wqe;
176 dseg = (__m128i *)(wqe + 1);
178 if (!(ds++ % nb_dword_per_wqebb)) {
180 &((volatile struct mlx5_wqe64 *)
181 txq->wqes)[++wqe_ci & wq_mask];
183 txq_wr_dseg_v(txq, dseg++, &buf, 1);
184 (*txq->elts)[elts_head++ & elts_m] = buf;
188 /* Fill CTRL in the header. */
189 ctrl = _mm_set_epi32(0, 0, txq->qp_num_8s | ds,
190 MLX5_OPC_MOD_MPW << 24 |
191 txq->wqe_ci << 8 | MLX5_OPCODE_TSO);
192 ctrl = _mm_shuffle_epi8(ctrl, shuf_mask_ctrl);
193 _mm_store_si128(t_wqe, ctrl);
194 /* Fill ESEG in the header. */
195 _mm_store_si128(t_wqe + 1,
196 _mm_set_epi16(0, 0, 0, 0,
197 rte_cpu_to_be_16(len), cs_flags,
199 txq->wqe_ci = wqe_ci;
203 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head);
204 txq->elts_head = elts_head;
205 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) {
206 /* A CQE slot must always be available. */
207 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
208 wqe->ctrl[2] = rte_cpu_to_be_32(8);
209 wqe->ctrl[3] = txq->elts_head;
212 #ifdef MLX5_PMD_SOFT_COUNTERS
213 txq->stats.opackets += n;
215 mlx5_tx_dbrec(txq, wqe);
220 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet,
221 * it returns to make it processed by txq_scatter_v(). All the packets in
222 * the pkts list should be single segment packets having same offload flags.
223 * This must be checked by txq_check_multiseg() and txq_calc_offload().
226 * Pointer to TX queue structure.
228 * Pointer to array of packets to be sent.
230 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST).
232 * Checksum offload flags to be written in the descriptor.
235 * Number of packets successfully transmitted (<= pkts_n).
237 static inline uint16_t
238 txq_burst_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
241 struct rte_mbuf **elts;
242 uint16_t elts_head = txq->elts_head;
243 const uint16_t elts_n = 1 << txq->elts_n;
244 const uint16_t elts_m = elts_n - 1;
245 const unsigned int nb_dword_per_wqebb =
246 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
247 const unsigned int nb_dword_in_hdr =
248 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
253 uint32_t comp_req = 0;
254 const uint16_t wq_n = 1 << txq->wqe_n;
255 const uint16_t wq_mask = wq_n - 1;
256 uint16_t wq_idx = txq->wqe_ci & wq_mask;
257 volatile struct mlx5_wqe64 *wq =
258 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx];
259 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq;
260 const __m128i shuf_mask_ctrl =
261 _mm_set_epi8(15, 14, 13, 12,
262 8, 9, 10, 11, /* bswap32 */
263 4, 5, 6, 7, /* bswap32 */
264 0, 1, 2, 3 /* bswap32 */);
265 __m128i *t_wqe, *dseg;
268 /* Make sure all packets can fit into a single WQE. */
269 assert(elts_n > pkts_n);
270 mlx5_tx_complete(txq);
271 max_elts = (elts_n - (elts_head - txq->elts_tail));
272 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
273 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts);
274 assert(pkts_n <= MLX5_DSEG_MAX - nb_dword_in_hdr);
275 if (unlikely(!pkts_n))
277 elts = &(*txq->elts)[elts_head & elts_m];
278 /* Loop for available tailroom first. */
279 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n);
280 for (pos = 0; pos < (n & -2); pos += 2)
281 _mm_storeu_si128((__m128i *)&elts[pos],
282 _mm_loadu_si128((__m128i *)&pkts[pos]));
284 elts[pos] = pkts[pos];
285 /* Check if it crosses the end of the queue. */
286 if (unlikely(n < pkts_n)) {
287 elts = &(*txq->elts)[0];
288 for (pos = 0; pos < pkts_n - n; ++pos)
289 elts[pos] = pkts[n + pos];
291 txq->elts_head += pkts_n;
292 /* Save title WQEBB pointer. */
293 t_wqe = (__m128i *)wqe;
294 dseg = (__m128i *)(wqe + 1);
295 /* Calculate the number of entries to the end. */
297 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr,
300 txq_wr_dseg_v(txq, dseg, pkts, n);
301 /* Check if it crosses the end of the queue. */
303 dseg = (__m128i *)txq->wqes;
304 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n);
306 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) {
307 txq->elts_comp += pkts_n;
309 /* A CQE slot must always be available. */
310 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
311 /* Request a completion. */
315 /* Fill CTRL in the header. */
316 ctrl = _mm_set_epi32(txq->elts_head, comp_req,
317 txq->qp_num_8s | (pkts_n + 2),
318 MLX5_OPC_MOD_ENHANCED_MPSW << 24 |
319 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW);
320 ctrl = _mm_shuffle_epi8(ctrl, shuf_mask_ctrl);
321 _mm_store_si128(t_wqe, ctrl);
322 /* Fill ESEG in the header. */
323 _mm_store_si128(t_wqe + 1,
324 _mm_set_epi8(0, 0, 0, 0,
328 #ifdef MLX5_PMD_SOFT_COUNTERS
329 txq->stats.opackets += pkts_n;
331 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) /
333 /* Ring QP doorbell. */
334 mlx5_tx_dbrec_cond_wmb(txq, wqe, pkts_n < MLX5_VPMD_TX_MAX_BURST);
339 * Store free buffers to RX SW ring.
342 * Pointer to RX queue structure.
344 * Pointer to array of packets to be stored.
346 * Number of packets to be stored.
349 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n)
351 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
352 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
356 for (pos = 0; pos < p; pos += 2) {
359 mbp = _mm_loadu_si128((__m128i *)&elts[pos]);
360 _mm_storeu_si128((__m128i *)&pkts[pos], mbp);
363 pkts[pos] = elts[pos];
367 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
368 * extracted from the title completion descriptor.
371 * Pointer to RX queue structure.
373 * Pointer to completion array having a compressed completion at first.
375 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
376 * the title completion descriptor to be copied to the rest of mbufs.
379 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
380 struct rte_mbuf **elts)
382 volatile struct mlx5_mini_cqe8 *mcq = (void *)(cq + 1);
383 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
386 unsigned int inv = 0;
387 /* Mask to shuffle from extracted mini CQE to mbuf. */
388 const __m128i shuf_mask1 =
389 _mm_set_epi8(0, 1, 2, 3, /* rss, bswap32 */
390 -1, -1, /* skip vlan_tci */
391 6, 7, /* data_len, bswap16 */
392 -1, -1, 6, 7, /* pkt_len, bswap16 */
393 -1, -1, -1, -1 /* skip packet_type */);
394 const __m128i shuf_mask2 =
395 _mm_set_epi8(8, 9, 10, 11, /* rss, bswap32 */
396 -1, -1, /* skip vlan_tci */
397 14, 15, /* data_len, bswap16 */
398 -1, -1, 14, 15, /* pkt_len, bswap16 */
399 -1, -1, -1, -1 /* skip packet_type */);
400 /* Restore the compressed count. Must be 16 bits. */
401 const uint16_t mcqe_n = t_pkt->data_len +
402 (rxq->crc_present * ETHER_CRC_LEN);
403 const __m128i rearm =
404 _mm_loadu_si128((__m128i *)&t_pkt->rearm_data);
406 _mm_loadu_si128((__m128i *)&t_pkt->rx_descriptor_fields1);
407 const __m128i crc_adj =
408 _mm_set_epi16(0, 0, 0,
409 rxq->crc_present * ETHER_CRC_LEN,
411 rxq->crc_present * ETHER_CRC_LEN,
413 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
414 #ifdef MLX5_PMD_SOFT_COUNTERS
415 const __m128i zero = _mm_setzero_si128();
416 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
417 uint32_t rcvd_byte = 0;
418 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
419 const __m128i len_shuf_mask =
420 _mm_set_epi8(-1, -1, -1, -1,
427 * A. load mCQEs into a 128bit register.
428 * B. store rearm data to mbuf.
429 * C. combine data from mCQEs with rx_descriptor_fields1.
430 * D. store rx_descriptor_fields1.
431 * E. store flow tag (rte_flow mark).
433 for (pos = 0; pos < mcqe_n; ) {
434 __m128i mcqe1, mcqe2;
435 __m128i rxdf1, rxdf2;
436 #ifdef MLX5_PMD_SOFT_COUNTERS
437 __m128i byte_cnt, invalid_mask;
440 if (!(pos & 0x7) && pos + 8 < mcqe_n)
441 rte_prefetch0((void *)(cq + pos + 8));
442 /* A.1 load mCQEs into a 128bit register. */
443 mcqe1 = _mm_loadu_si128((__m128i *)&mcq[pos % 8]);
444 mcqe2 = _mm_loadu_si128((__m128i *)&mcq[pos % 8 + 2]);
445 /* B.1 store rearm data to mbuf. */
446 _mm_storeu_si128((__m128i *)&elts[pos]->rearm_data, rearm);
447 _mm_storeu_si128((__m128i *)&elts[pos + 1]->rearm_data, rearm);
448 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
449 rxdf1 = _mm_shuffle_epi8(mcqe1, shuf_mask1);
450 rxdf2 = _mm_shuffle_epi8(mcqe1, shuf_mask2);
451 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
452 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
453 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
454 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
455 /* D.1 store rx_descriptor_fields1. */
456 _mm_storeu_si128((__m128i *)
457 &elts[pos]->rx_descriptor_fields1,
459 _mm_storeu_si128((__m128i *)
460 &elts[pos + 1]->rx_descriptor_fields1,
462 /* B.1 store rearm data to mbuf. */
463 _mm_storeu_si128((__m128i *)&elts[pos + 2]->rearm_data, rearm);
464 _mm_storeu_si128((__m128i *)&elts[pos + 3]->rearm_data, rearm);
465 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
466 rxdf1 = _mm_shuffle_epi8(mcqe2, shuf_mask1);
467 rxdf2 = _mm_shuffle_epi8(mcqe2, shuf_mask2);
468 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
469 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
470 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
471 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
472 /* D.1 store rx_descriptor_fields1. */
473 _mm_storeu_si128((__m128i *)
474 &elts[pos + 2]->rx_descriptor_fields1,
476 _mm_storeu_si128((__m128i *)
477 &elts[pos + 3]->rx_descriptor_fields1,
479 #ifdef MLX5_PMD_SOFT_COUNTERS
480 invalid_mask = _mm_set_epi64x(0,
482 sizeof(uint16_t) * 8);
483 invalid_mask = _mm_sll_epi64(ones, invalid_mask);
484 mcqe1 = _mm_srli_si128(mcqe1, 4);
485 byte_cnt = _mm_blend_epi16(mcqe1, mcqe2, 0xcc);
486 byte_cnt = _mm_shuffle_epi8(byte_cnt, len_shuf_mask);
487 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
488 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
489 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
492 /* E.1 store flow tag (rte_flow mark). */
493 elts[pos]->hash.fdir.hi = flow_tag;
494 elts[pos + 1]->hash.fdir.hi = flow_tag;
495 elts[pos + 2]->hash.fdir.hi = flow_tag;
496 elts[pos + 3]->hash.fdir.hi = flow_tag;
498 pos += MLX5_VPMD_DESCS_PER_LOOP;
499 /* Move to next CQE and invalidate consumed CQEs. */
500 if (!(pos & 0x7) && pos < mcqe_n) {
501 mcq = (void *)(cq + pos);
502 for (i = 0; i < 8; ++i)
503 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
506 /* Invalidate the rest of CQEs. */
507 for (; inv < mcqe_n; ++inv)
508 cq[inv].op_own = MLX5_CQE_INVALIDATE;
509 #ifdef MLX5_PMD_SOFT_COUNTERS
510 rxq->stats.ipackets += mcqe_n;
511 rxq->stats.ibytes += rcvd_byte;
513 rxq->cq_ci += mcqe_n;
517 * Calculate packet type and offload flag for mbuf and store it.
520 * Pointer to RX queue structure.
522 * Array of four 16bytes completions extracted from the original completion
525 * Opcode vector having responder error status. Each field is 4B.
527 * Pointer to array of packets to be filled.
530 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq, __m128i cqes[4],
531 __m128i op_err, struct rte_mbuf **pkts)
533 __m128i pinfo0, pinfo1;
534 __m128i pinfo, ptype;
535 __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH |
536 rxq->hw_timestamp * PKT_RX_TIMESTAMP);
538 const __m128i zero = _mm_setzero_si128();
539 const __m128i ptype_mask =
540 _mm_set_epi32(0xfd06, 0xfd06, 0xfd06, 0xfd06);
541 const __m128i ptype_ol_mask =
542 _mm_set_epi32(0x106, 0x106, 0x106, 0x106);
543 const __m128i pinfo_mask =
544 _mm_set_epi32(0x3, 0x3, 0x3, 0x3);
545 const __m128i cv_flag_sel =
546 _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
547 (uint8_t)((PKT_RX_IP_CKSUM_GOOD |
548 PKT_RX_L4_CKSUM_GOOD) >> 1),
550 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
552 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
553 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED),
555 const __m128i cv_mask =
556 _mm_set_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
557 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
558 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
559 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
560 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
561 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
562 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
563 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
564 const __m128i mbuf_init =
565 _mm_loadl_epi64((__m128i *)&rxq->mbuf_initializer);
566 __m128i rearm0, rearm1, rearm2, rearm3;
568 /* Extract pkt_info field. */
569 pinfo0 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
570 pinfo1 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
571 pinfo = _mm_unpacklo_epi64(pinfo0, pinfo1);
572 /* Extract hdr_type_etc field. */
573 pinfo0 = _mm_unpackhi_epi32(cqes[0], cqes[1]);
574 pinfo1 = _mm_unpackhi_epi32(cqes[2], cqes[3]);
575 ptype = _mm_unpacklo_epi64(pinfo0, pinfo1);
577 const __m128i pinfo_ft_mask =
578 _mm_set_epi32(0xffffff00, 0xffffff00,
579 0xffffff00, 0xffffff00);
580 const __m128i fdir_flags = _mm_set1_epi32(PKT_RX_FDIR);
581 __m128i fdir_id_flags = _mm_set1_epi32(PKT_RX_FDIR_ID);
582 __m128i flow_tag, invalid_mask;
584 flow_tag = _mm_and_si128(pinfo, pinfo_ft_mask);
585 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
586 invalid_mask = _mm_cmpeq_epi32(flow_tag, zero);
587 ol_flags = _mm_or_si128(ol_flags,
588 _mm_andnot_si128(invalid_mask,
590 /* Mask out invalid entries. */
591 fdir_id_flags = _mm_andnot_si128(invalid_mask, fdir_id_flags);
592 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
593 ol_flags = _mm_or_si128(ol_flags,
595 _mm_cmpeq_epi32(flow_tag,
600 * Merge the two fields to generate the following:
604 * bit[11:10] = l3_hdr_type
605 * bit[14:12] = l4_hdr_type
608 * bit[17] = outer_l3_type
610 ptype = _mm_and_si128(ptype, ptype_mask);
611 pinfo = _mm_and_si128(pinfo, pinfo_mask);
612 pinfo = _mm_slli_epi32(pinfo, 16);
613 /* Make pinfo has merged fields for ol_flags calculation. */
614 pinfo = _mm_or_si128(ptype, pinfo);
615 ptype = _mm_srli_epi32(pinfo, 10);
616 ptype = _mm_packs_epi32(ptype, zero);
617 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
618 op_err = _mm_srli_epi16(op_err, 8);
619 ptype = _mm_or_si128(ptype, op_err);
620 pkts[0]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 0)];
621 pkts[1]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 2)];
622 pkts[2]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 4)];
623 pkts[3]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 6)];
624 /* Fill flags for checksum and VLAN. */
625 pinfo = _mm_and_si128(pinfo, ptype_ol_mask);
626 pinfo = _mm_shuffle_epi8(cv_flag_sel, pinfo);
627 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
628 cv_flags = _mm_slli_epi32(pinfo, 9);
629 cv_flags = _mm_or_si128(pinfo, cv_flags);
630 /* Move back flags to start from byte[0]. */
631 cv_flags = _mm_srli_epi32(cv_flags, 8);
632 /* Mask out garbage bits. */
633 cv_flags = _mm_and_si128(cv_flags, cv_mask);
634 /* Merge to ol_flags. */
635 ol_flags = _mm_or_si128(ol_flags, cv_flags);
636 /* Merge mbuf_init and ol_flags. */
637 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 8), 0x30);
638 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 4), 0x30);
639 rearm2 = _mm_blend_epi16(mbuf_init, ol_flags, 0x30);
640 rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(ol_flags, 4), 0x30);
641 /* Write 8B rearm_data and 8B ol_flags. */
642 _mm_store_si128((__m128i *)&pkts[0]->rearm_data, rearm0);
643 _mm_store_si128((__m128i *)&pkts[1]->rearm_data, rearm1);
644 _mm_store_si128((__m128i *)&pkts[2]->rearm_data, rearm2);
645 _mm_store_si128((__m128i *)&pkts[3]->rearm_data, rearm3);
649 * Receive burst of packets. An errored completion also consumes a mbuf, but the
650 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
651 * before returning to application.
654 * Pointer to RX queue structure.
656 * Array to store received packets.
658 * Maximum number of packets in array.
660 * Pointer to a flag. Set non-zero value if pkts array has at least one error
664 * Number of packets received including errors (<= pkts_n).
666 static inline uint16_t
667 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,
670 const uint16_t q_n = 1 << rxq->cqe_n;
671 const uint16_t q_mask = q_n - 1;
672 volatile struct mlx5_cqe *cq;
673 struct rte_mbuf **elts;
677 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
678 uint16_t nocmp_n = 0;
679 uint16_t rcvd_pkt = 0;
680 unsigned int cq_idx = rxq->cq_ci & q_mask;
681 unsigned int elts_idx;
682 unsigned int ownership = !!(rxq->cq_ci & (q_mask + 1));
683 const __m128i owner_check =
684 _mm_set_epi64x(0x0100000001000000LL, 0x0100000001000000LL);
685 const __m128i opcode_check =
686 _mm_set_epi64x(0xf0000000f0000000LL, 0xf0000000f0000000LL);
687 const __m128i format_check =
688 _mm_set_epi64x(0x0c0000000c000000LL, 0x0c0000000c000000LL);
689 const __m128i resp_err_check =
690 _mm_set_epi64x(0xe0000000e0000000LL, 0xe0000000e0000000LL);
691 #ifdef MLX5_PMD_SOFT_COUNTERS
692 uint32_t rcvd_byte = 0;
693 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
694 const __m128i len_shuf_mask =
695 _mm_set_epi8(-1, -1, -1, -1,
700 /* Mask to shuffle from extracted CQE to mbuf. */
701 const __m128i shuf_mask =
702 _mm_set_epi8(-1, 3, 2, 1, /* fdir.hi */
703 12, 13, 14, 15, /* rss, bswap32 */
704 10, 11, /* vlan_tci, bswap16 */
705 4, 5, /* data_len, bswap16 */
706 -1, -1, /* zero out 2nd half of pkt_len */
707 4, 5 /* pkt_len, bswap16 */);
708 /* Mask to blend from the last Qword to the first DQword. */
709 const __m128i blend_mask =
710 _mm_set_epi8(-1, -1, -1, -1,
714 const __m128i zero = _mm_setzero_si128();
715 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
716 const __m128i crc_adj =
717 _mm_set_epi16(0, 0, 0, 0, 0,
718 rxq->crc_present * ETHER_CRC_LEN,
720 rxq->crc_present * ETHER_CRC_LEN);
721 const __m128i flow_mark_adj = _mm_set_epi32(rxq->mark * (-1), 0, 0, 0);
723 assert(rxq->sges_n == 0);
724 assert(rxq->cqe_n == rxq->elts_n);
725 cq = &(*rxq->cqes)[cq_idx];
727 rte_prefetch0(cq + 1);
728 rte_prefetch0(cq + 2);
729 rte_prefetch0(cq + 3);
730 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
733 * rq_ci >= cq_ci >= rq_pi
734 * Definition of indexes:
735 * rq_ci - cq_ci := # of buffers owned by HW (posted).
736 * cq_ci - rq_pi := # of buffers not returned to app (decompressed).
737 * N - (rq_ci - rq_pi) := # of buffers consumed (to be replenished).
739 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
740 if (repl_n >= MLX5_VPMD_RXQ_RPLNSH_THRESH(q_n))
741 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n);
742 /* See if there're unreturned mbufs from compressed CQE. */
743 rcvd_pkt = rxq->cq_ci - rxq->rq_pi;
745 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
746 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
747 rxq->rq_pi += rcvd_pkt;
750 elts_idx = rxq->rq_pi & q_mask;
751 elts = &(*rxq->elts)[elts_idx];
752 /* Not to overflow pkts array. */
753 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
754 /* Not to cross queue end. */
755 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
758 /* At this point, there shouldn't be any remained packets. */
759 assert(rxq->rq_pi == rxq->cq_ci);
761 * A. load first Qword (8bytes) in one loop.
762 * B. copy 4 mbuf pointers from elts ring to returing pkts.
763 * C. load remained CQE data and extract necessary fields.
764 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
765 * following structure:
768 * uint8_t flow_tag[3];
772 * uint16_t hdr_type_etc;
773 * uint16_t vlan_info;
774 * uint32_t rx_has_res;
778 * F. find compressed CQE.
782 pos += MLX5_VPMD_DESCS_PER_LOOP) {
783 __m128i cqes[MLX5_VPMD_DESCS_PER_LOOP];
784 __m128i cqe_tmp1, cqe_tmp2;
785 __m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3;
786 __m128i op_own, op_own_tmp1, op_own_tmp2;
787 __m128i opcode, owner_mask, invalid_mask;
790 #ifdef MLX5_PMD_SOFT_COUNTERS
794 __m128i p = _mm_set_epi16(0, 0, 0, 0, 3, 2, 1, 0);
795 unsigned int p1, p2, p3;
797 /* Prefetch next 4 CQEs. */
798 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
799 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP]);
800 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 1]);
801 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 2]);
802 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 3]);
804 /* A.0 do not cross the end of CQ. */
805 mask = _mm_set_epi64x(0, (pkts_n - pos) * sizeof(uint16_t) * 8);
806 mask = _mm_sll_epi64(ones, mask);
807 p = _mm_andnot_si128(mask, p);
809 p3 = _mm_extract_epi16(p, 3);
810 cqes[3] = _mm_loadl_epi64((__m128i *)
811 &cq[pos + p3].sop_drop_qpn);
812 rte_compiler_barrier();
813 p2 = _mm_extract_epi16(p, 2);
814 cqes[2] = _mm_loadl_epi64((__m128i *)
815 &cq[pos + p2].sop_drop_qpn);
816 rte_compiler_barrier();
817 /* B.1 load mbuf pointers. */
818 mbp1 = _mm_loadu_si128((__m128i *)&elts[pos]);
819 mbp2 = _mm_loadu_si128((__m128i *)&elts[pos + 2]);
820 /* A.1 load a block having op_own. */
821 p1 = _mm_extract_epi16(p, 1);
822 cqes[1] = _mm_loadl_epi64((__m128i *)
823 &cq[pos + p1].sop_drop_qpn);
824 rte_compiler_barrier();
825 cqes[0] = _mm_loadl_epi64((__m128i *)
826 &cq[pos].sop_drop_qpn);
827 /* B.2 copy mbuf pointers. */
828 _mm_storeu_si128((__m128i *)&pkts[pos], mbp1);
829 _mm_storeu_si128((__m128i *)&pkts[pos + 2], mbp2);
831 /* C.1 load remained CQE data and extract necessary fields. */
832 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p3]);
833 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos + p2]);
834 cqes[3] = _mm_blendv_epi8(cqes[3], cqe_tmp2, blend_mask);
835 cqes[2] = _mm_blendv_epi8(cqes[2], cqe_tmp1, blend_mask);
836 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p3].rsvd1[3]);
837 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos + p2].rsvd1[3]);
838 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x30);
839 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x30);
840 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p3].rsvd2[10]);
841 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos + p2].rsvd2[10]);
842 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x04);
843 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x04);
844 /* C.2 generate final structure for mbuf with swapping bytes. */
845 pkt_mb3 = _mm_shuffle_epi8(cqes[3], shuf_mask);
846 pkt_mb2 = _mm_shuffle_epi8(cqes[2], shuf_mask);
847 /* C.3 adjust CRC length. */
848 pkt_mb3 = _mm_sub_epi16(pkt_mb3, crc_adj);
849 pkt_mb2 = _mm_sub_epi16(pkt_mb2, crc_adj);
850 /* C.4 adjust flow mark. */
851 pkt_mb3 = _mm_add_epi32(pkt_mb3, flow_mark_adj);
852 pkt_mb2 = _mm_add_epi32(pkt_mb2, flow_mark_adj);
853 /* D.1 fill in mbuf - rx_descriptor_fields1. */
854 _mm_storeu_si128((void *)&pkts[pos + 3]->pkt_len, pkt_mb3);
855 _mm_storeu_si128((void *)&pkts[pos + 2]->pkt_len, pkt_mb2);
856 /* E.1 extract op_own field. */
857 op_own_tmp2 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
858 /* C.1 load remained CQE data and extract necessary fields. */
859 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p1]);
860 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos]);
861 cqes[1] = _mm_blendv_epi8(cqes[1], cqe_tmp2, blend_mask);
862 cqes[0] = _mm_blendv_epi8(cqes[0], cqe_tmp1, blend_mask);
863 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p1].rsvd1[3]);
864 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos].rsvd1[3]);
865 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x30);
866 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x30);
867 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p1].rsvd2[10]);
868 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos].rsvd2[10]);
869 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x04);
870 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x04);
871 /* C.2 generate final structure for mbuf with swapping bytes. */
872 pkt_mb1 = _mm_shuffle_epi8(cqes[1], shuf_mask);
873 pkt_mb0 = _mm_shuffle_epi8(cqes[0], shuf_mask);
874 /* C.3 adjust CRC length. */
875 pkt_mb1 = _mm_sub_epi16(pkt_mb1, crc_adj);
876 pkt_mb0 = _mm_sub_epi16(pkt_mb0, crc_adj);
877 /* C.4 adjust flow mark. */
878 pkt_mb1 = _mm_add_epi32(pkt_mb1, flow_mark_adj);
879 pkt_mb0 = _mm_add_epi32(pkt_mb0, flow_mark_adj);
880 /* E.1 extract op_own byte. */
881 op_own_tmp1 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
882 op_own = _mm_unpackhi_epi64(op_own_tmp1, op_own_tmp2);
883 /* D.1 fill in mbuf - rx_descriptor_fields1. */
884 _mm_storeu_si128((void *)&pkts[pos + 1]->pkt_len, pkt_mb1);
885 _mm_storeu_si128((void *)&pkts[pos]->pkt_len, pkt_mb0);
886 /* E.2 flip owner bit to mark CQEs from last round. */
887 owner_mask = _mm_and_si128(op_own, owner_check);
889 owner_mask = _mm_xor_si128(owner_mask, owner_check);
890 owner_mask = _mm_cmpeq_epi32(owner_mask, owner_check);
891 owner_mask = _mm_packs_epi32(owner_mask, zero);
892 /* E.3 get mask for invalidated CQEs. */
893 opcode = _mm_and_si128(op_own, opcode_check);
894 invalid_mask = _mm_cmpeq_epi32(opcode_check, opcode);
895 invalid_mask = _mm_packs_epi32(invalid_mask, zero);
896 /* E.4 mask out beyond boundary. */
897 invalid_mask = _mm_or_si128(invalid_mask, mask);
898 /* E.5 merge invalid_mask with invalid owner. */
899 invalid_mask = _mm_or_si128(invalid_mask, owner_mask);
900 /* F.1 find compressed CQE format. */
901 comp_mask = _mm_and_si128(op_own, format_check);
902 comp_mask = _mm_cmpeq_epi32(comp_mask, format_check);
903 comp_mask = _mm_packs_epi32(comp_mask, zero);
904 /* F.2 mask out invalid entries. */
905 comp_mask = _mm_andnot_si128(invalid_mask, comp_mask);
906 comp_idx = _mm_cvtsi128_si64(comp_mask);
907 /* F.3 get the first compressed CQE. */
908 comp_idx = comp_idx ?
909 __builtin_ctzll(comp_idx) /
910 (sizeof(uint16_t) * 8) :
911 MLX5_VPMD_DESCS_PER_LOOP;
912 /* E.6 mask out entries after the compressed CQE. */
913 mask = _mm_set_epi64x(0, comp_idx * sizeof(uint16_t) * 8);
914 mask = _mm_sll_epi64(ones, mask);
915 invalid_mask = _mm_or_si128(invalid_mask, mask);
916 /* E.7 count non-compressed valid CQEs. */
917 n = _mm_cvtsi128_si64(invalid_mask);
918 n = n ? __builtin_ctzll(n) / (sizeof(uint16_t) * 8) :
919 MLX5_VPMD_DESCS_PER_LOOP;
921 /* D.2 get the final invalid mask. */
922 mask = _mm_set_epi64x(0, n * sizeof(uint16_t) * 8);
923 mask = _mm_sll_epi64(ones, mask);
924 invalid_mask = _mm_or_si128(invalid_mask, mask);
925 /* D.3 check error in opcode. */
926 opcode = _mm_cmpeq_epi32(resp_err_check, opcode);
927 opcode = _mm_packs_epi32(opcode, zero);
928 opcode = _mm_andnot_si128(invalid_mask, opcode);
929 /* D.4 mark if any error is set */
930 *err |= _mm_cvtsi128_si64(opcode);
931 /* D.5 fill in mbuf - rearm_data and packet_type. */
932 rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);
933 if (rxq->hw_timestamp) {
934 pkts[pos]->timestamp =
935 rte_be_to_cpu_64(cq[pos].timestamp);
936 pkts[pos + 1]->timestamp =
937 rte_be_to_cpu_64(cq[pos + p1].timestamp);
938 pkts[pos + 2]->timestamp =
939 rte_be_to_cpu_64(cq[pos + p2].timestamp);
940 pkts[pos + 3]->timestamp =
941 rte_be_to_cpu_64(cq[pos + p3].timestamp);
943 #ifdef MLX5_PMD_SOFT_COUNTERS
944 /* Add up received bytes count. */
945 byte_cnt = _mm_shuffle_epi8(op_own, len_shuf_mask);
946 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
947 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
948 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
951 * Break the loop unless more valid CQE is expected, or if
952 * there's a compressed CQE.
954 if (n != MLX5_VPMD_DESCS_PER_LOOP)
957 /* If no new CQE seen, return without updating cq_db. */
958 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
960 /* Update the consumer indexes for non-compressed CQEs. */
961 assert(nocmp_n <= pkts_n);
962 rxq->cq_ci += nocmp_n;
963 rxq->rq_pi += nocmp_n;
965 #ifdef MLX5_PMD_SOFT_COUNTERS
966 rxq->stats.ipackets += nocmp_n;
967 rxq->stats.ibytes += rcvd_byte;
969 /* Decompress the last CQE if compressed. */
970 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
971 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
972 rxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]);
973 /* Return more packets if needed. */
974 if (nocmp_n < pkts_n) {
975 uint16_t n = rxq->cq_ci - rxq->rq_pi;
977 n = RTE_MIN(n, pkts_n - nocmp_n);
978 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
983 rte_compiler_barrier();
984 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
988 #endif /* RTE_PMD_MLX5_RXTX_VEC_SSE_H_ */