4 * Copyright(c) 2017 Marvell International Ltd.
5 * Copyright(c) 2017 Semihalf.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
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20 * from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <rte_ethdev.h>
36 #include <rte_kvargs.h>
38 #include <rte_malloc.h>
39 #include <rte_bus_vdev.h>
41 /* Unluckily, container_of is defined by both DPDK and MUSDK,
42 * we'll declare only one version.
44 * Note that it is not used in this PMD anyway.
50 #include <drivers/mv_pp2.h>
51 #include <drivers/mv_pp2_bpool.h>
52 #include <drivers/mv_pp2_hif.h>
55 #include <linux/ethtool.h>
56 #include <linux/sockios.h>
58 #include <net/if_arp.h>
59 #include <sys/ioctl.h>
60 #include <sys/socket.h>
62 #include <sys/types.h>
64 #include "mrvl_ethdev.h"
67 /* bitmask with reserved hifs */
68 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
69 /* bitmask with reserved bpools */
70 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
71 /* bitmask with reserved kernel RSS tables */
72 #define MRVL_MUSDK_RSS_RESERVED 0x01
73 /* maximum number of available hifs */
74 #define MRVL_MUSDK_HIFS_MAX 9
77 #define MRVL_MUSDK_PREFETCH_SHIFT 2
79 /* TCAM has 25 entries reserved for uc/mc filter entries */
80 #define MRVL_MAC_ADDRS_MAX 25
81 #define MRVL_MATCH_LEN 16
82 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
83 /* Maximum allowable packet size */
84 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
86 #define MRVL_IFACE_NAME_ARG "iface"
87 #define MRVL_CFG_ARG "cfg"
89 #define MRVL_BURST_SIZE 64
91 #define MRVL_ARP_LENGTH 28
93 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
95 #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8)
96 #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
98 /* Memory size (in bytes) for MUSDK dma buffers */
99 #define MRVL_MUSDK_DMA_MEMSIZE 41943040
101 static const char * const valid_args[] = {
107 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
108 static struct pp2_hif *hifs[RTE_MAX_LCORE];
109 static int used_bpools[PP2_NUM_PKT_PROC] = {
110 MRVL_MUSDK_BPOOLS_RESERVED,
111 MRVL_MUSDK_BPOOLS_RESERVED
114 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
115 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
116 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
118 struct mrvl_ifnames {
119 const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
124 * To use buffer harvesting based on loopback port shadow queue structure
125 * was introduced for buffers information bookkeeping.
127 * Before sending the packet, related buffer information (pp2_buff_inf) is
128 * stored in shadow queue. After packet is transmitted no longer used
129 * packet buffer is released back to it's original hardware pool,
130 * on condition it originated from interface.
131 * In case it was generated by application itself i.e: mbuf->port field is
132 * 0xff then its released to software mempool.
134 struct mrvl_shadow_txq {
135 int head; /* write index - used when sending buffers */
136 int tail; /* read index - used when releasing buffers */
137 u16 size; /* queue occupied size */
138 u16 num_to_release; /* number of buffers sent, that can be released */
139 struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
143 struct mrvl_priv *priv;
144 struct rte_mempool *mp;
153 struct mrvl_priv *priv;
157 struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
160 static int mrvl_lcore_first;
161 static int mrvl_lcore_last;
162 static int mrvl_dev_num;
164 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
165 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
166 struct pp2_hif *hif, unsigned int core_id,
167 struct mrvl_shadow_txq *sq, int qid, int force);
170 mrvl_get_bpool_size(int pp2_id, int pool_id)
175 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
176 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
182 mrvl_reserve_bit(int *bitmap, int max)
184 int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
195 mrvl_init_hif(int core_id)
197 struct pp2_hif_params params;
198 char match[MRVL_MATCH_LEN];
201 ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
203 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
207 snprintf(match, sizeof(match), "hif-%d", ret);
208 memset(¶ms, 0, sizeof(params));
209 params.match = match;
210 params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
211 ret = pp2_hif_init(¶ms, &hifs[core_id]);
213 RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", core_id);
220 static inline struct pp2_hif*
221 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
225 if (likely(hifs[core_id] != NULL))
226 return hifs[core_id];
228 rte_spinlock_lock(&priv->lock);
230 ret = mrvl_init_hif(core_id);
232 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
236 if (core_id < mrvl_lcore_first)
237 mrvl_lcore_first = core_id;
239 if (core_id > mrvl_lcore_last)
240 mrvl_lcore_last = core_id;
242 rte_spinlock_unlock(&priv->lock);
244 return hifs[core_id];
248 * Configure rss based on dpdk rss configuration.
251 * Pointer to private structure.
253 * Pointer to RSS configuration.
256 * 0 on success, negative error value otherwise.
259 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
261 if (rss_conf->rss_key)
262 RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
264 if (rss_conf->rss_hf == 0) {
265 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
266 } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
267 priv->ppio_params.inqs_params.hash_type =
268 PP2_PPIO_HASH_T_2_TUPLE;
269 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
270 priv->ppio_params.inqs_params.hash_type =
271 PP2_PPIO_HASH_T_5_TUPLE;
272 priv->rss_hf_tcp = 1;
273 } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
274 priv->ppio_params.inqs_params.hash_type =
275 PP2_PPIO_HASH_T_5_TUPLE;
276 priv->rss_hf_tcp = 0;
285 * Ethernet device configuration.
287 * Prepare the driver for a given number of TX and RX queues and
291 * Pointer to Ethernet device structure.
294 * 0 on success, negative error value otherwise.
297 mrvl_dev_configure(struct rte_eth_dev *dev)
299 struct mrvl_priv *priv = dev->data->dev_private;
302 if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
303 dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
304 RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
305 dev->data->dev_conf.rxmode.mq_mode);
309 if (!dev->data->dev_conf.rxmode.hw_strip_crc) {
311 "L2 CRC stripping is always enabled in hw\n");
312 dev->data->dev_conf.rxmode.hw_strip_crc = 1;
315 if (dev->data->dev_conf.rxmode.hw_vlan_strip) {
316 RTE_LOG(INFO, PMD, "VLAN stripping not supported\n");
320 if (dev->data->dev_conf.rxmode.split_hdr_size) {
321 RTE_LOG(INFO, PMD, "Split headers not supported\n");
325 if (dev->data->dev_conf.rxmode.enable_scatter) {
326 RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n");
330 if (dev->data->dev_conf.rxmode.enable_lro) {
331 RTE_LOG(INFO, PMD, "LRO not supported\n");
335 if (dev->data->dev_conf.rxmode.jumbo_frame)
336 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
337 ETHER_HDR_LEN - ETHER_CRC_LEN;
339 ret = mrvl_configure_rxqs(priv, dev->data->port_id,
340 dev->data->nb_rx_queues);
344 priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
345 priv->ppio_params.maintain_stats = 1;
346 priv->nb_rx_queues = dev->data->nb_rx_queues;
348 if (dev->data->nb_rx_queues == 1 &&
349 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
350 RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
351 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
356 return mrvl_configure_rss(priv,
357 &dev->data->dev_conf.rx_adv_conf.rss_conf);
361 * DPDK callback to change the MTU.
363 * Setting the MTU affects hardware MRU (packets larger than the MRU
367 * Pointer to Ethernet device structure.
372 * 0 on success, negative error value otherwise.
375 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
377 struct mrvl_priv *priv = dev->data->dev_private;
378 /* extra MV_MH_SIZE bytes are required for Marvell tag */
379 uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
382 if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
385 ret = pp2_ppio_set_mru(priv->ppio, mru);
389 return pp2_ppio_set_mtu(priv->ppio, mtu);
393 * DPDK callback to bring the link up.
396 * Pointer to Ethernet device structure.
399 * 0 on success, negative error value otherwise.
402 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
404 struct mrvl_priv *priv = dev->data->dev_private;
407 ret = pp2_ppio_enable(priv->ppio);
412 * mtu/mru can be updated if pp2_ppio_enable() was called at least once
413 * as pp2_ppio_enable() changes port->t_mode from default 0 to
414 * PP2_TRAFFIC_INGRESS_EGRESS.
416 * Set mtu to default DPDK value here.
418 ret = mrvl_mtu_set(dev, dev->data->mtu);
420 pp2_ppio_disable(priv->ppio);
422 dev->data->dev_link.link_status = ETH_LINK_UP;
428 * DPDK callback to bring the link down.
431 * Pointer to Ethernet device structure.
434 * 0 on success, negative error value otherwise.
437 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
439 struct mrvl_priv *priv = dev->data->dev_private;
442 ret = pp2_ppio_disable(priv->ppio);
446 dev->data->dev_link.link_status = ETH_LINK_DOWN;
452 * DPDK callback to start the device.
455 * Pointer to Ethernet device structure.
458 * 0 on success, negative errno value on failure.
461 mrvl_dev_start(struct rte_eth_dev *dev)
463 struct mrvl_priv *priv = dev->data->dev_private;
464 char match[MRVL_MATCH_LEN];
465 int ret = 0, def_init_size;
467 snprintf(match, sizeof(match), "ppio-%d:%d",
468 priv->pp_id, priv->ppio_id);
469 priv->ppio_params.match = match;
472 * Calculate the minimum bpool size for refill feature as follows:
473 * 2 default burst sizes multiply by number of rx queues.
474 * If the bpool size will be below this value, new buffers will
475 * be added to the pool.
477 priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
479 /* In case initial bpool size configured in queues setup is
480 * smaller than minimum size add more buffers
482 def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
483 if (priv->bpool_init_size < def_init_size) {
484 int buffs_to_add = def_init_size - priv->bpool_init_size;
486 priv->bpool_init_size += buffs_to_add;
487 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
489 RTE_LOG(ERR, PMD, "Failed to add buffers to bpool\n");
493 * Calculate the maximum bpool size for refill feature as follows:
494 * maximum number of descriptors in rx queue multiply by number
495 * of rx queues plus minimum bpool size.
496 * In case the bpool size will exceed this value, superfluous buffers
499 priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
500 priv->bpool_min_size;
502 ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
507 * In case there are some some stale uc/mc mac addresses flush them
508 * here. It cannot be done during mrvl_dev_close() as port information
509 * is already gone at that point (due to pp2_ppio_deinit() in
512 if (!priv->uc_mc_flushed) {
513 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
516 "Failed to flush uc/mc filter list\n");
519 priv->uc_mc_flushed = 1;
522 if (!priv->vlan_flushed) {
523 ret = pp2_ppio_flush_vlan(priv->ppio);
525 RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
528 * once pp2_ppio_flush_vlan() is supported jump to out
532 priv->vlan_flushed = 1;
535 /* For default QoS config, don't start classifier. */
537 ret = mrvl_start_qos_mapping(priv);
539 pp2_ppio_deinit(priv->ppio);
544 ret = mrvl_dev_set_link_up(dev);
550 pp2_ppio_deinit(priv->ppio);
555 * Flush receive queues.
558 * Pointer to Ethernet device structure.
561 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
565 RTE_LOG(INFO, PMD, "Flushing rx queues\n");
566 for (i = 0; i < dev->data->nb_rx_queues; i++) {
570 struct mrvl_rxq *q = dev->data->rx_queues[i];
571 struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
573 num = MRVL_PP2_RXD_MAX;
574 ret = pp2_ppio_recv(q->priv->ppio,
575 q->priv->rxq_map[q->queue_id].tc,
576 q->priv->rxq_map[q->queue_id].inq,
577 descs, (uint16_t *)&num);
578 } while (ret == 0 && num);
583 * Flush transmit shadow queues.
586 * Pointer to Ethernet device structure.
589 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
592 struct mrvl_txq *txq;
594 RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
595 for (i = 0; i < dev->data->nb_tx_queues; i++) {
596 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
598 for (j = 0; j < RTE_MAX_LCORE; j++) {
599 struct mrvl_shadow_txq *sq;
604 sq = &txq->shadow_txqs[j];
605 mrvl_free_sent_buffers(txq->priv->ppio,
606 hifs[j], j, sq, txq->queue_id, 1);
607 while (sq->tail != sq->head) {
608 uint64_t addr = cookie_addr_high |
609 sq->ent[sq->tail].buff.cookie;
611 (struct rte_mbuf *)addr);
612 sq->tail = (sq->tail + 1) &
613 MRVL_PP2_TX_SHADOWQ_MASK;
615 memset(sq, 0, sizeof(*sq));
621 * Flush hardware bpool (buffer-pool).
624 * Pointer to Ethernet device structure.
627 mrvl_flush_bpool(struct rte_eth_dev *dev)
629 struct mrvl_priv *priv = dev->data->dev_private;
633 unsigned int core_id = rte_lcore_id();
635 if (core_id == LCORE_ID_ANY)
638 hif = mrvl_get_hif(priv, core_id);
640 ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
642 RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
647 struct pp2_buff_inf inf;
650 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
654 addr = cookie_addr_high | inf.cookie;
655 rte_pktmbuf_free((struct rte_mbuf *)addr);
660 * DPDK callback to stop the device.
663 * Pointer to Ethernet device structure.
666 mrvl_dev_stop(struct rte_eth_dev *dev)
668 struct mrvl_priv *priv = dev->data->dev_private;
670 mrvl_dev_set_link_down(dev);
671 mrvl_flush_rx_queues(dev);
672 mrvl_flush_tx_shadow_queues(dev);
674 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
675 priv->qos_tbl = NULL;
678 pp2_ppio_deinit(priv->ppio);
683 * DPDK callback to close the device.
686 * Pointer to Ethernet device structure.
689 mrvl_dev_close(struct rte_eth_dev *dev)
691 struct mrvl_priv *priv = dev->data->dev_private;
694 for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
695 struct pp2_ppio_tc_params *tc_params =
696 &priv->ppio_params.inqs_params.tcs_params[i];
698 if (tc_params->inqs_params) {
699 rte_free(tc_params->inqs_params);
700 tc_params->inqs_params = NULL;
704 mrvl_flush_bpool(dev);
708 * DPDK callback to retrieve physical link information.
711 * Pointer to Ethernet device structure.
712 * @param wait_to_complete
713 * Wait for request completion (ignored).
716 * 0 on success, negative error value otherwise.
719 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
723 * once MUSDK provides necessary API use it here
725 struct ethtool_cmd edata;
729 edata.cmd = ETHTOOL_GSET;
731 strcpy(req.ifr_name, dev->data->name);
732 req.ifr_data = (void *)&edata;
734 fd = socket(AF_INET, SOCK_DGRAM, 0);
738 ret = ioctl(fd, SIOCETHTOOL, &req);
746 switch (ethtool_cmd_speed(&edata)) {
748 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
751 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
754 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
757 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
760 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
763 dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
764 ETH_LINK_HALF_DUPLEX;
765 dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
772 * DPDK callback to enable promiscuous mode.
775 * Pointer to Ethernet device structure.
778 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
780 struct mrvl_priv *priv = dev->data->dev_private;
783 ret = pp2_ppio_set_uc_promisc(priv->ppio, 1);
785 RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
789 * DPDK callback to enable allmulti mode.
792 * Pointer to Ethernet device structure.
795 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
797 struct mrvl_priv *priv = dev->data->dev_private;
800 ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
802 RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
806 * DPDK callback to disable promiscuous mode.
809 * Pointer to Ethernet device structure.
812 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
814 struct mrvl_priv *priv = dev->data->dev_private;
817 ret = pp2_ppio_set_uc_promisc(priv->ppio, 0);
819 RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
823 * DPDK callback to disable allmulticast mode.
826 * Pointer to Ethernet device structure.
829 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
831 struct mrvl_priv *priv = dev->data->dev_private;
834 ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
836 RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
840 * DPDK callback to remove a MAC address.
843 * Pointer to Ethernet device structure.
848 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
850 struct mrvl_priv *priv = dev->data->dev_private;
851 char buf[ETHER_ADDR_FMT_SIZE];
854 ret = pp2_ppio_remove_mac_addr(priv->ppio,
855 dev->data->mac_addrs[index].addr_bytes);
857 ether_format_addr(buf, sizeof(buf),
858 &dev->data->mac_addrs[index]);
859 RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
864 * DPDK callback to add a MAC address.
867 * Pointer to Ethernet device structure.
869 * MAC address to register.
873 * VMDq pool index to associate address with (unused).
876 * 0 on success, negative error value otherwise.
879 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
880 uint32_t index, uint32_t vmdq __rte_unused)
882 struct mrvl_priv *priv = dev->data->dev_private;
883 char buf[ETHER_ADDR_FMT_SIZE];
887 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
891 * Maximum number of uc addresses can be tuned via kernel module mvpp2x
892 * parameter uc_filter_max. Maximum number of mc addresses is then
893 * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
896 * If more than uc_filter_max uc addresses were added to filter list
897 * then NIC will switch to promiscuous mode automatically.
899 * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
900 * were added to filter list then NIC will switch to all-multicast mode
903 ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
905 ether_format_addr(buf, sizeof(buf), mac_addr);
906 RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
914 * DPDK callback to set the primary MAC address.
917 * Pointer to Ethernet device structure.
919 * MAC address to register.
922 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
924 struct mrvl_priv *priv = dev->data->dev_private;
926 pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
929 * Port stops sending packets if pp2_ppio_set_mac_addr()
930 * was called after pp2_ppio_enable(). As a quick fix issue
931 * enable port once again.
933 pp2_ppio_enable(priv->ppio);
937 * DPDK callback to get device statistics.
940 * Pointer to Ethernet device structure.
942 * Stats structure output buffer.
945 * 0 on success, negative error value otherwise.
948 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
950 struct mrvl_priv *priv = dev->data->dev_private;
951 struct pp2_ppio_statistics ppio_stats;
952 uint64_t drop_mac = 0;
953 unsigned int i, idx, ret;
955 for (i = 0; i < dev->data->nb_rx_queues; i++) {
956 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
957 struct pp2_ppio_inq_statistics rx_stats;
963 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
965 "rx queue %d stats out of range (0 - %d)\n",
966 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
970 ret = pp2_ppio_inq_get_statistics(priv->ppio,
971 priv->rxq_map[idx].tc,
972 priv->rxq_map[idx].inq,
976 "Failed to update rx queue %d stats\n", idx);
980 stats->q_ibytes[idx] = rxq->bytes_recv;
981 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
982 stats->q_errors[idx] = rx_stats.drop_early +
983 rx_stats.drop_fullq +
986 stats->ibytes += rxq->bytes_recv;
987 drop_mac += rxq->drop_mac;
990 for (i = 0; i < dev->data->nb_tx_queues; i++) {
991 struct mrvl_txq *txq = dev->data->tx_queues[i];
992 struct pp2_ppio_outq_statistics tx_stats;
998 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1000 "tx queue %d stats out of range (0 - %d)\n",
1001 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1004 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1006 if (unlikely(ret)) {
1008 "Failed to update tx queue %d stats\n", idx);
1012 stats->q_opackets[idx] = tx_stats.deq_desc;
1013 stats->q_obytes[idx] = txq->bytes_sent;
1014 stats->obytes += txq->bytes_sent;
1017 ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1018 if (unlikely(ret)) {
1019 RTE_LOG(ERR, PMD, "Failed to update port statistics\n");
1023 stats->ipackets += ppio_stats.rx_packets - drop_mac;
1024 stats->opackets += ppio_stats.tx_packets;
1025 stats->imissed += ppio_stats.rx_fullq_dropped +
1026 ppio_stats.rx_bm_dropped +
1027 ppio_stats.rx_early_dropped +
1028 ppio_stats.rx_fifo_dropped +
1029 ppio_stats.rx_cls_dropped;
1030 stats->ierrors = drop_mac;
1036 * DPDK callback to clear device statistics.
1039 * Pointer to Ethernet device structure.
1042 mrvl_stats_reset(struct rte_eth_dev *dev)
1044 struct mrvl_priv *priv = dev->data->dev_private;
1047 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1048 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1050 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1051 priv->rxq_map[i].inq, NULL, 1);
1052 rxq->bytes_recv = 0;
1056 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1057 struct mrvl_txq *txq = dev->data->tx_queues[i];
1059 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1060 txq->bytes_sent = 0;
1063 pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1067 * DPDK callback to get information about the device.
1070 * Pointer to Ethernet device structure (unused).
1072 * Info structure output buffer.
1075 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1076 struct rte_eth_dev_info *info)
1078 info->speed_capa = ETH_LINK_SPEED_10M |
1079 ETH_LINK_SPEED_100M |
1083 info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1084 info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1085 info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1087 info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1088 info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1089 info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1091 info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1092 info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1093 info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1095 info->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME |
1096 DEV_RX_OFFLOAD_VLAN_FILTER |
1097 DEV_RX_OFFLOAD_IPV4_CKSUM |
1098 DEV_RX_OFFLOAD_UDP_CKSUM |
1099 DEV_RX_OFFLOAD_TCP_CKSUM;
1101 info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
1102 DEV_TX_OFFLOAD_UDP_CKSUM |
1103 DEV_TX_OFFLOAD_TCP_CKSUM;
1105 info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1106 ETH_RSS_NONFRAG_IPV4_TCP |
1107 ETH_RSS_NONFRAG_IPV4_UDP;
1109 /* By default packets are dropped if no descriptors are available */
1110 info->default_rxconf.rx_drop_en = 1;
1112 info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1116 * Return supported packet types.
1119 * Pointer to Ethernet device structure (unused).
1122 * Const pointer to the table with supported packet types.
1124 static const uint32_t *
1125 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1127 static const uint32_t ptypes[] = {
1130 RTE_PTYPE_L3_IPV4_EXT,
1131 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1133 RTE_PTYPE_L3_IPV6_EXT,
1134 RTE_PTYPE_L2_ETHER_ARP,
1143 * DPDK callback to get information about specific receive queue.
1146 * Pointer to Ethernet device structure.
1147 * @param rx_queue_id
1148 * Receive queue index.
1150 * Receive queue information structure.
1152 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1153 struct rte_eth_rxq_info *qinfo)
1155 struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1156 struct mrvl_priv *priv = dev->data->dev_private;
1157 int inq = priv->rxq_map[rx_queue_id].inq;
1158 int tc = priv->rxq_map[rx_queue_id].tc;
1159 struct pp2_ppio_tc_params *tc_params =
1160 &priv->ppio_params.inqs_params.tcs_params[tc];
1163 qinfo->nb_desc = tc_params->inqs_params[inq].size;
1167 * DPDK callback to get information about specific transmit queue.
1170 * Pointer to Ethernet device structure.
1171 * @param tx_queue_id
1172 * Transmit queue index.
1174 * Transmit queue information structure.
1176 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1177 struct rte_eth_txq_info *qinfo)
1179 struct mrvl_priv *priv = dev->data->dev_private;
1182 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1186 * DPDK callback to Configure a VLAN filter.
1189 * Pointer to Ethernet device structure.
1191 * VLAN ID to filter.
1196 * 0 on success, negative error value otherwise.
1199 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1201 struct mrvl_priv *priv = dev->data->dev_private;
1203 return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1204 pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1208 * Release buffers to hardware bpool (buffer-pool)
1211 * Receive queue pointer.
1213 * Number of buffers to release to bpool.
1216 * 0 on success, negative error value otherwise.
1219 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1221 struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
1222 struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
1224 unsigned int core_id;
1225 struct pp2_hif *hif;
1226 struct pp2_bpool *bpool;
1228 core_id = rte_lcore_id();
1229 if (core_id == LCORE_ID_ANY)
1232 hif = mrvl_get_hif(rxq->priv, core_id);
1236 bpool = rxq->priv->bpool;
1238 ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1242 if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1244 (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1246 for (i = 0; i < num; i++) {
1247 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1248 != cookie_addr_high) {
1250 "mbuf virtual addr high 0x%lx out of range\n",
1251 (uint64_t)mbufs[i] >> 32);
1255 entries[i].buff.addr =
1256 rte_mbuf_data_iova_default(mbufs[i]);
1257 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1258 entries[i].bpool = bpool;
1261 pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1262 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1269 for (; i < num; i++)
1270 rte_pktmbuf_free(mbufs[i]);
1276 * DPDK callback to configure the receive queue.
1279 * Pointer to Ethernet device structure.
1283 * Number of descriptors to configure in queue.
1285 * NUMA socket on which memory must be allocated.
1287 * Thresholds parameters (unused_).
1289 * Memory pool for buffer allocations.
1292 * 0 on success, negative error value otherwise.
1295 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1296 unsigned int socket,
1297 const struct rte_eth_rxconf *conf __rte_unused,
1298 struct rte_mempool *mp)
1300 struct mrvl_priv *priv = dev->data->dev_private;
1301 struct mrvl_rxq *rxq;
1303 max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1306 if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1308 * Unknown TC mapping, mapping will not have a correct queue.
1310 RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
1311 idx, priv->ppio_id);
1315 min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1316 MRVL_PKT_EFFEC_OFFS;
1317 if (min_size < max_rx_pkt_len) {
1319 "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
1320 max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1321 MRVL_PKT_EFFEC_OFFS,
1326 if (dev->data->rx_queues[idx]) {
1327 rte_free(dev->data->rx_queues[idx]);
1328 dev->data->rx_queues[idx] = NULL;
1331 rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1337 rxq->cksum_enabled = dev->data->dev_conf.rxmode.hw_ip_checksum;
1338 rxq->queue_id = idx;
1339 rxq->port_id = dev->data->port_id;
1340 mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1342 tc = priv->rxq_map[rxq->queue_id].tc,
1343 inq = priv->rxq_map[rxq->queue_id].inq;
1344 priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1347 ret = mrvl_fill_bpool(rxq, desc);
1353 priv->bpool_init_size += desc;
1355 dev->data->rx_queues[idx] = rxq;
1361 * DPDK callback to release the receive queue.
1364 * Generic receive queue pointer.
1367 mrvl_rx_queue_release(void *rxq)
1369 struct mrvl_rxq *q = rxq;
1370 struct pp2_ppio_tc_params *tc_params;
1371 int i, num, tc, inq;
1372 struct pp2_hif *hif;
1373 unsigned int core_id = rte_lcore_id();
1375 if (core_id == LCORE_ID_ANY)
1381 hif = mrvl_get_hif(q->priv, core_id);
1386 tc = q->priv->rxq_map[q->queue_id].tc;
1387 inq = q->priv->rxq_map[q->queue_id].inq;
1388 tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1389 num = tc_params->inqs_params[inq].size;
1390 for (i = 0; i < num; i++) {
1391 struct pp2_buff_inf inf;
1394 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1395 addr = cookie_addr_high | inf.cookie;
1396 rte_pktmbuf_free((struct rte_mbuf *)addr);
1403 * DPDK callback to configure the transmit queue.
1406 * Pointer to Ethernet device structure.
1408 * Transmit queue index.
1410 * Number of descriptors to configure in the queue.
1412 * NUMA socket on which memory must be allocated.
1414 * Thresholds parameters (unused).
1417 * 0 on success, negative error value otherwise.
1420 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1421 unsigned int socket,
1422 const struct rte_eth_txconf *conf __rte_unused)
1424 struct mrvl_priv *priv = dev->data->dev_private;
1425 struct mrvl_txq *txq;
1427 if (dev->data->tx_queues[idx]) {
1428 rte_free(dev->data->tx_queues[idx]);
1429 dev->data->tx_queues[idx] = NULL;
1432 txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1437 txq->queue_id = idx;
1438 txq->port_id = dev->data->port_id;
1439 dev->data->tx_queues[idx] = txq;
1441 priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1442 priv->ppio_params.outqs_params.outqs_params[idx].weight = 1;
1448 * DPDK callback to release the transmit queue.
1451 * Generic transmit queue pointer.
1454 mrvl_tx_queue_release(void *txq)
1456 struct mrvl_txq *q = txq;
1465 * Update RSS hash configuration
1468 * Pointer to Ethernet device structure.
1470 * Pointer to RSS configuration.
1473 * 0 on success, negative error value otherwise.
1476 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1477 struct rte_eth_rss_conf *rss_conf)
1479 struct mrvl_priv *priv = dev->data->dev_private;
1481 return mrvl_configure_rss(priv, rss_conf);
1485 * DPDK callback to get RSS hash configuration.
1488 * Pointer to Ethernet device structure.
1490 * Pointer to RSS configuration.
1496 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1497 struct rte_eth_rss_conf *rss_conf)
1499 struct mrvl_priv *priv = dev->data->dev_private;
1500 enum pp2_ppio_hash_type hash_type =
1501 priv->ppio_params.inqs_params.hash_type;
1503 rss_conf->rss_key = NULL;
1505 if (hash_type == PP2_PPIO_HASH_T_NONE)
1506 rss_conf->rss_hf = 0;
1507 else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1508 rss_conf->rss_hf = ETH_RSS_IPV4;
1509 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1510 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1511 else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1512 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1517 static const struct eth_dev_ops mrvl_ops = {
1518 .dev_configure = mrvl_dev_configure,
1519 .dev_start = mrvl_dev_start,
1520 .dev_stop = mrvl_dev_stop,
1521 .dev_set_link_up = mrvl_dev_set_link_up,
1522 .dev_set_link_down = mrvl_dev_set_link_down,
1523 .dev_close = mrvl_dev_close,
1524 .link_update = mrvl_link_update,
1525 .promiscuous_enable = mrvl_promiscuous_enable,
1526 .allmulticast_enable = mrvl_allmulticast_enable,
1527 .promiscuous_disable = mrvl_promiscuous_disable,
1528 .allmulticast_disable = mrvl_allmulticast_disable,
1529 .mac_addr_remove = mrvl_mac_addr_remove,
1530 .mac_addr_add = mrvl_mac_addr_add,
1531 .mac_addr_set = mrvl_mac_addr_set,
1532 .mtu_set = mrvl_mtu_set,
1533 .stats_get = mrvl_stats_get,
1534 .stats_reset = mrvl_stats_reset,
1535 .dev_infos_get = mrvl_dev_infos_get,
1536 .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1537 .rxq_info_get = mrvl_rxq_info_get,
1538 .txq_info_get = mrvl_txq_info_get,
1539 .vlan_filter_set = mrvl_vlan_filter_set,
1540 .rx_queue_setup = mrvl_rx_queue_setup,
1541 .rx_queue_release = mrvl_rx_queue_release,
1542 .tx_queue_setup = mrvl_tx_queue_setup,
1543 .tx_queue_release = mrvl_tx_queue_release,
1544 .rss_hash_update = mrvl_rss_hash_update,
1545 .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1549 * Return packet type information and l3/l4 offsets.
1552 * Pointer to the received packet descriptor.
1559 * Packet type information.
1561 static inline uint64_t
1562 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1563 uint8_t *l3_offset, uint8_t *l4_offset)
1565 enum pp2_inq_l3_type l3_type;
1566 enum pp2_inq_l4_type l4_type;
1567 uint64_t packet_type;
1569 pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1570 pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1572 packet_type = RTE_PTYPE_L2_ETHER;
1575 case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1576 packet_type |= RTE_PTYPE_L3_IPV4;
1578 case PP2_INQ_L3_TYPE_IPV4_OK:
1579 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1581 case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1582 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1584 case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1585 packet_type |= RTE_PTYPE_L3_IPV6;
1587 case PP2_INQ_L3_TYPE_IPV6_EXT:
1588 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1590 case PP2_INQ_L3_TYPE_ARP:
1591 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1593 * In case of ARP l4_offset is set to wrong value.
1594 * Set it to proper one so that later on mbuf->l3_len can be
1595 * calculated subtracting l4_offset and l3_offset.
1597 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1600 RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n");
1605 case PP2_INQ_L4_TYPE_TCP:
1606 packet_type |= RTE_PTYPE_L4_TCP;
1608 case PP2_INQ_L4_TYPE_UDP:
1609 packet_type |= RTE_PTYPE_L4_UDP;
1612 RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n");
1620 * Get offload information from the received packet descriptor.
1623 * Pointer to the received packet descriptor.
1626 * Mbuf offload flags.
1628 static inline uint64_t
1629 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1632 enum pp2_inq_desc_status status;
1634 status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
1635 if (unlikely(status != PP2_DESC_ERR_OK))
1636 flags = PKT_RX_IP_CKSUM_BAD;
1638 flags = PKT_RX_IP_CKSUM_GOOD;
1640 status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
1641 if (unlikely(status != PP2_DESC_ERR_OK))
1642 flags |= PKT_RX_L4_CKSUM_BAD;
1644 flags |= PKT_RX_L4_CKSUM_GOOD;
1650 * DPDK callback for receive.
1653 * Generic pointer to the receive queue.
1655 * Array to store received packets.
1657 * Maximum number of packets in array.
1660 * Number of packets successfully received.
1663 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1665 struct mrvl_rxq *q = rxq;
1666 struct pp2_ppio_desc descs[nb_pkts];
1667 struct pp2_bpool *bpool;
1668 int i, ret, rx_done = 0;
1670 struct pp2_hif *hif;
1671 unsigned int core_id = rte_lcore_id();
1673 hif = mrvl_get_hif(q->priv, core_id);
1675 if (unlikely(!q->priv->ppio || !hif))
1678 bpool = q->priv->bpool;
1680 ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
1681 q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
1682 if (unlikely(ret < 0)) {
1683 RTE_LOG(ERR, PMD, "Failed to receive packets\n");
1686 mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
1688 for (i = 0; i < nb_pkts; i++) {
1689 struct rte_mbuf *mbuf;
1690 uint8_t l3_offset, l4_offset;
1691 enum pp2_inq_desc_status status;
1694 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1695 struct pp2_ppio_desc *pref_desc;
1698 pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
1699 pref_addr = cookie_addr_high |
1700 pp2_ppio_inq_desc_get_cookie(pref_desc);
1701 rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
1702 rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
1705 addr = cookie_addr_high |
1706 pp2_ppio_inq_desc_get_cookie(&descs[i]);
1707 mbuf = (struct rte_mbuf *)addr;
1708 rte_pktmbuf_reset(mbuf);
1710 /* drop packet in case of mac, overrun or resource error */
1711 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
1712 if (unlikely(status != PP2_DESC_ERR_OK)) {
1713 struct pp2_buff_inf binf = {
1714 .addr = rte_mbuf_data_iova_default(mbuf),
1715 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
1718 pp2_bpool_put_buff(hif, bpool, &binf);
1719 mrvl_port_bpool_size
1720 [bpool->pp2_id][bpool->id][core_id]++;
1725 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
1726 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
1727 mbuf->data_len = mbuf->pkt_len;
1728 mbuf->port = q->port_id;
1730 mrvl_desc_to_packet_type_and_offset(&descs[i],
1733 mbuf->l2_len = l3_offset;
1734 mbuf->l3_len = l4_offset - l3_offset;
1736 if (likely(q->cksum_enabled))
1737 mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
1739 rx_pkts[rx_done++] = mbuf;
1740 q->bytes_recv += mbuf->pkt_len;
1743 if (rte_spinlock_trylock(&q->priv->lock) == 1) {
1744 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
1746 if (unlikely(num <= q->priv->bpool_min_size ||
1747 (!rx_done && num < q->priv->bpool_init_size))) {
1748 ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
1750 RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
1751 } else if (unlikely(num > q->priv->bpool_max_size)) {
1753 int pkt_to_remove = num - q->priv->bpool_init_size;
1754 struct rte_mbuf *mbuf;
1755 struct pp2_buff_inf buff;
1758 "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
1759 bpool->pp2_id, q->priv->ppio->port_id,
1760 bpool->id, pkt_to_remove, num,
1761 q->priv->bpool_init_size);
1763 for (i = 0; i < pkt_to_remove; i++) {
1764 ret = pp2_bpool_get_buff(hif, bpool, &buff);
1767 mbuf = (struct rte_mbuf *)
1768 (cookie_addr_high | buff.cookie);
1769 rte_pktmbuf_free(mbuf);
1771 mrvl_port_bpool_size
1772 [bpool->pp2_id][bpool->id][core_id] -= i;
1774 rte_spinlock_unlock(&q->priv->lock);
1781 * Prepare offload information.
1785 * @param packet_type
1786 * Packet type bitfield.
1788 * Pointer to the pp2_ouq_l3_type structure.
1790 * Pointer to the pp2_outq_l4_type structure.
1791 * @param gen_l3_cksum
1792 * Will be set to 1 in case l3 checksum is computed.
1794 * Will be set to 1 in case l4 checksum is computed.
1797 * 0 on success, negative error value otherwise.
1800 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
1801 enum pp2_outq_l3_type *l3_type,
1802 enum pp2_outq_l4_type *l4_type,
1807 * Based on ol_flags prepare information
1808 * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
1811 if (ol_flags & PKT_TX_IPV4) {
1812 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
1813 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
1814 } else if (ol_flags & PKT_TX_IPV6) {
1815 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
1816 /* no checksum for ipv6 header */
1819 /* if something different then stop processing */
1823 ol_flags &= PKT_TX_L4_MASK;
1824 if ((packet_type & RTE_PTYPE_L4_TCP) &&
1825 ol_flags == PKT_TX_TCP_CKSUM) {
1826 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
1828 } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
1829 ol_flags == PKT_TX_UDP_CKSUM) {
1830 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
1833 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
1834 /* no checksum for other type */
1842 * Release already sent buffers to bpool (buffer-pool).
1845 * Pointer to the port structure.
1847 * Pointer to the MUSDK hardware interface.
1849 * Pointer to the shadow queue.
1853 * Force releasing packets.
1856 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
1857 unsigned int core_id, struct mrvl_shadow_txq *sq,
1860 struct buff_release_entry *entry;
1861 uint16_t nb_done = 0, num = 0, skip_bufs = 0;
1864 pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
1866 sq->num_to_release += nb_done;
1868 if (likely(!force &&
1869 sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
1872 nb_done = sq->num_to_release;
1873 sq->num_to_release = 0;
1875 for (i = 0; i < nb_done; i++) {
1876 entry = &sq->ent[sq->tail + num];
1877 if (unlikely(!entry->buff.addr)) {
1879 "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
1880 sq->tail, (u64)entry->buff.cookie,
1881 (u64)entry->buff.addr);
1886 if (unlikely(!entry->bpool)) {
1887 struct rte_mbuf *mbuf;
1889 mbuf = (struct rte_mbuf *)
1890 (cookie_addr_high | entry->buff.cookie);
1891 rte_pktmbuf_free(mbuf);
1896 mrvl_port_bpool_size
1897 [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
1899 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
1904 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1906 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1913 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1914 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1920 * DPDK callback for transmit.
1923 * Generic pointer transmit queue.
1925 * Packets to transmit.
1927 * Number of packets in array.
1930 * Number of packets successfully transmitted.
1933 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1935 struct mrvl_txq *q = txq;
1936 struct mrvl_shadow_txq *sq;
1937 struct pp2_hif *hif;
1938 struct pp2_ppio_desc descs[nb_pkts];
1939 unsigned int core_id = rte_lcore_id();
1940 int i, ret, bytes_sent = 0;
1941 uint16_t num, sq_free_size;
1944 hif = mrvl_get_hif(q->priv, core_id);
1945 sq = &q->shadow_txqs[core_id];
1947 if (unlikely(!q->priv->ppio || !hif))
1951 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
1952 sq, q->queue_id, 0);
1954 sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
1955 if (unlikely(nb_pkts > sq_free_size)) {
1957 "No room in shadow queue for %d packets! %d packets will be sent.\n",
1958 nb_pkts, sq_free_size);
1959 nb_pkts = sq_free_size;
1962 for (i = 0; i < nb_pkts; i++) {
1963 struct rte_mbuf *mbuf = tx_pkts[i];
1964 int gen_l3_cksum, gen_l4_cksum;
1965 enum pp2_outq_l3_type l3_type;
1966 enum pp2_outq_l4_type l4_type;
1968 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1969 struct rte_mbuf *pref_pkt_hdr;
1971 pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
1972 rte_mbuf_prefetch_part1(pref_pkt_hdr);
1973 rte_mbuf_prefetch_part2(pref_pkt_hdr);
1976 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
1977 sq->ent[sq->head].buff.addr =
1978 rte_mbuf_data_iova_default(mbuf);
1979 sq->ent[sq->head].bpool =
1980 (unlikely(mbuf->port == 0xff || mbuf->refcnt > 1)) ?
1981 NULL : mrvl_port_to_bpool_lookup[mbuf->port];
1982 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
1985 pp2_ppio_outq_desc_reset(&descs[i]);
1986 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
1987 rte_pktmbuf_iova(mbuf));
1988 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
1989 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
1990 rte_pktmbuf_pkt_len(mbuf));
1992 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
1994 * in case unsupported ol_flags were passed
1995 * do not update descriptor offload information
1997 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
1998 &l3_type, &l4_type, &gen_l3_cksum,
2003 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2005 mbuf->l2_len + mbuf->l3_len,
2006 gen_l3_cksum, gen_l4_cksum);
2010 pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2011 /* number of packets that were not sent */
2012 if (unlikely(num > nb_pkts)) {
2013 for (i = nb_pkts; i < num; i++) {
2014 sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2015 MRVL_PP2_TX_SHADOWQ_MASK;
2016 addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2018 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2020 sq->size -= num - nb_pkts;
2023 q->bytes_sent += bytes_sent;
2029 * Initialize packet processor.
2032 * 0 on success, negative error value otherwise.
2037 struct pp2_init_params init_params;
2039 memset(&init_params, 0, sizeof(init_params));
2040 init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2041 init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2042 init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2044 return pp2_init(&init_params);
2048 * Deinitialize packet processor.
2051 * 0 on success, negative error value otherwise.
2054 mrvl_deinit_pp2(void)
2060 * Create private device structure.
2063 * Pointer to the port name passed in the initialization parameters.
2066 * Pointer to the newly allocated private device structure.
2068 static struct mrvl_priv *
2069 mrvl_priv_create(const char *dev_name)
2071 struct pp2_bpool_params bpool_params;
2072 char match[MRVL_MATCH_LEN];
2073 struct mrvl_priv *priv;
2076 priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2080 ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2081 &priv->pp_id, &priv->ppio_id);
2085 bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2086 PP2_BPOOL_NUM_POOLS);
2089 priv->bpool_bit = bpool_bit;
2091 snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2093 memset(&bpool_params, 0, sizeof(bpool_params));
2094 bpool_params.match = match;
2095 bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2096 ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2098 goto out_clear_bpool_bit;
2100 priv->ppio_params.type = PP2_PPIO_T_NIC;
2101 rte_spinlock_init(&priv->lock);
2104 out_clear_bpool_bit:
2105 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2112 * Create device representing Ethernet port.
2115 * Pointer to the port's name.
2118 * 0 on success, negative error value otherwise.
2121 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2123 int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2124 struct rte_eth_dev *eth_dev;
2125 struct mrvl_priv *priv;
2128 eth_dev = rte_eth_dev_allocate(name);
2132 priv = mrvl_priv_create(name);
2138 eth_dev->data->mac_addrs =
2139 rte_zmalloc("mac_addrs",
2140 ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2141 if (!eth_dev->data->mac_addrs) {
2142 RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
2147 memset(&req, 0, sizeof(req));
2148 strcpy(req.ifr_name, name);
2149 ret = ioctl(fd, SIOCGIFHWADDR, &req);
2153 memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2154 req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2156 eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2157 eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2158 eth_dev->data->kdrv = RTE_KDRV_NONE;
2159 eth_dev->data->dev_private = priv;
2160 eth_dev->device = &vdev->device;
2161 eth_dev->dev_ops = &mrvl_ops;
2165 rte_free(eth_dev->data->mac_addrs);
2167 rte_eth_dev_release_port(eth_dev);
2175 * Cleanup previously created device representing Ethernet port.
2178 * Pointer to the port name.
2181 mrvl_eth_dev_destroy(const char *name)
2183 struct rte_eth_dev *eth_dev;
2184 struct mrvl_priv *priv;
2186 eth_dev = rte_eth_dev_allocated(name);
2190 priv = eth_dev->data->dev_private;
2191 pp2_bpool_deinit(priv->bpool);
2192 used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2194 rte_free(eth_dev->data->mac_addrs);
2195 rte_eth_dev_release_port(eth_dev);
2199 * Callback used by rte_kvargs_process() during argument parsing.
2202 * Pointer to the parsed key (unused).
2204 * Pointer to the parsed value.
2206 * Pointer to the extra arguments which contains address of the
2207 * table of pointers to parsed interface names.
2213 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2216 struct mrvl_ifnames *ifnames = extra_args;
2218 ifnames->names[ifnames->idx++] = value;
2224 * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2227 mrvl_deinit_hifs(void)
2231 for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2233 pp2_hif_deinit(hifs[i]);
2235 used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2236 memset(hifs, 0, sizeof(hifs));
2240 * DPDK callback to register the virtual device.
2243 * Pointer to the virtual device.
2246 * 0 on success, negative error value otherwise.
2249 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2251 struct rte_kvargs *kvlist;
2252 struct mrvl_ifnames ifnames;
2254 uint32_t i, ifnum, cfgnum;
2257 params = rte_vdev_device_args(vdev);
2261 kvlist = rte_kvargs_parse(params, valid_args);
2265 ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2266 if (ifnum > RTE_DIM(ifnames.names))
2267 goto out_free_kvlist;
2270 rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2271 mrvl_get_ifnames, &ifnames);
2275 * The below system initialization should be done only once,
2276 * on the first provided configuration file
2278 if (!mrvl_qos_cfg) {
2279 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2280 RTE_LOG(INFO, PMD, "Parsing config file!\n");
2282 RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
2283 goto out_free_kvlist;
2284 } else if (cfgnum == 1) {
2285 rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2286 mrvl_get_qoscfg, &mrvl_qos_cfg);
2293 RTE_LOG(INFO, PMD, "Perform MUSDK initializations\n");
2295 * ret == -EEXIST is correct, it means DMA
2296 * has been already initialized (by another PMD).
2298 ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
2301 goto out_free_kvlist;
2304 "DMA memory has been already initialized by a different driver.\n");
2307 ret = mrvl_init_pp2();
2309 RTE_LOG(ERR, PMD, "Failed to init PP!\n");
2310 goto out_deinit_dma;
2313 memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2315 mrvl_lcore_first = RTE_MAX_LCORE;
2316 mrvl_lcore_last = 0;
2319 for (i = 0; i < ifnum; i++) {
2320 RTE_LOG(INFO, PMD, "Creating %s\n", ifnames.names[i]);
2321 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2325 mrvl_dev_num += ifnum;
2327 rte_kvargs_free(kvlist);
2332 mrvl_eth_dev_destroy(ifnames.names[i]);
2334 if (mrvl_dev_num == 0)
2337 if (mrvl_dev_num == 0)
2338 mv_sys_dma_mem_destroy();
2340 rte_kvargs_free(kvlist);
2346 * DPDK callback to remove virtual device.
2349 * Pointer to the removed virtual device.
2352 * 0 on success, negative error value otherwise.
2355 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2360 name = rte_vdev_device_name(vdev);
2364 RTE_LOG(INFO, PMD, "Removing %s\n", name);
2366 for (i = 0; i < rte_eth_dev_count(); i++) {
2367 char ifname[RTE_ETH_NAME_MAX_LEN];
2369 rte_eth_dev_get_name_by_port(i, ifname);
2370 mrvl_eth_dev_destroy(ifname);
2374 if (mrvl_dev_num == 0) {
2375 RTE_LOG(INFO, PMD, "Perform MUSDK deinit\n");
2378 mv_sys_dma_mem_destroy();
2384 static struct rte_vdev_driver pmd_mrvl_drv = {
2385 .probe = rte_pmd_mrvl_probe,
2386 .remove = rte_pmd_mrvl_remove,
2389 RTE_PMD_REGISTER_VDEV(net_mrvl, pmd_mrvl_drv);
2390 RTE_PMD_REGISTER_ALIAS(net_mrvl, eth_mrvl);