2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
47 #include <rte_debug.h>
48 #include <rte_ethdev.h>
50 #include <rte_ether.h>
51 #include <rte_malloc.h>
52 #include <rte_memzone.h>
53 #include <rte_mempool.h>
54 #include <rte_version.h>
55 #include <rte_string_fns.h>
56 #include <rte_alarm.h>
57 #include <rte_spinlock.h>
59 #include "nfp_net_pmd.h"
60 #include "nfp_net_logs.h"
61 #include "nfp_net_ctrl.h"
64 static void nfp_net_close(struct rte_eth_dev *dev);
65 static int nfp_net_configure(struct rte_eth_dev *dev);
66 static void nfp_net_dev_interrupt_handler(struct rte_intr_handle *handle,
68 static void nfp_net_dev_interrupt_delayed_handler(void *param);
69 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
70 static void nfp_net_infos_get(struct rte_eth_dev *dev,
71 struct rte_eth_dev_info *dev_info);
72 static int nfp_net_init(struct rte_eth_dev *eth_dev);
73 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
74 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
75 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
76 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
77 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
79 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
81 static void nfp_net_rx_queue_release(void *rxq);
82 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
83 uint16_t nb_desc, unsigned int socket_id,
84 const struct rte_eth_rxconf *rx_conf,
85 struct rte_mempool *mp);
86 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
87 static void nfp_net_tx_queue_release(void *txq);
88 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
89 uint16_t nb_desc, unsigned int socket_id,
90 const struct rte_eth_txconf *tx_conf);
91 static int nfp_net_start(struct rte_eth_dev *dev);
92 static void nfp_net_stats_get(struct rte_eth_dev *dev,
93 struct rte_eth_stats *stats);
94 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
95 static void nfp_net_stop(struct rte_eth_dev *dev);
96 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
100 * The offset of the queue controller queues in the PCIe Target. These
101 * happen to be at the same offset on the NFP6000 and the NFP3200 so
102 * we use a single macro here.
104 #define NFP_PCIE_QUEUE(_q) (0x80000 + (0x800 * ((_q) & 0xff)))
106 /* Maximum value which can be added to a queue with one transaction */
107 #define NFP_QCP_MAX_ADD 0x7f
109 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
110 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
112 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
114 NFP_QCP_READ_PTR = 0,
119 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
120 * @q: Base address for queue structure
121 * @ptr: Add to the Read or Write pointer
122 * @val: Value to add to the queue pointer
124 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
127 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
131 if (ptr == NFP_QCP_READ_PTR)
132 off = NFP_QCP_QUEUE_ADD_RPTR;
134 off = NFP_QCP_QUEUE_ADD_WPTR;
136 while (val > NFP_QCP_MAX_ADD) {
137 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
138 val -= NFP_QCP_MAX_ADD;
141 nn_writel(rte_cpu_to_le_32(val), q + off);
145 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
146 * @q: Base address for queue structure
147 * @ptr: Read or Write pointer
149 static inline uint32_t
150 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
155 if (ptr == NFP_QCP_READ_PTR)
156 off = NFP_QCP_QUEUE_STS_LO;
158 off = NFP_QCP_QUEUE_STS_HI;
160 val = rte_cpu_to_le_32(nn_readl(q + off));
162 if (ptr == NFP_QCP_READ_PTR)
163 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
165 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
169 * Functions to read/write from/to Config BAR
170 * Performs any endian conversion necessary.
172 static inline uint8_t
173 nn_cfg_readb(struct nfp_net_hw *hw, int off)
175 return nn_readb(hw->ctrl_bar + off);
179 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
181 nn_writeb(val, hw->ctrl_bar + off);
184 static inline uint32_t
185 nn_cfg_readl(struct nfp_net_hw *hw, int off)
187 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
191 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
193 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
196 static inline uint64_t
197 nn_cfg_readq(struct nfp_net_hw *hw, int off)
199 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
203 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
205 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
208 /* Creating memzone for hardware rings. */
209 static const struct rte_memzone *
210 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
211 uint16_t queue_id, uint32_t ring_size, int socket_id)
213 char z_name[RTE_MEMZONE_NAMESIZE];
214 const struct rte_memzone *mz;
216 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
217 dev->driver->pci_drv.driver.name,
218 ring_name, dev->data->port_id, queue_id);
220 mz = rte_memzone_lookup(z_name);
224 return rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0,
229 * Atomically reads link status information from global structure rte_eth_dev.
232 * - Pointer to the structure rte_eth_dev to read from.
233 * - Pointer to the buffer to be saved with the link status.
236 * - On success, zero.
237 * - On failure, negative value.
240 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
241 struct rte_eth_link *link)
243 struct rte_eth_link *dst = link;
244 struct rte_eth_link *src = &dev->data->dev_link;
246 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
247 *(uint64_t *)src) == 0)
254 * Atomically writes the link status information into global
255 * structure rte_eth_dev.
258 * - Pointer to the structure rte_eth_dev to read from.
259 * - Pointer to the buffer to be saved with the link status.
262 * - On success, zero.
263 * - On failure, negative value.
266 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
267 struct rte_eth_link *link)
269 struct rte_eth_link *dst = &dev->data->dev_link;
270 struct rte_eth_link *src = link;
272 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
273 *(uint64_t *)src) == 0)
280 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
284 if (rxq->rxbufs == NULL)
287 for (i = 0; i < rxq->rx_count; i++) {
288 if (rxq->rxbufs[i].mbuf) {
289 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
290 rxq->rxbufs[i].mbuf = NULL;
296 nfp_net_rx_queue_release(void *rx_queue)
298 struct nfp_net_rxq *rxq = rx_queue;
301 nfp_net_rx_queue_release_mbufs(rxq);
302 rte_free(rxq->rxbufs);
308 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
310 nfp_net_rx_queue_release_mbufs(rxq);
317 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
321 if (txq->txbufs == NULL)
324 for (i = 0; i < txq->tx_count; i++) {
325 if (txq->txbufs[i].mbuf) {
326 rte_pktmbuf_free(txq->txbufs[i].mbuf);
327 txq->txbufs[i].mbuf = NULL;
333 nfp_net_tx_queue_release(void *tx_queue)
335 struct nfp_net_txq *txq = tx_queue;
338 nfp_net_tx_queue_release_mbufs(txq);
339 rte_free(txq->txbufs);
345 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
347 nfp_net_tx_queue_release_mbufs(txq);
355 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
359 struct timespec wait;
361 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
364 if (hw->qcp_cfg == NULL)
365 rte_panic("Bad configuration queue pointer\n");
367 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
370 wait.tv_nsec = 1000000;
372 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
374 /* Poll update field, waiting for NFP to ack the config */
375 for (cnt = 0; ; cnt++) {
376 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
379 if (new & NFP_NET_CFG_UPDATE_ERR) {
380 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x\n", new);
383 if (cnt >= NFP_NET_POLL_TIMEOUT) {
384 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
385 " %dms\n", update, cnt);
386 rte_panic("Exiting\n");
388 nanosleep(&wait, 0); /* waiting for a 1ms */
390 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
395 * Reconfigure the NIC
396 * @nn: device to reconfigure
397 * @ctrl: The value for the ctrl field in the BAR config
398 * @update: The value for the update field in the BAR config
400 * Write the update word to the BAR and ping the reconfig queue. Then poll
401 * until the firmware has acknowledged the update by zeroing the update word.
404 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
408 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
411 rte_spinlock_lock(&hw->reconfig_lock);
413 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
414 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
418 err = __nfp_net_reconfig(hw, update);
420 rte_spinlock_unlock(&hw->reconfig_lock);
426 * Reconfig errors imply situations where they can be handled.
427 * Otherwise, rte_panic is called inside __nfp_net_reconfig
429 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x\n",
435 * Configure an Ethernet device. This function must be invoked first
436 * before any other function in the Ethernet API. This function can
437 * also be re-invoked when a device is in the stopped state.
440 nfp_net_configure(struct rte_eth_dev *dev)
442 struct rte_eth_conf *dev_conf;
443 struct rte_eth_rxmode *rxmode;
444 struct rte_eth_txmode *txmode;
445 uint32_t new_ctrl = 0;
447 struct nfp_net_hw *hw;
449 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
452 * A DPDK app sends info about how many queues to use and how
453 * those queues need to be configured. This is used by the
454 * DPDK core and it makes sure no more queues than those
455 * advertised by the driver are requested. This function is
456 * called after that internal process
459 PMD_INIT_LOG(DEBUG, "Configure\n");
461 dev_conf = &dev->data->dev_conf;
462 rxmode = &dev_conf->rxmode;
463 txmode = &dev_conf->txmode;
465 /* Checking TX mode */
466 if (txmode->mq_mode) {
467 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported\n");
471 /* Checking RX mode */
472 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
473 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
474 update = NFP_NET_CFG_UPDATE_RSS;
475 new_ctrl = NFP_NET_CFG_CTRL_RSS;
477 PMD_INIT_LOG(INFO, "RSS not supported\n");
482 if (rxmode->split_hdr_size) {
483 PMD_INIT_LOG(INFO, "rxmode does not support split header\n");
487 if (rxmode->hw_ip_checksum) {
488 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
489 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
491 PMD_INIT_LOG(INFO, "RXCSUM not supported\n");
496 if (rxmode->hw_vlan_filter) {
497 PMD_INIT_LOG(INFO, "VLAN filter not supported\n");
501 if (rxmode->hw_vlan_strip) {
502 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
503 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
505 PMD_INIT_LOG(INFO, "hw vlan strip not supported\n");
510 if (rxmode->hw_vlan_extend) {
511 PMD_INIT_LOG(INFO, "VLAN extended not supported\n");
515 /* Supporting VLAN insertion by default */
516 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
517 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
519 if (rxmode->jumbo_frame)
520 /* this is handled in rte_eth_dev_configure */
522 if (rxmode->hw_strip_crc) {
523 PMD_INIT_LOG(INFO, "strip CRC not supported\n");
527 if (rxmode->enable_scatter) {
528 PMD_INIT_LOG(INFO, "Scatter not supported\n");
535 update |= NFP_NET_CFG_UPDATE_GEN;
537 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
538 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
547 nfp_net_enable_queues(struct rte_eth_dev *dev)
549 struct nfp_net_hw *hw;
550 uint64_t enabled_queues = 0;
553 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
555 /* Enabling the required TX queues in the device */
556 for (i = 0; i < dev->data->nb_tx_queues; i++)
557 enabled_queues |= (1 << i);
559 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
563 /* Enabling the required RX queues in the device */
564 for (i = 0; i < dev->data->nb_rx_queues; i++)
565 enabled_queues |= (1 << i);
567 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
571 nfp_net_disable_queues(struct rte_eth_dev *dev)
573 struct nfp_net_hw *hw;
574 uint32_t new_ctrl, update = 0;
576 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
578 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
579 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
581 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
582 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
583 NFP_NET_CFG_UPDATE_MSIX;
585 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
586 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
588 /* If an error when reconfig we avoid to change hw state */
589 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
596 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
600 for (i = 0; i < dev->data->nb_rx_queues; i++) {
601 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
608 nfp_net_params_setup(struct nfp_net_hw *hw)
610 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
611 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
615 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
617 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
620 static void nfp_net_read_mac(struct nfp_net_hw *hw)
624 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
625 memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
627 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
628 memcpy(&hw->mac_addr[4], &tmp, 2);
632 nfp_net_start(struct rte_eth_dev *dev)
634 uint32_t new_ctrl, update = 0;
635 struct nfp_net_hw *hw;
638 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
640 PMD_INIT_LOG(DEBUG, "Start\n");
642 /* Disabling queues just in case... */
643 nfp_net_disable_queues(dev);
645 /* Writing configuration parameters in the device */
646 nfp_net_params_setup(hw);
648 /* Enabling the required queues in the device */
649 nfp_net_enable_queues(dev);
652 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE | NFP_NET_CFG_UPDATE_MSIX;
653 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
655 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
656 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
658 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
659 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
663 * Allocating rte mbuffs for configured rx queues.
664 * This requires queues being enabled before
666 if (nfp_net_rx_freelist_setup(dev) < 0) {
677 * An error returned by this function should mean the app
678 * exiting and then the system releasing all the memory
679 * allocated even memory coming from hugepages.
681 * The device could be enabled at this point with some queues
682 * ready for getting packets. This is true if the call to
683 * nfp_net_rx_freelist_setup() succeeds for some queues but
684 * fails for subsequent queues.
686 * This should make the app exiting but better if we tell the
689 nfp_net_disable_queues(dev);
694 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
696 nfp_net_stop(struct rte_eth_dev *dev)
700 PMD_INIT_LOG(DEBUG, "Stop\n");
702 nfp_net_disable_queues(dev);
705 for (i = 0; i < dev->data->nb_tx_queues; i++) {
706 nfp_net_reset_tx_queue(
707 (struct nfp_net_txq *)dev->data->tx_queues[i]);
710 for (i = 0; i < dev->data->nb_rx_queues; i++) {
711 nfp_net_reset_rx_queue(
712 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
716 /* Reset and stop device. The device can not be restarted. */
718 nfp_net_close(struct rte_eth_dev *dev)
720 struct nfp_net_hw *hw;
722 PMD_INIT_LOG(DEBUG, "Close\n");
724 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
727 * We assume that the DPDK application is stopping all the
728 * threads/queues before calling the device close function.
733 rte_intr_disable(&dev->pci_dev->intr_handle);
734 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
736 /* unregister callback func from eal lib */
737 rte_intr_callback_unregister(&dev->pci_dev->intr_handle,
738 nfp_net_dev_interrupt_handler,
742 * The ixgbe PMD driver disables the pcie master on the
743 * device. The i40e does not...
748 nfp_net_promisc_enable(struct rte_eth_dev *dev)
750 uint32_t new_ctrl, update = 0;
751 struct nfp_net_hw *hw;
753 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
755 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
757 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
758 PMD_INIT_LOG(INFO, "Promiscuous mode not supported\n");
762 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
763 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
767 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
768 update = NFP_NET_CFG_UPDATE_GEN;
771 * DPDK sets promiscuous mode on just after this call assuming
772 * it can not fail ...
774 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
781 nfp_net_promisc_disable(struct rte_eth_dev *dev)
783 uint32_t new_ctrl, update = 0;
784 struct nfp_net_hw *hw;
786 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
788 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
789 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
793 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
794 update = NFP_NET_CFG_UPDATE_GEN;
797 * DPDK sets promiscuous mode off just before this call
798 * assuming it can not fail ...
800 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
807 * return 0 means link status changed, -1 means not changed
809 * Wait to complete is needed as it can take up to 9 seconds to get the Link
813 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
815 struct nfp_net_hw *hw;
816 struct rte_eth_link link, old;
817 uint32_t nn_link_status;
819 PMD_DRV_LOG(DEBUG, "Link update\n");
821 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
823 memset(&old, 0, sizeof(old));
824 nfp_net_dev_atomic_read_link_status(dev, &old);
826 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
828 memset(&link, 0, sizeof(struct rte_eth_link));
830 if (nn_link_status & NFP_NET_CFG_STS_LINK)
831 link.link_status = ETH_LINK_UP;
833 link.link_duplex = ETH_LINK_FULL_DUPLEX;
834 /* Other cards can limit the tx and rx rate per VF */
835 link.link_speed = ETH_SPEED_NUM_40G;
837 if (old.link_status != link.link_status) {
838 nfp_net_dev_atomic_write_link_status(dev, &link);
839 if (link.link_status)
840 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
842 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
850 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
853 struct nfp_net_hw *hw;
854 struct rte_eth_stats nfp_dev_stats;
856 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
858 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
860 memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
862 /* reading per RX ring stats */
863 for (i = 0; i < dev->data->nb_rx_queues; i++) {
864 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
867 nfp_dev_stats.q_ipackets[i] =
868 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
870 nfp_dev_stats.q_ipackets[i] -=
871 hw->eth_stats_base.q_ipackets[i];
873 nfp_dev_stats.q_ibytes[i] =
874 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
876 nfp_dev_stats.q_ibytes[i] -=
877 hw->eth_stats_base.q_ibytes[i];
880 /* reading per TX ring stats */
881 for (i = 0; i < dev->data->nb_tx_queues; i++) {
882 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
885 nfp_dev_stats.q_opackets[i] =
886 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
888 nfp_dev_stats.q_opackets[i] -=
889 hw->eth_stats_base.q_opackets[i];
891 nfp_dev_stats.q_obytes[i] =
892 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
894 nfp_dev_stats.q_obytes[i] -=
895 hw->eth_stats_base.q_obytes[i];
898 nfp_dev_stats.ipackets =
899 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
901 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
903 nfp_dev_stats.ibytes =
904 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
906 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
908 nfp_dev_stats.opackets =
909 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
911 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
913 nfp_dev_stats.obytes =
914 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
916 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
918 /* reading general device stats */
919 nfp_dev_stats.ierrors =
920 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
922 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
924 nfp_dev_stats.oerrors =
925 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
927 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
929 /* RX ring mbuf allocation failures */
930 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
932 nfp_dev_stats.imissed =
933 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
935 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
938 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
942 nfp_net_stats_reset(struct rte_eth_dev *dev)
945 struct nfp_net_hw *hw;
947 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
950 * hw->eth_stats_base records the per counter starting point.
954 /* reading per RX ring stats */
955 for (i = 0; i < dev->data->nb_rx_queues; i++) {
956 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
959 hw->eth_stats_base.q_ipackets[i] =
960 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
962 hw->eth_stats_base.q_ibytes[i] =
963 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
966 /* reading per TX ring stats */
967 for (i = 0; i < dev->data->nb_tx_queues; i++) {
968 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
971 hw->eth_stats_base.q_opackets[i] =
972 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
974 hw->eth_stats_base.q_obytes[i] =
975 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
978 hw->eth_stats_base.ipackets =
979 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
981 hw->eth_stats_base.ibytes =
982 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
984 hw->eth_stats_base.opackets =
985 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
987 hw->eth_stats_base.obytes =
988 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
990 /* reading general device stats */
991 hw->eth_stats_base.ierrors =
992 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
994 hw->eth_stats_base.oerrors =
995 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
997 /* RX ring mbuf allocation failures */
998 dev->data->rx_mbuf_alloc_failed = 0;
1000 hw->eth_stats_base.imissed =
1001 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1005 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1007 struct nfp_net_hw *hw;
1009 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1011 dev_info->driver_name = dev->driver->pci_drv.driver.name;
1012 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1013 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1014 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1015 dev_info->max_rx_pktlen = hw->mtu;
1016 /* Next should change when PF support is implemented */
1017 dev_info->max_mac_addrs = 1;
1019 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1020 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1022 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1023 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1024 DEV_RX_OFFLOAD_UDP_CKSUM |
1025 DEV_RX_OFFLOAD_TCP_CKSUM;
1027 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1028 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1030 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1031 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1032 DEV_TX_OFFLOAD_UDP_CKSUM |
1033 DEV_TX_OFFLOAD_TCP_CKSUM;
1035 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1037 .pthresh = DEFAULT_RX_PTHRESH,
1038 .hthresh = DEFAULT_RX_HTHRESH,
1039 .wthresh = DEFAULT_RX_WTHRESH,
1041 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1045 dev_info->default_txconf = (struct rte_eth_txconf) {
1047 .pthresh = DEFAULT_TX_PTHRESH,
1048 .hthresh = DEFAULT_TX_HTHRESH,
1049 .wthresh = DEFAULT_TX_WTHRESH,
1051 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1052 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1053 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1054 ETH_TXQ_FLAGS_NOOFFLOADS,
1057 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1058 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1060 dev_info->speed_capa = ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1063 static const uint32_t *
1064 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1066 static const uint32_t ptypes[] = {
1067 /* refers to nfp_net_set_hash() */
1068 RTE_PTYPE_INNER_L3_IPV4,
1069 RTE_PTYPE_INNER_L3_IPV6,
1070 RTE_PTYPE_INNER_L3_IPV6_EXT,
1071 RTE_PTYPE_INNER_L4_MASK,
1075 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1081 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1083 struct nfp_net_rxq *rxq;
1084 struct nfp_net_rx_desc *rxds;
1088 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1091 PMD_INIT_LOG(ERR, "Bad queue: %u\n", queue_idx);
1095 idx = rxq->rd_p % rxq->rx_count;
1096 rxds = &rxq->rxds[idx];
1101 * Other PMDs are just checking the DD bit in intervals of 4
1102 * descriptors and counting all four if the first has the DD
1103 * bit on. Of course, this is not accurate but can be good for
1104 * perfomance. But ideally that should be done in descriptors
1105 * chunks belonging to the same cache line
1108 while (count < rxq->rx_count) {
1109 rxds = &rxq->rxds[idx];
1110 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1117 if ((idx) == rxq->rx_count)
1125 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1127 struct rte_eth_link link;
1129 memset(&link, 0, sizeof(link));
1130 nfp_net_dev_atomic_read_link_status(dev, &link);
1131 if (link.link_status)
1132 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1133 (int)(dev->data->port_id), (unsigned)link.link_speed,
1134 link.link_duplex == ETH_LINK_FULL_DUPLEX
1135 ? "full-duplex" : "half-duplex");
1137 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1138 (int)(dev->data->port_id));
1140 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1141 dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1142 dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1145 /* Interrupt configuration and handling */
1148 * nfp_net_irq_unmask - Unmask an interrupt
1150 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1151 * clear the ICR for the entry.
1154 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1156 struct nfp_net_hw *hw;
1158 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1160 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1161 /* If MSI-X auto-masking is used, clear the entry */
1163 rte_intr_enable(&dev->pci_dev->intr_handle);
1165 /* Make sure all updates are written before un-masking */
1167 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1168 NFP_NET_CFG_ICR_UNMASKED);
1173 nfp_net_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1177 struct rte_eth_link link;
1178 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1180 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1182 /* get the link status */
1183 memset(&link, 0, sizeof(link));
1184 nfp_net_dev_atomic_read_link_status(dev, &link);
1186 nfp_net_link_update(dev, 0);
1189 if (!link.link_status) {
1190 /* handle it 1 sec later, wait it being stable */
1191 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1192 /* likely to down */
1194 /* handle it 4 sec later, wait it being stable */
1195 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1198 if (rte_eal_alarm_set(timeout * 1000,
1199 nfp_net_dev_interrupt_delayed_handler,
1201 RTE_LOG(ERR, PMD, "Error setting alarm");
1203 nfp_net_irq_unmask(dev);
1208 * Interrupt handler which shall be registered for alarm callback for delayed
1209 * handling specific interrupt to wait for the stable nic state. As the NIC
1210 * interrupt state is not stable for nfp after link is just down, it needs
1211 * to wait 4 seconds to get the stable status.
1213 * @param handle Pointer to interrupt handle.
1214 * @param param The address of parameter (struct rte_eth_dev *)
1219 nfp_net_dev_interrupt_delayed_handler(void *param)
1221 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1223 nfp_net_link_update(dev, 0);
1224 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1226 nfp_net_dev_link_status_print(dev);
1229 nfp_net_irq_unmask(dev);
1233 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1235 struct nfp_net_hw *hw;
1237 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1239 /* check that mtu is within the allowed range */
1240 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1243 /* switch to jumbo mode if needed */
1244 if ((uint32_t)mtu > ETHER_MAX_LEN)
1245 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1247 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1249 /* update max frame size */
1250 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1252 /* writing to configuration space */
1253 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1261 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1262 uint16_t queue_idx, uint16_t nb_desc,
1263 unsigned int socket_id,
1264 const struct rte_eth_rxconf *rx_conf,
1265 struct rte_mempool *mp)
1267 const struct rte_memzone *tz;
1268 struct nfp_net_rxq *rxq;
1269 struct nfp_net_hw *hw;
1271 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1273 PMD_INIT_FUNC_TRACE();
1275 /* Validating number of descriptors */
1276 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1277 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1278 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1279 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1284 * Free memory prior to re-allocation if needed. This is the case after
1285 * calling nfp_net_stop
1287 if (dev->data->rx_queues[queue_idx]) {
1288 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1289 dev->data->rx_queues[queue_idx] = NULL;
1292 /* Allocating rx queue data structure */
1293 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1294 RTE_CACHE_LINE_SIZE, socket_id);
1298 /* Hw queues mapping based on firmware confifguration */
1299 rxq->qidx = queue_idx;
1300 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1301 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1302 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1303 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1306 * Tracking mbuf size for detecting a potential mbuf overflow due to
1310 rxq->mbuf_size = rxq->mem_pool->elt_size;
1311 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1312 hw->flbufsz = rxq->mbuf_size;
1314 rxq->rx_count = nb_desc;
1315 rxq->port_id = dev->data->port_id;
1316 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1317 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1319 rxq->drop_en = rx_conf->rx_drop_en;
1322 * Allocate RX ring hardware descriptors. A memzone large enough to
1323 * handle the maximum ring size is allocated in order to allow for
1324 * resizing in later calls to the queue setup function.
1326 tz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
1327 sizeof(struct nfp_net_rx_desc) *
1328 NFP_NET_MAX_RX_DESC, socket_id);
1331 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1332 nfp_net_rx_queue_release(rxq);
1336 /* Saving physical and virtual addresses for the RX ring */
1337 rxq->dma = (uint64_t)tz->phys_addr;
1338 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1340 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1341 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1342 sizeof(*rxq->rxbufs) * nb_desc,
1343 RTE_CACHE_LINE_SIZE, socket_id);
1344 if (rxq->rxbufs == NULL) {
1345 nfp_net_rx_queue_release(rxq);
1349 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1350 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1352 nfp_net_reset_rx_queue(rxq);
1354 dev->data->rx_queues[queue_idx] = rxq;
1358 * Telling the HW about the physical address of the RX ring and number
1359 * of descriptors in log2 format
1361 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1362 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), log2(nb_desc));
1368 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1370 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1374 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1377 for (i = 0; i < rxq->rx_count; i++) {
1378 struct nfp_net_rx_desc *rxd;
1379 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1382 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1383 (unsigned)rxq->qidx);
1387 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1389 rxd = &rxq->rxds[i];
1391 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1392 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1394 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1399 /* Make sure all writes are flushed before telling the hardware */
1402 /* Not advertising the whole ring as the firmware gets confused if so */
1403 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1406 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1412 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1413 uint16_t nb_desc, unsigned int socket_id,
1414 const struct rte_eth_txconf *tx_conf)
1416 const struct rte_memzone *tz;
1417 struct nfp_net_txq *txq;
1418 uint16_t tx_free_thresh;
1419 struct nfp_net_hw *hw;
1421 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1423 PMD_INIT_FUNC_TRACE();
1425 /* Validating number of descriptors */
1426 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1427 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1428 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1429 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1433 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1434 tx_conf->tx_free_thresh :
1435 DEFAULT_TX_FREE_THRESH);
1437 if (tx_free_thresh > (nb_desc)) {
1439 "tx_free_thresh must be less than the number of TX "
1440 "descriptors. (tx_free_thresh=%u port=%d "
1441 "queue=%d)\n", (unsigned int)tx_free_thresh,
1442 (int)dev->data->port_id, (int)queue_idx);
1447 * Free memory prior to re-allocation if needed. This is the case after
1448 * calling nfp_net_stop
1450 if (dev->data->tx_queues[queue_idx]) {
1451 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1453 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1454 dev->data->tx_queues[queue_idx] = NULL;
1457 /* Allocating tx queue data structure */
1458 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1459 RTE_CACHE_LINE_SIZE, socket_id);
1461 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1466 * Allocate TX ring hardware descriptors. A memzone large enough to
1467 * handle the maximum ring size is allocated in order to allow for
1468 * resizing in later calls to the queue setup function.
1470 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1471 sizeof(struct nfp_net_tx_desc) *
1472 NFP_NET_MAX_TX_DESC, socket_id);
1474 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1475 nfp_net_tx_queue_release(txq);
1479 txq->tx_count = nb_desc;
1481 txq->tx_free_thresh = tx_free_thresh;
1482 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1483 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1484 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1486 /* queue mapping based on firmware configuration */
1487 txq->qidx = queue_idx;
1488 txq->tx_qcidx = queue_idx * hw->stride_tx;
1489 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1491 txq->port_id = dev->data->port_id;
1492 txq->txq_flags = tx_conf->txq_flags;
1494 /* Saving physical and virtual addresses for the TX ring */
1495 txq->dma = (uint64_t)tz->phys_addr;
1496 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1498 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1499 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1500 sizeof(*txq->txbufs) * nb_desc,
1501 RTE_CACHE_LINE_SIZE, socket_id);
1502 if (txq->txbufs == NULL) {
1503 nfp_net_tx_queue_release(txq);
1506 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1507 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1509 nfp_net_reset_tx_queue(txq);
1511 dev->data->tx_queues[queue_idx] = txq;
1515 * Telling the HW about the physical address of the TX ring and number
1516 * of descriptors in log2 format
1518 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1519 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), log2(nb_desc));
1524 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1526 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1527 struct rte_mbuf *mb)
1530 struct nfp_net_hw *hw = txq->hw;
1532 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1535 ol_flags = mb->ol_flags;
1537 /* IPv6 does not need checksum */
1538 if (ol_flags & PKT_TX_IP_CKSUM)
1539 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1541 switch (ol_flags & PKT_TX_L4_MASK) {
1542 case PKT_TX_UDP_CKSUM:
1543 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1545 case PKT_TX_TCP_CKSUM:
1546 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1550 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1551 txd->flags |= PCIE_DESC_TX_CSUM;
1554 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1556 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1557 struct rte_mbuf *mb)
1559 struct nfp_net_hw *hw = rxq->hw;
1561 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1564 /* If IPv4 and IP checksum error, fail */
1565 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1566 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1567 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1569 /* If neither UDP nor TCP return */
1570 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1571 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1574 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1575 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1576 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1578 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1579 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1580 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1583 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1584 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1587 * nfp_net_set_hash - Set mbuf hash data
1589 * The RSS hash and hash-type are pre-pended to the packet data.
1590 * Extract and decode it and set the mbuf fields.
1593 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1594 struct rte_mbuf *mbuf)
1598 struct nfp_net_hw *hw = rxq->hw;
1600 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1603 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1606 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1607 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1610 * hash type is sharing the same word with input port info
1615 mbuf->hash.rss = hash;
1616 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1618 switch (hash_type) {
1619 case NFP_NET_RSS_IPV4:
1620 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1622 case NFP_NET_RSS_IPV6:
1623 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1625 case NFP_NET_RSS_IPV6_EX:
1626 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1629 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1633 /* nfp_net_check_port - Set mbuf in_port field */
1635 nfp_net_check_port(struct nfp_net_rx_desc *rxd, struct rte_mbuf *mbuf)
1639 if (!(rxd->rxd.flags & PCIE_DESC_RX_INGRESS_PORT)) {
1644 port = rte_be_to_cpu_32(*(uint32_t *)((uint8_t *)mbuf->buf_addr +
1645 mbuf->data_off - 8));
1648 * hash type is sharing the same word with input port info
1652 port = (uint8_t)(port >> 8);
1657 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1659 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1662 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1667 * There are some decissions to take:
1668 * 1) How to check DD RX descriptors bit
1669 * 2) How and when to allocate new mbufs
1671 * Current implementation checks just one single DD bit each loop. As each
1672 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1673 * a single cache line instead. Tests with this change have not shown any
1674 * performance improvement but it requires further investigation. For example,
1675 * depending on which descriptor is next, the number of descriptors could be
1676 * less than 8 for just checking those in the same cache line. This implies
1677 * extra work which could be counterproductive by itself. Indeed, last firmware
1678 * changes are just doing this: writing several descriptors with the DD bit
1679 * for saving PCIe bandwidth and DMA operations from the NFP.
1681 * Mbuf allocation is done when a new packet is received. Then the descriptor
1682 * is automatically linked with the new mbuf and the old one is given to the
1683 * user. The main drawback with this design is mbuf allocation is heavier than
1684 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1685 * cache point of view it does not seem allocating the mbuf early on as we are
1686 * doing now have any benefit at all. Again, tests with this change have not
1687 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1688 * so looking at the implications of this type of allocation should be studied
1693 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1695 struct nfp_net_rxq *rxq;
1696 struct nfp_net_rx_desc *rxds;
1697 struct nfp_net_rx_buff *rxb;
1698 struct nfp_net_hw *hw;
1699 struct rte_mbuf *mb;
1700 struct rte_mbuf *new_mb;
1707 if (unlikely(rxq == NULL)) {
1709 * DPDK just checks the queue is lower than max queues
1710 * enabled. But the queue needs to be configured
1712 RTE_LOG(ERR, PMD, "RX Bad queue\n");
1720 while (avail < nb_pkts) {
1721 idx = rxq->rd_p % rxq->rx_count;
1723 rxb = &rxq->rxbufs[idx];
1724 if (unlikely(rxb == NULL)) {
1725 RTE_LOG(ERR, PMD, "rxb does not exist!\n");
1730 * Memory barrier to ensure that we won't do other
1731 * reads before the DD bit.
1735 rxds = &rxq->rxds[idx];
1736 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1740 * We got a packet. Let's alloc a new mbuff for refilling the
1741 * free descriptor ring as soon as possible
1743 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1744 if (unlikely(new_mb == NULL)) {
1745 RTE_LOG(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1746 "queue_id=%u\n", (unsigned)rxq->port_id,
1747 (unsigned)rxq->qidx);
1748 nfp_net_mbuf_alloc_failed(rxq);
1755 * Grab the mbuff and refill the descriptor with the
1756 * previously allocated mbuff
1761 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1762 rxds->rxd.data_len, rxq->mbuf_size);
1764 /* Size of this segment */
1765 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1766 /* Size of the whole packet. We just support 1 segment */
1767 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1769 if (unlikely((mb->data_len + hw->rx_offset) >
1772 * This should not happen and the user has the
1773 * responsibility of avoiding it. But we have
1774 * to give some info about the error
1777 "mbuf overflow likely due to the RX offset.\n"
1778 "\t\tYour mbuf size should have extra space for"
1779 " RX offset=%u bytes.\n"
1780 "\t\tCurrently you just have %u bytes available"
1781 " but the received packet is %u bytes long",
1783 rxq->mbuf_size - hw->rx_offset,
1788 /* Filling the received mbuff with packet info */
1790 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1792 mb->data_off = RTE_PKTMBUF_HEADROOM +
1793 NFP_DESC_META_LEN(rxds);
1795 /* No scatter mode supported */
1799 /* Checking the RSS flag */
1800 nfp_net_set_hash(rxq, rxds, mb);
1802 /* Checking the checksum flag */
1803 nfp_net_rx_cksum(rxq, rxds, mb);
1805 /* Checking the port flag */
1806 nfp_net_check_port(rxds, mb);
1808 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1809 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1810 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1811 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1814 /* Adding the mbuff to the mbuff array passed by the app */
1815 rx_pkts[avail++] = mb;
1817 /* Now resetting and updating the descriptor */
1820 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1822 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1823 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1831 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
1832 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1834 nb_hold += rxq->nb_rx_hold;
1837 * FL descriptors needs to be written before incrementing the
1838 * FL queue WR pointer
1841 if (nb_hold > rxq->rx_free_thresh) {
1842 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1843 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1844 (unsigned)nb_hold, (unsigned)avail);
1845 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1848 rxq->nb_rx_hold = nb_hold;
1854 * nfp_net_tx_free_bufs - Check for descriptors with a complete
1856 * @txq: TX queue to work with
1857 * Returns number of descriptors freed
1860 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1865 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1866 " status\n", txq->qidx);
1868 /* Work out how many packets have been sent */
1869 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1871 if (qcp_rd_p == txq->qcp_rd_p) {
1872 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1873 "packets (%u, %u)\n", txq->qidx,
1874 qcp_rd_p, txq->qcp_rd_p);
1878 if (qcp_rd_p > txq->qcp_rd_p)
1879 todo = qcp_rd_p - txq->qcp_rd_p;
1881 todo = qcp_rd_p + txq->tx_count - txq->qcp_rd_p;
1883 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->qcp_rd_p: %u, qcp->rd_p: %u\n",
1884 qcp_rd_p, txq->qcp_rd_p, txq->rd_p);
1889 txq->qcp_rd_p += todo;
1890 txq->qcp_rd_p %= txq->tx_count;
1896 /* Leaving always free descriptors for avoiding wrapping confusion */
1897 #define NFP_FREE_TX_DESC(t) (t->tx_count - (t->wr_p - t->rd_p) - 8)
1900 * nfp_net_txq_full - Check if the TX queue free descriptors
1901 * is below tx_free_threshold
1903 * @txq: TX queue to check
1905 * This function uses the host copy* of read/write pointers
1908 int nfp_net_txq_full(struct nfp_net_txq *txq)
1910 return NFP_FREE_TX_DESC(txq) < txq->tx_free_thresh;
1914 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1916 struct nfp_net_txq *txq;
1917 struct nfp_net_hw *hw;
1918 struct nfp_net_tx_desc *txds;
1919 struct rte_mbuf *pkt;
1921 int pkt_size, pkt_len, dma_size;
1922 uint16_t free_descs, issued_descs;
1923 struct rte_mbuf **lmbuf;
1928 txds = &txq->txds[txq->tail];
1930 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
1931 txq->qidx, txq->tail, nb_pkts);
1933 if ((NFP_FREE_TX_DESC(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
1934 nfp_net_tx_free_bufs(txq);
1936 free_descs = (uint16_t)NFP_FREE_TX_DESC(txq);
1937 if (unlikely(free_descs == 0))
1944 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
1945 txq->qidx, nb_pkts);
1946 /* Sending packets */
1947 while ((i < nb_pkts) && free_descs) {
1948 /* Grabbing the mbuf linked to the current descriptor */
1949 lmbuf = &txq->txbufs[txq->tail].mbuf;
1950 /* Warming the cache for releasing the mbuf later on */
1951 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
1953 pkt = *(tx_pkts + i);
1955 if (unlikely((pkt->nb_segs > 1) &&
1956 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
1957 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set\n");
1958 rte_panic("Multisegment packet unsupported\n");
1961 /* Checking if we have enough descriptors */
1962 if (unlikely(pkt->nb_segs > free_descs))
1966 * Checksum and VLAN flags just in the first descriptor for a
1967 * multisegment packet
1970 txds->data_len = pkt->pkt_len;
1971 nfp_net_tx_cksum(txq, txds, pkt);
1973 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
1974 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
1975 txds->flags |= PCIE_DESC_TX_VLAN;
1976 txds->vlan = pkt->vlan_tci;
1979 if (pkt->ol_flags & PKT_TX_TCP_SEG)
1980 rte_panic("TSO is not supported\n");
1983 * mbuf data_len is the data in one segment and pkt_len data
1984 * in the whole packet. When the packet is just one segment,
1985 * then data_len = pkt_len
1987 pkt_size = pkt->pkt_len;
1988 pkt_len = pkt->pkt_len;
1990 /* Releasing mbuf which was prefetched above */
1992 rte_pktmbuf_free(*lmbuf);
1994 * Linking mbuf with descriptor for being released
1995 * next time descriptor is used
2000 dma_size = pkt->data_len;
2001 dma_addr = rte_mbuf_data_dma_addr(pkt);
2002 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2003 "%" PRIx64 "\n", dma_addr);
2005 /* Filling descriptors fields */
2006 txds->dma_len = dma_size;
2007 txds->data_len = pkt_len;
2008 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2009 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2010 ASSERT(free_descs > 0);
2015 if (unlikely(txq->tail == txq->tx_count)) /* wrapping?*/
2018 pkt_size -= dma_size;
2021 txds->offset_eop |= PCIE_DESC_TX_EOP;
2023 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2026 /* Referencing next free TX descriptor */
2027 txds = &txq->txds[txq->tail];
2034 /* Increment write pointers. Force memory write before we let HW know */
2036 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2042 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2044 uint32_t new_ctrl, update;
2045 struct nfp_net_hw *hw;
2047 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2050 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2051 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2052 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2053 " ETH_VLAN_EXTEND_OFFLOAD");
2055 /* Enable vlan strip if it is not configured yet */
2056 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2057 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2058 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2060 /* Disable vlan strip just if it is configured */
2061 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2062 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2063 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2068 update = NFP_NET_CFG_UPDATE_GEN;
2070 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2073 hw->ctrl = new_ctrl;
2076 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2078 nfp_net_reta_update(struct rte_eth_dev *dev,
2079 struct rte_eth_rss_reta_entry64 *reta_conf,
2082 uint32_t reta, mask;
2086 struct nfp_net_hw *hw =
2087 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2089 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2092 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2093 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2094 "(%d) doesn't match the number hardware can supported "
2095 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2100 * Update Redirection Table. There are 128 8bit-entries which can be
2101 * manage as 32 32bit-entries
2103 for (i = 0; i < reta_size; i += 4) {
2104 /* Handling 4 RSS entries per loop */
2105 idx = i / RTE_RETA_GROUP_SIZE;
2106 shift = i % RTE_RETA_GROUP_SIZE;
2107 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2113 /* If all 4 entries were set, don't need read RETA register */
2115 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2117 for (j = 0; j < 4; j++) {
2118 if (!(mask & (0x1 << j)))
2121 /* Clearing the entry bits */
2122 reta &= ~(0xFF << (8 * j));
2123 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2125 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2129 update = NFP_NET_CFG_UPDATE_RSS;
2131 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2137 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2139 nfp_net_reta_query(struct rte_eth_dev *dev,
2140 struct rte_eth_rss_reta_entry64 *reta_conf,
2146 struct nfp_net_hw *hw;
2148 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2153 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2154 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2155 "(%d) doesn't match the number hardware can supported "
2156 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2161 * Reading Redirection Table. There are 128 8bit-entries which can be
2162 * manage as 32 32bit-entries
2164 for (i = 0; i < reta_size; i += 4) {
2165 /* Handling 4 RSS entries per loop */
2166 idx = i / RTE_RETA_GROUP_SIZE;
2167 shift = i % RTE_RETA_GROUP_SIZE;
2168 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2173 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2175 for (j = 0; j < 4; j++) {
2176 if (!(mask & (0x1 << j)))
2178 reta_conf->reta[shift + j] =
2179 (uint8_t)((reta >> (8 * j)) & 0xF);
2186 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2187 struct rte_eth_rss_conf *rss_conf)
2190 uint32_t cfg_rss_ctrl = 0;
2194 struct nfp_net_hw *hw;
2196 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2198 rss_hf = rss_conf->rss_hf;
2200 /* Checking if RSS is enabled */
2201 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2202 if (rss_hf != 0) { /* Enable RSS? */
2203 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2206 return 0; /* Nothing to do */
2209 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2210 RTE_LOG(ERR, PMD, "hash key too long\n");
2214 if (rss_hf & ETH_RSS_IPV4)
2215 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2216 NFP_NET_CFG_RSS_IPV4_TCP |
2217 NFP_NET_CFG_RSS_IPV4_UDP;
2219 if (rss_hf & ETH_RSS_IPV6)
2220 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2221 NFP_NET_CFG_RSS_IPV6_TCP |
2222 NFP_NET_CFG_RSS_IPV6_UDP;
2224 cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2225 cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2227 /* configuring where to apply the RSS hash */
2228 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2230 /* Writing the key byte a byte */
2231 for (i = 0; i < rss_conf->rss_key_len; i++) {
2232 memcpy(&key, &rss_conf->rss_key[i], 1);
2233 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2236 /* Writing the key size */
2237 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2239 update = NFP_NET_CFG_UPDATE_RSS;
2241 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2248 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2249 struct rte_eth_rss_conf *rss_conf)
2252 uint32_t cfg_rss_ctrl;
2255 struct nfp_net_hw *hw;
2257 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2259 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2262 rss_hf = rss_conf->rss_hf;
2263 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2265 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2266 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2268 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2269 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2271 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2272 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2274 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2275 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2277 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2278 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2280 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2281 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2283 /* Reading the key size */
2284 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2286 /* Reading the key byte a byte */
2287 for (i = 0; i < rss_conf->rss_key_len; i++) {
2288 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2289 memcpy(&rss_conf->rss_key[i], &key, 1);
2295 /* Initialise and register driver with DPDK Application */
2296 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2297 .dev_configure = nfp_net_configure,
2298 .dev_start = nfp_net_start,
2299 .dev_stop = nfp_net_stop,
2300 .dev_close = nfp_net_close,
2301 .promiscuous_enable = nfp_net_promisc_enable,
2302 .promiscuous_disable = nfp_net_promisc_disable,
2303 .link_update = nfp_net_link_update,
2304 .stats_get = nfp_net_stats_get,
2305 .stats_reset = nfp_net_stats_reset,
2306 .dev_infos_get = nfp_net_infos_get,
2307 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2308 .mtu_set = nfp_net_dev_mtu_set,
2309 .vlan_offload_set = nfp_net_vlan_offload_set,
2310 .reta_update = nfp_net_reta_update,
2311 .reta_query = nfp_net_reta_query,
2312 .rss_hash_update = nfp_net_rss_hash_update,
2313 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2314 .rx_queue_setup = nfp_net_rx_queue_setup,
2315 .rx_queue_release = nfp_net_rx_queue_release,
2316 .rx_queue_count = nfp_net_rx_queue_count,
2317 .tx_queue_setup = nfp_net_tx_queue_setup,
2318 .tx_queue_release = nfp_net_tx_queue_release,
2322 nfp_net_init(struct rte_eth_dev *eth_dev)
2324 struct rte_pci_device *pci_dev;
2325 struct nfp_net_hw *hw;
2327 uint32_t tx_bar_off, rx_bar_off;
2331 PMD_INIT_FUNC_TRACE();
2333 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2335 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2336 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2337 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2339 /* For secondary processes, the primary has done all the work */
2340 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2343 pci_dev = eth_dev->pci_dev;
2344 rte_eth_copy_pci_info(eth_dev, pci_dev);
2346 hw->device_id = pci_dev->id.device_id;
2347 hw->vendor_id = pci_dev->id.vendor_id;
2348 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2349 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2351 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u\n",
2352 pci_dev->id.vendor_id, pci_dev->id.device_id,
2353 pci_dev->addr.domain, pci_dev->addr.bus,
2354 pci_dev->addr.devid, pci_dev->addr.function);
2356 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2357 if (hw->ctrl_bar == NULL) {
2359 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2362 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2363 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2365 /* Work out where in the BAR the queues start. */
2366 switch (pci_dev->id.device_id) {
2367 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2368 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2369 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2370 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2371 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2374 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2378 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x\n", tx_bar_off);
2379 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x\n", rx_bar_off);
2381 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2382 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2384 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p\n",
2385 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2387 nfp_net_cfg_queue_setup(hw);
2389 /* Get some of the read-only fields from the config BAR */
2390 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2391 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2392 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2393 hw->mtu = hw->max_mtu;
2395 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2396 hw->rx_offset = NFP_NET_RX_OFFSET;
2398 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2400 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d\n",
2401 hw->ver, hw->max_mtu);
2402 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s\n", hw->cap,
2403 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2404 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2405 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2406 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2407 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2408 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2409 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2410 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2411 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2413 pci_dev = eth_dev->pci_dev;
2416 hw->stride_rx = stride;
2417 hw->stride_tx = stride;
2419 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u\n",
2420 hw->max_rx_queues, hw->max_tx_queues);
2422 /* Initializing spinlock for reconfigs */
2423 rte_spinlock_init(&hw->reconfig_lock);
2425 /* Allocating memory for mac addr */
2426 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2427 if (eth_dev->data->mac_addrs == NULL) {
2428 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2432 nfp_net_read_mac(hw);
2434 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr))
2435 /* Using random mac addresses for VFs */
2436 eth_random_addr(&hw->mac_addr[0]);
2438 /* Copying mac address to DPDK eth_dev struct */
2439 ether_addr_copy((struct ether_addr *)hw->mac_addr,
2440 ð_dev->data->mac_addrs[0]);
2442 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2443 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2444 eth_dev->data->port_id, pci_dev->id.vendor_id,
2445 pci_dev->id.device_id,
2446 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2447 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2449 /* Registering LSC interrupt handler */
2450 rte_intr_callback_register(&pci_dev->intr_handle,
2451 nfp_net_dev_interrupt_handler,
2454 /* enable uio intr after callback register */
2455 rte_intr_enable(&pci_dev->intr_handle);
2457 /* Telling the firmware about the LSC interrupt entry */
2458 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2460 /* Recording current stats counters values */
2461 nfp_net_stats_reset(eth_dev);
2466 static struct rte_pci_id pci_id_nfp_net_map[] = {
2468 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2469 PCI_DEVICE_ID_NFP6000_PF_NIC)
2472 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2473 PCI_DEVICE_ID_NFP6000_VF_NIC)
2480 static struct eth_driver rte_nfp_net_pmd = {
2482 .id_table = pci_id_nfp_net_map,
2483 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2484 RTE_PCI_DRV_DETACHABLE,
2485 .probe = rte_eth_dev_pci_probe,
2486 .remove = rte_eth_dev_pci_remove,
2488 .eth_dev_init = nfp_net_init,
2489 .dev_private_size = sizeof(struct nfp_net_adapter),
2492 RTE_PMD_REGISTER_PCI(net_nfp, rte_nfp_net_pmd.pci_drv);
2493 RTE_PMD_REGISTER_PCI_TABLE(net_nfp, pci_id_nfp_net_map);
2497 * c-file-style: "Linux"
2498 * indent-tabs-mode: t