2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
12 #include "ecore_status.h"
13 #include "ecore_hsi_eth.h"
14 #include "ecore_chain.h"
15 #include "ecore_spq.h"
16 #include "ecore_init_fw_funcs.h"
17 #include "ecore_cxt.h"
19 #include "ecore_sp_commands.h"
20 #include "ecore_gtt_reg_addr.h"
21 #include "ecore_iro.h"
23 #include "ecore_int.h"
26 #include "ecore_sriov.h"
27 #include "ecore_mcp.h"
29 #define ECORE_MAX_SGES_NUM 16
30 #define CRC32_POLY 0x1edc6f41
33 ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn,
34 struct ecore_sp_vport_start_params *p_params)
36 struct vport_start_ramrod_data *p_ramrod = OSAL_NULL;
37 struct ecore_spq_entry *p_ent = OSAL_NULL;
38 enum _ecore_status_t rc = ECORE_NOTIMPL;
39 struct ecore_sp_init_data init_data;
43 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
44 if (rc != ECORE_SUCCESS)
48 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
49 init_data.cid = ecore_spq_get_cid(p_hwfn);
50 init_data.opaque_fid = p_params->opaque_fid;
51 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
53 rc = ecore_sp_init_request(p_hwfn, &p_ent,
54 ETH_RAMROD_VPORT_START,
55 PROTOCOLID_ETH, &init_data);
56 if (rc != ECORE_SUCCESS)
59 p_ramrod = &p_ent->ramrod.vport_start;
60 p_ramrod->vport_id = abs_vport_id;
62 p_ramrod->mtu = OSAL_CPU_TO_LE16(p_params->mtu);
63 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
64 p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
65 p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
66 p_ramrod->untagged = p_params->only_untagged;
67 p_ramrod->zero_placement_offset = p_params->zero_placement_offset;
69 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
70 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
72 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(rx_mode);
74 /* TPA related fields */
75 OSAL_MEMSET(&p_ramrod->tpa_param, 0,
76 sizeof(struct eth_vport_tpa_param));
77 p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
79 switch (p_params->tpa_mode) {
80 case ECORE_TPA_MODE_GRO:
81 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
82 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
83 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
84 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
85 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
86 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
87 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
88 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
94 p_ramrod->tx_switching_en = p_params->tx_switching;
96 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
97 p_ramrod->tx_switching_en = 0;
100 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
101 p_ramrod->sw_fid = ecore_concrete_to_sw_fid(p_hwfn->p_dev,
102 p_params->concrete_fid);
104 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
108 ecore_sp_vport_start(struct ecore_hwfn *p_hwfn,
109 struct ecore_sp_vport_start_params *p_params)
111 if (IS_VF(p_hwfn->p_dev))
112 return ecore_vf_pf_vport_start(p_hwfn, p_params->vport_id,
114 p_params->remove_inner_vlan,
116 p_params->max_buffers_per_cqe,
117 p_params->only_untagged);
119 return ecore_sp_eth_vport_start(p_hwfn, p_params);
122 static enum _ecore_status_t
123 ecore_sp_vport_update_rss(struct ecore_hwfn *p_hwfn,
124 struct vport_update_ramrod_data *p_ramrod,
125 struct ecore_rss_params *p_rss)
127 enum _ecore_status_t rc = ECORE_SUCCESS;
128 struct eth_vport_rss_config *p_config;
129 u16 abs_l2_queue = 0;
133 p_ramrod->common.update_rss_flg = 0;
136 p_config = &p_ramrod->rss_config;
138 OSAL_BUILD_BUG_ON(ECORE_RSS_IND_TABLE_SIZE !=
139 ETH_RSS_IND_TABLE_ENTRIES_NUM);
141 rc = ecore_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
142 if (rc != ECORE_SUCCESS)
145 p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
146 p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
147 p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
148 p_config->update_rss_key = p_rss->update_rss_key;
150 p_config->rss_mode = p_rss->rss_enable ?
151 ETH_VPORT_RSS_MODE_REGULAR : ETH_VPORT_RSS_MODE_DISABLED;
153 p_config->capabilities = 0;
155 SET_FIELD(p_config->capabilities,
156 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
157 !!(p_rss->rss_caps & ECORE_RSS_IPV4));
158 SET_FIELD(p_config->capabilities,
159 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
160 !!(p_rss->rss_caps & ECORE_RSS_IPV6));
161 SET_FIELD(p_config->capabilities,
162 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
163 !!(p_rss->rss_caps & ECORE_RSS_IPV4_TCP));
164 SET_FIELD(p_config->capabilities,
165 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
166 !!(p_rss->rss_caps & ECORE_RSS_IPV6_TCP));
167 SET_FIELD(p_config->capabilities,
168 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
169 !!(p_rss->rss_caps & ECORE_RSS_IPV4_UDP));
170 SET_FIELD(p_config->capabilities,
171 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
172 !!(p_rss->rss_caps & ECORE_RSS_IPV6_UDP));
173 p_config->tbl_size = p_rss->rss_table_size_log;
174 p_config->capabilities = OSAL_CPU_TO_LE16(p_config->capabilities);
176 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
177 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
178 p_ramrod->common.update_rss_flg,
180 p_config->update_rss_capabilities,
181 p_config->capabilities,
182 p_config->update_rss_ind_table, p_config->update_rss_key);
184 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
185 rc = ecore_fw_l2_queue(p_hwfn,
186 (u8)p_rss->rss_ind_table[i],
188 if (rc != ECORE_SUCCESS)
191 p_config->indirection_table[i] = OSAL_CPU_TO_LE16(abs_l2_queue);
192 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP, "i= %d, queue = %d\n",
193 i, p_config->indirection_table[i]);
196 for (i = 0; i < 10; i++)
197 p_config->rss_key[i] = OSAL_CPU_TO_LE32(p_rss->rss_key[i]);
203 ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn,
204 struct vport_update_ramrod_data *p_ramrod,
205 struct ecore_filter_accept_flags flags)
207 p_ramrod->common.update_rx_mode_flg = flags.update_rx_mode_config;
208 p_ramrod->common.update_tx_mode_flg = flags.update_tx_mode_config;
211 /* On B0 emulation we cannot enable Tx, since this would cause writes
212 * to PVFC HW block which isn't implemented in emulation.
214 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
215 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
216 "Non-Asic - prevent Tx mode in vport update\n");
217 p_ramrod->common.update_tx_mode_flg = 0;
221 /* Set Rx mode accept flags */
222 if (p_ramrod->common.update_rx_mode_flg) {
223 __le16 *state = &p_ramrod->rx_mode.state;
224 u8 accept_filter = flags.rx_accept_filter;
227 * SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
228 * !!(accept_filter & ECORE_ACCEPT_NONE));
231 SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL,
232 (!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) &&
233 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
235 SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
236 !(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) ||
237 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
239 SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
240 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED));
242 * SET_FIELD(*state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
243 * !!(accept_filter & ECORE_ACCEPT_NONE));
245 SET_FIELD(*state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
246 !(!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) ||
247 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
249 SET_FIELD(*state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
250 (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
251 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
253 SET_FIELD(*state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
254 !!(accept_filter & ECORE_ACCEPT_BCAST));
256 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
257 "p_ramrod->rx_mode.state = 0x%x\n",
258 p_ramrod->rx_mode.state);
261 /* Set Tx mode accept flags */
262 if (p_ramrod->common.update_tx_mode_flg) {
263 __le16 *state = &p_ramrod->tx_mode.state;
264 u8 accept_filter = flags.tx_accept_filter;
266 SET_FIELD(*state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
267 !!(accept_filter & ECORE_ACCEPT_NONE));
269 SET_FIELD(*state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
270 !!(accept_filter & ECORE_ACCEPT_NONE));
272 SET_FIELD(*state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
273 (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
274 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
276 SET_FIELD(*state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
277 !!(accept_filter & ECORE_ACCEPT_BCAST));
279 /* ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL and
280 * ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL
281 * needs to be set for VF-VF communication to work
282 * when dest macaddr is unknown.
284 SET_FIELD(*state, ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL,
285 (!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) &&
286 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
288 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
289 "p_ramrod->tx_mode.state = 0x%x\n",
290 p_ramrod->tx_mode.state);
295 ecore_sp_vport_update_sge_tpa(struct ecore_hwfn *p_hwfn,
296 struct vport_update_ramrod_data *p_ramrod,
297 struct ecore_sge_tpa_params *p_params)
299 struct eth_vport_tpa_param *p_tpa;
302 p_ramrod->common.update_tpa_param_flg = 0;
303 p_ramrod->common.update_tpa_en_flg = 0;
304 p_ramrod->common.update_tpa_param_flg = 0;
308 p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
309 p_tpa = &p_ramrod->tpa_param;
310 p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
311 p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
312 p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
313 p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
315 p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
316 p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
317 p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
318 p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
319 p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
320 p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
321 p_tpa->tpa_max_size = p_params->tpa_max_size;
322 p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
323 p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
327 ecore_sp_update_mcast_bin(struct ecore_hwfn *p_hwfn,
328 struct vport_update_ramrod_data *p_ramrod,
329 struct ecore_sp_vport_update_params *p_params)
333 OSAL_MEMSET(&p_ramrod->approx_mcast.bins, 0,
334 sizeof(p_ramrod->approx_mcast.bins));
336 if (!p_params->update_approx_mcast_flg)
339 p_ramrod->common.update_approx_mcast_flg = 1;
340 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
341 u32 *p_bins = (u32 *)p_params->bins;
343 p_ramrod->approx_mcast.bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
348 ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,
349 struct ecore_sp_vport_update_params *p_params,
350 enum spq_mode comp_mode,
351 struct ecore_spq_comp_cb *p_comp_data)
353 struct ecore_rss_params *p_rss_params = p_params->rss_params;
354 struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
355 struct ecore_spq_entry *p_ent = OSAL_NULL;
356 enum _ecore_status_t rc = ECORE_NOTIMPL;
357 struct ecore_sp_init_data init_data;
358 u8 abs_vport_id = 0, val;
361 if (IS_VF(p_hwfn->p_dev)) {
362 rc = ecore_vf_pf_vport_update(p_hwfn, p_params);
366 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
367 if (rc != ECORE_SUCCESS)
371 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
372 init_data.cid = ecore_spq_get_cid(p_hwfn);
373 init_data.opaque_fid = p_params->opaque_fid;
374 init_data.comp_mode = comp_mode;
375 init_data.p_comp_data = p_comp_data;
377 rc = ecore_sp_init_request(p_hwfn, &p_ent,
378 ETH_RAMROD_VPORT_UPDATE,
379 PROTOCOLID_ETH, &init_data);
380 if (rc != ECORE_SUCCESS)
383 /* Copy input params to ramrod according to FW struct */
384 p_ramrod = &p_ent->ramrod.vport_update;
386 p_ramrod->common.vport_id = abs_vport_id;
388 p_ramrod->common.rx_active_flg = p_params->vport_active_rx_flg;
389 p_ramrod->common.tx_active_flg = p_params->vport_active_tx_flg;
390 val = p_params->update_vport_active_rx_flg;
391 p_ramrod->common.update_rx_active_flg = val;
392 val = p_params->update_vport_active_tx_flg;
393 p_ramrod->common.update_tx_active_flg = val;
394 val = p_params->update_inner_vlan_removal_flg;
395 p_ramrod->common.update_inner_vlan_removal_en_flg = val;
396 val = p_params->inner_vlan_removal_flg;
397 p_ramrod->common.inner_vlan_removal_en = val;
398 val = p_params->silent_vlan_removal_flg;
399 p_ramrod->common.silent_vlan_removal_en = val;
400 val = p_params->update_tx_switching_flg;
401 p_ramrod->common.update_tx_switching_en_flg = val;
402 val = p_params->update_default_vlan_enable_flg;
403 p_ramrod->common.update_default_vlan_en_flg = val;
404 p_ramrod->common.default_vlan_en = p_params->default_vlan_enable_flg;
405 val = p_params->update_default_vlan_flg;
406 p_ramrod->common.update_default_vlan_flg = val;
407 wordval = p_params->default_vlan;
408 p_ramrod->common.default_vlan = OSAL_CPU_TO_LE16(wordval);
410 p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
413 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
414 if (p_ramrod->common.tx_switching_en ||
415 p_ramrod->common.update_tx_switching_en_flg) {
416 DP_NOTICE(p_hwfn, false,
417 "FPGA - why are we seeing tx-switching? Overriding it\n");
418 p_ramrod->common.tx_switching_en = 0;
419 p_ramrod->common.update_tx_switching_en_flg = 1;
423 val = p_params->update_anti_spoofing_en_flg;
424 p_ramrod->common.update_anti_spoofing_en_flg = val;
425 p_ramrod->common.anti_spoofing_en = p_params->anti_spoofing_en;
426 p_ramrod->common.accept_any_vlan = p_params->accept_any_vlan;
427 val = p_params->update_accept_any_vlan_flg;
428 p_ramrod->common.update_accept_any_vlan_flg = val;
430 rc = ecore_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
431 if (rc != ECORE_SUCCESS) {
432 /* Return spq entry which is taken in ecore_sp_init_request() */
433 ecore_spq_return_entry(p_hwfn, p_ent);
437 /* Update mcast bins for VFs, PF doesn't use this functionality */
438 ecore_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
440 ecore_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
441 ecore_sp_vport_update_sge_tpa(p_hwfn, p_ramrod,
442 p_params->sge_tpa_params);
443 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
446 enum _ecore_status_t ecore_sp_vport_stop(struct ecore_hwfn *p_hwfn,
447 u16 opaque_fid, u8 vport_id)
449 struct vport_stop_ramrod_data *p_ramrod;
450 struct ecore_sp_init_data init_data;
451 struct ecore_spq_entry *p_ent;
452 enum _ecore_status_t rc;
455 if (IS_VF(p_hwfn->p_dev))
456 return ecore_vf_pf_vport_stop(p_hwfn);
458 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
459 if (rc != ECORE_SUCCESS)
463 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
464 init_data.cid = ecore_spq_get_cid(p_hwfn);
465 init_data.opaque_fid = opaque_fid;
466 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
468 rc = ecore_sp_init_request(p_hwfn, &p_ent,
469 ETH_RAMROD_VPORT_STOP,
470 PROTOCOLID_ETH, &init_data);
471 if (rc != ECORE_SUCCESS)
474 p_ramrod = &p_ent->ramrod.vport_stop;
475 p_ramrod->vport_id = abs_vport_id;
477 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
480 static enum _ecore_status_t
481 ecore_vf_pf_accept_flags(struct ecore_hwfn *p_hwfn,
482 struct ecore_filter_accept_flags *p_accept_flags)
484 struct ecore_sp_vport_update_params s_params;
486 OSAL_MEMSET(&s_params, 0, sizeof(s_params));
487 OSAL_MEMCPY(&s_params.accept_flags, p_accept_flags,
488 sizeof(struct ecore_filter_accept_flags));
490 return ecore_vf_pf_vport_update(p_hwfn, &s_params);
494 ecore_filter_accept_cmd(struct ecore_dev *p_dev,
496 struct ecore_filter_accept_flags accept_flags,
497 u8 update_accept_any_vlan,
499 enum spq_mode comp_mode,
500 struct ecore_spq_comp_cb *p_comp_data)
502 struct ecore_sp_vport_update_params update_params;
505 /* Prepare and send the vport rx_mode change */
506 OSAL_MEMSET(&update_params, 0, sizeof(update_params));
507 update_params.vport_id = vport;
508 update_params.accept_flags = accept_flags;
509 update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
510 update_params.accept_any_vlan = accept_any_vlan;
512 for_each_hwfn(p_dev, i) {
513 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
515 update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
518 rc = ecore_vf_pf_accept_flags(p_hwfn, &accept_flags);
519 if (rc != ECORE_SUCCESS)
524 rc = ecore_sp_vport_update(p_hwfn, &update_params,
525 comp_mode, p_comp_data);
526 if (rc != ECORE_SUCCESS) {
527 DP_ERR(p_dev, "Update rx_mode failed %d\n", rc);
531 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
532 "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
533 accept_flags.rx_accept_filter,
534 accept_flags.tx_accept_filter);
536 if (update_accept_any_vlan)
537 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
538 "accept_any_vlan=%d configured\n",
545 static void ecore_sp_release_queue_cid(struct ecore_hwfn *p_hwfn,
546 struct ecore_hw_cid_data *p_cid_data)
548 if (!p_cid_data->b_cid_allocated)
551 ecore_cxt_release_cid(p_hwfn, p_cid_data->cid);
552 p_cid_data->b_cid_allocated = false;
556 ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,
565 dma_addr_t bd_chain_phys_addr,
566 dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
568 struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
569 struct rx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
570 struct ecore_spq_entry *p_ent = OSAL_NULL;
571 enum _ecore_status_t rc = ECORE_NOTIMPL;
572 struct ecore_sp_init_data init_data;
576 /* Store information for the stop */
578 p_rx_cid->opaque_fid = opaque_fid;
579 p_rx_cid->vport_id = vport_id;
581 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
582 if (rc != ECORE_SUCCESS)
585 rc = ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
586 if (rc != ECORE_SUCCESS)
589 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
590 "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
591 opaque_fid, cid, rx_queue_id, vport_id, sb);
594 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
596 init_data.opaque_fid = opaque_fid;
597 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
599 rc = ecore_sp_init_request(p_hwfn, &p_ent,
600 ETH_RAMROD_RX_QUEUE_START,
601 PROTOCOLID_ETH, &init_data);
602 if (rc != ECORE_SUCCESS)
605 p_ramrod = &p_ent->ramrod.rx_queue_start;
607 p_ramrod->sb_id = OSAL_CPU_TO_LE16(sb);
608 p_ramrod->sb_index = sb_index;
609 p_ramrod->vport_id = abs_vport_id;
610 p_ramrod->stats_counter_id = stats_id;
611 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
612 p_ramrod->complete_cqe_flg = 0;
613 p_ramrod->complete_event_flg = 1;
615 p_ramrod->bd_max_bytes = OSAL_CPU_TO_LE16(bd_max_bytes);
616 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
618 p_ramrod->num_of_pbl_pages = OSAL_CPU_TO_LE16(cqe_pbl_size);
619 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
621 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
624 enum _ecore_status_t ecore_sp_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,
632 dma_addr_t bd_chain_phys_addr,
633 dma_addr_t cqe_pbl_addr,
635 void OSAL_IOMEM * *pp_prod)
637 struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
639 u16 abs_l2_queue = 0;
640 enum _ecore_status_t rc;
641 u64 init_prod_val = 0;
643 if (IS_VF(p_hwfn->p_dev)) {
644 return ecore_vf_pf_rxq_start(p_hwfn,
651 cqe_pbl_size, pp_prod);
654 rc = ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_l2_queue);
655 if (rc != ECORE_SUCCESS)
658 rc = ecore_fw_vport(p_hwfn, stats_id, &abs_stats_id);
659 if (rc != ECORE_SUCCESS)
662 *pp_prod = (u8 OSAL_IOMEM *)p_hwfn->regview +
663 GTT_BAR0_MAP_REG_MSDM_RAM + MSTORM_PRODS_OFFSET(abs_l2_queue);
665 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
666 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u64),
667 (u32 *)(&init_prod_val));
669 /* Allocate a CID for the queue */
670 rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_rx_cid->cid);
671 if (rc != ECORE_SUCCESS) {
672 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
675 p_rx_cid->b_cid_allocated = true;
677 rc = ecore_sp_eth_rxq_start_ramrod(p_hwfn,
687 cqe_pbl_addr, cqe_pbl_size);
689 if (rc != ECORE_SUCCESS)
690 ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
696 ecore_sp_eth_rx_queues_update(struct ecore_hwfn *p_hwfn,
700 u8 complete_event_flg,
701 enum spq_mode comp_mode,
702 struct ecore_spq_comp_cb *p_comp_data)
704 struct rx_queue_update_ramrod_data *p_ramrod = OSAL_NULL;
705 struct ecore_spq_entry *p_ent = OSAL_NULL;
706 enum _ecore_status_t rc = ECORE_NOTIMPL;
707 struct ecore_sp_init_data init_data;
708 struct ecore_hw_cid_data *p_rx_cid;
709 u16 qid, abs_rx_q_id = 0;
712 if (IS_VF(p_hwfn->p_dev))
713 return ecore_vf_pf_rxqs_update(p_hwfn,
719 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
720 init_data.comp_mode = comp_mode;
721 init_data.p_comp_data = p_comp_data;
723 for (i = 0; i < num_rxqs; i++) {
724 qid = rx_queue_id + i;
725 p_rx_cid = &p_hwfn->p_rx_cids[qid];
728 init_data.cid = p_rx_cid->cid;
729 init_data.opaque_fid = p_rx_cid->opaque_fid;
731 rc = ecore_sp_init_request(p_hwfn, &p_ent,
732 ETH_RAMROD_RX_QUEUE_UPDATE,
733 PROTOCOLID_ETH, &init_data);
734 if (rc != ECORE_SUCCESS)
737 p_ramrod = &p_ent->ramrod.rx_queue_update;
739 ecore_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
740 ecore_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
741 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
742 p_ramrod->complete_cqe_flg = complete_cqe_flg;
743 p_ramrod->complete_event_flg = complete_event_flg;
745 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
754 ecore_sp_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn,
756 bool eq_completion_only, bool cqe_completion)
758 struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
759 struct rx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL;
760 struct ecore_spq_entry *p_ent = OSAL_NULL;
761 enum _ecore_status_t rc = ECORE_NOTIMPL;
762 struct ecore_sp_init_data init_data;
765 if (IS_VF(p_hwfn->p_dev))
766 return ecore_vf_pf_rxq_stop(p_hwfn, rx_queue_id,
770 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
771 init_data.cid = p_rx_cid->cid;
772 init_data.opaque_fid = p_rx_cid->opaque_fid;
773 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
775 rc = ecore_sp_init_request(p_hwfn, &p_ent,
776 ETH_RAMROD_RX_QUEUE_STOP,
777 PROTOCOLID_ETH, &init_data);
778 if (rc != ECORE_SUCCESS)
781 p_ramrod = &p_ent->ramrod.rx_queue_stop;
783 ecore_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
784 ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
785 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
787 /* Cleaning the queue requires the completion to arrive there.
788 * In addition, VFs require the answer to come as eqe to PF.
790 p_ramrod->complete_cqe_flg = (!!(p_rx_cid->opaque_fid ==
791 p_hwfn->hw_info.opaque_fid) &&
792 !eq_completion_only) || cqe_completion;
793 p_ramrod->complete_event_flg = !(p_rx_cid->opaque_fid ==
794 p_hwfn->hw_info.opaque_fid) ||
797 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
798 if (rc != ECORE_SUCCESS)
801 ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
807 ecore_sp_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn,
817 union ecore_qm_pq_params *p_pq_params)
819 struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
820 struct tx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
821 struct ecore_spq_entry *p_ent = OSAL_NULL;
822 enum _ecore_status_t rc = ECORE_NOTIMPL;
823 struct ecore_sp_init_data init_data;
824 u16 pq_id, abs_tx_q_id = 0;
827 /* Store information for the stop */
829 p_tx_cid->opaque_fid = opaque_fid;
831 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
832 if (rc != ECORE_SUCCESS)
835 rc = ecore_fw_l2_queue(p_hwfn, tx_queue_id, &abs_tx_q_id);
836 if (rc != ECORE_SUCCESS)
840 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
842 init_data.opaque_fid = opaque_fid;
843 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
845 rc = ecore_sp_init_request(p_hwfn, &p_ent,
846 ETH_RAMROD_TX_QUEUE_START,
847 PROTOCOLID_ETH, &init_data);
848 if (rc != ECORE_SUCCESS)
851 p_ramrod = &p_ent->ramrod.tx_queue_start;
852 p_ramrod->vport_id = abs_vport_id;
854 p_ramrod->sb_id = OSAL_CPU_TO_LE16(sb);
855 p_ramrod->sb_index = sb_index;
856 p_ramrod->stats_counter_id = stats_id;
858 p_ramrod->queue_zone_id = OSAL_CPU_TO_LE16(abs_tx_q_id);
860 p_ramrod->pbl_size = OSAL_CPU_TO_LE16(pbl_size);
861 p_ramrod->pbl_base_addr.hi = DMA_HI_LE(pbl_addr);
862 p_ramrod->pbl_base_addr.lo = DMA_LO_LE(pbl_addr);
864 pq_id = ecore_get_qm_pq(p_hwfn, PROTOCOLID_ETH, p_pq_params);
865 p_ramrod->qm_pq_id = OSAL_CPU_TO_LE16(pq_id);
867 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
870 enum _ecore_status_t ecore_sp_eth_tx_queue_start(struct ecore_hwfn *p_hwfn,
879 void OSAL_IOMEM * *pp_doorbell)
881 struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
882 union ecore_qm_pq_params pq_params;
883 enum _ecore_status_t rc;
886 if (IS_VF(p_hwfn->p_dev)) {
887 return ecore_vf_pf_txq_start(p_hwfn,
891 pbl_addr, pbl_size, pp_doorbell);
894 rc = ecore_fw_vport(p_hwfn, stats_id, &abs_stats_id);
895 if (rc != ECORE_SUCCESS)
898 OSAL_MEMSET(p_tx_cid, 0, sizeof(*p_tx_cid));
899 OSAL_MEMSET(&pq_params, 0, sizeof(pq_params));
901 /* Allocate a CID for the queue */
902 rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_tx_cid->cid);
903 if (rc != ECORE_SUCCESS) {
904 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
907 p_tx_cid->b_cid_allocated = true;
909 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
910 "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
911 opaque_fid, p_tx_cid->cid, tx_queue_id, vport_id, sb);
913 /* TODO - set tc in the pq_params for multi-cos */
914 rc = ecore_sp_eth_txq_start_ramrod(p_hwfn,
922 pbl_addr, pbl_size, &pq_params);
924 *pp_doorbell = (u8 OSAL_IOMEM *)p_hwfn->doorbells +
925 DB_ADDR(p_tx_cid->cid, DQ_DEMS_LEGACY);
927 if (rc != ECORE_SUCCESS)
928 ecore_sp_release_queue_cid(p_hwfn, p_tx_cid);
933 enum _ecore_status_t ecore_sp_eth_tx_queue_update(struct ecore_hwfn *p_hwfn)
935 return ECORE_NOTIMPL;
938 enum _ecore_status_t ecore_sp_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn,
941 struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
942 struct tx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL;
943 struct ecore_spq_entry *p_ent = OSAL_NULL;
944 enum _ecore_status_t rc = ECORE_NOTIMPL;
945 struct ecore_sp_init_data init_data;
947 if (IS_VF(p_hwfn->p_dev))
948 return ecore_vf_pf_txq_stop(p_hwfn, tx_queue_id);
951 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
952 init_data.cid = p_tx_cid->cid;
953 init_data.opaque_fid = p_tx_cid->opaque_fid;
954 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
956 rc = ecore_sp_init_request(p_hwfn, &p_ent,
957 ETH_RAMROD_TX_QUEUE_STOP,
958 PROTOCOLID_ETH, &init_data);
959 if (rc != ECORE_SUCCESS)
962 p_ramrod = &p_ent->ramrod.tx_queue_stop;
964 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
965 if (rc != ECORE_SUCCESS)
968 ecore_sp_release_queue_cid(p_hwfn, p_tx_cid);
972 static enum eth_filter_action
973 ecore_filter_action(enum ecore_filter_opcode opcode)
975 enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
978 case ECORE_FILTER_ADD:
979 action = ETH_FILTER_ACTION_ADD;
981 case ECORE_FILTER_REMOVE:
982 action = ETH_FILTER_ACTION_REMOVE;
984 case ECORE_FILTER_FLUSH:
985 action = ETH_FILTER_ACTION_REMOVE_ALL;
988 action = MAX_ETH_FILTER_ACTION;
994 static void ecore_set_fw_mac_addr(__le16 *fw_msb,
995 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
997 ((u8 *)fw_msb)[0] = mac[1];
998 ((u8 *)fw_msb)[1] = mac[0];
999 ((u8 *)fw_mid)[0] = mac[3];
1000 ((u8 *)fw_mid)[1] = mac[2];
1001 ((u8 *)fw_lsb)[0] = mac[5];
1002 ((u8 *)fw_lsb)[1] = mac[4];
1005 static enum _ecore_status_t
1006 ecore_filter_ucast_common(struct ecore_hwfn *p_hwfn,
1008 struct ecore_filter_ucast *p_filter_cmd,
1009 struct vport_filter_update_ramrod_data **pp_ramrod,
1010 struct ecore_spq_entry **pp_ent,
1011 enum spq_mode comp_mode,
1012 struct ecore_spq_comp_cb *p_comp_data)
1014 struct vport_filter_update_ramrod_data *p_ramrod;
1015 u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1016 struct eth_filter_cmd *p_first_filter;
1017 struct eth_filter_cmd *p_second_filter;
1018 struct ecore_sp_init_data init_data;
1019 enum eth_filter_action action;
1020 enum _ecore_status_t rc;
1022 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1023 &vport_to_remove_from);
1024 if (rc != ECORE_SUCCESS)
1027 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1029 if (rc != ECORE_SUCCESS)
1033 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1034 init_data.cid = ecore_spq_get_cid(p_hwfn);
1035 init_data.opaque_fid = opaque_fid;
1036 init_data.comp_mode = comp_mode;
1037 init_data.p_comp_data = p_comp_data;
1039 rc = ecore_sp_init_request(p_hwfn, pp_ent,
1040 ETH_RAMROD_FILTERS_UPDATE,
1041 PROTOCOLID_ETH, &init_data);
1042 if (rc != ECORE_SUCCESS)
1045 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1046 p_ramrod = *pp_ramrod;
1047 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1048 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1051 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1052 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1053 "Non-Asic - prevent Tx filters\n");
1054 p_ramrod->filter_cmd_hdr.tx = 0;
1058 switch (p_filter_cmd->opcode) {
1059 case ECORE_FILTER_REPLACE:
1060 case ECORE_FILTER_MOVE:
1061 p_ramrod->filter_cmd_hdr.cmd_cnt = 2;
1064 p_ramrod->filter_cmd_hdr.cmd_cnt = 1;
1068 p_first_filter = &p_ramrod->filter_cmds[0];
1069 p_second_filter = &p_ramrod->filter_cmds[1];
1071 switch (p_filter_cmd->type) {
1072 case ECORE_FILTER_MAC:
1073 p_first_filter->type = ETH_FILTER_TYPE_MAC;
1075 case ECORE_FILTER_VLAN:
1076 p_first_filter->type = ETH_FILTER_TYPE_VLAN;
1078 case ECORE_FILTER_MAC_VLAN:
1079 p_first_filter->type = ETH_FILTER_TYPE_PAIR;
1081 case ECORE_FILTER_INNER_MAC:
1082 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC;
1084 case ECORE_FILTER_INNER_VLAN:
1085 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN;
1087 case ECORE_FILTER_INNER_PAIR:
1088 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR;
1090 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1091 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1093 case ECORE_FILTER_MAC_VNI_PAIR:
1094 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR;
1096 case ECORE_FILTER_VNI:
1097 p_first_filter->type = ETH_FILTER_TYPE_VNI;
1101 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1102 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1103 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1104 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1105 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1106 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR))
1107 ecore_set_fw_mac_addr(&p_first_filter->mac_msb,
1108 &p_first_filter->mac_mid,
1109 &p_first_filter->mac_lsb,
1110 (u8 *)p_filter_cmd->mac);
1112 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1113 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1114 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1115 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1116 p_first_filter->vlan_id = OSAL_CPU_TO_LE16(p_filter_cmd->vlan);
1118 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1119 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1120 (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1121 p_first_filter->vni = OSAL_CPU_TO_LE32(p_filter_cmd->vni);
1123 if (p_filter_cmd->opcode == ECORE_FILTER_MOVE) {
1124 p_second_filter->type = p_first_filter->type;
1125 p_second_filter->mac_msb = p_first_filter->mac_msb;
1126 p_second_filter->mac_mid = p_first_filter->mac_mid;
1127 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1128 p_second_filter->vlan_id = p_first_filter->vlan_id;
1129 p_second_filter->vni = p_first_filter->vni;
1131 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1133 p_first_filter->vport_id = vport_to_remove_from;
1135 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1136 p_second_filter->vport_id = vport_to_add_to;
1137 } else if (p_filter_cmd->opcode == ECORE_FILTER_REPLACE) {
1138 p_first_filter->vport_id = vport_to_add_to;
1139 OSAL_MEMCPY(p_second_filter, p_first_filter,
1140 sizeof(*p_second_filter));
1141 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1142 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1144 action = ecore_filter_action(p_filter_cmd->opcode);
1146 if (action == MAX_ETH_FILTER_ACTION) {
1147 DP_NOTICE(p_hwfn, true,
1148 "%d is not supported yet\n",
1149 p_filter_cmd->opcode);
1150 return ECORE_NOTIMPL;
1153 p_first_filter->action = action;
1154 p_first_filter->vport_id =
1155 (p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1156 vport_to_remove_from : vport_to_add_to;
1159 return ECORE_SUCCESS;
1162 enum _ecore_status_t
1163 ecore_sp_eth_filter_ucast(struct ecore_hwfn *p_hwfn,
1165 struct ecore_filter_ucast *p_filter_cmd,
1166 enum spq_mode comp_mode,
1167 struct ecore_spq_comp_cb *p_comp_data)
1169 struct vport_filter_update_ramrod_data *p_ramrod = OSAL_NULL;
1170 struct ecore_spq_entry *p_ent = OSAL_NULL;
1171 struct eth_filter_cmd_header *p_header;
1172 enum _ecore_status_t rc;
1174 rc = ecore_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1176 comp_mode, p_comp_data);
1177 if (rc != ECORE_SUCCESS) {
1178 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1181 p_header = &p_ramrod->filter_cmd_hdr;
1182 p_header->assert_on_error = p_filter_cmd->assert_on_error;
1184 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1185 if (rc != ECORE_SUCCESS) {
1186 DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1190 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1191 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1192 (p_filter_cmd->opcode == ECORE_FILTER_ADD) ? "ADD" :
1193 ((p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1195 ((p_filter_cmd->opcode == ECORE_FILTER_MOVE) ?
1196 "MOVE" : "REPLACE")),
1197 (p_filter_cmd->type == ECORE_FILTER_MAC) ? "MAC" :
1198 ((p_filter_cmd->type == ECORE_FILTER_VLAN) ?
1199 "VLAN" : "MAC & VLAN"),
1200 p_ramrod->filter_cmd_hdr.cmd_cnt,
1201 p_filter_cmd->is_rx_filter, p_filter_cmd->is_tx_filter);
1202 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1203 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1204 p_filter_cmd->vport_to_add_to,
1205 p_filter_cmd->vport_to_remove_from,
1206 p_filter_cmd->mac[0], p_filter_cmd->mac[1],
1207 p_filter_cmd->mac[2], p_filter_cmd->mac[3],
1208 p_filter_cmd->mac[4], p_filter_cmd->mac[5],
1209 p_filter_cmd->vlan);
1211 return ECORE_SUCCESS;
1214 /*******************************************************************************
1216 * Calculates crc 32 on a buffer
1217 * Note: crc32_length MUST be aligned to 8
1219 ******************************************************************************/
1220 static u32 ecore_calc_crc32c(u8 *crc32_packet,
1221 u32 crc32_length, u32 crc32_seed, u8 complement)
1223 u32 byte = 0, bit = 0, crc32_result = crc32_seed;
1224 u8 msb = 0, current_byte = 0;
1226 if ((crc32_packet == OSAL_NULL) ||
1227 (crc32_length == 0) || ((crc32_length % 8) != 0)) {
1228 return crc32_result;
1231 for (byte = 0; byte < crc32_length; byte++) {
1232 current_byte = crc32_packet[byte];
1233 for (bit = 0; bit < 8; bit++) {
1234 msb = (u8)(crc32_result >> 31);
1235 crc32_result = crc32_result << 1;
1236 if (msb != (0x1 & (current_byte >> bit))) {
1237 crc32_result = crc32_result ^ CRC32_POLY;
1243 return crc32_result;
1246 static OSAL_INLINE u32 ecore_crc32c_le(u32 seed, u8 *mac, u32 len)
1248 u32 packet_buf[2] = { 0 };
1250 OSAL_MEMCPY((u8 *)(&packet_buf[0]), &mac[0], 6);
1251 return ecore_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1254 u8 ecore_mcast_bin_from_mac(u8 *mac)
1256 u32 crc = ecore_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1262 static enum _ecore_status_t
1263 ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn,
1265 struct ecore_filter_mcast *p_filter_cmd,
1266 enum spq_mode comp_mode,
1267 struct ecore_spq_comp_cb *p_comp_data)
1269 struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
1270 unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1271 struct ecore_spq_entry *p_ent = OSAL_NULL;
1272 struct ecore_sp_init_data init_data;
1273 enum _ecore_status_t rc;
1274 u8 abs_vport_id = 0;
1277 rc = ecore_fw_vport(p_hwfn,
1278 (p_filter_cmd->opcode == ECORE_FILTER_ADD) ?
1279 p_filter_cmd->vport_to_add_to :
1280 p_filter_cmd->vport_to_remove_from, &abs_vport_id);
1281 if (rc != ECORE_SUCCESS)
1285 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1286 init_data.cid = ecore_spq_get_cid(p_hwfn);
1287 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1288 init_data.comp_mode = comp_mode;
1289 init_data.p_comp_data = p_comp_data;
1291 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1292 ETH_RAMROD_VPORT_UPDATE,
1293 PROTOCOLID_ETH, &init_data);
1294 if (rc != ECORE_SUCCESS) {
1295 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1299 p_ramrod = &p_ent->ramrod.vport_update;
1300 p_ramrod->common.update_approx_mcast_flg = 1;
1302 /* explicitly clear out the entire vector */
1303 OSAL_MEMSET(&p_ramrod->approx_mcast.bins,
1304 0, sizeof(p_ramrod->approx_mcast.bins));
1305 OSAL_MEMSET(bins, 0, sizeof(unsigned long) *
1306 ETH_MULTICAST_MAC_BINS_IN_REGS);
1308 if (p_filter_cmd->opcode == ECORE_FILTER_ADD) {
1309 /* filter ADD op is explicit set op and it removes
1310 * any existing filters for the vport.
1312 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1315 bit = ecore_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1316 OSAL_SET_BIT(bit, bins);
1319 /* Convert to correct endianity */
1320 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1321 struct vport_update_ramrod_mcast *p_ramrod_bins;
1322 u32 *p_bins = (u32 *)bins;
1324 p_ramrod_bins = &p_ramrod->approx_mcast;
1325 p_ramrod_bins->bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
1329 p_ramrod->common.vport_id = abs_vport_id;
1331 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1332 if (rc != ECORE_SUCCESS)
1333 DP_ERR(p_hwfn, "Multicast filter command failed %d\n", rc);
1338 enum _ecore_status_t
1339 ecore_filter_mcast_cmd(struct ecore_dev *p_dev,
1340 struct ecore_filter_mcast *p_filter_cmd,
1341 enum spq_mode comp_mode,
1342 struct ecore_spq_comp_cb *p_comp_data)
1344 enum _ecore_status_t rc = ECORE_SUCCESS;
1347 /* only ADD and REMOVE operations are supported for multi-cast */
1348 if ((p_filter_cmd->opcode != ECORE_FILTER_ADD &&
1349 (p_filter_cmd->opcode != ECORE_FILTER_REMOVE)) ||
1350 (p_filter_cmd->num_mc_addrs > ECORE_MAX_MC_ADDRS)) {
1354 for_each_hwfn(p_dev, i) {
1355 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1358 ecore_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1362 rc = ecore_sp_eth_filter_mcast(p_hwfn,
1363 p_hwfn->hw_info.opaque_fid,
1365 comp_mode, p_comp_data);
1366 if (rc != ECORE_SUCCESS)
1373 enum _ecore_status_t
1374 ecore_filter_ucast_cmd(struct ecore_dev *p_dev,
1375 struct ecore_filter_ucast *p_filter_cmd,
1376 enum spq_mode comp_mode,
1377 struct ecore_spq_comp_cb *p_comp_data)
1379 enum _ecore_status_t rc = ECORE_SUCCESS;
1382 for_each_hwfn(p_dev, i) {
1383 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1386 rc = ecore_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1390 rc = ecore_sp_eth_filter_ucast(p_hwfn,
1391 p_hwfn->hw_info.opaque_fid,
1393 comp_mode, p_comp_data);
1394 if (rc != ECORE_SUCCESS)
1402 enum _ecore_status_t ecore_sp_vf_start(struct ecore_hwfn *p_hwfn,
1403 u32 concrete_vfid, u16 opaque_vfid)
1405 struct vf_start_ramrod_data *p_ramrod = OSAL_NULL;
1406 struct ecore_spq_entry *p_ent = OSAL_NULL;
1407 enum _ecore_status_t rc = ECORE_NOTIMPL;
1408 struct ecore_sp_init_data init_data;
1411 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1412 init_data.cid = ecore_spq_get_cid(p_hwfn);
1413 init_data.opaque_fid = opaque_vfid;
1414 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
1416 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1417 COMMON_RAMROD_VF_START,
1418 PROTOCOLID_COMMON, &init_data);
1419 if (rc != ECORE_SUCCESS)
1422 p_ramrod = &p_ent->ramrod.vf_start;
1424 p_ramrod->vf_id = GET_FIELD(concrete_vfid, PXP_CONCRETE_FID_VFID);
1425 p_ramrod->opaque_fid = OSAL_CPU_TO_LE16(opaque_vfid);
1427 switch (p_hwfn->hw_info.personality) {
1429 p_ramrod->personality = PERSONALITY_ETH;
1432 DP_NOTICE(p_hwfn, true, "Unknown VF personality %d\n",
1433 p_hwfn->hw_info.personality);
1437 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1440 enum _ecore_status_t ecore_sp_vf_update(struct ecore_hwfn *p_hwfn)
1442 return ECORE_NOTIMPL;
1445 enum _ecore_status_t ecore_sp_vf_stop(struct ecore_hwfn *p_hwfn,
1446 u32 concrete_vfid, u16 opaque_vfid)
1448 enum _ecore_status_t rc = ECORE_NOTIMPL;
1449 struct vf_stop_ramrod_data *p_ramrod = OSAL_NULL;
1450 struct ecore_spq_entry *p_ent = OSAL_NULL;
1451 struct ecore_sp_init_data init_data;
1454 OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1455 init_data.cid = ecore_spq_get_cid(p_hwfn);
1456 init_data.opaque_fid = opaque_vfid;
1457 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
1459 rc = ecore_sp_init_request(p_hwfn, &p_ent,
1460 COMMON_RAMROD_VF_STOP,
1461 PROTOCOLID_COMMON, &init_data);
1462 if (rc != ECORE_SUCCESS)
1465 p_ramrod = &p_ent->ramrod.vf_stop;
1467 p_ramrod->vf_id = GET_FIELD(concrete_vfid, PXP_CONCRETE_FID_VFID);
1469 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1472 /* Statistics related code */
1473 static void __ecore_get_vport_pstats_addrlen(struct ecore_hwfn *p_hwfn,
1474 u32 *p_addr, u32 *p_len,
1477 if (IS_PF(p_hwfn->p_dev)) {
1478 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1479 PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1480 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1482 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1483 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1485 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1486 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1490 static void __ecore_get_vport_pstats(struct ecore_hwfn *p_hwfn,
1491 struct ecore_ptt *p_ptt,
1492 struct ecore_eth_stats *p_stats,
1495 struct eth_pstorm_per_queue_stat pstats;
1496 u32 pstats_addr = 0, pstats_len = 0;
1498 __ecore_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1501 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1502 ecore_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1504 p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1505 p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1506 p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1507 p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1508 p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1509 p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1510 p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts);
1513 static void __ecore_get_vport_tstats(struct ecore_hwfn *p_hwfn,
1514 struct ecore_ptt *p_ptt,
1515 struct ecore_eth_stats *p_stats,
1518 struct tstorm_per_port_stat tstats;
1519 u32 tstats_addr, tstats_len;
1521 if (IS_PF(p_hwfn->p_dev)) {
1522 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1523 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1524 tstats_len = sizeof(struct tstorm_per_port_stat);
1526 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1527 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1529 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1530 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1533 OSAL_MEMSET(&tstats, 0, sizeof(tstats));
1534 ecore_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
1536 p_stats->mftag_filter_discards +=
1537 HILO_64_REGPAIR(tstats.mftag_filter_discard);
1538 p_stats->mac_filter_discards +=
1539 HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1542 static void __ecore_get_vport_ustats_addrlen(struct ecore_hwfn *p_hwfn,
1543 u32 *p_addr, u32 *p_len,
1546 if (IS_PF(p_hwfn->p_dev)) {
1547 *p_addr = BAR0_MAP_REG_USDM_RAM +
1548 USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1549 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1551 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1552 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1554 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1555 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1559 static void __ecore_get_vport_ustats(struct ecore_hwfn *p_hwfn,
1560 struct ecore_ptt *p_ptt,
1561 struct ecore_eth_stats *p_stats,
1564 struct eth_ustorm_per_queue_stat ustats;
1565 u32 ustats_addr = 0, ustats_len = 0;
1567 __ecore_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1570 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1571 ecore_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1573 p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1574 p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1575 p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1576 p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1577 p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1578 p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
1581 static void __ecore_get_vport_mstats_addrlen(struct ecore_hwfn *p_hwfn,
1582 u32 *p_addr, u32 *p_len,
1585 if (IS_PF(p_hwfn->p_dev)) {
1586 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1587 MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1588 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1590 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1591 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1593 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1594 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1598 static void __ecore_get_vport_mstats(struct ecore_hwfn *p_hwfn,
1599 struct ecore_ptt *p_ptt,
1600 struct ecore_eth_stats *p_stats,
1603 struct eth_mstorm_per_queue_stat mstats;
1604 u32 mstats_addr = 0, mstats_len = 0;
1606 __ecore_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1609 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1610 ecore_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
1612 p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard);
1613 p_stats->packet_too_big_discard +=
1614 HILO_64_REGPAIR(mstats.packet_too_big_discard);
1615 p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
1616 p_stats->tpa_coalesced_pkts +=
1617 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1618 p_stats->tpa_coalesced_events +=
1619 HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1620 p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num);
1621 p_stats->tpa_coalesced_bytes +=
1622 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
1625 static void __ecore_get_vport_port_stats(struct ecore_hwfn *p_hwfn,
1626 struct ecore_ptt *p_ptt,
1627 struct ecore_eth_stats *p_stats)
1629 struct port_stats port_stats;
1632 OSAL_MEMSET(&port_stats, 0, sizeof(port_stats));
1634 ecore_memcpy_from(p_hwfn, p_ptt, &port_stats,
1635 p_hwfn->mcp_info->port_addr +
1636 OFFSETOF(struct public_port, stats),
1637 sizeof(port_stats));
1639 p_stats->rx_64_byte_packets += port_stats.pmm.r64;
1640 p_stats->rx_65_to_127_byte_packets += port_stats.pmm.r127;
1641 p_stats->rx_128_to_255_byte_packets += port_stats.pmm.r255;
1642 p_stats->rx_256_to_511_byte_packets += port_stats.pmm.r511;
1643 p_stats->rx_512_to_1023_byte_packets += port_stats.pmm.r1023;
1644 p_stats->rx_1024_to_1518_byte_packets += port_stats.pmm.r1518;
1645 p_stats->rx_1519_to_1522_byte_packets += port_stats.pmm.r1522;
1646 p_stats->rx_1519_to_2047_byte_packets += port_stats.pmm.r2047;
1647 p_stats->rx_2048_to_4095_byte_packets += port_stats.pmm.r4095;
1648 p_stats->rx_4096_to_9216_byte_packets += port_stats.pmm.r9216;
1649 p_stats->rx_9217_to_16383_byte_packets += port_stats.pmm.r16383;
1650 p_stats->rx_crc_errors += port_stats.pmm.rfcs;
1651 p_stats->rx_mac_crtl_frames += port_stats.pmm.rxcf;
1652 p_stats->rx_pause_frames += port_stats.pmm.rxpf;
1653 p_stats->rx_pfc_frames += port_stats.pmm.rxpp;
1654 p_stats->rx_align_errors += port_stats.pmm.raln;
1655 p_stats->rx_carrier_errors += port_stats.pmm.rfcr;
1656 p_stats->rx_oversize_packets += port_stats.pmm.rovr;
1657 p_stats->rx_jabbers += port_stats.pmm.rjbr;
1658 p_stats->rx_undersize_packets += port_stats.pmm.rund;
1659 p_stats->rx_fragments += port_stats.pmm.rfrg;
1660 p_stats->tx_64_byte_packets += port_stats.pmm.t64;
1661 p_stats->tx_65_to_127_byte_packets += port_stats.pmm.t127;
1662 p_stats->tx_128_to_255_byte_packets += port_stats.pmm.t255;
1663 p_stats->tx_256_to_511_byte_packets += port_stats.pmm.t511;
1664 p_stats->tx_512_to_1023_byte_packets += port_stats.pmm.t1023;
1665 p_stats->tx_1024_to_1518_byte_packets += port_stats.pmm.t1518;
1666 p_stats->tx_1519_to_2047_byte_packets += port_stats.pmm.t2047;
1667 p_stats->tx_2048_to_4095_byte_packets += port_stats.pmm.t4095;
1668 p_stats->tx_4096_to_9216_byte_packets += port_stats.pmm.t9216;
1669 p_stats->tx_9217_to_16383_byte_packets += port_stats.pmm.t16383;
1670 p_stats->tx_pause_frames += port_stats.pmm.txpf;
1671 p_stats->tx_pfc_frames += port_stats.pmm.txpp;
1672 p_stats->tx_lpi_entry_count += port_stats.pmm.tlpiec;
1673 p_stats->tx_total_collisions += port_stats.pmm.tncl;
1674 p_stats->rx_mac_bytes += port_stats.pmm.rbyte;
1675 p_stats->rx_mac_uc_packets += port_stats.pmm.rxuca;
1676 p_stats->rx_mac_mc_packets += port_stats.pmm.rxmca;
1677 p_stats->rx_mac_bc_packets += port_stats.pmm.rxbca;
1678 p_stats->rx_mac_frames_ok += port_stats.pmm.rxpok;
1679 p_stats->tx_mac_bytes += port_stats.pmm.tbyte;
1680 p_stats->tx_mac_uc_packets += port_stats.pmm.txuca;
1681 p_stats->tx_mac_mc_packets += port_stats.pmm.txmca;
1682 p_stats->tx_mac_bc_packets += port_stats.pmm.txbca;
1683 p_stats->tx_mac_ctrl_frames += port_stats.pmm.txcf;
1684 for (j = 0; j < 8; j++) {
1685 p_stats->brb_truncates += port_stats.brb.brb_truncate[j];
1686 p_stats->brb_discards += port_stats.brb.brb_discard[j];
1690 void __ecore_get_vport_stats(struct ecore_hwfn *p_hwfn,
1691 struct ecore_ptt *p_ptt,
1692 struct ecore_eth_stats *stats,
1693 u16 statistics_bin, bool b_get_port_stats)
1695 __ecore_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1696 __ecore_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1697 __ecore_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1698 __ecore_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1701 /* Avoid getting PORT stats for emulation. */
1702 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1706 if (b_get_port_stats && p_hwfn->mcp_info)
1707 __ecore_get_vport_port_stats(p_hwfn, p_ptt, stats);
1710 static void _ecore_get_vport_stats(struct ecore_dev *p_dev,
1711 struct ecore_eth_stats *stats)
1716 OSAL_MEMSET(stats, 0, sizeof(*stats));
1718 for_each_hwfn(p_dev, i) {
1719 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1720 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1721 ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1724 /* The main vport index is relative first */
1725 if (ecore_fw_vport(p_hwfn, 0, &fw_vport)) {
1726 DP_ERR(p_hwfn, "No vport available!\n");
1731 if (IS_PF(p_dev) && !p_ptt) {
1732 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1736 __ecore_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1737 IS_PF(p_dev) ? true : false);
1741 ecore_ptt_release(p_hwfn, p_ptt);
1745 void ecore_get_vport_stats(struct ecore_dev *p_dev,
1746 struct ecore_eth_stats *stats)
1751 OSAL_MEMSET(stats, 0, sizeof(*stats));
1755 _ecore_get_vport_stats(p_dev, stats);
1757 if (!p_dev->reset_stats)
1760 /* Reduce the statistics baseline */
1761 for (i = 0; i < sizeof(struct ecore_eth_stats) / sizeof(u64); i++)
1762 ((u64 *)stats)[i] -= ((u64 *)p_dev->reset_stats)[i];
1765 /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1766 void ecore_reset_vport_stats(struct ecore_dev *p_dev)
1770 for_each_hwfn(p_dev, i) {
1771 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1772 struct eth_mstorm_per_queue_stat mstats;
1773 struct eth_ustorm_per_queue_stat ustats;
1774 struct eth_pstorm_per_queue_stat pstats;
1775 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1776 ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1777 u32 addr = 0, len = 0;
1779 if (IS_PF(p_dev) && !p_ptt) {
1780 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1784 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1785 __ecore_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
1786 ecore_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
1788 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1789 __ecore_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
1790 ecore_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
1792 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1793 __ecore_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
1794 ecore_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
1797 ecore_ptt_release(p_hwfn, p_ptt);
1800 /* PORT statistics are not necessarily reset, so we need to
1801 * read and create a baseline for future statistics.
1803 if (!p_dev->reset_stats)
1804 DP_INFO(p_dev, "Reset stats not allocated\n");
1806 _ecore_get_vport_stats(p_dev, p_dev->reset_stats);