2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #include "qede_ethdev.h"
10 #include <rte_alarm.h>
11 #include <rte_version.h>
14 static const struct qed_eth_ops *qed_ops;
15 static int64_t timer_period = 1;
17 /* VXLAN tunnel classification mapping */
18 const struct _qede_vxlan_tunn_types {
19 uint16_t rte_filter_type;
20 enum ecore_filter_ucast_type qede_type;
21 enum ecore_tunn_clss qede_tunn_clss;
23 } qede_tunn_types[] = {
25 ETH_TUNNEL_FILTER_OMAC,
27 ECORE_TUNN_CLSS_MAC_VLAN,
31 ETH_TUNNEL_FILTER_TENID,
33 ECORE_TUNN_CLSS_MAC_VNI,
37 ETH_TUNNEL_FILTER_IMAC,
38 ECORE_FILTER_INNER_MAC,
39 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
43 ETH_TUNNEL_FILTER_IVLAN,
44 ECORE_FILTER_INNER_VLAN,
45 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
49 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
50 ECORE_FILTER_MAC_VNI_PAIR,
51 ECORE_TUNN_CLSS_MAC_VNI,
55 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
58 "outer-mac and inner-mac"
61 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
64 "outer-mac and inner-vlan"
67 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
68 ECORE_FILTER_INNER_MAC_VNI_PAIR,
69 ECORE_TUNN_CLSS_INNER_MAC_VNI,
73 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
79 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
80 ECORE_FILTER_INNER_PAIR,
81 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
82 "inner-mac and inner-vlan",
85 ETH_TUNNEL_FILTER_OIP,
91 ETH_TUNNEL_FILTER_IIP,
97 RTE_TUNNEL_FILTER_IMAC_IVLAN,
103 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
109 RTE_TUNNEL_FILTER_IMAC_TENID,
115 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
122 struct rte_qede_xstats_name_off {
123 char name[RTE_ETH_XSTATS_NAME_SIZE];
127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
129 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
130 {"rx_multicast_bytes",
131 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
132 {"rx_broadcast_bytes",
133 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
134 {"rx_unicast_packets",
135 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
136 {"rx_multicast_packets",
137 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
138 {"rx_broadcast_packets",
139 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
142 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
143 {"tx_multicast_bytes",
144 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
145 {"tx_broadcast_bytes",
146 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
147 {"tx_unicast_packets",
148 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
149 {"tx_multicast_packets",
150 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
151 {"tx_broadcast_packets",
152 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
154 {"rx_64_byte_packets",
155 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
156 {"rx_65_to_127_byte_packets",
157 offsetof(struct ecore_eth_stats_common,
158 rx_65_to_127_byte_packets)},
159 {"rx_128_to_255_byte_packets",
160 offsetof(struct ecore_eth_stats_common,
161 rx_128_to_255_byte_packets)},
162 {"rx_256_to_511_byte_packets",
163 offsetof(struct ecore_eth_stats_common,
164 rx_256_to_511_byte_packets)},
165 {"rx_512_to_1023_byte_packets",
166 offsetof(struct ecore_eth_stats_common,
167 rx_512_to_1023_byte_packets)},
168 {"rx_1024_to_1518_byte_packets",
169 offsetof(struct ecore_eth_stats_common,
170 rx_1024_to_1518_byte_packets)},
171 {"tx_64_byte_packets",
172 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
173 {"tx_65_to_127_byte_packets",
174 offsetof(struct ecore_eth_stats_common,
175 tx_65_to_127_byte_packets)},
176 {"tx_128_to_255_byte_packets",
177 offsetof(struct ecore_eth_stats_common,
178 tx_128_to_255_byte_packets)},
179 {"tx_256_to_511_byte_packets",
180 offsetof(struct ecore_eth_stats_common,
181 tx_256_to_511_byte_packets)},
182 {"tx_512_to_1023_byte_packets",
183 offsetof(struct ecore_eth_stats_common,
184 tx_512_to_1023_byte_packets)},
185 {"tx_1024_to_1518_byte_packets",
186 offsetof(struct ecore_eth_stats_common,
187 tx_1024_to_1518_byte_packets)},
189 {"rx_mac_crtl_frames",
190 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
191 {"tx_mac_control_frames",
192 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
194 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
196 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
197 {"rx_priority_flow_control_frames",
198 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
199 {"tx_priority_flow_control_frames",
200 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
203 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
205 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
206 {"rx_carrier_errors",
207 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
208 {"rx_oversize_packet_errors",
209 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
211 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
212 {"rx_undersize_packet_errors",
213 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
214 {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
215 {"rx_host_buffer_not_available",
216 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
217 /* Number of packets discarded because they are bigger than MTU */
218 {"rx_packet_too_big_discards",
219 offsetof(struct ecore_eth_stats_common,
220 packet_too_big_discard)},
221 {"rx_ttl_zero_discards",
222 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
223 {"rx_multi_function_tag_filter_discards",
224 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
225 {"rx_mac_filter_discards",
226 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
227 {"rx_hw_buffer_truncates",
228 offsetof(struct ecore_eth_stats_common, brb_truncates)},
229 {"rx_hw_buffer_discards",
230 offsetof(struct ecore_eth_stats_common, brb_discards)},
231 {"tx_error_drop_packets",
232 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
234 {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
235 {"rx_mac_unicast_packets",
236 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
237 {"rx_mac_multicast_packets",
238 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
239 {"rx_mac_broadcast_packets",
240 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
242 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
243 {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
244 {"tx_mac_unicast_packets",
245 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
246 {"tx_mac_multicast_packets",
247 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
248 {"tx_mac_broadcast_packets",
249 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
251 {"lro_coalesced_packets",
252 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
253 {"lro_coalesced_events",
254 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
256 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
257 {"lro_not_coalesced_packets",
258 offsetof(struct ecore_eth_stats_common,
259 tpa_not_coalesced_pkts)},
260 {"lro_coalesced_bytes",
261 offsetof(struct ecore_eth_stats_common,
262 tpa_coalesced_bytes)},
265 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
266 {"rx_1519_to_1522_byte_packets",
267 offsetof(struct ecore_eth_stats, bb) +
268 offsetof(struct ecore_eth_stats_bb,
269 rx_1519_to_1522_byte_packets)},
270 {"rx_1519_to_2047_byte_packets",
271 offsetof(struct ecore_eth_stats, bb) +
272 offsetof(struct ecore_eth_stats_bb,
273 rx_1519_to_2047_byte_packets)},
274 {"rx_2048_to_4095_byte_packets",
275 offsetof(struct ecore_eth_stats, bb) +
276 offsetof(struct ecore_eth_stats_bb,
277 rx_2048_to_4095_byte_packets)},
278 {"rx_4096_to_9216_byte_packets",
279 offsetof(struct ecore_eth_stats, bb) +
280 offsetof(struct ecore_eth_stats_bb,
281 rx_4096_to_9216_byte_packets)},
282 {"rx_9217_to_16383_byte_packets",
283 offsetof(struct ecore_eth_stats, bb) +
284 offsetof(struct ecore_eth_stats_bb,
285 rx_9217_to_16383_byte_packets)},
287 {"tx_1519_to_2047_byte_packets",
288 offsetof(struct ecore_eth_stats, bb) +
289 offsetof(struct ecore_eth_stats_bb,
290 tx_1519_to_2047_byte_packets)},
291 {"tx_2048_to_4095_byte_packets",
292 offsetof(struct ecore_eth_stats, bb) +
293 offsetof(struct ecore_eth_stats_bb,
294 tx_2048_to_4095_byte_packets)},
295 {"tx_4096_to_9216_byte_packets",
296 offsetof(struct ecore_eth_stats, bb) +
297 offsetof(struct ecore_eth_stats_bb,
298 tx_4096_to_9216_byte_packets)},
299 {"tx_9217_to_16383_byte_packets",
300 offsetof(struct ecore_eth_stats, bb) +
301 offsetof(struct ecore_eth_stats_bb,
302 tx_9217_to_16383_byte_packets)},
304 {"tx_lpi_entry_count",
305 offsetof(struct ecore_eth_stats, bb) +
306 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
307 {"tx_total_collisions",
308 offsetof(struct ecore_eth_stats, bb) +
309 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
312 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
313 {"rx_1519_to_max_byte_packets",
314 offsetof(struct ecore_eth_stats, ah) +
315 offsetof(struct ecore_eth_stats_ah,
316 rx_1519_to_max_byte_packets)},
317 {"tx_1519_to_max_byte_packets",
318 offsetof(struct ecore_eth_stats, ah) +
319 offsetof(struct ecore_eth_stats_ah,
320 tx_1519_to_max_byte_packets)},
323 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
325 offsetof(struct qede_rx_queue, rx_segs)},
327 offsetof(struct qede_rx_queue, rx_hw_errors)},
328 {"rx_q_allocation_errors",
329 offsetof(struct qede_rx_queue, rx_alloc_errors)}
332 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
334 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
338 qede_interrupt_handler(void *param)
340 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
341 struct qede_dev *qdev = eth_dev->data->dev_private;
342 struct ecore_dev *edev = &qdev->edev;
344 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
345 if (rte_intr_enable(eth_dev->intr_handle))
346 DP_ERR(edev, "rte_intr_enable failed\n");
350 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
352 rte_memcpy(&qdev->dev_info, info, sizeof(*info));
356 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
357 static void qede_print_adapter_info(struct qede_dev *qdev)
359 struct ecore_dev *edev = &qdev->edev;
360 struct qed_dev_info *info = &qdev->dev_info.common;
361 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
362 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
364 DP_INFO(edev, "*********************************\n");
365 DP_INFO(edev, " DPDK version:%s\n", rte_version());
366 DP_INFO(edev, " Chip details : %s %c%d\n",
367 ECORE_IS_BB(edev) ? "BB" : "AH",
368 'A' + edev->chip_rev,
369 (int)edev->chip_metal);
370 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
371 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
372 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
373 ver_str, QEDE_PMD_VERSION);
374 DP_INFO(edev, " Driver version : %s\n", drv_ver);
375 DP_INFO(edev, " Firmware version : %s\n", ver_str);
377 snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
379 (info->mfw_rev >> 24) & 0xff,
380 (info->mfw_rev >> 16) & 0xff,
381 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
382 DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
383 DP_INFO(edev, " Firmware file : %s\n", fw_file);
384 DP_INFO(edev, "*********************************\n");
389 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
391 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
392 struct ecore_sp_vport_start_params params;
393 struct ecore_hwfn *p_hwfn;
397 memset(¶ms, 0, sizeof(params));
400 /* @DPDK - Disable FW placement */
401 params.zero_placement_offset = 1;
402 for_each_hwfn(edev, i) {
403 p_hwfn = &edev->hwfns[i];
404 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
405 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
406 rc = ecore_sp_vport_start(p_hwfn, ¶ms);
407 if (rc != ECORE_SUCCESS) {
408 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
412 ecore_reset_vport_stats(edev);
413 DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
419 qede_stop_vport(struct ecore_dev *edev)
421 struct ecore_hwfn *p_hwfn;
427 for_each_hwfn(edev, i) {
428 p_hwfn = &edev->hwfns[i];
429 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
431 if (rc != ECORE_SUCCESS) {
432 DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
440 /* Activate or deactivate vport via vport-update */
441 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
443 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
444 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
445 struct ecore_sp_vport_update_params params;
446 struct ecore_hwfn *p_hwfn;
450 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
452 params.update_vport_active_rx_flg = 1;
453 params.update_vport_active_tx_flg = 1;
454 params.vport_active_rx_flg = flg;
455 params.vport_active_tx_flg = flg;
456 #ifndef RTE_LIBRTE_QEDE_VF_TX_SWITCH
458 params.update_tx_switching_flg = 1;
459 params.tx_switching_flg = !flg;
462 for_each_hwfn(edev, i) {
463 p_hwfn = &edev->hwfns[i];
464 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
465 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
466 ECORE_SPQ_MODE_EBLOCK, NULL);
467 if (rc != ECORE_SUCCESS) {
468 DP_ERR(edev, "Failed to update vport\n");
472 DP_INFO(edev, "vport %s VF tx-switch %s\n", flg ? "activated" : "deactivated",
473 params.tx_switching_flg ? "enabled" : "disabled");
478 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
479 uint16_t mtu, bool enable)
481 /* Enable LRO in split mode */
482 sge_tpa_params->tpa_ipv4_en_flg = enable;
483 sge_tpa_params->tpa_ipv6_en_flg = enable;
484 sge_tpa_params->tpa_ipv4_tunn_en_flg = false;
485 sge_tpa_params->tpa_ipv6_tunn_en_flg = false;
486 /* set if tpa enable changes */
487 sge_tpa_params->update_tpa_en_flg = 1;
488 /* set if tpa parameters should be handled */
489 sge_tpa_params->update_tpa_param_flg = enable;
491 sge_tpa_params->max_buffers_per_cqe = 20;
492 /* Enable TPA in split mode. In this mode each TPA segment
493 * starts on the new BD, so there is one BD per segment.
495 sge_tpa_params->tpa_pkt_split_flg = 1;
496 sge_tpa_params->tpa_hdr_data_split_flg = 0;
497 sge_tpa_params->tpa_gro_consistent_flg = 0;
498 sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
499 sge_tpa_params->tpa_max_size = 0x7FFF;
500 sge_tpa_params->tpa_min_size_to_start = mtu / 2;
501 sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
504 /* Enable/disable LRO via vport-update */
505 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
507 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
508 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
509 struct ecore_sp_vport_update_params params;
510 struct ecore_sge_tpa_params tpa_params;
511 struct ecore_hwfn *p_hwfn;
515 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
516 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
517 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
519 params.sge_tpa_params = &tpa_params;
520 for_each_hwfn(edev, i) {
521 p_hwfn = &edev->hwfns[i];
522 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
523 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
524 ECORE_SPQ_MODE_EBLOCK, NULL);
525 if (rc != ECORE_SUCCESS) {
526 DP_ERR(edev, "Failed to update LRO\n");
530 qdev->enable_lro = flg;
531 DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
536 /* Update MTU via vport-update without doing port restart.
537 * The vport must be deactivated before calling this API.
539 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
541 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
542 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
543 struct ecore_sp_vport_update_params params;
544 struct ecore_hwfn *p_hwfn;
548 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
552 for_each_hwfn(edev, i) {
553 p_hwfn = &edev->hwfns[i];
554 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
555 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
556 ECORE_SPQ_MODE_EBLOCK, NULL);
557 if (rc != ECORE_SUCCESS) {
558 DP_ERR(edev, "Failed to update MTU\n");
562 DP_INFO(edev, "MTU updated to %u\n", mtu);
567 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
569 memset(ucast, 0, sizeof(struct ecore_filter_ucast));
570 ucast->is_rx_filter = true;
571 ucast->is_tx_filter = true;
572 /* ucast->assert_on_error = true; - For debug */
576 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
577 enum qed_filter_rx_mode_type type)
579 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
580 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
581 struct ecore_filter_accept_flags flags;
583 memset(&flags, 0, sizeof(flags));
585 flags.update_rx_mode_config = 1;
586 flags.update_tx_mode_config = 1;
587 flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
588 ECORE_ACCEPT_MCAST_MATCHED |
591 flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
592 ECORE_ACCEPT_MCAST_MATCHED |
595 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
596 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
598 flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
599 DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
601 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
602 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
603 } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
604 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
605 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
606 ECORE_ACCEPT_MCAST_UNMATCHED;
609 return ecore_filter_accept_cmd(edev, 0, flags, false, false,
610 ECORE_SPQ_MODE_CB, NULL);
614 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
615 bool enable, bool mask)
617 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
618 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
619 enum _ecore_status_t rc = ECORE_INVAL;
620 struct ecore_ptt *p_ptt;
621 struct ecore_tunnel_info tunn;
622 struct ecore_hwfn *p_hwfn;
625 memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
626 tunn.vxlan.b_update_mode = enable;
627 tunn.vxlan.b_mode_enabled = mask;
628 tunn.b_update_rx_cls = true;
629 tunn.b_update_tx_cls = true;
630 tunn.vxlan.tun_cls = clss;
632 for_each_hwfn(edev, i) {
633 p_hwfn = &edev->hwfns[i];
635 p_ptt = ecore_ptt_acquire(p_hwfn);
641 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
642 &tunn, ECORE_SPQ_MODE_CB, NULL);
643 if (rc != ECORE_SUCCESS) {
644 DP_ERR(edev, "Failed to update tunn_clss %u\n",
647 ecore_ptt_release(p_hwfn, p_ptt);
652 if (rc == ECORE_SUCCESS) {
653 qdev->vxlan.enable = enable;
654 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
655 DP_INFO(edev, "vxlan is %s\n", enable ? "enabled" : "disabled");
662 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
665 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
666 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
667 struct qede_ucast_entry *tmp = NULL;
668 struct qede_ucast_entry *u;
669 struct ether_addr *mac_addr;
671 mac_addr = (struct ether_addr *)ucast->mac;
673 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
674 if ((memcmp(mac_addr, &tmp->mac,
675 ETHER_ADDR_LEN) == 0) &&
676 ucast->vni == tmp->vni &&
677 ucast->vlan == tmp->vlan) {
678 DP_ERR(edev, "Unicast MAC is already added"
679 " with vlan = %u, vni = %u\n",
680 ucast->vlan, ucast->vni);
684 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
685 RTE_CACHE_LINE_SIZE);
687 DP_ERR(edev, "Did not allocate memory for ucast\n");
690 ether_addr_copy(mac_addr, &u->mac);
691 u->vlan = ucast->vlan;
693 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
696 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
697 if ((memcmp(mac_addr, &tmp->mac,
698 ETHER_ADDR_LEN) == 0) &&
699 ucast->vlan == tmp->vlan &&
700 ucast->vni == tmp->vni)
704 DP_INFO(edev, "Unicast MAC is not found\n");
707 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
715 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
718 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
719 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
720 struct ether_addr *mac_addr;
721 struct qede_mcast_entry *tmp = NULL;
722 struct qede_mcast_entry *m;
724 mac_addr = (struct ether_addr *)mcast->mac;
726 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
727 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
729 "Multicast MAC is already added\n");
733 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
734 RTE_CACHE_LINE_SIZE);
737 "Did not allocate memory for mcast\n");
740 ether_addr_copy(mac_addr, &m->mac);
741 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
744 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
745 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
749 DP_INFO(edev, "Multicast mac is not found\n");
752 SLIST_REMOVE(&qdev->mc_list_head, tmp,
753 qede_mcast_entry, list);
760 static enum _ecore_status_t
761 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
764 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
765 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
766 enum _ecore_status_t rc;
767 struct ecore_filter_mcast mcast;
768 struct qede_mcast_entry *tmp;
772 if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
774 if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
776 "Mcast filter table limit exceeded, "
777 "Please enable mcast promisc mode\n");
781 rc = qede_mcast_filter(eth_dev, ucast, add);
783 DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
784 memset(&mcast, 0, sizeof(mcast));
785 mcast.num_mc_addrs = qdev->num_mc_addr;
786 mcast.opcode = ECORE_FILTER_ADD;
787 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
788 ether_addr_copy(&tmp->mac,
789 (struct ether_addr *)&mcast.mac[j]);
792 rc = ecore_filter_mcast_cmd(edev, &mcast,
793 ECORE_SPQ_MODE_CB, NULL);
795 if (rc != ECORE_SUCCESS) {
796 DP_ERR(edev, "Failed to add multicast filter"
797 " rc = %d, op = %d\n", rc, add);
799 } else { /* Unicast */
801 if (qdev->num_uc_addr >=
802 qdev->dev_info.num_mac_filters) {
804 "Ucast filter table limit exceeded,"
805 " Please enable promisc mode\n");
809 rc = qede_ucast_filter(eth_dev, ucast, add);
811 rc = ecore_filter_ucast_cmd(edev, ucast,
812 ECORE_SPQ_MODE_CB, NULL);
813 if (rc != ECORE_SUCCESS) {
814 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
823 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
824 __rte_unused uint32_t index, __rte_unused uint32_t pool)
826 struct ecore_filter_ucast ucast;
829 qede_set_ucast_cmn_params(&ucast);
830 ucast.type = ECORE_FILTER_MAC;
831 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
832 re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
837 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
839 struct qede_dev *qdev = eth_dev->data->dev_private;
840 struct ecore_dev *edev = &qdev->edev;
841 struct ecore_filter_ucast ucast;
843 PMD_INIT_FUNC_TRACE(edev);
845 if (index >= qdev->dev_info.num_mac_filters) {
846 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
847 index, qdev->dev_info.num_mac_filters);
851 qede_set_ucast_cmn_params(&ucast);
852 ucast.opcode = ECORE_FILTER_REMOVE;
853 ucast.type = ECORE_FILTER_MAC;
855 /* Use the index maintained by rte */
856 ether_addr_copy(ð_dev->data->mac_addrs[index],
857 (struct ether_addr *)&ucast.mac);
859 ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
863 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
865 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
866 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
868 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
869 mac_addr->addr_bytes)) {
870 DP_ERR(edev, "Setting MAC address is not allowed\n");
871 ether_addr_copy(&qdev->primary_mac,
872 ð_dev->data->mac_addrs[0]);
876 qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
879 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
881 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
882 struct ecore_sp_vport_update_params params;
883 struct ecore_hwfn *p_hwfn;
887 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
889 params.update_accept_any_vlan_flg = 1;
890 params.accept_any_vlan = flg;
891 for_each_hwfn(edev, i) {
892 p_hwfn = &edev->hwfns[i];
893 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
894 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
895 ECORE_SPQ_MODE_EBLOCK, NULL);
896 if (rc != ECORE_SUCCESS) {
897 DP_ERR(edev, "Failed to configure accept-any-vlan\n");
902 DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
905 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
907 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
908 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
909 struct ecore_sp_vport_update_params params;
910 struct ecore_hwfn *p_hwfn;
914 memset(¶ms, 0, sizeof(struct ecore_sp_vport_update_params));
916 params.update_inner_vlan_removal_flg = 1;
917 params.inner_vlan_removal_flg = flg;
918 for_each_hwfn(edev, i) {
919 p_hwfn = &edev->hwfns[i];
920 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
921 rc = ecore_sp_vport_update(p_hwfn, ¶ms,
922 ECORE_SPQ_MODE_EBLOCK, NULL);
923 if (rc != ECORE_SUCCESS) {
924 DP_ERR(edev, "Failed to update vport\n");
929 DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
933 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
934 uint16_t vlan_id, int on)
936 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
937 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
938 struct qed_dev_eth_info *dev_info = &qdev->dev_info;
939 struct qede_vlan_entry *tmp = NULL;
940 struct qede_vlan_entry *vlan;
941 struct ecore_filter_ucast ucast;
945 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
946 DP_ERR(edev, "Reached max VLAN filter limit"
947 " enabling accept_any_vlan\n");
948 qede_config_accept_any_vlan(qdev, true);
952 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
953 if (tmp->vid == vlan_id) {
954 DP_ERR(edev, "VLAN %u already configured\n",
960 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
961 RTE_CACHE_LINE_SIZE);
964 DP_ERR(edev, "Did not allocate memory for VLAN\n");
968 qede_set_ucast_cmn_params(&ucast);
969 ucast.opcode = ECORE_FILTER_ADD;
970 ucast.type = ECORE_FILTER_VLAN;
971 ucast.vlan = vlan_id;
972 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
975 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
980 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
981 qdev->configured_vlans++;
982 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
983 vlan_id, qdev->configured_vlans);
986 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
987 if (tmp->vid == vlan_id)
992 if (qdev->configured_vlans == 0) {
994 "No VLAN filters configured yet\n");
998 DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
1002 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
1004 qede_set_ucast_cmn_params(&ucast);
1005 ucast.opcode = ECORE_FILTER_REMOVE;
1006 ucast.type = ECORE_FILTER_VLAN;
1007 ucast.vlan = vlan_id;
1008 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1011 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1014 qdev->configured_vlans--;
1015 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1016 vlan_id, qdev->configured_vlans);
1023 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1025 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1026 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1027 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1029 if (mask & ETH_VLAN_STRIP_MASK) {
1030 if (rxmode->hw_vlan_strip)
1031 (void)qede_vlan_stripping(eth_dev, 1);
1033 (void)qede_vlan_stripping(eth_dev, 0);
1036 if (mask & ETH_VLAN_FILTER_MASK) {
1037 /* VLAN filtering kicks in when a VLAN is added */
1038 if (rxmode->hw_vlan_filter) {
1039 qede_vlan_filter_set(eth_dev, 0, 1);
1041 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1043 " Please remove existing VLAN filters"
1044 " before disabling VLAN filtering\n");
1045 /* Signal app that VLAN filtering is still
1048 rxmode->hw_vlan_filter = true;
1050 qede_vlan_filter_set(eth_dev, 0, 0);
1055 if (mask & ETH_VLAN_EXTEND_MASK)
1056 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
1057 " and classification is based on outer tag only\n");
1059 DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
1060 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
1065 static void qede_prandom_bytes(uint32_t *buff)
1069 srand((unsigned int)time(NULL));
1070 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1074 int qede_config_rss(struct rte_eth_dev *eth_dev)
1076 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1077 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
1078 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1080 uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1081 struct rte_eth_rss_reta_entry64 reta_conf[2];
1082 struct rte_eth_rss_conf rss_conf;
1083 uint32_t i, id, pos, q;
1085 rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1086 if (!rss_conf.rss_key) {
1087 DP_INFO(edev, "Applying driver default key\n");
1088 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1089 qede_prandom_bytes(&def_rss_key[0]);
1090 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1093 /* Configure RSS hash */
1094 if (qede_rss_hash_update(eth_dev, &rss_conf))
1097 /* Configure default RETA */
1098 memset(reta_conf, 0, sizeof(reta_conf));
1099 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1100 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1102 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1103 id = i / RTE_RETA_GROUP_SIZE;
1104 pos = i % RTE_RETA_GROUP_SIZE;
1105 q = i % QEDE_RSS_COUNT(qdev);
1106 reta_conf[id].reta[pos] = q;
1108 if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1109 ECORE_RSS_IND_TABLE_SIZE))
1115 static void qede_fastpath_start(struct ecore_dev *edev)
1117 struct ecore_hwfn *p_hwfn;
1120 for_each_hwfn(edev, i) {
1121 p_hwfn = &edev->hwfns[i];
1122 ecore_hw_start_fastpath(p_hwfn);
1126 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1128 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1129 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1130 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1132 PMD_INIT_FUNC_TRACE(edev);
1134 /* Update MTU only if it has changed */
1135 if (qdev->mtu != qdev->new_mtu) {
1136 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1138 qdev->mtu = qdev->new_mtu;
1141 /* Configure TPA parameters */
1142 if (rxmode->enable_lro) {
1143 if (qede_enable_tpa(eth_dev, true))
1145 /* Enable scatter mode for LRO */
1146 if (!rxmode->enable_scatter)
1147 eth_dev->data->scattered_rx = 1;
1151 if (qede_start_queues(eth_dev))
1154 /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1155 * enabling RSS. Hence RSS configuration is deferred upto this point.
1156 * Also, we would like to retain similar behavior in PF case, so we
1157 * don't do PF/VF specific check here.
1159 if (rxmode->mq_mode == ETH_MQ_RX_RSS)
1160 if (qede_config_rss(eth_dev))
1164 if (qede_activate_vport(eth_dev, true))
1167 /* Bring-up the link */
1168 qede_dev_set_link_state(eth_dev, true);
1170 /* Update link status */
1171 qede_link_update(eth_dev, 0);
1173 /* Start/resume traffic */
1174 qede_fastpath_start(edev);
1176 DP_INFO(edev, "Device started\n");
1180 DP_ERR(edev, "Device start fails\n");
1181 return -1; /* common error code is < 0 */
1184 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1186 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1187 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1189 PMD_INIT_FUNC_TRACE(edev);
1192 if (qede_activate_vport(eth_dev, false))
1195 if (qdev->enable_lro)
1196 qede_enable_tpa(eth_dev, false);
1199 qede_stop_queues(eth_dev);
1201 /* Disable traffic */
1202 ecore_hw_stop_fastpath(edev); /* TBD - loop */
1204 /* Bring the link down */
1205 qede_dev_set_link_state(eth_dev, false);
1207 DP_INFO(edev, "Device is stopped\n");
1210 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1212 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1213 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1214 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
1217 PMD_INIT_FUNC_TRACE(edev);
1219 /* Check requirements for 100G mode */
1220 if (ECORE_IS_CMT(edev)) {
1221 if (eth_dev->data->nb_rx_queues < 2 ||
1222 eth_dev->data->nb_tx_queues < 2) {
1223 DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1227 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1228 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1230 "100G mode needs even no. of RX/TX queues\n");
1235 /* Sanity checks and throw warnings */
1236 if (rxmode->enable_scatter)
1237 eth_dev->data->scattered_rx = 1;
1239 if (!rxmode->hw_strip_crc)
1240 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
1242 if (!rxmode->hw_ip_checksum)
1243 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
1245 if (rxmode->header_split)
1246 DP_INFO(edev, "Header split enable is not supported\n");
1247 if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode ==
1249 DP_ERR(edev, "Unsupported multi-queue mode\n");
1252 /* Flow director mode check */
1253 if (qede_check_fdir_support(eth_dev))
1256 /* Deallocate resources if held previously. It is needed only if the
1257 * queue count has been changed from previous configuration. If its
1258 * going to change then it means RX/TX queue setup will be called
1259 * again and the fastpath pointers will be reinitialized there.
1261 if (qdev->num_tx_queues != eth_dev->data->nb_tx_queues ||
1262 qdev->num_rx_queues != eth_dev->data->nb_rx_queues) {
1263 qede_dealloc_fp_resc(eth_dev);
1264 /* Proceed with updated queue count */
1265 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1266 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1267 if (qede_alloc_fp_resc(qdev))
1271 /* VF's MTU has to be set using vport-start where as
1272 * PF's MTU can be updated via vport-update.
1275 if (qede_start_vport(qdev, rxmode->max_rx_pkt_len))
1278 if (qede_update_mtu(eth_dev, rxmode->max_rx_pkt_len))
1282 qdev->mtu = rxmode->max_rx_pkt_len;
1283 qdev->new_mtu = qdev->mtu;
1285 /* Enable VLAN offloads by default */
1286 ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK |
1287 ETH_VLAN_FILTER_MASK |
1288 ETH_VLAN_EXTEND_MASK);
1292 DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1293 QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1298 /* Info about HW descriptor ring limitations */
1299 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1300 .nb_max = 0x8000, /* 32K */
1302 .nb_align = 128 /* lowest common multiple */
1305 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1306 .nb_max = 0x8000, /* 32K */
1309 .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1310 .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1314 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1315 struct rte_eth_dev_info *dev_info)
1317 struct qede_dev *qdev = eth_dev->data->dev_private;
1318 struct ecore_dev *edev = &qdev->edev;
1319 struct qed_link_output link;
1320 uint32_t speed_cap = 0;
1322 PMD_INIT_FUNC_TRACE(edev);
1324 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1325 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1326 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1327 dev_info->rx_desc_lim = qede_rx_desc_lim;
1328 dev_info->tx_desc_lim = qede_tx_desc_lim;
1331 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1332 QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1334 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1335 QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1336 dev_info->max_tx_queues = dev_info->max_rx_queues;
1338 dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1339 dev_info->max_vfs = 0;
1340 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1341 dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1342 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1344 dev_info->default_txconf = (struct rte_eth_txconf) {
1345 .txq_flags = QEDE_TXQ_FLAGS,
1348 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP |
1349 DEV_RX_OFFLOAD_IPV4_CKSUM |
1350 DEV_RX_OFFLOAD_UDP_CKSUM |
1351 DEV_RX_OFFLOAD_TCP_CKSUM |
1352 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1353 DEV_RX_OFFLOAD_TCP_LRO);
1355 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1356 DEV_TX_OFFLOAD_IPV4_CKSUM |
1357 DEV_TX_OFFLOAD_UDP_CKSUM |
1358 DEV_TX_OFFLOAD_TCP_CKSUM |
1359 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1360 DEV_TX_OFFLOAD_TCP_TSO |
1361 DEV_TX_OFFLOAD_VXLAN_TNL_TSO);
1363 memset(&link, 0, sizeof(struct qed_link_output));
1364 qdev->ops->common->get_link(edev, &link);
1365 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1366 speed_cap |= ETH_LINK_SPEED_1G;
1367 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1368 speed_cap |= ETH_LINK_SPEED_10G;
1369 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1370 speed_cap |= ETH_LINK_SPEED_25G;
1371 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1372 speed_cap |= ETH_LINK_SPEED_40G;
1373 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1374 speed_cap |= ETH_LINK_SPEED_50G;
1375 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1376 speed_cap |= ETH_LINK_SPEED_100G;
1377 dev_info->speed_capa = speed_cap;
1380 /* return 0 means link status changed, -1 means not changed */
1382 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1384 struct qede_dev *qdev = eth_dev->data->dev_private;
1385 struct ecore_dev *edev = &qdev->edev;
1386 uint16_t link_duplex;
1387 struct qed_link_output link;
1388 struct rte_eth_link *curr = ð_dev->data->dev_link;
1390 memset(&link, 0, sizeof(struct qed_link_output));
1391 qdev->ops->common->get_link(edev, &link);
1394 curr->link_speed = link.speed;
1397 switch (link.duplex) {
1398 case QEDE_DUPLEX_HALF:
1399 link_duplex = ETH_LINK_HALF_DUPLEX;
1401 case QEDE_DUPLEX_FULL:
1402 link_duplex = ETH_LINK_FULL_DUPLEX;
1404 case QEDE_DUPLEX_UNKNOWN:
1408 curr->link_duplex = link_duplex;
1411 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1414 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1415 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1417 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1418 curr->link_speed, curr->link_duplex,
1419 curr->link_autoneg, curr->link_status);
1421 /* return 0 means link status changed, -1 means not changed */
1422 return ((curr->link_status == link.link_up) ? -1 : 0);
1425 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1427 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1428 struct qede_dev *qdev = eth_dev->data->dev_private;
1429 struct ecore_dev *edev = &qdev->edev;
1431 PMD_INIT_FUNC_TRACE(edev);
1434 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1436 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1437 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1439 qed_configure_filter_rx_mode(eth_dev, type);
1442 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1444 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1445 struct qede_dev *qdev = eth_dev->data->dev_private;
1446 struct ecore_dev *edev = &qdev->edev;
1448 PMD_INIT_FUNC_TRACE(edev);
1451 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1452 qed_configure_filter_rx_mode(eth_dev,
1453 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1455 qed_configure_filter_rx_mode(eth_dev,
1456 QED_FILTER_RX_MODE_TYPE_REGULAR);
1459 static void qede_poll_sp_sb_cb(void *param)
1461 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1462 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1463 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1466 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1467 qede_interrupt_action(&edev->hwfns[1]);
1469 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1473 DP_ERR(edev, "Unable to start periodic"
1474 " timer rc %d\n", rc);
1475 assert(false && "Unable to start periodic timer");
1479 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1481 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1482 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1483 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1485 PMD_INIT_FUNC_TRACE(edev);
1487 /* dev_stop() shall cleanup fp resources in hw but without releasing
1488 * dma memories and sw structures so that dev_start() can be called
1489 * by the app without reconfiguration. However, in dev_close() we
1490 * can release all the resources and device can be brought up newly
1492 if (eth_dev->data->dev_started)
1493 qede_dev_stop(eth_dev);
1495 qede_stop_vport(edev);
1496 qede_fdir_dealloc_resc(eth_dev);
1497 qede_dealloc_fp_resc(eth_dev);
1499 eth_dev->data->nb_rx_queues = 0;
1500 eth_dev->data->nb_tx_queues = 0;
1502 qdev->ops->common->slowpath_stop(edev);
1503 qdev->ops->common->remove(edev);
1504 rte_intr_disable(&pci_dev->intr_handle);
1505 rte_intr_callback_unregister(&pci_dev->intr_handle,
1506 qede_interrupt_handler, (void *)eth_dev);
1507 if (ECORE_IS_CMT(edev))
1508 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1512 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1514 struct qede_dev *qdev = eth_dev->data->dev_private;
1515 struct ecore_dev *edev = &qdev->edev;
1516 struct ecore_eth_stats stats;
1517 unsigned int i = 0, j = 0, qid;
1518 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1519 struct qede_tx_queue *txq;
1521 ecore_get_vport_stats(edev, &stats);
1524 eth_stats->ipackets = stats.common.rx_ucast_pkts +
1525 stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1527 eth_stats->ibytes = stats.common.rx_ucast_bytes +
1528 stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1530 eth_stats->ierrors = stats.common.rx_crc_errors +
1531 stats.common.rx_align_errors +
1532 stats.common.rx_carrier_errors +
1533 stats.common.rx_oversize_packets +
1534 stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1536 eth_stats->rx_nombuf = stats.common.no_buff_discards;
1538 eth_stats->imissed = stats.common.mftag_filter_discards +
1539 stats.common.mac_filter_discards +
1540 stats.common.no_buff_discards +
1541 stats.common.brb_truncates + stats.common.brb_discards;
1544 eth_stats->opackets = stats.common.tx_ucast_pkts +
1545 stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1547 eth_stats->obytes = stats.common.tx_ucast_bytes +
1548 stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1550 eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1553 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1554 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1555 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1556 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1557 if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1558 (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1559 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1560 "Not all the queue stats will be displayed. Set"
1561 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1562 " appropriately and retry.\n");
1565 eth_stats->q_ipackets[i] =
1567 ((char *)(qdev->fp_array[qid].rxq)) +
1568 offsetof(struct qede_rx_queue,
1570 eth_stats->q_errors[i] =
1572 ((char *)(qdev->fp_array[qid].rxq)) +
1573 offsetof(struct qede_rx_queue,
1576 ((char *)(qdev->fp_array[qid].rxq)) +
1577 offsetof(struct qede_rx_queue,
1580 if (i == rxq_stat_cntrs)
1585 txq = qdev->fp_array[qid].txq;
1586 eth_stats->q_opackets[j] =
1587 *((uint64_t *)(uintptr_t)
1588 (((uint64_t)(uintptr_t)(txq)) +
1589 offsetof(struct qede_tx_queue,
1592 if (j == txq_stat_cntrs)
1600 qede_get_xstats_count(struct qede_dev *qdev) {
1601 if (ECORE_IS_BB(&qdev->edev))
1602 return RTE_DIM(qede_xstats_strings) +
1603 RTE_DIM(qede_bb_xstats_strings) +
1604 (RTE_DIM(qede_rxq_xstats_strings) *
1605 RTE_MIN(QEDE_RSS_COUNT(qdev),
1606 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1608 return RTE_DIM(qede_xstats_strings) +
1609 RTE_DIM(qede_ah_xstats_strings) +
1610 (RTE_DIM(qede_rxq_xstats_strings) *
1611 RTE_MIN(QEDE_RSS_COUNT(qdev),
1612 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1616 qede_get_xstats_names(struct rte_eth_dev *dev,
1617 struct rte_eth_xstat_name *xstats_names,
1618 __rte_unused unsigned int limit)
1620 struct qede_dev *qdev = dev->data->dev_private;
1621 struct ecore_dev *edev = &qdev->edev;
1622 const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1623 unsigned int i, qid, stat_idx = 0;
1624 unsigned int rxq_stat_cntrs;
1626 if (xstats_names != NULL) {
1627 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1628 snprintf(xstats_names[stat_idx].name,
1629 sizeof(xstats_names[stat_idx].name),
1631 qede_xstats_strings[i].name);
1635 if (ECORE_IS_BB(edev)) {
1636 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1637 snprintf(xstats_names[stat_idx].name,
1638 sizeof(xstats_names[stat_idx].name),
1640 qede_bb_xstats_strings[i].name);
1644 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1645 snprintf(xstats_names[stat_idx].name,
1646 sizeof(xstats_names[stat_idx].name),
1648 qede_ah_xstats_strings[i].name);
1653 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1654 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1655 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1656 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1657 snprintf(xstats_names[stat_idx].name,
1658 sizeof(xstats_names[stat_idx].name),
1660 qede_rxq_xstats_strings[i].name, qid,
1661 qede_rxq_xstats_strings[i].name + 4);
1671 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1674 struct qede_dev *qdev = dev->data->dev_private;
1675 struct ecore_dev *edev = &qdev->edev;
1676 struct ecore_eth_stats stats;
1677 const unsigned int num = qede_get_xstats_count(qdev);
1678 unsigned int i, qid, stat_idx = 0;
1679 unsigned int rxq_stat_cntrs;
1684 ecore_get_vport_stats(edev, &stats);
1686 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1687 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1688 qede_xstats_strings[i].offset);
1689 xstats[stat_idx].id = stat_idx;
1693 if (ECORE_IS_BB(edev)) {
1694 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1695 xstats[stat_idx].value =
1696 *(uint64_t *)(((char *)&stats) +
1697 qede_bb_xstats_strings[i].offset);
1698 xstats[stat_idx].id = stat_idx;
1702 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1703 xstats[stat_idx].value =
1704 *(uint64_t *)(((char *)&stats) +
1705 qede_ah_xstats_strings[i].offset);
1706 xstats[stat_idx].id = stat_idx;
1711 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1712 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1713 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1715 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1716 xstats[stat_idx].value = *(uint64_t *)(
1717 ((char *)(qdev->fp_array[qid].rxq)) +
1718 qede_rxq_xstats_strings[i].offset);
1719 xstats[stat_idx].id = stat_idx;
1729 qede_reset_xstats(struct rte_eth_dev *dev)
1731 struct qede_dev *qdev = dev->data->dev_private;
1732 struct ecore_dev *edev = &qdev->edev;
1734 ecore_reset_vport_stats(edev);
1737 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1739 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1740 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1741 struct qed_link_params link_params;
1744 DP_INFO(edev, "setting link state %d\n", link_up);
1745 memset(&link_params, 0, sizeof(link_params));
1746 link_params.link_up = link_up;
1747 rc = qdev->ops->common->set_link(edev, &link_params);
1748 if (rc != ECORE_SUCCESS)
1749 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1754 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1756 return qede_dev_set_link_state(eth_dev, true);
1759 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1761 return qede_dev_set_link_state(eth_dev, false);
1764 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1766 struct qede_dev *qdev = eth_dev->data->dev_private;
1767 struct ecore_dev *edev = &qdev->edev;
1769 ecore_reset_vport_stats(edev);
1772 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1774 enum qed_filter_rx_mode_type type =
1775 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1777 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1778 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1780 qed_configure_filter_rx_mode(eth_dev, type);
1783 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1785 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1786 qed_configure_filter_rx_mode(eth_dev,
1787 QED_FILTER_RX_MODE_TYPE_PROMISC);
1789 qed_configure_filter_rx_mode(eth_dev,
1790 QED_FILTER_RX_MODE_TYPE_REGULAR);
1793 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1794 struct rte_eth_fc_conf *fc_conf)
1796 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1797 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1798 struct qed_link_output current_link;
1799 struct qed_link_params params;
1801 memset(¤t_link, 0, sizeof(current_link));
1802 qdev->ops->common->get_link(edev, ¤t_link);
1804 memset(¶ms, 0, sizeof(params));
1805 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1806 if (fc_conf->autoneg) {
1807 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1808 DP_ERR(edev, "Autoneg not supported\n");
1811 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1814 /* Pause is assumed to be supported (SUPPORTED_Pause) */
1815 if (fc_conf->mode == RTE_FC_FULL)
1816 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1817 QED_LINK_PAUSE_RX_ENABLE);
1818 if (fc_conf->mode == RTE_FC_TX_PAUSE)
1819 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1820 if (fc_conf->mode == RTE_FC_RX_PAUSE)
1821 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1823 params.link_up = true;
1824 (void)qdev->ops->common->set_link(edev, ¶ms);
1829 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1830 struct rte_eth_fc_conf *fc_conf)
1832 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1833 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1834 struct qed_link_output current_link;
1836 memset(¤t_link, 0, sizeof(current_link));
1837 qdev->ops->common->get_link(edev, ¤t_link);
1839 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1840 fc_conf->autoneg = true;
1842 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1843 QED_LINK_PAUSE_TX_ENABLE))
1844 fc_conf->mode = RTE_FC_FULL;
1845 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1846 fc_conf->mode = RTE_FC_RX_PAUSE;
1847 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1848 fc_conf->mode = RTE_FC_TX_PAUSE;
1850 fc_conf->mode = RTE_FC_NONE;
1855 static const uint32_t *
1856 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1858 static const uint32_t ptypes[] = {
1860 RTE_PTYPE_L2_ETHER_VLAN,
1865 RTE_PTYPE_TUNNEL_VXLAN,
1868 RTE_PTYPE_INNER_L2_ETHER,
1869 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1870 RTE_PTYPE_INNER_L3_IPV4,
1871 RTE_PTYPE_INNER_L3_IPV6,
1872 RTE_PTYPE_INNER_L4_TCP,
1873 RTE_PTYPE_INNER_L4_UDP,
1874 RTE_PTYPE_INNER_L4_FRAG,
1878 if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1884 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1887 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
1888 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
1889 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
1890 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
1891 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
1892 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
1893 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0;
1894 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0;
1897 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1898 struct rte_eth_rss_conf *rss_conf)
1900 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1901 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1902 struct ecore_sp_vport_update_params vport_update_params;
1903 struct ecore_rss_params rss_params;
1904 struct ecore_hwfn *p_hwfn;
1905 uint32_t *key = (uint32_t *)rss_conf->rss_key;
1906 uint64_t hf = rss_conf->rss_hf;
1907 uint8_t len = rss_conf->rss_key_len;
1912 memset(&vport_update_params, 0, sizeof(vport_update_params));
1913 memset(&rss_params, 0, sizeof(rss_params));
1915 DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1916 (unsigned long)hf, len, key);
1920 DP_INFO(edev, "Enabling rss\n");
1923 qede_init_rss_caps(&rss_params.rss_caps, hf);
1924 rss_params.update_rss_capabilities = 1;
1928 if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1929 DP_ERR(edev, "RSS key length exceeds limit\n");
1932 DP_INFO(edev, "Applying user supplied hash key\n");
1933 rss_params.update_rss_key = 1;
1934 memcpy(&rss_params.rss_key, key, len);
1936 rss_params.rss_enable = 1;
1939 rss_params.update_rss_config = 1;
1940 /* tbl_size has to be set with capabilities */
1941 rss_params.rss_table_size_log = 7;
1942 vport_update_params.vport_id = 0;
1943 /* pass the L2 handles instead of qids */
1944 for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
1945 idx = qdev->rss_ind_table[i];
1946 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
1948 vport_update_params.rss_params = &rss_params;
1950 for_each_hwfn(edev, i) {
1951 p_hwfn = &edev->hwfns[i];
1952 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1953 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1954 ECORE_SPQ_MODE_EBLOCK, NULL);
1956 DP_ERR(edev, "vport-update for RSS failed\n");
1960 qdev->rss_enable = rss_params.rss_enable;
1962 /* Update local structure for hash query */
1963 qdev->rss_conf.rss_hf = hf;
1964 qdev->rss_conf.rss_key_len = len;
1965 if (qdev->rss_enable) {
1966 if (qdev->rss_conf.rss_key == NULL) {
1967 qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
1968 if (qdev->rss_conf.rss_key == NULL) {
1969 DP_ERR(edev, "No memory to store RSS key\n");
1974 DP_INFO(edev, "Storing RSS key\n");
1975 memcpy(qdev->rss_conf.rss_key, key, len);
1977 } else if (!qdev->rss_enable && len == 0) {
1978 if (qdev->rss_conf.rss_key) {
1979 free(qdev->rss_conf.rss_key);
1980 qdev->rss_conf.rss_key = NULL;
1981 DP_INFO(edev, "Free RSS key\n");
1988 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1989 struct rte_eth_rss_conf *rss_conf)
1991 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1993 rss_conf->rss_hf = qdev->rss_conf.rss_hf;
1994 rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
1996 if (rss_conf->rss_key && qdev->rss_conf.rss_key)
1997 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
1998 rss_conf->rss_key_len);
2002 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2003 struct ecore_rss_params *rss)
2006 bool rss_mode = 1; /* enable */
2007 struct ecore_queue_cid *cid;
2008 struct ecore_rss_params *t_rss;
2010 /* In regular scenario, we'd simply need to take input handlers.
2011 * But in CMT, we'd have to split the handlers according to the
2012 * engine they were configured on. We'd then have to understand
2013 * whether RSS is really required, since 2-queues on CMT doesn't
2017 /* CMT should be round-robin */
2018 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2019 cid = rss->rss_ind_table[i];
2021 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2026 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2030 t_rss->update_rss_ind_table = 1;
2031 t_rss->rss_table_size_log = 7;
2032 t_rss->update_rss_config = 1;
2034 /* Make sure RSS is actually required */
2035 for_each_hwfn(edev, fn) {
2036 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2038 if (rss[fn].rss_ind_table[i] !=
2039 rss[fn].rss_ind_table[0])
2043 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2045 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2052 t_rss->rss_enable = rss_mode;
2057 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2058 struct rte_eth_rss_reta_entry64 *reta_conf,
2061 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2062 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2063 struct ecore_sp_vport_update_params vport_update_params;
2064 struct ecore_rss_params *params;
2065 struct ecore_hwfn *p_hwfn;
2066 uint16_t i, idx, shift;
2070 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2071 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2076 memset(&vport_update_params, 0, sizeof(vport_update_params));
2077 params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2078 RTE_CACHE_LINE_SIZE);
2079 if (params == NULL) {
2080 DP_ERR(edev, "failed to allocate memory\n");
2084 for (i = 0; i < reta_size; i++) {
2085 idx = i / RTE_RETA_GROUP_SIZE;
2086 shift = i % RTE_RETA_GROUP_SIZE;
2087 if (reta_conf[idx].mask & (1ULL << shift)) {
2088 entry = reta_conf[idx].reta[shift];
2089 /* Pass rxq handles to ecore */
2090 params->rss_ind_table[i] =
2091 qdev->fp_array[entry].rxq->handle;
2092 /* Update the local copy for RETA query command */
2093 qdev->rss_ind_table[i] = entry;
2097 params->update_rss_ind_table = 1;
2098 params->rss_table_size_log = 7;
2099 params->update_rss_config = 1;
2101 /* Fix up RETA for CMT mode device */
2102 if (ECORE_IS_CMT(edev))
2103 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2105 vport_update_params.vport_id = 0;
2106 /* Use the current value of rss_enable */
2107 params->rss_enable = qdev->rss_enable;
2108 vport_update_params.rss_params = params;
2110 for_each_hwfn(edev, i) {
2111 p_hwfn = &edev->hwfns[i];
2112 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2113 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2114 ECORE_SPQ_MODE_EBLOCK, NULL);
2116 DP_ERR(edev, "vport-update for RSS failed\n");
2126 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2127 struct rte_eth_rss_reta_entry64 *reta_conf,
2130 struct qede_dev *qdev = eth_dev->data->dev_private;
2131 struct ecore_dev *edev = &qdev->edev;
2132 uint16_t i, idx, shift;
2135 if (reta_size > ETH_RSS_RETA_SIZE_128) {
2136 DP_ERR(edev, "reta_size %d is not supported\n",
2141 for (i = 0; i < reta_size; i++) {
2142 idx = i / RTE_RETA_GROUP_SIZE;
2143 shift = i % RTE_RETA_GROUP_SIZE;
2144 if (reta_conf[idx].mask & (1ULL << shift)) {
2145 entry = qdev->rss_ind_table[i];
2146 reta_conf[idx].reta[shift] = entry;
2155 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2157 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2158 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2159 struct rte_eth_dev_info dev_info = {0};
2160 struct qede_fastpath *fp;
2161 uint32_t frame_size;
2162 uint16_t rx_buf_size;
2166 PMD_INIT_FUNC_TRACE(edev);
2167 qede_dev_info_get(dev, &dev_info);
2168 frame_size = mtu + QEDE_ETH_OVERHEAD;
2169 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2170 DP_ERR(edev, "MTU %u out of range\n", mtu);
2173 if (!dev->data->scattered_rx &&
2174 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2175 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2176 dev->data->min_rx_buf_size);
2179 /* Temporarily replace I/O functions with dummy ones. It cannot
2180 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2182 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2183 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2187 /* Fix up RX buf size for all queues of the port */
2189 fp = &qdev->fp_array[i];
2190 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2191 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2192 if (dev->data->scattered_rx)
2193 rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
2195 rx_buf_size = mtu + QEDE_ETH_OVERHEAD;
2196 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2197 fp->rxq->rx_buf_size = rx_buf_size;
2198 DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
2200 qede_dev_start(dev);
2201 if (frame_size > ETHER_MAX_LEN)
2202 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2204 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2205 /* update max frame size */
2206 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2208 dev->rx_pkt_burst = qede_recv_pkts;
2209 dev->tx_pkt_burst = qede_xmit_pkts;
2215 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
2216 struct rte_eth_udp_tunnel *tunnel_udp,
2219 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2220 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2221 struct ecore_tunnel_info tunn; /* @DPDK */
2222 struct ecore_hwfn *p_hwfn;
2223 struct ecore_ptt *p_ptt;
2227 PMD_INIT_FUNC_TRACE(edev);
2229 memset(&tunn, 0, sizeof(tunn));
2230 if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
2231 /* Enable VxLAN tunnel if needed before UDP port update using
2232 * default MAC/VLAN classification.
2235 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2237 "UDP port %u was already configured\n",
2238 tunnel_udp->udp_port);
2239 return ECORE_SUCCESS;
2241 /* Enable VXLAN if it was not enabled while adding
2244 if (!qdev->vxlan.enable) {
2245 rc = qede_vxlan_enable(eth_dev,
2246 ECORE_TUNN_CLSS_MAC_VLAN, true, true);
2247 if (rc != ECORE_SUCCESS) {
2248 DP_ERR(edev, "Failed to enable VXLAN "
2249 "prior to updating UDP port\n");
2253 udp_port = tunnel_udp->udp_port;
2255 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2256 DP_ERR(edev, "UDP port %u doesn't exist\n",
2257 tunnel_udp->udp_port);
2263 tunn.vxlan_port.b_update_port = true;
2264 tunn.vxlan_port.port = udp_port;
2265 for_each_hwfn(edev, i) {
2266 p_hwfn = &edev->hwfns[i];
2268 p_ptt = ecore_ptt_acquire(p_hwfn);
2274 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt, &tunn,
2275 ECORE_SPQ_MODE_CB, NULL);
2276 if (rc != ECORE_SUCCESS) {
2277 DP_ERR(edev, "Unable to config UDP port %u\n",
2278 tunn.vxlan_port.port);
2280 ecore_ptt_release(p_hwfn, p_ptt);
2285 qdev->vxlan.udp_port = udp_port;
2286 /* If the request is to delete UDP port and if the number of
2287 * VXLAN filters have reached 0 then VxLAN offload can be be
2290 if (!add && qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2291 return qede_vxlan_enable(eth_dev,
2292 ECORE_TUNN_CLSS_MAC_VLAN, false, true);
2299 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2300 struct rte_eth_udp_tunnel *tunnel_udp)
2302 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
2306 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2307 struct rte_eth_udp_tunnel *tunnel_udp)
2309 return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
2312 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2313 uint32_t *clss, char *str)
2316 *clss = MAX_ECORE_TUNN_CLSS;
2318 for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2319 if (filter == qede_tunn_types[j].rte_filter_type) {
2320 *type = qede_tunn_types[j].qede_type;
2321 *clss = qede_tunn_types[j].qede_tunn_clss;
2322 strcpy(str, qede_tunn_types[j].string);
2329 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2330 const struct rte_eth_tunnel_filter_conf *conf,
2333 /* Init commmon ucast params first */
2334 qede_set_ucast_cmn_params(ucast);
2336 /* Copy out the required fields based on classification type */
2340 case ECORE_FILTER_VNI:
2341 ucast->vni = conf->tenant_id;
2343 case ECORE_FILTER_INNER_VLAN:
2344 ucast->vlan = conf->inner_vlan;
2346 case ECORE_FILTER_MAC:
2347 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2350 case ECORE_FILTER_INNER_MAC:
2351 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2354 case ECORE_FILTER_MAC_VNI_PAIR:
2355 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2357 ucast->vni = conf->tenant_id;
2359 case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2360 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2362 ucast->vni = conf->tenant_id;
2364 case ECORE_FILTER_INNER_PAIR:
2365 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2367 ucast->vlan = conf->inner_vlan;
2373 return ECORE_SUCCESS;
2376 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
2377 enum rte_filter_op filter_op,
2378 const struct rte_eth_tunnel_filter_conf *conf)
2380 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2381 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2382 enum ecore_filter_ucast_type type;
2383 enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2384 struct ecore_filter_ucast ucast = {0};
2386 uint16_t filter_type = 0;
2389 PMD_INIT_FUNC_TRACE(edev);
2391 switch (filter_op) {
2392 case RTE_ETH_FILTER_ADD:
2394 return qede_vxlan_enable(eth_dev,
2395 ECORE_TUNN_CLSS_MAC_VLAN, true, true);
2397 filter_type = conf->filter_type;
2398 /* Determine if the given filter classification is supported */
2399 qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
2400 if (clss == MAX_ECORE_TUNN_CLSS) {
2401 DP_ERR(edev, "Unsupported filter type\n");
2404 /* Init tunnel ucast params */
2405 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2406 if (rc != ECORE_SUCCESS) {
2407 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
2411 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2412 str, filter_op, ucast.type);
2414 ucast.opcode = ECORE_FILTER_ADD;
2416 /* Skip MAC/VLAN if filter is based on VNI */
2417 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2418 rc = qede_mac_int_ops(eth_dev, &ucast, 1);
2420 /* Enable accept anyvlan */
2421 qede_config_accept_any_vlan(qdev, true);
2424 rc = qede_ucast_filter(eth_dev, &ucast, 1);
2426 rc = ecore_filter_ucast_cmd(edev, &ucast,
2427 ECORE_SPQ_MODE_CB, NULL);
2430 if (rc != ECORE_SUCCESS)
2433 qdev->vxlan.num_filters++;
2434 qdev->vxlan.filter_type = filter_type;
2435 if (!qdev->vxlan.enable)
2436 return qede_vxlan_enable(eth_dev, clss, true, true);
2439 case RTE_ETH_FILTER_DELETE:
2441 return qede_vxlan_enable(eth_dev,
2442 ECORE_TUNN_CLSS_MAC_VLAN, false, true);
2444 filter_type = conf->filter_type;
2445 /* Determine if the given filter classification is supported */
2446 qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
2447 if (clss == MAX_ECORE_TUNN_CLSS) {
2448 DP_ERR(edev, "Unsupported filter type\n");
2451 /* Init tunnel ucast params */
2452 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2453 if (rc != ECORE_SUCCESS) {
2454 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
2458 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2459 str, filter_op, ucast.type);
2461 ucast.opcode = ECORE_FILTER_REMOVE;
2463 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2464 rc = qede_mac_int_ops(eth_dev, &ucast, 0);
2466 rc = qede_ucast_filter(eth_dev, &ucast, 0);
2468 rc = ecore_filter_ucast_cmd(edev, &ucast,
2469 ECORE_SPQ_MODE_CB, NULL);
2471 if (rc != ECORE_SUCCESS)
2474 qdev->vxlan.num_filters--;
2476 /* Disable VXLAN if VXLAN filters become 0 */
2477 if (qdev->vxlan.num_filters == 0)
2478 return qede_vxlan_enable(eth_dev, clss, false, true);
2481 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2488 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2489 enum rte_filter_type filter_type,
2490 enum rte_filter_op filter_op,
2493 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2494 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2495 struct rte_eth_tunnel_filter_conf *filter_conf =
2496 (struct rte_eth_tunnel_filter_conf *)arg;
2498 switch (filter_type) {
2499 case RTE_ETH_FILTER_TUNNEL:
2500 switch (filter_conf->tunnel_type) {
2501 case RTE_TUNNEL_TYPE_VXLAN:
2503 "Packet steering to the specified Rx queue"
2504 " is not supported with VXLAN tunneling");
2505 return(qede_vxlan_tunn_config(eth_dev, filter_op,
2507 /* Place holders for future tunneling support */
2508 case RTE_TUNNEL_TYPE_GENEVE:
2509 case RTE_TUNNEL_TYPE_TEREDO:
2510 case RTE_TUNNEL_TYPE_NVGRE:
2511 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2512 case RTE_L2_TUNNEL_TYPE_E_TAG:
2513 DP_ERR(edev, "Unsupported tunnel type %d\n",
2514 filter_conf->tunnel_type);
2516 case RTE_TUNNEL_TYPE_NONE:
2521 case RTE_ETH_FILTER_FDIR:
2522 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2523 case RTE_ETH_FILTER_NTUPLE:
2524 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2525 case RTE_ETH_FILTER_MACVLAN:
2526 case RTE_ETH_FILTER_ETHERTYPE:
2527 case RTE_ETH_FILTER_FLEXIBLE:
2528 case RTE_ETH_FILTER_SYN:
2529 case RTE_ETH_FILTER_HASH:
2530 case RTE_ETH_FILTER_L2_TUNNEL:
2531 case RTE_ETH_FILTER_MAX:
2533 DP_ERR(edev, "Unsupported filter type %d\n",
2541 static const struct eth_dev_ops qede_eth_dev_ops = {
2542 .dev_configure = qede_dev_configure,
2543 .dev_infos_get = qede_dev_info_get,
2544 .rx_queue_setup = qede_rx_queue_setup,
2545 .rx_queue_release = qede_rx_queue_release,
2546 .tx_queue_setup = qede_tx_queue_setup,
2547 .tx_queue_release = qede_tx_queue_release,
2548 .dev_start = qede_dev_start,
2549 .dev_set_link_up = qede_dev_set_link_up,
2550 .dev_set_link_down = qede_dev_set_link_down,
2551 .link_update = qede_link_update,
2552 .promiscuous_enable = qede_promiscuous_enable,
2553 .promiscuous_disable = qede_promiscuous_disable,
2554 .allmulticast_enable = qede_allmulticast_enable,
2555 .allmulticast_disable = qede_allmulticast_disable,
2556 .dev_stop = qede_dev_stop,
2557 .dev_close = qede_dev_close,
2558 .stats_get = qede_get_stats,
2559 .stats_reset = qede_reset_stats,
2560 .xstats_get = qede_get_xstats,
2561 .xstats_reset = qede_reset_xstats,
2562 .xstats_get_names = qede_get_xstats_names,
2563 .mac_addr_add = qede_mac_addr_add,
2564 .mac_addr_remove = qede_mac_addr_remove,
2565 .mac_addr_set = qede_mac_addr_set,
2566 .vlan_offload_set = qede_vlan_offload_set,
2567 .vlan_filter_set = qede_vlan_filter_set,
2568 .flow_ctrl_set = qede_flow_ctrl_set,
2569 .flow_ctrl_get = qede_flow_ctrl_get,
2570 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2571 .rss_hash_update = qede_rss_hash_update,
2572 .rss_hash_conf_get = qede_rss_hash_conf_get,
2573 .reta_update = qede_rss_reta_update,
2574 .reta_query = qede_rss_reta_query,
2575 .mtu_set = qede_set_mtu,
2576 .filter_ctrl = qede_dev_filter_ctrl,
2577 .udp_tunnel_port_add = qede_udp_dst_port_add,
2578 .udp_tunnel_port_del = qede_udp_dst_port_del,
2581 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2582 .dev_configure = qede_dev_configure,
2583 .dev_infos_get = qede_dev_info_get,
2584 .rx_queue_setup = qede_rx_queue_setup,
2585 .rx_queue_release = qede_rx_queue_release,
2586 .tx_queue_setup = qede_tx_queue_setup,
2587 .tx_queue_release = qede_tx_queue_release,
2588 .dev_start = qede_dev_start,
2589 .dev_set_link_up = qede_dev_set_link_up,
2590 .dev_set_link_down = qede_dev_set_link_down,
2591 .link_update = qede_link_update,
2592 .promiscuous_enable = qede_promiscuous_enable,
2593 .promiscuous_disable = qede_promiscuous_disable,
2594 .allmulticast_enable = qede_allmulticast_enable,
2595 .allmulticast_disable = qede_allmulticast_disable,
2596 .dev_stop = qede_dev_stop,
2597 .dev_close = qede_dev_close,
2598 .stats_get = qede_get_stats,
2599 .stats_reset = qede_reset_stats,
2600 .xstats_get = qede_get_xstats,
2601 .xstats_reset = qede_reset_xstats,
2602 .xstats_get_names = qede_get_xstats_names,
2603 .vlan_offload_set = qede_vlan_offload_set,
2604 .vlan_filter_set = qede_vlan_filter_set,
2605 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2606 .rss_hash_update = qede_rss_hash_update,
2607 .rss_hash_conf_get = qede_rss_hash_conf_get,
2608 .reta_update = qede_rss_reta_update,
2609 .reta_query = qede_rss_reta_query,
2610 .mtu_set = qede_set_mtu,
2611 .udp_tunnel_port_add = qede_udp_dst_port_add,
2612 .udp_tunnel_port_del = qede_udp_dst_port_del,
2615 static void qede_update_pf_params(struct ecore_dev *edev)
2617 struct ecore_pf_params pf_params;
2619 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2620 pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2621 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2622 qed_ops->common->update_pf_params(edev, &pf_params);
2625 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2627 struct rte_pci_device *pci_dev;
2628 struct rte_pci_addr pci_addr;
2629 struct qede_dev *adapter;
2630 struct ecore_dev *edev;
2631 struct qed_dev_eth_info dev_info;
2632 struct qed_slowpath_params params;
2633 static bool do_once = true;
2634 uint8_t bulletin_change;
2635 uint8_t vf_mac[ETHER_ADDR_LEN];
2636 uint8_t is_mac_forced;
2638 /* Fix up ecore debug level */
2639 uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2640 uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2643 /* Extract key data structures */
2644 adapter = eth_dev->data->dev_private;
2645 adapter->ethdev = eth_dev;
2646 edev = &adapter->edev;
2647 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2648 pci_addr = pci_dev->addr;
2650 PMD_INIT_FUNC_TRACE(edev);
2652 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2653 pci_addr.bus, pci_addr.devid, pci_addr.function,
2654 eth_dev->data->port_id);
2656 eth_dev->rx_pkt_burst = qede_recv_pkts;
2657 eth_dev->tx_pkt_burst = qede_xmit_pkts;
2658 eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2660 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2661 DP_ERR(edev, "Skipping device init from secondary process\n");
2665 rte_eth_copy_pci_info(eth_dev, pci_dev);
2668 edev->vendor_id = pci_dev->id.vendor_id;
2669 edev->device_id = pci_dev->id.device_id;
2671 qed_ops = qed_get_eth_ops();
2673 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2677 DP_INFO(edev, "Starting qede probe\n");
2678 rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2681 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2684 qede_update_pf_params(edev);
2685 rte_intr_callback_register(&pci_dev->intr_handle,
2686 qede_interrupt_handler, (void *)eth_dev);
2687 if (rte_intr_enable(&pci_dev->intr_handle)) {
2688 DP_ERR(edev, "rte_intr_enable() failed\n");
2692 /* Start the Slowpath-process */
2693 memset(¶ms, 0, sizeof(struct qed_slowpath_params));
2694 params.int_mode = ECORE_INT_MODE_MSIX;
2695 params.drv_major = QEDE_PMD_VERSION_MAJOR;
2696 params.drv_minor = QEDE_PMD_VERSION_MINOR;
2697 params.drv_rev = QEDE_PMD_VERSION_REVISION;
2698 params.drv_eng = QEDE_PMD_VERSION_PATCH;
2699 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2700 QEDE_PMD_DRV_VER_STR_SIZE);
2702 /* For CMT mode device do periodic polling for slowpath events.
2703 * This is required since uio device uses only one MSI-x
2704 * interrupt vector but we need one for each engine.
2706 if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2707 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2711 DP_ERR(edev, "Unable to start periodic"
2712 " timer rc %d\n", rc);
2717 rc = qed_ops->common->slowpath_start(edev, ¶ms);
2719 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2720 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2725 rc = qed_ops->fill_dev_info(edev, &dev_info);
2727 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2728 qed_ops->common->slowpath_stop(edev);
2729 qed_ops->common->remove(edev);
2730 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2735 qede_alloc_etherdev(adapter, &dev_info);
2737 adapter->ops->common->set_name(edev, edev->name);
2740 adapter->dev_info.num_mac_filters =
2741 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2744 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2745 (uint32_t *)&adapter->dev_info.num_mac_filters);
2747 /* Allocate memory for storing MAC addr */
2748 eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2750 adapter->dev_info.num_mac_filters),
2751 RTE_CACHE_LINE_SIZE);
2753 if (eth_dev->data->mac_addrs == NULL) {
2754 DP_ERR(edev, "Failed to allocate MAC address\n");
2755 qed_ops->common->slowpath_stop(edev);
2756 qed_ops->common->remove(edev);
2757 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2763 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2764 hw_info.hw_mac_addr,
2765 ð_dev->data->mac_addrs[0]);
2766 ether_addr_copy(ð_dev->data->mac_addrs[0],
2767 &adapter->primary_mac);
2769 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2771 if (bulletin_change) {
2773 ecore_vf_bulletin_get_forced_mac(
2774 ECORE_LEADING_HWFN(edev),
2777 if (is_mac_exist && is_mac_forced) {
2778 DP_INFO(edev, "VF macaddr received from PF\n");
2779 ether_addr_copy((struct ether_addr *)&vf_mac,
2780 ð_dev->data->mac_addrs[0]);
2781 ether_addr_copy(ð_dev->data->mac_addrs[0],
2782 &adapter->primary_mac);
2784 DP_ERR(edev, "No VF macaddr assigned\n");
2789 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2792 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
2793 qede_print_adapter_info(adapter);
2798 adapter->num_tx_queues = 0;
2799 adapter->num_rx_queues = 0;
2800 SLIST_INIT(&adapter->fdir_info.fdir_list_head);
2801 SLIST_INIT(&adapter->vlan_list_head);
2802 SLIST_INIT(&adapter->uc_list_head);
2803 adapter->mtu = ETHER_MTU;
2804 adapter->new_mtu = ETHER_MTU;
2806 if (qede_start_vport(adapter, adapter->mtu))
2809 DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2810 adapter->primary_mac.addr_bytes[0],
2811 adapter->primary_mac.addr_bytes[1],
2812 adapter->primary_mac.addr_bytes[2],
2813 adapter->primary_mac.addr_bytes[3],
2814 adapter->primary_mac.addr_bytes[4],
2815 adapter->primary_mac.addr_bytes[5]);
2817 DP_INFO(edev, "Device initialized\n");
2822 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2824 return qede_common_dev_init(eth_dev, 1);
2827 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2829 return qede_common_dev_init(eth_dev, 0);
2832 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2834 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
2835 struct qede_dev *qdev = eth_dev->data->dev_private;
2836 struct ecore_dev *edev = &qdev->edev;
2838 PMD_INIT_FUNC_TRACE(edev);
2841 /* only uninitialize in the primary process */
2842 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2845 /* safe to close dev here */
2846 qede_dev_close(eth_dev);
2848 eth_dev->dev_ops = NULL;
2849 eth_dev->rx_pkt_burst = NULL;
2850 eth_dev->tx_pkt_burst = NULL;
2852 if (eth_dev->data->mac_addrs)
2853 rte_free(eth_dev->data->mac_addrs);
2855 eth_dev->data->mac_addrs = NULL;
2860 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2862 return qede_dev_common_uninit(eth_dev);
2865 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2867 return qede_dev_common_uninit(eth_dev);
2870 static const struct rte_pci_id pci_id_qedevf_map[] = {
2871 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2873 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2876 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2879 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2884 static const struct rte_pci_id pci_id_qede_map[] = {
2885 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2887 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2890 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2893 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2896 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2899 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2902 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2905 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2908 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2911 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2914 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2919 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2920 struct rte_pci_device *pci_dev)
2922 return rte_eth_dev_pci_generic_probe(pci_dev,
2923 sizeof(struct qede_dev), qedevf_eth_dev_init);
2926 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2928 return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2931 static struct rte_pci_driver rte_qedevf_pmd = {
2932 .id_table = pci_id_qedevf_map,
2933 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2934 .probe = qedevf_eth_dev_pci_probe,
2935 .remove = qedevf_eth_dev_pci_remove,
2938 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2939 struct rte_pci_device *pci_dev)
2941 return rte_eth_dev_pci_generic_probe(pci_dev,
2942 sizeof(struct qede_dev), qede_eth_dev_init);
2945 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2947 return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2950 static struct rte_pci_driver rte_qede_pmd = {
2951 .id_table = pci_id_qede_map,
2952 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2953 .probe = qede_eth_dev_pci_probe,
2954 .remove = qede_eth_dev_pci_remove,
2957 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2958 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2959 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2960 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2961 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2962 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");