2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
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39 static __checkReturn efx_rc_t
47 static __checkReturn efx_rc_t
51 static __checkReturn efx_rc_t
54 __inout efx_filter_spec_t *spec,
55 __in boolean_t may_replace);
57 static __checkReturn efx_rc_t
60 __inout efx_filter_spec_t *spec);
62 static __checkReturn efx_rc_t
63 siena_filter_supported_filters(
65 __out_ecount(buffer_length) uint32_t *buffer,
66 __in size_t buffer_length,
67 __out size_t *list_lengthp);
69 #endif /* EFSYS_OPT_SIENA */
72 static const efx_filter_ops_t __efx_filter_siena_ops = {
73 siena_filter_init, /* efo_init */
74 siena_filter_fini, /* efo_fini */
75 siena_filter_restore, /* efo_restore */
76 siena_filter_add, /* efo_add */
77 siena_filter_delete, /* efo_delete */
78 siena_filter_supported_filters, /* efo_supported_filters */
79 NULL, /* efo_reconfigure */
81 #endif /* EFSYS_OPT_SIENA */
83 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
84 static const efx_filter_ops_t __efx_filter_ef10_ops = {
85 ef10_filter_init, /* efo_init */
86 ef10_filter_fini, /* efo_fini */
87 ef10_filter_restore, /* efo_restore */
88 ef10_filter_add, /* efo_add */
89 ef10_filter_delete, /* efo_delete */
90 ef10_filter_supported_filters, /* efo_supported_filters */
91 ef10_filter_reconfigure, /* efo_reconfigure */
93 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
95 __checkReturn efx_rc_t
98 __inout efx_filter_spec_t *spec)
100 const efx_filter_ops_t *efop = enp->en_efop;
102 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
103 EFSYS_ASSERT3P(spec, !=, NULL);
104 EFSYS_ASSERT3U(spec->efs_flags, &, EFX_FILTER_FLAG_RX);
106 return (efop->efo_add(enp, spec, B_FALSE));
109 __checkReturn efx_rc_t
112 __inout efx_filter_spec_t *spec)
114 const efx_filter_ops_t *efop = enp->en_efop;
116 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
117 EFSYS_ASSERT3P(spec, !=, NULL);
118 EFSYS_ASSERT3U(spec->efs_flags, &, EFX_FILTER_FLAG_RX);
120 #if EFSYS_OPT_RX_SCALE
121 spec->efs_rss_context = enp->en_rss_context;
124 return (efop->efo_delete(enp, spec));
127 __checkReturn efx_rc_t
133 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
135 if ((rc = enp->en_efop->efo_restore(enp)) != 0)
141 EFSYS_PROBE1(fail1, efx_rc_t, rc);
146 __checkReturn efx_rc_t
150 const efx_filter_ops_t *efop;
153 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
154 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
155 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_FILTER));
157 switch (enp->en_family) {
159 case EFX_FAMILY_SIENA:
160 efop = &__efx_filter_siena_ops;
162 #endif /* EFSYS_OPT_SIENA */
164 #if EFSYS_OPT_HUNTINGTON
165 case EFX_FAMILY_HUNTINGTON:
166 efop = &__efx_filter_ef10_ops;
168 #endif /* EFSYS_OPT_HUNTINGTON */
170 #if EFSYS_OPT_MEDFORD
171 case EFX_FAMILY_MEDFORD:
172 efop = &__efx_filter_ef10_ops;
174 #endif /* EFSYS_OPT_MEDFORD */
182 if ((rc = efop->efo_init(enp)) != 0)
186 enp->en_mod_flags |= EFX_MOD_FILTER;
192 EFSYS_PROBE1(fail1, efx_rc_t, rc);
195 enp->en_mod_flags &= ~EFX_MOD_FILTER;
203 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
204 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
205 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
207 enp->en_efop->efo_fini(enp);
210 enp->en_mod_flags &= ~EFX_MOD_FILTER;
214 * Query the possible combinations of match flags which can be filtered on.
215 * These are returned as a list, of which each 32 bit element is a bitmask
216 * formed of EFX_FILTER_MATCH flags.
218 * The combinations are ordered in priority from highest to lowest.
220 * If the provided buffer is too short to hold the list, the call with fail with
221 * ENOSPC and *list_lengthp will be set to the buffer length required.
223 __checkReturn efx_rc_t
224 efx_filter_supported_filters(
226 __out_ecount(buffer_length) uint32_t *buffer,
227 __in size_t buffer_length,
228 __out size_t *list_lengthp)
232 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
233 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
234 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
235 EFSYS_ASSERT(enp->en_efop->efo_supported_filters != NULL);
237 if (buffer == NULL) {
242 rc = enp->en_efop->efo_supported_filters(enp, buffer, buffer_length,
252 EFSYS_PROBE1(fail1, efx_rc_t, rc);
257 __checkReturn efx_rc_t
258 efx_filter_reconfigure(
260 __in_ecount(6) uint8_t const *mac_addr,
261 __in boolean_t all_unicst,
262 __in boolean_t mulcst,
263 __in boolean_t all_mulcst,
264 __in boolean_t brdcst,
265 __in_ecount(6*count) uint8_t const *addrs,
270 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
271 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
272 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
274 if (enp->en_efop->efo_reconfigure != NULL) {
275 if ((rc = enp->en_efop->efo_reconfigure(enp, mac_addr,
285 EFSYS_PROBE1(fail1, efx_rc_t, rc);
291 efx_filter_spec_init_rx(
292 __out efx_filter_spec_t *spec,
293 __in efx_filter_priority_t priority,
294 __in efx_filter_flags_t flags,
297 EFSYS_ASSERT3P(spec, !=, NULL);
298 EFSYS_ASSERT3P(erp, !=, NULL);
299 EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS |
300 EFX_FILTER_FLAG_RX_SCATTER)) == 0);
302 memset(spec, 0, sizeof (*spec));
303 spec->efs_priority = priority;
304 spec->efs_flags = EFX_FILTER_FLAG_RX | flags;
305 spec->efs_rss_context = EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT;
306 spec->efs_dmaq_id = (uint16_t)erp->er_index;
310 efx_filter_spec_init_tx(
311 __out efx_filter_spec_t *spec,
314 EFSYS_ASSERT3P(spec, !=, NULL);
315 EFSYS_ASSERT3P(etp, !=, NULL);
317 memset(spec, 0, sizeof (*spec));
318 spec->efs_priority = EFX_FILTER_PRI_REQUIRED;
319 spec->efs_flags = EFX_FILTER_FLAG_TX;
320 spec->efs_dmaq_id = (uint16_t)etp->et_index;
325 * Specify IPv4 host, transport protocol and port in a filter specification
327 __checkReturn efx_rc_t
328 efx_filter_spec_set_ipv4_local(
329 __inout efx_filter_spec_t *spec,
334 EFSYS_ASSERT3P(spec, !=, NULL);
336 spec->efs_match_flags |=
337 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
338 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
339 spec->efs_ether_type = EFX_ETHER_TYPE_IPV4;
340 spec->efs_ip_proto = proto;
341 spec->efs_loc_host.eo_u32[0] = host;
342 spec->efs_loc_port = port;
347 * Specify IPv4 hosts, transport protocol and ports in a filter specification
349 __checkReturn efx_rc_t
350 efx_filter_spec_set_ipv4_full(
351 __inout efx_filter_spec_t *spec,
358 EFSYS_ASSERT3P(spec, !=, NULL);
360 spec->efs_match_flags |=
361 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
362 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
363 EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT;
364 spec->efs_ether_type = EFX_ETHER_TYPE_IPV4;
365 spec->efs_ip_proto = proto;
366 spec->efs_loc_host.eo_u32[0] = lhost;
367 spec->efs_loc_port = lport;
368 spec->efs_rem_host.eo_u32[0] = rhost;
369 spec->efs_rem_port = rport;
374 * Specify local Ethernet address and/or VID in filter specification
376 __checkReturn efx_rc_t
377 efx_filter_spec_set_eth_local(
378 __inout efx_filter_spec_t *spec,
380 __in const uint8_t *addr)
382 EFSYS_ASSERT3P(spec, !=, NULL);
383 EFSYS_ASSERT3P(addr, !=, NULL);
385 if (vid == EFX_FILTER_SPEC_VID_UNSPEC && addr == NULL)
388 if (vid != EFX_FILTER_SPEC_VID_UNSPEC) {
389 spec->efs_match_flags |= EFX_FILTER_MATCH_OUTER_VID;
390 spec->efs_outer_vid = vid;
393 spec->efs_match_flags |= EFX_FILTER_MATCH_LOC_MAC;
394 memcpy(spec->efs_loc_mac, addr, EFX_MAC_ADDR_LEN);
400 * Specify matching otherwise-unmatched unicast in a filter specification
402 __checkReturn efx_rc_t
403 efx_filter_spec_set_uc_def(
404 __inout efx_filter_spec_t *spec)
406 EFSYS_ASSERT3P(spec, !=, NULL);
408 spec->efs_match_flags |= EFX_FILTER_MATCH_UNKNOWN_UCAST_DST;
413 * Specify matching otherwise-unmatched multicast in a filter specification
415 __checkReturn efx_rc_t
416 efx_filter_spec_set_mc_def(
417 __inout efx_filter_spec_t *spec)
419 EFSYS_ASSERT3P(spec, !=, NULL);
421 spec->efs_match_flags |= EFX_FILTER_MATCH_UNKNOWN_MCAST_DST;
430 * "Fudge factors" - difference between programmed value and actual depth.
431 * Due to pipelined implementation we need to program H/W with a value that
432 * is larger than the hop limit we want.
434 #define FILTER_CTL_SRCH_FUDGE_WILD 3
435 #define FILTER_CTL_SRCH_FUDGE_FULL 1
438 * Hard maximum hop limit. Hardware will time-out beyond 200-something.
439 * We also need to avoid infinite loops in efx_filter_search() when the
442 #define FILTER_CTL_SRCH_MAX 200
444 static __checkReturn efx_rc_t
445 siena_filter_spec_from_gen_spec(
446 __out siena_filter_spec_t *sf_spec,
447 __in efx_filter_spec_t *gen_spec)
450 boolean_t is_full = B_FALSE;
452 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX)
453 EFSYS_ASSERT3U(gen_spec->efs_flags, ==, EFX_FILTER_FLAG_TX);
455 EFSYS_ASSERT3U(gen_spec->efs_flags, &, EFX_FILTER_FLAG_RX);
457 /* Falconsiena only has one RSS context */
458 if ((gen_spec->efs_flags & EFX_FILTER_FLAG_RX_RSS) &&
459 gen_spec->efs_rss_context != 0) {
464 sf_spec->sfs_flags = gen_spec->efs_flags;
465 sf_spec->sfs_dmaq_id = gen_spec->efs_dmaq_id;
467 switch (gen_spec->efs_match_flags) {
468 case EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
469 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
470 EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT:
473 case EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
474 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT: {
475 uint32_t rhost, host1, host2;
476 uint16_t rport, port1, port2;
478 if (gen_spec->efs_ether_type != EFX_ETHER_TYPE_IPV4) {
482 if (gen_spec->efs_loc_port == 0 ||
483 (is_full && gen_spec->efs_rem_port == 0)) {
487 switch (gen_spec->efs_ip_proto) {
488 case EFX_IPPROTO_TCP:
489 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
490 sf_spec->sfs_type = (is_full ?
491 EFX_SIENA_FILTER_TX_TCP_FULL :
492 EFX_SIENA_FILTER_TX_TCP_WILD);
494 sf_spec->sfs_type = (is_full ?
495 EFX_SIENA_FILTER_RX_TCP_FULL :
496 EFX_SIENA_FILTER_RX_TCP_WILD);
499 case EFX_IPPROTO_UDP:
500 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
501 sf_spec->sfs_type = (is_full ?
502 EFX_SIENA_FILTER_TX_UDP_FULL :
503 EFX_SIENA_FILTER_TX_UDP_WILD);
505 sf_spec->sfs_type = (is_full ?
506 EFX_SIENA_FILTER_RX_UDP_FULL :
507 EFX_SIENA_FILTER_RX_UDP_WILD);
515 * The filter is constructed in terms of source and destination,
516 * with the odd wrinkle that the ports are swapped in a UDP
517 * wildcard filter. We need to convert from local and remote
518 * addresses (zero for a wildcard).
520 rhost = is_full ? gen_spec->efs_rem_host.eo_u32[0] : 0;
521 rport = is_full ? gen_spec->efs_rem_port : 0;
522 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
523 host1 = gen_spec->efs_loc_host.eo_u32[0];
527 host2 = gen_spec->efs_loc_host.eo_u32[0];
529 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
530 if (sf_spec->sfs_type ==
531 EFX_SIENA_FILTER_TX_UDP_WILD) {
533 port2 = gen_spec->efs_loc_port;
535 port1 = gen_spec->efs_loc_port;
539 if (sf_spec->sfs_type ==
540 EFX_SIENA_FILTER_RX_UDP_WILD) {
541 port1 = gen_spec->efs_loc_port;
545 port2 = gen_spec->efs_loc_port;
548 sf_spec->sfs_dword[0] = (host1 << 16) | port1;
549 sf_spec->sfs_dword[1] = (port2 << 16) | (host1 >> 16);
550 sf_spec->sfs_dword[2] = host2;
554 case EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_OUTER_VID:
557 case EFX_FILTER_MATCH_LOC_MAC:
558 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
559 sf_spec->sfs_type = (is_full ?
560 EFX_SIENA_FILTER_TX_MAC_FULL :
561 EFX_SIENA_FILTER_TX_MAC_WILD);
563 sf_spec->sfs_type = (is_full ?
564 EFX_SIENA_FILTER_RX_MAC_FULL :
565 EFX_SIENA_FILTER_RX_MAC_WILD);
567 sf_spec->sfs_dword[0] = is_full ? gen_spec->efs_outer_vid : 0;
568 sf_spec->sfs_dword[1] =
569 gen_spec->efs_loc_mac[2] << 24 |
570 gen_spec->efs_loc_mac[3] << 16 |
571 gen_spec->efs_loc_mac[4] << 8 |
572 gen_spec->efs_loc_mac[5];
573 sf_spec->sfs_dword[2] =
574 gen_spec->efs_loc_mac[0] << 8 |
575 gen_spec->efs_loc_mac[1];
579 EFSYS_ASSERT(B_FALSE);
595 EFSYS_PROBE1(fail1, efx_rc_t, rc);
601 * The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit
602 * key derived from the n-tuple.
605 siena_filter_tbl_hash(
610 /* First 16 rounds */
611 tmp = 0x1fff ^ (uint16_t)(key >> 16);
612 tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
613 tmp = tmp ^ tmp >> 9;
616 tmp = tmp ^ tmp << 13 ^ (uint16_t)(key & 0xffff);
617 tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
618 tmp = tmp ^ tmp >> 9;
624 * To allow for hash collisions, filter search continues at these
625 * increments from the first possible entry selected by the hash.
628 siena_filter_tbl_increment(
631 return ((uint16_t)(key * 2 - 1));
634 static __checkReturn boolean_t
635 siena_filter_test_used(
636 __in siena_filter_tbl_t *sftp,
637 __in unsigned int index)
639 EFSYS_ASSERT3P(sftp->sft_bitmap, !=, NULL);
640 return ((sftp->sft_bitmap[index / 32] & (1 << (index % 32))) != 0);
644 siena_filter_set_used(
645 __in siena_filter_tbl_t *sftp,
646 __in unsigned int index)
648 EFSYS_ASSERT3P(sftp->sft_bitmap, !=, NULL);
649 sftp->sft_bitmap[index / 32] |= (1 << (index % 32));
654 siena_filter_clear_used(
655 __in siena_filter_tbl_t *sftp,
656 __in unsigned int index)
658 EFSYS_ASSERT3P(sftp->sft_bitmap, !=, NULL);
659 sftp->sft_bitmap[index / 32] &= ~(1 << (index % 32));
662 EFSYS_ASSERT3U(sftp->sft_used, >=, 0);
666 static siena_filter_tbl_id_t
668 __in siena_filter_type_t type)
670 siena_filter_tbl_id_t tbl_id;
673 case EFX_SIENA_FILTER_RX_TCP_FULL:
674 case EFX_SIENA_FILTER_RX_TCP_WILD:
675 case EFX_SIENA_FILTER_RX_UDP_FULL:
676 case EFX_SIENA_FILTER_RX_UDP_WILD:
677 tbl_id = EFX_SIENA_FILTER_TBL_RX_IP;
680 case EFX_SIENA_FILTER_RX_MAC_FULL:
681 case EFX_SIENA_FILTER_RX_MAC_WILD:
682 tbl_id = EFX_SIENA_FILTER_TBL_RX_MAC;
685 case EFX_SIENA_FILTER_TX_TCP_FULL:
686 case EFX_SIENA_FILTER_TX_TCP_WILD:
687 case EFX_SIENA_FILTER_TX_UDP_FULL:
688 case EFX_SIENA_FILTER_TX_UDP_WILD:
689 tbl_id = EFX_SIENA_FILTER_TBL_TX_IP;
692 case EFX_SIENA_FILTER_TX_MAC_FULL:
693 case EFX_SIENA_FILTER_TX_MAC_WILD:
694 tbl_id = EFX_SIENA_FILTER_TBL_TX_MAC;
698 EFSYS_ASSERT(B_FALSE);
699 tbl_id = EFX_SIENA_FILTER_NTBLS;
706 siena_filter_reset_search_depth(
707 __inout siena_filter_t *sfp,
708 __in siena_filter_tbl_id_t tbl_id)
711 case EFX_SIENA_FILTER_TBL_RX_IP:
712 sfp->sf_depth[EFX_SIENA_FILTER_RX_TCP_FULL] = 0;
713 sfp->sf_depth[EFX_SIENA_FILTER_RX_TCP_WILD] = 0;
714 sfp->sf_depth[EFX_SIENA_FILTER_RX_UDP_FULL] = 0;
715 sfp->sf_depth[EFX_SIENA_FILTER_RX_UDP_WILD] = 0;
718 case EFX_SIENA_FILTER_TBL_RX_MAC:
719 sfp->sf_depth[EFX_SIENA_FILTER_RX_MAC_FULL] = 0;
720 sfp->sf_depth[EFX_SIENA_FILTER_RX_MAC_WILD] = 0;
723 case EFX_SIENA_FILTER_TBL_TX_IP:
724 sfp->sf_depth[EFX_SIENA_FILTER_TX_TCP_FULL] = 0;
725 sfp->sf_depth[EFX_SIENA_FILTER_TX_TCP_WILD] = 0;
726 sfp->sf_depth[EFX_SIENA_FILTER_TX_UDP_FULL] = 0;
727 sfp->sf_depth[EFX_SIENA_FILTER_TX_UDP_WILD] = 0;
730 case EFX_SIENA_FILTER_TBL_TX_MAC:
731 sfp->sf_depth[EFX_SIENA_FILTER_TX_MAC_FULL] = 0;
732 sfp->sf_depth[EFX_SIENA_FILTER_TX_MAC_WILD] = 0;
736 EFSYS_ASSERT(B_FALSE);
742 siena_filter_push_rx_limits(
745 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
748 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
750 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TCP_FULL_SRCH_LIMIT,
751 sfp->sf_depth[EFX_SIENA_FILTER_RX_TCP_FULL] +
752 FILTER_CTL_SRCH_FUDGE_FULL);
753 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TCP_WILD_SRCH_LIMIT,
754 sfp->sf_depth[EFX_SIENA_FILTER_RX_TCP_WILD] +
755 FILTER_CTL_SRCH_FUDGE_WILD);
756 EFX_SET_OWORD_FIELD(oword, FRF_AZ_UDP_FULL_SRCH_LIMIT,
757 sfp->sf_depth[EFX_SIENA_FILTER_RX_UDP_FULL] +
758 FILTER_CTL_SRCH_FUDGE_FULL);
759 EFX_SET_OWORD_FIELD(oword, FRF_AZ_UDP_WILD_SRCH_LIMIT,
760 sfp->sf_depth[EFX_SIENA_FILTER_RX_UDP_WILD] +
761 FILTER_CTL_SRCH_FUDGE_WILD);
763 if (sfp->sf_tbl[EFX_SIENA_FILTER_TBL_RX_MAC].sft_size) {
764 EFX_SET_OWORD_FIELD(oword,
765 FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT,
766 sfp->sf_depth[EFX_SIENA_FILTER_RX_MAC_FULL] +
767 FILTER_CTL_SRCH_FUDGE_FULL);
768 EFX_SET_OWORD_FIELD(oword,
769 FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT,
770 sfp->sf_depth[EFX_SIENA_FILTER_RX_MAC_WILD] +
771 FILTER_CTL_SRCH_FUDGE_WILD);
774 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
778 siena_filter_push_tx_limits(
781 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
784 EFX_BAR_READO(enp, FR_AZ_TX_CFG_REG, &oword);
786 if (sfp->sf_tbl[EFX_SIENA_FILTER_TBL_TX_IP].sft_size != 0) {
787 EFX_SET_OWORD_FIELD(oword,
788 FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE,
789 sfp->sf_depth[EFX_SIENA_FILTER_TX_TCP_FULL] +
790 FILTER_CTL_SRCH_FUDGE_FULL);
791 EFX_SET_OWORD_FIELD(oword,
792 FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE,
793 sfp->sf_depth[EFX_SIENA_FILTER_TX_TCP_WILD] +
794 FILTER_CTL_SRCH_FUDGE_WILD);
795 EFX_SET_OWORD_FIELD(oword,
796 FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE,
797 sfp->sf_depth[EFX_SIENA_FILTER_TX_UDP_FULL] +
798 FILTER_CTL_SRCH_FUDGE_FULL);
799 EFX_SET_OWORD_FIELD(oword,
800 FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE,
801 sfp->sf_depth[EFX_SIENA_FILTER_TX_UDP_WILD] +
802 FILTER_CTL_SRCH_FUDGE_WILD);
805 if (sfp->sf_tbl[EFX_SIENA_FILTER_TBL_TX_MAC].sft_size != 0) {
807 oword, FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE,
808 sfp->sf_depth[EFX_SIENA_FILTER_TX_MAC_FULL] +
809 FILTER_CTL_SRCH_FUDGE_FULL);
811 oword, FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE,
812 sfp->sf_depth[EFX_SIENA_FILTER_TX_MAC_WILD] +
813 FILTER_CTL_SRCH_FUDGE_WILD);
816 EFX_BAR_WRITEO(enp, FR_AZ_TX_CFG_REG, &oword);
819 /* Build a filter entry and return its n-tuple key. */
820 static __checkReturn uint32_t
822 __out efx_oword_t *filter,
823 __in siena_filter_spec_t *spec)
827 uint8_t type = spec->sfs_type;
828 uint32_t flags = spec->sfs_flags;
830 switch (siena_filter_tbl_id(type)) {
831 case EFX_SIENA_FILTER_TBL_RX_IP: {
832 boolean_t is_udp = (type == EFX_SIENA_FILTER_RX_UDP_FULL ||
833 type == EFX_SIENA_FILTER_RX_UDP_WILD);
834 EFX_POPULATE_OWORD_7(*filter,
836 (flags & EFX_FILTER_FLAG_RX_RSS) ? 1 : 0,
838 (flags & EFX_FILTER_FLAG_RX_SCATTER) ? 1 : 0,
839 FRF_AZ_TCP_UDP, is_udp,
840 FRF_AZ_RXQ_ID, spec->sfs_dmaq_id,
841 EFX_DWORD_2, spec->sfs_dword[2],
842 EFX_DWORD_1, spec->sfs_dword[1],
843 EFX_DWORD_0, spec->sfs_dword[0]);
848 case EFX_SIENA_FILTER_TBL_RX_MAC: {
849 boolean_t is_wild = (type == EFX_SIENA_FILTER_RX_MAC_WILD);
850 EFX_POPULATE_OWORD_7(*filter,
852 (flags & EFX_FILTER_FLAG_RX_RSS) ? 1 : 0,
853 FRF_CZ_RMFT_SCATTER_EN,
854 (flags & EFX_FILTER_FLAG_RX_SCATTER) ? 1 : 0,
855 FRF_CZ_RMFT_RXQ_ID, spec->sfs_dmaq_id,
856 FRF_CZ_RMFT_WILDCARD_MATCH, is_wild,
857 FRF_CZ_RMFT_DEST_MAC_DW1, spec->sfs_dword[2],
858 FRF_CZ_RMFT_DEST_MAC_DW0, spec->sfs_dword[1],
859 FRF_CZ_RMFT_VLAN_ID, spec->sfs_dword[0]);
864 case EFX_SIENA_FILTER_TBL_TX_IP: {
865 boolean_t is_udp = (type == EFX_SIENA_FILTER_TX_UDP_FULL ||
866 type == EFX_SIENA_FILTER_TX_UDP_WILD);
867 EFX_POPULATE_OWORD_5(*filter,
868 FRF_CZ_TIFT_TCP_UDP, is_udp,
869 FRF_CZ_TIFT_TXQ_ID, spec->sfs_dmaq_id,
870 EFX_DWORD_2, spec->sfs_dword[2],
871 EFX_DWORD_1, spec->sfs_dword[1],
872 EFX_DWORD_0, spec->sfs_dword[0]);
873 dword3 = is_udp | spec->sfs_dmaq_id << 1;
877 case EFX_SIENA_FILTER_TBL_TX_MAC: {
878 boolean_t is_wild = (type == EFX_SIENA_FILTER_TX_MAC_WILD);
879 EFX_POPULATE_OWORD_5(*filter,
880 FRF_CZ_TMFT_TXQ_ID, spec->sfs_dmaq_id,
881 FRF_CZ_TMFT_WILDCARD_MATCH, is_wild,
882 FRF_CZ_TMFT_SRC_MAC_DW1, spec->sfs_dword[2],
883 FRF_CZ_TMFT_SRC_MAC_DW0, spec->sfs_dword[1],
884 FRF_CZ_TMFT_VLAN_ID, spec->sfs_dword[0]);
885 dword3 = is_wild | spec->sfs_dmaq_id << 1;
890 EFSYS_ASSERT(B_FALSE);
903 static __checkReturn efx_rc_t
904 siena_filter_push_entry(
905 __inout efx_nic_t *enp,
906 __in siena_filter_type_t type,
908 __in efx_oword_t *eop)
913 case EFX_SIENA_FILTER_RX_TCP_FULL:
914 case EFX_SIENA_FILTER_RX_TCP_WILD:
915 case EFX_SIENA_FILTER_RX_UDP_FULL:
916 case EFX_SIENA_FILTER_RX_UDP_WILD:
917 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_FILTER_TBL0, index,
921 case EFX_SIENA_FILTER_RX_MAC_FULL:
922 case EFX_SIENA_FILTER_RX_MAC_WILD:
923 EFX_BAR_TBL_WRITEO(enp, FR_CZ_RX_MAC_FILTER_TBL0, index,
927 case EFX_SIENA_FILTER_TX_TCP_FULL:
928 case EFX_SIENA_FILTER_TX_TCP_WILD:
929 case EFX_SIENA_FILTER_TX_UDP_FULL:
930 case EFX_SIENA_FILTER_TX_UDP_WILD:
931 EFX_BAR_TBL_WRITEO(enp, FR_CZ_TX_FILTER_TBL0, index,
935 case EFX_SIENA_FILTER_TX_MAC_FULL:
936 case EFX_SIENA_FILTER_TX_MAC_WILD:
937 EFX_BAR_TBL_WRITEO(enp, FR_CZ_TX_MAC_FILTER_TBL0, index,
942 EFSYS_ASSERT(B_FALSE);
953 static __checkReturn boolean_t
955 __in const siena_filter_spec_t *left,
956 __in const siena_filter_spec_t *right)
958 siena_filter_tbl_id_t tbl_id;
960 tbl_id = siena_filter_tbl_id(left->sfs_type);
963 if (left->sfs_type != right->sfs_type)
966 if (memcmp(left->sfs_dword, right->sfs_dword,
967 sizeof (left->sfs_dword)))
970 if ((tbl_id == EFX_SIENA_FILTER_TBL_TX_IP ||
971 tbl_id == EFX_SIENA_FILTER_TBL_TX_MAC) &&
972 left->sfs_dmaq_id != right->sfs_dmaq_id)
978 static __checkReturn efx_rc_t
980 __in siena_filter_tbl_t *sftp,
981 __in siena_filter_spec_t *spec,
983 __in boolean_t for_insert,
984 __out int *filter_index,
985 __out unsigned int *depth_required)
987 unsigned int hash, incr, filter_idx, depth;
989 hash = siena_filter_tbl_hash(key);
990 incr = siena_filter_tbl_increment(key);
992 filter_idx = hash & (sftp->sft_size - 1);
997 * Return success if entry is used and matches this spec
998 * or entry is unused and we are trying to insert.
1000 if (siena_filter_test_used(sftp, filter_idx) ?
1001 siena_filter_equal(spec,
1002 &sftp->sft_spec[filter_idx]) :
1004 *filter_index = filter_idx;
1005 *depth_required = depth;
1009 /* Return failure if we reached the maximum search depth */
1010 if (depth == FILTER_CTL_SRCH_MAX)
1011 return (for_insert ? EBUSY : ENOENT);
1013 filter_idx = (filter_idx + incr) & (sftp->sft_size - 1);
1019 siena_filter_clear_entry(
1020 __in efx_nic_t *enp,
1021 __in siena_filter_tbl_t *sftp,
1026 if (siena_filter_test_used(sftp, index)) {
1027 siena_filter_clear_used(sftp, index);
1029 EFX_ZERO_OWORD(filter);
1030 siena_filter_push_entry(enp,
1031 sftp->sft_spec[index].sfs_type,
1034 memset(&sftp->sft_spec[index],
1035 0, sizeof (sftp->sft_spec[0]));
1040 siena_filter_tbl_clear(
1041 __in efx_nic_t *enp,
1042 __in siena_filter_tbl_id_t tbl_id)
1044 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1045 siena_filter_tbl_t *sftp = &sfp->sf_tbl[tbl_id];
1047 efsys_lock_state_t state;
1049 EFSYS_LOCK(enp->en_eslp, state);
1051 for (index = 0; index < sftp->sft_size; ++index) {
1052 siena_filter_clear_entry(enp, sftp, index);
1055 if (sftp->sft_used == 0)
1056 siena_filter_reset_search_depth(sfp, tbl_id);
1058 EFSYS_UNLOCK(enp->en_eslp, state);
1061 static __checkReturn efx_rc_t
1063 __in efx_nic_t *enp)
1065 siena_filter_t *sfp;
1066 siena_filter_tbl_t *sftp;
1070 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (siena_filter_t), sfp);
1077 enp->en_filter.ef_siena_filter = sfp;
1079 switch (enp->en_family) {
1080 case EFX_FAMILY_SIENA:
1081 sftp = &sfp->sf_tbl[EFX_SIENA_FILTER_TBL_RX_IP];
1082 sftp->sft_size = FR_AZ_RX_FILTER_TBL0_ROWS;
1084 sftp = &sfp->sf_tbl[EFX_SIENA_FILTER_TBL_RX_MAC];
1085 sftp->sft_size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS;
1087 sftp = &sfp->sf_tbl[EFX_SIENA_FILTER_TBL_TX_IP];
1088 sftp->sft_size = FR_CZ_TX_FILTER_TBL0_ROWS;
1090 sftp = &sfp->sf_tbl[EFX_SIENA_FILTER_TBL_TX_MAC];
1091 sftp->sft_size = FR_CZ_TX_MAC_FILTER_TBL0_ROWS;
1099 for (tbl_id = 0; tbl_id < EFX_SIENA_FILTER_NTBLS; tbl_id++) {
1100 unsigned int bitmap_size;
1102 sftp = &sfp->sf_tbl[tbl_id];
1103 if (sftp->sft_size == 0)
1106 EFX_STATIC_ASSERT(sizeof (sftp->sft_bitmap[0]) ==
1109 (sftp->sft_size + (sizeof (uint32_t) * 8) - 1) / 8;
1111 EFSYS_KMEM_ALLOC(enp->en_esip, bitmap_size, sftp->sft_bitmap);
1112 if (!sftp->sft_bitmap) {
1117 EFSYS_KMEM_ALLOC(enp->en_esip,
1118 sftp->sft_size * sizeof (*sftp->sft_spec),
1120 if (!sftp->sft_spec) {
1124 memset(sftp->sft_spec, 0,
1125 sftp->sft_size * sizeof (*sftp->sft_spec));
1138 siena_filter_fini(enp);
1141 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1147 __in efx_nic_t *enp)
1149 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1150 siena_filter_tbl_id_t tbl_id;
1152 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1153 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
1158 for (tbl_id = 0; tbl_id < EFX_SIENA_FILTER_NTBLS; tbl_id++) {
1159 siena_filter_tbl_t *sftp = &sfp->sf_tbl[tbl_id];
1160 unsigned int bitmap_size;
1162 EFX_STATIC_ASSERT(sizeof (sftp->sft_bitmap[0]) ==
1165 (sftp->sft_size + (sizeof (uint32_t) * 8) - 1) / 8;
1167 if (sftp->sft_bitmap != NULL) {
1168 EFSYS_KMEM_FREE(enp->en_esip, bitmap_size,
1170 sftp->sft_bitmap = NULL;
1173 if (sftp->sft_spec != NULL) {
1174 EFSYS_KMEM_FREE(enp->en_esip, sftp->sft_size *
1175 sizeof (*sftp->sft_spec), sftp->sft_spec);
1176 sftp->sft_spec = NULL;
1180 EFSYS_KMEM_FREE(enp->en_esip, sizeof (siena_filter_t),
1181 enp->en_filter.ef_siena_filter);
1184 /* Restore filter state after a reset */
1185 static __checkReturn efx_rc_t
1186 siena_filter_restore(
1187 __in efx_nic_t *enp)
1189 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1190 siena_filter_tbl_id_t tbl_id;
1191 siena_filter_tbl_t *sftp;
1192 siena_filter_spec_t *spec;
1195 efsys_lock_state_t state;
1199 EFSYS_LOCK(enp->en_eslp, state);
1201 for (tbl_id = 0; tbl_id < EFX_SIENA_FILTER_NTBLS; tbl_id++) {
1202 sftp = &sfp->sf_tbl[tbl_id];
1203 for (filter_idx = 0;
1204 filter_idx < sftp->sft_size;
1206 if (!siena_filter_test_used(sftp, filter_idx))
1209 spec = &sftp->sft_spec[filter_idx];
1210 if ((key = siena_filter_build(&filter, spec)) == 0) {
1214 if ((rc = siena_filter_push_entry(enp,
1215 spec->sfs_type, filter_idx, &filter)) != 0)
1220 siena_filter_push_rx_limits(enp);
1221 siena_filter_push_tx_limits(enp);
1223 EFSYS_UNLOCK(enp->en_eslp, state);
1231 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1233 EFSYS_UNLOCK(enp->en_eslp, state);
1238 static __checkReturn efx_rc_t
1240 __in efx_nic_t *enp,
1241 __inout efx_filter_spec_t *spec,
1242 __in boolean_t may_replace)
1245 siena_filter_spec_t sf_spec;
1246 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1247 siena_filter_tbl_id_t tbl_id;
1248 siena_filter_tbl_t *sftp;
1249 siena_filter_spec_t *saved_sf_spec;
1253 efsys_lock_state_t state;
1257 EFSYS_ASSERT3P(spec, !=, NULL);
1259 if ((rc = siena_filter_spec_from_gen_spec(&sf_spec, spec)) != 0)
1262 tbl_id = siena_filter_tbl_id(sf_spec.sfs_type);
1263 sftp = &sfp->sf_tbl[tbl_id];
1265 if (sftp->sft_size == 0) {
1270 key = siena_filter_build(&filter, &sf_spec);
1272 EFSYS_LOCK(enp->en_eslp, state);
1274 rc = siena_filter_search(sftp, &sf_spec, key, B_TRUE,
1275 &filter_idx, &depth);
1279 EFSYS_ASSERT3U(filter_idx, <, sftp->sft_size);
1280 saved_sf_spec = &sftp->sft_spec[filter_idx];
1282 if (siena_filter_test_used(sftp, filter_idx)) {
1283 if (may_replace == B_FALSE) {
1288 siena_filter_set_used(sftp, filter_idx);
1289 *saved_sf_spec = sf_spec;
1291 if (sfp->sf_depth[sf_spec.sfs_type] < depth) {
1292 sfp->sf_depth[sf_spec.sfs_type] = depth;
1293 if (tbl_id == EFX_SIENA_FILTER_TBL_TX_IP ||
1294 tbl_id == EFX_SIENA_FILTER_TBL_TX_MAC)
1295 siena_filter_push_tx_limits(enp);
1297 siena_filter_push_rx_limits(enp);
1300 siena_filter_push_entry(enp, sf_spec.sfs_type,
1301 filter_idx, &filter);
1303 EFSYS_UNLOCK(enp->en_eslp, state);
1310 EFSYS_UNLOCK(enp->en_eslp, state);
1317 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1321 static __checkReturn efx_rc_t
1322 siena_filter_delete(
1323 __in efx_nic_t *enp,
1324 __inout efx_filter_spec_t *spec)
1327 siena_filter_spec_t sf_spec;
1328 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1329 siena_filter_tbl_id_t tbl_id;
1330 siena_filter_tbl_t *sftp;
1334 efsys_lock_state_t state;
1337 EFSYS_ASSERT3P(spec, !=, NULL);
1339 if ((rc = siena_filter_spec_from_gen_spec(&sf_spec, spec)) != 0)
1342 tbl_id = siena_filter_tbl_id(sf_spec.sfs_type);
1343 sftp = &sfp->sf_tbl[tbl_id];
1345 key = siena_filter_build(&filter, &sf_spec);
1347 EFSYS_LOCK(enp->en_eslp, state);
1349 rc = siena_filter_search(sftp, &sf_spec, key, B_FALSE,
1350 &filter_idx, &depth);
1354 siena_filter_clear_entry(enp, sftp, filter_idx);
1355 if (sftp->sft_used == 0)
1356 siena_filter_reset_search_depth(sfp, tbl_id);
1358 EFSYS_UNLOCK(enp->en_eslp, state);
1362 EFSYS_UNLOCK(enp->en_eslp, state);
1366 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1370 #define SIENA_MAX_SUPPORTED_MATCHES 4
1372 static __checkReturn efx_rc_t
1373 siena_filter_supported_filters(
1374 __in efx_nic_t *enp,
1375 __out_ecount(buffer_length) uint32_t *buffer,
1376 __in size_t buffer_length,
1377 __out size_t *list_lengthp)
1380 uint32_t rx_matches[SIENA_MAX_SUPPORTED_MATCHES];
1384 rx_matches[index++] =
1385 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
1386 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
1387 EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT;
1389 rx_matches[index++] =
1390 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
1391 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
1393 if (enp->en_features & EFX_FEATURE_MAC_HEADER_FILTERS) {
1394 rx_matches[index++] =
1395 EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC;
1397 rx_matches[index++] = EFX_FILTER_MATCH_LOC_MAC;
1400 EFSYS_ASSERT3U(index, <=, SIENA_MAX_SUPPORTED_MATCHES);
1401 list_length = index;
1403 *list_lengthp = list_length;
1405 if (buffer_length < list_length) {
1410 memcpy(buffer, rx_matches, list_length * sizeof (rx_matches[0]));
1415 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1420 #undef MAX_SUPPORTED
1422 #endif /* EFSYS_OPT_SIENA */
1424 #endif /* EFSYS_OPT_FILTER */