4 * Copyright (C) Cavium, Inc. 2016.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Cavium, Inc nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <netinet/in.h>
43 #include <sys/queue.h>
45 #include <rte_alarm.h>
46 #include <rte_atomic.h>
47 #include <rte_branch_prediction.h>
48 #include <rte_byteorder.h>
49 #include <rte_common.h>
50 #include <rte_cycles.h>
51 #include <rte_debug.h>
54 #include <rte_ether.h>
55 #include <rte_ethdev.h>
56 #include <rte_ethdev_pci.h>
57 #include <rte_interrupts.h>
59 #include <rte_memory.h>
60 #include <rte_memzone.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
64 #include <rte_bus_pci.h>
65 #include <rte_tailq.h>
67 #include "base/nicvf_plat.h"
69 #include "nicvf_ethdev.h"
70 #include "nicvf_rxtx.h"
71 #include "nicvf_svf.h"
72 #include "nicvf_logs.h"
74 static void nicvf_dev_stop(struct rte_eth_dev *dev);
75 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup);
76 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic,
80 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
81 struct rte_eth_link *link)
83 struct rte_eth_link *dst = &dev->data->dev_link;
84 struct rte_eth_link *src = link;
86 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
87 *(uint64_t *)src) == 0)
94 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
96 link->link_status = nic->link_up;
97 link->link_duplex = ETH_LINK_AUTONEG;
98 if (nic->duplex == NICVF_HALF_DUPLEX)
99 link->link_duplex = ETH_LINK_HALF_DUPLEX;
100 else if (nic->duplex == NICVF_FULL_DUPLEX)
101 link->link_duplex = ETH_LINK_FULL_DUPLEX;
102 link->link_speed = nic->speed;
103 link->link_autoneg = ETH_LINK_AUTONEG;
107 nicvf_interrupt(void *arg)
109 struct rte_eth_dev *dev = arg;
110 struct nicvf *nic = nicvf_pmd_priv(dev);
112 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
113 if (dev->data->dev_conf.intr_conf.lsc)
114 nicvf_set_eth_link_status(nic, &dev->data->dev_link);
115 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
119 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
120 nicvf_interrupt, dev);
124 nicvf_vf_interrupt(void *arg)
126 struct nicvf *nic = arg;
128 nicvf_reg_poll_interrupts(nic);
130 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
131 nicvf_vf_interrupt, nic);
135 nicvf_periodic_alarm_start(void (fn)(void *), void *arg)
137 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg);
141 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg)
143 return rte_eal_alarm_cancel(fn, arg);
147 * Return 0 means link status changed, -1 means not changed
150 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
152 #define CHECK_INTERVAL 100 /* 100ms */
153 #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */
154 struct rte_eth_link link;
155 struct nicvf *nic = nicvf_pmd_priv(dev);
158 PMD_INIT_FUNC_TRACE();
160 if (wait_to_complete) {
161 /* rte_eth_link_get() might need to wait up to 9 seconds */
162 for (i = 0; i < MAX_CHECK_TIME; i++) {
163 memset(&link, 0, sizeof(link));
164 nicvf_set_eth_link_status(nic, &link);
165 if (link.link_status)
167 rte_delay_ms(CHECK_INTERVAL);
170 memset(&link, 0, sizeof(link));
171 nicvf_set_eth_link_status(nic, &link);
173 return nicvf_atomic_write_link_status(dev, &link);
177 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
179 struct nicvf *nic = nicvf_pmd_priv(dev);
180 uint32_t buffsz, frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
183 PMD_INIT_FUNC_TRACE();
185 if (frame_size > NIC_HW_MAX_FRS)
188 if (frame_size < NIC_HW_MIN_FRS)
191 buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
194 * Refuse mtu that requires the support of scattered packets
195 * when this feature has not been enabled before.
197 if (!dev->data->scattered_rx &&
198 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
201 /* check <seg size> * <max_seg> >= max_frame */
202 if (dev->data->scattered_rx &&
203 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
206 if (frame_size > ETHER_MAX_LEN)
207 dev->data->dev_conf.rxmode.jumbo_frame = 1;
209 dev->data->dev_conf.rxmode.jumbo_frame = 0;
211 if (nicvf_mbox_update_hw_max_frs(nic, frame_size))
214 /* Update max frame size */
215 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)frame_size;
218 for (i = 0; i < nic->sqs_count; i++)
219 nic->snicvf[i]->mtu = mtu;
225 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
227 uint64_t *data = regs->data;
228 struct nicvf *nic = nicvf_pmd_priv(dev);
231 regs->length = nicvf_reg_get_count();
232 regs->width = THUNDERX_REG_BYTES;
236 /* Support only full register dump */
237 if ((regs->length == 0) ||
238 (regs->length == (uint32_t)nicvf_reg_get_count())) {
239 regs->version = nic->vendor_id << 16 | nic->device_id;
240 nicvf_reg_dump(nic, data);
247 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
250 struct nicvf_hw_rx_qstats rx_qstats;
251 struct nicvf_hw_tx_qstats tx_qstats;
252 struct nicvf_hw_stats port_stats;
253 struct nicvf *nic = nicvf_pmd_priv(dev);
254 uint16_t rx_start, rx_end;
255 uint16_t tx_start, tx_end;
258 /* RX queue indices for the first VF */
259 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
261 /* Reading per RX ring stats */
262 for (qidx = rx_start; qidx <= rx_end; qidx++) {
263 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
266 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx);
267 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
268 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
271 /* TX queue indices for the first VF */
272 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
274 /* Reading per TX ring stats */
275 for (qidx = tx_start; qidx <= tx_end; qidx++) {
276 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
279 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx);
280 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
281 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
284 for (i = 0; i < nic->sqs_count; i++) {
285 struct nicvf *snic = nic->snicvf[i];
290 /* RX queue indices for a secondary VF */
291 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
293 /* Reading per RX ring stats */
294 for (qidx = rx_start; qidx <= rx_end; qidx++) {
295 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
298 nicvf_hw_get_rx_qstats(snic, &rx_qstats,
299 qidx % MAX_RCV_QUEUES_PER_QS);
300 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
301 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
304 /* TX queue indices for a secondary VF */
305 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
306 /* Reading per TX ring stats */
307 for (qidx = tx_start; qidx <= tx_end; qidx++) {
308 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
311 nicvf_hw_get_tx_qstats(snic, &tx_qstats,
312 qidx % MAX_SND_QUEUES_PER_QS);
313 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
314 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
318 nicvf_hw_get_stats(nic, &port_stats);
319 stats->ibytes = port_stats.rx_bytes;
320 stats->ipackets = port_stats.rx_ucast_frames;
321 stats->ipackets += port_stats.rx_bcast_frames;
322 stats->ipackets += port_stats.rx_mcast_frames;
323 stats->ierrors = port_stats.rx_l2_errors;
324 stats->imissed = port_stats.rx_drop_red;
325 stats->imissed += port_stats.rx_drop_overrun;
326 stats->imissed += port_stats.rx_drop_bcast;
327 stats->imissed += port_stats.rx_drop_mcast;
328 stats->imissed += port_stats.rx_drop_l3_bcast;
329 stats->imissed += port_stats.rx_drop_l3_mcast;
331 stats->obytes = port_stats.tx_bytes_ok;
332 stats->opackets = port_stats.tx_ucast_frames_ok;
333 stats->opackets += port_stats.tx_bcast_frames_ok;
334 stats->opackets += port_stats.tx_mcast_frames_ok;
335 stats->oerrors = port_stats.tx_drops;
340 static const uint32_t *
341 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev)
344 static uint32_t ptypes[32];
345 struct nicvf *nic = nicvf_pmd_priv(dev);
346 static const uint32_t ptypes_common[] = {
348 RTE_PTYPE_L3_IPV4_EXT,
350 RTE_PTYPE_L3_IPV6_EXT,
355 static const uint32_t ptypes_tunnel[] = {
356 RTE_PTYPE_TUNNEL_GRE,
357 RTE_PTYPE_TUNNEL_GENEVE,
358 RTE_PTYPE_TUNNEL_VXLAN,
359 RTE_PTYPE_TUNNEL_NVGRE,
361 static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN;
363 copied = sizeof(ptypes_common);
364 memcpy(ptypes, ptypes_common, copied);
365 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
366 memcpy((char *)ptypes + copied, ptypes_tunnel,
367 sizeof(ptypes_tunnel));
368 copied += sizeof(ptypes_tunnel);
371 memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end));
372 if (dev->rx_pkt_burst == nicvf_recv_pkts ||
373 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg)
380 nicvf_dev_stats_reset(struct rte_eth_dev *dev)
383 uint16_t rxqs = 0, txqs = 0;
384 struct nicvf *nic = nicvf_pmd_priv(dev);
385 uint16_t rx_start, rx_end;
386 uint16_t tx_start, tx_end;
388 /* Reset all primary nic counters */
389 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
390 for (i = rx_start; i <= rx_end; i++)
391 rxqs |= (0x3 << (i * 2));
393 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
394 for (i = tx_start; i <= tx_end; i++)
395 txqs |= (0x3 << (i * 2));
397 nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs);
399 /* Reset secondary nic queue counters */
400 for (i = 0; i < nic->sqs_count; i++) {
401 struct nicvf *snic = nic->snicvf[i];
405 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
406 for (i = rx_start; i <= rx_end; i++)
407 rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2));
409 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
410 for (i = tx_start; i <= tx_end; i++)
411 txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2));
413 nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs);
417 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
419 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
423 static inline uint64_t
424 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
426 uint64_t nic_rss = 0;
428 if (ethdev_rss & ETH_RSS_IPV4)
429 nic_rss |= RSS_IP_ENA;
431 if (ethdev_rss & ETH_RSS_IPV6)
432 nic_rss |= RSS_IP_ENA;
434 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
435 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
437 if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
438 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
440 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
441 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
443 if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
444 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
446 if (ethdev_rss & ETH_RSS_PORT)
447 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
449 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
450 if (ethdev_rss & ETH_RSS_VXLAN)
451 nic_rss |= RSS_TUN_VXLAN_ENA;
453 if (ethdev_rss & ETH_RSS_GENEVE)
454 nic_rss |= RSS_TUN_GENEVE_ENA;
456 if (ethdev_rss & ETH_RSS_NVGRE)
457 nic_rss |= RSS_TUN_NVGRE_ENA;
463 static inline uint64_t
464 nicvf_rss_nic_to_ethdev(struct nicvf *nic, uint64_t nic_rss)
466 uint64_t ethdev_rss = 0;
468 if (nic_rss & RSS_IP_ENA)
469 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
471 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
472 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
473 ETH_RSS_NONFRAG_IPV6_TCP);
475 if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
476 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
477 ETH_RSS_NONFRAG_IPV6_UDP);
479 if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
480 ethdev_rss |= ETH_RSS_PORT;
482 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
483 if (nic_rss & RSS_TUN_VXLAN_ENA)
484 ethdev_rss |= ETH_RSS_VXLAN;
486 if (nic_rss & RSS_TUN_GENEVE_ENA)
487 ethdev_rss |= ETH_RSS_GENEVE;
489 if (nic_rss & RSS_TUN_NVGRE_ENA)
490 ethdev_rss |= ETH_RSS_NVGRE;
496 nicvf_dev_reta_query(struct rte_eth_dev *dev,
497 struct rte_eth_rss_reta_entry64 *reta_conf,
500 struct nicvf *nic = nicvf_pmd_priv(dev);
501 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
504 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
505 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
506 "(%d) doesn't match the number hardware can supported "
507 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
511 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
515 /* Copy RETA table */
516 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
517 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
518 if ((reta_conf[i].mask >> j) & 0x01)
519 reta_conf[i].reta[j] = tbl[j];
526 nicvf_dev_reta_update(struct rte_eth_dev *dev,
527 struct rte_eth_rss_reta_entry64 *reta_conf,
530 struct nicvf *nic = nicvf_pmd_priv(dev);
531 uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
534 if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
535 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
536 "(%d) doesn't match the number hardware can supported "
537 "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
541 ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
545 /* Copy RETA table */
546 for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
547 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
548 if ((reta_conf[i].mask >> j) & 0x01)
549 tbl[j] = reta_conf[i].reta[j];
552 return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
556 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
557 struct rte_eth_rss_conf *rss_conf)
559 struct nicvf *nic = nicvf_pmd_priv(dev);
561 if (rss_conf->rss_key)
562 nicvf_rss_get_key(nic, rss_conf->rss_key);
564 rss_conf->rss_key_len = RSS_HASH_KEY_BYTE_SIZE;
565 rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
570 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
571 struct rte_eth_rss_conf *rss_conf)
573 struct nicvf *nic = nicvf_pmd_priv(dev);
576 if (rss_conf->rss_key &&
577 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
578 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
579 rss_conf->rss_key_len);
583 if (rss_conf->rss_key)
584 nicvf_rss_set_key(nic, rss_conf->rss_key);
586 nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
587 nicvf_rss_set_cfg(nic, nic_rss);
592 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
593 struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt)
595 const struct rte_memzone *rz;
596 uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t);
598 rz = rte_eth_dma_zone_reserve(dev, "cq_ring",
599 nicvf_netdev_qidx(nic, qidx), ring_size,
600 NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
602 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
606 memset(rz->addr, 0, ring_size);
608 rxq->phys = rz->iova;
609 rxq->desc = rz->addr;
610 rxq->qlen_mask = desc_cnt - 1;
616 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
617 struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt)
619 const struct rte_memzone *rz;
620 uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t);
622 rz = rte_eth_dma_zone_reserve(dev, "sq",
623 nicvf_netdev_qidx(nic, qidx), ring_size,
624 NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
626 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
630 memset(rz->addr, 0, ring_size);
634 sq->qlen_mask = desc_cnt - 1;
640 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
641 uint32_t desc_cnt, uint32_t buffsz)
643 struct nicvf_rbdr *rbdr;
644 const struct rte_memzone *rz;
647 assert(nic->rbdr == NULL);
648 rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr),
649 RTE_CACHE_LINE_SIZE, nic->node);
651 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr");
655 ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX;
656 rz = rte_eth_dma_zone_reserve(dev, "rbdr",
657 nicvf_netdev_qidx(nic, 0), ring_size,
658 NICVF_RBDR_BASE_ALIGN_BYTES, nic->node);
660 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring");
664 memset(rz->addr, 0, ring_size);
666 rbdr->phys = rz->iova;
669 rbdr->desc = rz->addr;
670 rbdr->buffsz = buffsz;
671 rbdr->qlen_mask = desc_cnt - 1;
673 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0;
675 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR;
682 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic,
683 nicvf_iova_addr_t phy)
687 struct nicvf_rxq *rxq;
688 uint16_t rx_start, rx_end;
690 /* Get queue ranges for this VF */
691 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
693 for (qidx = rx_start; qidx <= rx_end; qidx++) {
694 rxq = dev->data->rx_queues[qidx];
695 if (rxq->precharge_cnt) {
696 obj = (void *)nicvf_mbuff_phy2virt(phy,
698 rte_mempool_put(rxq->pool, obj);
699 rxq->precharge_cnt--;
706 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic)
708 uint32_t qlen_mask, head;
709 struct rbdr_entry_t *entry;
710 struct nicvf_rbdr *rbdr = nic->rbdr;
712 qlen_mask = rbdr->qlen_mask;
714 while (head != rbdr->tail) {
715 entry = rbdr->desc + head;
716 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr);
718 head = head & qlen_mask;
723 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
728 while (head != txq->tail) {
729 if (txq->txbuffs[head]) {
730 rte_pktmbuf_free_seg(txq->txbuffs[head]);
731 txq->txbuffs[head] = NULL;
734 head = head & txq->qlen_mask;
739 nicvf_tx_queue_reset(struct nicvf_txq *txq)
741 uint32_t txq_desc_cnt = txq->qlen_mask + 1;
743 memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
744 memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
751 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
754 struct nicvf_txq *txq;
757 assert(qidx < MAX_SND_QUEUES_PER_QS);
759 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
760 RTE_ETH_QUEUE_STATE_STARTED)
763 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
765 ret = nicvf_qset_sq_config(nic, qidx, txq);
767 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d",
768 nic->vf_id, qidx, ret);
769 goto config_sq_error;
772 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
773 RTE_ETH_QUEUE_STATE_STARTED;
777 nicvf_qset_sq_reclaim(nic, qidx);
782 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
785 struct nicvf_txq *txq;
788 assert(qidx < MAX_SND_QUEUES_PER_QS);
790 if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
791 RTE_ETH_QUEUE_STATE_STOPPED)
794 ret = nicvf_qset_sq_reclaim(nic, qidx);
796 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d",
797 nic->vf_id, qidx, ret);
799 txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
800 nicvf_tx_queue_release_mbufs(txq);
801 nicvf_tx_queue_reset(txq);
803 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
804 RTE_ETH_QUEUE_STATE_STOPPED;
809 nicvf_configure_cpi(struct rte_eth_dev *dev)
811 struct nicvf *nic = nicvf_pmd_priv(dev);
815 /* Count started rx queues */
816 for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++)
817 if (dev->data->rx_queue_state[qidx] ==
818 RTE_ETH_QUEUE_STATE_STARTED)
821 nic->cpi_alg = CPI_ALG_NONE;
822 ret = nicvf_mbox_config_cpi(nic, qcnt);
824 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret);
830 nicvf_configure_rss(struct rte_eth_dev *dev)
832 struct nicvf *nic = nicvf_pmd_priv(dev);
836 rsshf = nicvf_rss_ethdev_to_nic(nic,
837 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf);
838 PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64,
839 dev->data->dev_conf.rxmode.mq_mode,
840 dev->data->nb_rx_queues,
841 dev->data->dev_conf.lpbk_mode, rsshf);
843 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
844 ret = nicvf_rss_term(nic);
845 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
846 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf);
848 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret);
854 nicvf_configure_rss_reta(struct rte_eth_dev *dev)
856 struct nicvf *nic = nicvf_pmd_priv(dev);
857 unsigned int idx, qmap_size;
858 uint8_t qmap[RTE_MAX_QUEUES_PER_PORT];
859 uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE];
861 if (nic->cpi_alg != CPI_ALG_NONE)
864 /* Prepare queue map */
865 for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) {
866 if (dev->data->rx_queue_state[idx] ==
867 RTE_ETH_QUEUE_STATE_STARTED)
868 qmap[qmap_size++] = idx;
871 /* Update default RSS RETA */
872 for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
873 default_reta[idx] = qmap[idx % qmap_size];
875 return nicvf_rss_reta_update(nic, default_reta,
876 NIC_MAX_RSS_IDR_TBL_SIZE);
880 nicvf_dev_tx_queue_release(void *sq)
882 struct nicvf_txq *txq;
884 PMD_INIT_FUNC_TRACE();
886 txq = (struct nicvf_txq *)sq;
888 if (txq->txbuffs != NULL) {
889 nicvf_tx_queue_release_mbufs(txq);
890 rte_free(txq->txbuffs);
898 nicvf_set_tx_function(struct rte_eth_dev *dev)
900 struct nicvf_txq *txq = NULL;
902 bool multiseg = false;
904 for (i = 0; i < dev->data->nb_tx_queues; i++) {
905 txq = dev->data->tx_queues[i];
906 if ((txq->txq_flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) {
912 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
914 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback");
915 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg;
917 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback");
918 dev->tx_pkt_burst = nicvf_xmit_pkts;
924 if (txq->pool_free == nicvf_single_pool_free_xmited_buffers)
925 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method");
927 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method");
931 nicvf_set_rx_function(struct rte_eth_dev *dev)
933 if (dev->data->scattered_rx) {
934 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback");
935 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg;
937 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback");
938 dev->rx_pkt_burst = nicvf_recv_pkts;
943 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
944 uint16_t nb_desc, unsigned int socket_id,
945 const struct rte_eth_txconf *tx_conf)
947 uint16_t tx_free_thresh;
948 uint8_t is_single_pool;
949 struct nicvf_txq *txq;
950 struct nicvf *nic = nicvf_pmd_priv(dev);
952 PMD_INIT_FUNC_TRACE();
954 if (qidx >= MAX_SND_QUEUES_PER_QS)
955 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1];
957 qidx = qidx % MAX_SND_QUEUES_PER_QS;
959 /* Socket id check */
960 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
961 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
962 socket_id, nic->node);
964 /* Tx deferred start is not supported */
965 if (tx_conf->tx_deferred_start) {
966 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
970 /* Roundup nb_desc to available qsize and validate max number of desc */
971 nb_desc = nicvf_qsize_sq_roundup(nb_desc);
973 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
977 /* Validate tx_free_thresh */
978 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
979 tx_conf->tx_free_thresh :
980 NICVF_DEFAULT_TX_FREE_THRESH);
982 if (tx_free_thresh > (nb_desc) ||
983 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
985 "tx_free_thresh must be less than the number of TX "
986 "descriptors. (tx_free_thresh=%u port=%d "
987 "queue=%d)", (unsigned int)tx_free_thresh,
988 (int)dev->data->port_id, (int)qidx);
992 /* Free memory prior to re-allocation if needed. */
993 if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
994 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
995 nicvf_netdev_qidx(nic, qidx));
996 nicvf_dev_tx_queue_release(
997 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]);
998 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
1001 /* Allocating tx queue data structure */
1002 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
1003 RTE_CACHE_LINE_SIZE, nic->node);
1005 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d",
1006 nicvf_netdev_qidx(nic, qidx));
1011 txq->queue_id = qidx;
1012 txq->tx_free_thresh = tx_free_thresh;
1013 txq->txq_flags = tx_conf->txq_flags;
1014 txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
1015 txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
1016 is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&
1017 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);
1019 /* Choose optimum free threshold value for multipool case */
1020 if (!is_single_pool) {
1021 txq->tx_free_thresh = (uint16_t)
1022 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
1023 NICVF_TX_FREE_MPOOL_THRESH :
1024 tx_conf->tx_free_thresh);
1025 txq->pool_free = nicvf_multi_pool_free_xmited_buffers;
1027 txq->pool_free = nicvf_single_pool_free_xmited_buffers;
1030 /* Allocate software ring */
1031 txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
1032 nb_desc * sizeof(struct rte_mbuf *),
1033 RTE_CACHE_LINE_SIZE, nic->node);
1035 if (txq->txbuffs == NULL) {
1036 nicvf_dev_tx_queue_release(txq);
1040 if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) {
1041 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
1042 nicvf_dev_tx_queue_release(txq);
1046 nicvf_tx_queue_reset(txq);
1048 PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64,
1049 nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc,
1052 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq;
1053 dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1054 RTE_ETH_QUEUE_STATE_STOPPED;
1059 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq)
1062 uint32_t nb_pkts, released_pkts = 0;
1063 uint32_t refill_cnt = 0;
1064 struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH];
1066 if (dev->rx_pkt_burst == NULL)
1069 while ((rxq_cnt = nicvf_dev_rx_queue_count(dev,
1070 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) {
1071 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts,
1072 NICVF_MAX_RX_FREE_THRESH);
1073 PMD_DRV_LOG(INFO, "nb_pkts=%d rxq_cnt=%d", nb_pkts, rxq_cnt);
1075 rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]);
1081 refill_cnt += nicvf_dev_rbdr_refill(dev,
1082 nicvf_netdev_qidx(rxq->nic, rxq->queue_id));
1084 PMD_DRV_LOG(INFO, "free_cnt=%d refill_cnt=%d",
1085 released_pkts, refill_cnt);
1089 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
1092 rxq->available_space = 0;
1093 rxq->recv_buffers = 0;
1097 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1100 struct nicvf_rxq *rxq;
1103 assert(qidx < MAX_RCV_QUEUES_PER_QS);
1105 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1106 RTE_ETH_QUEUE_STATE_STARTED)
1109 /* Update rbdr pointer to all rxq */
1110 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1111 rxq->shared_rbdr = nic->rbdr;
1113 ret = nicvf_qset_rq_config(nic, qidx, rxq);
1115 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d",
1116 nic->vf_id, qidx, ret);
1117 goto config_rq_error;
1119 ret = nicvf_qset_cq_config(nic, qidx, rxq);
1121 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d",
1122 nic->vf_id, qidx, ret);
1123 goto config_cq_error;
1126 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1127 RTE_ETH_QUEUE_STATE_STARTED;
1131 nicvf_qset_cq_reclaim(nic, qidx);
1133 nicvf_qset_rq_reclaim(nic, qidx);
1138 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1141 struct nicvf_rxq *rxq;
1142 int ret, other_error;
1144 if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1145 RTE_ETH_QUEUE_STATE_STOPPED)
1148 ret = nicvf_qset_rq_reclaim(nic, qidx);
1150 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d",
1151 nic->vf_id, qidx, ret);
1154 rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1155 nicvf_rx_queue_release_mbufs(dev, rxq);
1156 nicvf_rx_queue_reset(rxq);
1158 ret = nicvf_qset_cq_reclaim(nic, qidx);
1160 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d",
1161 nic->vf_id, qidx, ret);
1164 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1165 RTE_ETH_QUEUE_STATE_STOPPED;
1170 nicvf_dev_rx_queue_release(void *rx_queue)
1172 PMD_INIT_FUNC_TRACE();
1178 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1180 struct nicvf *nic = nicvf_pmd_priv(dev);
1183 if (qidx >= MAX_RCV_QUEUES_PER_QS)
1184 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)];
1186 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1188 ret = nicvf_vf_start_rx_queue(dev, nic, qidx);
1192 ret = nicvf_configure_cpi(dev);
1196 return nicvf_configure_rss_reta(dev);
1200 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1203 struct nicvf *nic = nicvf_pmd_priv(dev);
1205 if (qidx >= MAX_SND_QUEUES_PER_QS)
1206 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1208 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1210 ret = nicvf_vf_stop_rx_queue(dev, nic, qidx);
1211 ret |= nicvf_configure_cpi(dev);
1212 ret |= nicvf_configure_rss_reta(dev);
1217 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1219 struct nicvf *nic = nicvf_pmd_priv(dev);
1221 if (qidx >= MAX_SND_QUEUES_PER_QS)
1222 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1224 qidx = qidx % MAX_SND_QUEUES_PER_QS;
1226 return nicvf_vf_start_tx_queue(dev, nic, qidx);
1230 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1232 struct nicvf *nic = nicvf_pmd_priv(dev);
1234 if (qidx >= MAX_SND_QUEUES_PER_QS)
1235 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1237 qidx = qidx % MAX_SND_QUEUES_PER_QS;
1239 return nicvf_vf_stop_tx_queue(dev, nic, qidx);
1243 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq)
1246 struct rte_mbuf mb_def;
1248 RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8);
1249 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
1250 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
1251 offsetof(struct rte_mbuf, data_off) != 2);
1252 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
1253 offsetof(struct rte_mbuf, data_off) != 4);
1254 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
1255 offsetof(struct rte_mbuf, data_off) != 6);
1257 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
1258 mb_def.port = rxq->port_id;
1259 rte_mbuf_refcnt_set(&mb_def, 1);
1261 /* Prevent compiler reordering: rearm_data covers previous fields */
1262 rte_compiler_barrier();
1263 p = (uintptr_t)&mb_def.rearm_data;
1264 rxq->mbuf_initializer.value = *(uint64_t *)p;
1268 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
1269 uint16_t nb_desc, unsigned int socket_id,
1270 const struct rte_eth_rxconf *rx_conf,
1271 struct rte_mempool *mp)
1273 uint16_t rx_free_thresh;
1274 struct nicvf_rxq *rxq;
1275 struct nicvf *nic = nicvf_pmd_priv(dev);
1277 PMD_INIT_FUNC_TRACE();
1279 if (qidx >= MAX_RCV_QUEUES_PER_QS)
1280 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1];
1282 qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1284 /* Socket id check */
1285 if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
1286 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
1287 socket_id, nic->node);
1289 /* Mempool memory must be contiguous, so must be one memory segment*/
1290 if (mp->nb_mem_chunks != 1) {
1291 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages");
1295 /* Mempool memory must be physically contiguous */
1296 if (mp->flags & MEMPOOL_F_NO_PHYS_CONTIG) {
1297 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous");
1301 /* Rx deferred start is not supported */
1302 if (rx_conf->rx_deferred_start) {
1303 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
1307 /* Roundup nb_desc to available qsize and validate max number of desc */
1308 nb_desc = nicvf_qsize_cq_roundup(nb_desc);
1310 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
1314 /* Check rx_free_thresh upper bound */
1315 rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
1316 rx_conf->rx_free_thresh :
1317 NICVF_DEFAULT_RX_FREE_THRESH);
1318 if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
1319 rx_free_thresh >= nb_desc * .75) {
1320 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
1325 /* Free memory prior to re-allocation if needed */
1326 if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
1327 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1328 nicvf_netdev_qidx(nic, qidx));
1329 nicvf_dev_rx_queue_release(
1330 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]);
1331 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
1334 /* Allocate rxq memory */
1335 rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
1336 RTE_CACHE_LINE_SIZE, nic->node);
1338 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d",
1339 nicvf_netdev_qidx(nic, qidx));
1345 rxq->queue_id = qidx;
1346 rxq->port_id = dev->data->port_id;
1347 rxq->rx_free_thresh = rx_free_thresh;
1348 rxq->rx_drop_en = rx_conf->rx_drop_en;
1349 rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
1350 rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
1351 rxq->precharge_cnt = 0;
1353 if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2)
1354 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD;
1356 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
1358 nicvf_rxq_mbuf_setup(rxq);
1360 /* Alloc completion queue */
1361 if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) {
1362 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
1363 nicvf_dev_rx_queue_release(rxq);
1367 nicvf_rx_queue_reset(rxq);
1369 PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64,
1370 nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc,
1371 rte_mempool_avail_count(mp), rxq->phys);
1373 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq;
1374 dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1375 RTE_ETH_QUEUE_STATE_STOPPED;
1380 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1382 struct nicvf *nic = nicvf_pmd_priv(dev);
1383 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1385 PMD_INIT_FUNC_TRACE();
1387 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1389 /* Autonegotiation may be disabled */
1390 dev_info->speed_capa = ETH_LINK_SPEED_FIXED;
1391 dev_info->speed_capa |= ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M |
1392 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
1393 if (nicvf_hw_version(nic) != PCI_SUB_DEVICE_ID_CN81XX_NICVF)
1394 dev_info->speed_capa |= ETH_LINK_SPEED_40G;
1396 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1397 dev_info->max_rx_pktlen = NIC_HW_MAX_FRS;
1398 dev_info->max_rx_queues =
1399 (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1400 dev_info->max_tx_queues =
1401 (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1402 dev_info->max_mac_addrs = 1;
1403 dev_info->max_vfs = pci_dev->max_vfs;
1405 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1406 dev_info->tx_offload_capa =
1407 DEV_TX_OFFLOAD_IPV4_CKSUM |
1408 DEV_TX_OFFLOAD_UDP_CKSUM |
1409 DEV_TX_OFFLOAD_TCP_CKSUM |
1410 DEV_TX_OFFLOAD_TCP_TSO |
1411 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
1413 dev_info->reta_size = nic->rss_info.rss_size;
1414 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
1415 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
1416 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
1417 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
1419 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1420 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
1424 dev_info->default_txconf = (struct rte_eth_txconf) {
1425 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
1427 ETH_TXQ_FLAGS_NOMULTSEGS |
1428 ETH_TXQ_FLAGS_NOREFCOUNT |
1429 ETH_TXQ_FLAGS_NOMULTMEMP |
1430 ETH_TXQ_FLAGS_NOVLANOFFL |
1431 ETH_TXQ_FLAGS_NOXSUMSCTP,
1435 static nicvf_iova_addr_t
1436 rbdr_rte_mempool_get(void *dev, void *opaque)
1440 struct nicvf_rxq *rxq;
1441 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev;
1442 struct nicvf *nic = (struct nicvf *)opaque;
1443 uint16_t rx_start, rx_end;
1445 /* Get queue ranges for this VF */
1446 nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end);
1448 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1449 rxq = eth_dev->data->rx_queues[qidx];
1450 /* Maintain equal buffer count across all pools */
1451 if (rxq->precharge_cnt >= rxq->qlen_mask)
1453 rxq->precharge_cnt++;
1454 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool);
1456 return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off);
1462 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz)
1465 uint16_t qidx, data_off;
1466 uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs;
1467 uint64_t mbuf_phys_off = 0;
1468 struct nicvf_rxq *rxq;
1469 struct rte_mbuf *mbuf;
1470 uint16_t rx_start, rx_end;
1471 uint16_t tx_start, tx_end;
1473 PMD_INIT_FUNC_TRACE();
1475 /* Userspace process exited without proper shutdown in last run */
1476 if (nicvf_qset_rbdr_active(nic, 0))
1477 nicvf_vf_stop(dev, nic, false);
1479 /* Get queue ranges for this VF */
1480 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1483 * Thunderx nicvf PMD can support more than one pool per port only when
1484 * 1) Data payload size is same across all the pools in given port
1486 * 2) All mbuffs in the pools are from the same hugepage
1488 * 3) Mbuff metadata size is same across all the pools in given port
1490 * This is to support existing application that uses multiple pool/port.
1491 * But, the purpose of using multipool for QoS will not be addressed.
1495 /* Validate mempool attributes */
1496 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1497 rxq = dev->data->rx_queues[qidx];
1498 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool);
1499 mbuf = rte_pktmbuf_alloc(rxq->pool);
1501 PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d "
1503 nic->vf_id, qidx, rxq->pool->name);
1506 data_off = nicvf_mbuff_meta_length(mbuf);
1507 data_off += RTE_PKTMBUF_HEADROOM;
1508 rte_pktmbuf_free(mbuf);
1510 if (data_off % RTE_CACHE_LINE_SIZE) {
1511 PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d",
1512 rxq->pool->name, data_off,
1513 data_off % RTE_CACHE_LINE_SIZE);
1516 rxq->mbuf_phys_off -= data_off;
1518 if (mbuf_phys_off == 0)
1519 mbuf_phys_off = rxq->mbuf_phys_off;
1520 if (mbuf_phys_off != rxq->mbuf_phys_off) {
1521 PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %"
1522 PRIx64, rxq->pool->name, nic->vf_id,
1528 /* Check the level of buffers in the pool */
1530 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1531 rxq = dev->data->rx_queues[qidx];
1532 /* Count total numbers of rxq descs */
1533 total_rxq_desc += rxq->qlen_mask + 1;
1534 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh;
1535 exp_buffs *= dev->data->nb_rx_queues;
1536 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) {
1537 PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)",
1539 rte_mempool_avail_count(rxq->pool),
1545 /* Check RBDR desc overflow */
1546 ret = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1548 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc "
1549 "VF%d", nic->vf_id);
1554 ret = nicvf_qset_config(nic);
1556 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret,
1561 /* Allocate RBDR and RBDR ring desc */
1562 nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1563 ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz);
1565 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc "
1566 "VF%d", nic->vf_id);
1570 /* Enable and configure RBDR registers */
1571 ret = nicvf_qset_rbdr_config(nic, 0);
1573 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret,
1575 goto qset_rbdr_free;
1578 /* Fill rte_mempool buffers in RBDR pool and precharge it */
1579 ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get,
1582 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret,
1584 goto qset_rbdr_reclaim;
1587 PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d",
1588 nic->rbdr->tail, nb_rbdr_desc, nic->vf_id);
1590 /* Configure VLAN Strip */
1591 nicvf_vlan_hw_strip(nic, dev->data->dev_conf.rxmode.hw_vlan_strip);
1593 /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data
1594 * to the 64bit memory address.
1595 * The alignment creates a hole in mbuf(between the end of headroom and
1596 * packet data start). The new revision of the HW provides an option to
1597 * disable the L3 alignment feature and make mbuf layout looks
1598 * more like other NICs. For better application compatibility, disabling
1599 * l3 alignment feature on the hardware revisions it supports
1601 nicvf_apad_config(nic, false);
1603 /* Get queue ranges for this VF */
1604 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1606 /* Configure TX queues */
1607 for (qidx = tx_start; qidx <= tx_end; qidx++) {
1608 ret = nicvf_vf_start_tx_queue(dev, nic,
1609 qidx % MAX_SND_QUEUES_PER_QS);
1611 goto start_txq_error;
1614 /* Configure RX queues */
1615 for (qidx = rx_start; qidx <= rx_end; qidx++) {
1616 ret = nicvf_vf_start_rx_queue(dev, nic,
1617 qidx % MAX_RCV_QUEUES_PER_QS);
1619 goto start_rxq_error;
1622 if (!nic->sqs_mode) {
1623 /* Configure CPI algorithm */
1624 ret = nicvf_configure_cpi(dev);
1626 goto start_txq_error;
1628 ret = nicvf_mbox_get_rss_size(nic);
1630 PMD_INIT_LOG(ERR, "Failed to get rss table size");
1631 goto qset_rss_error;
1635 ret = nicvf_configure_rss(dev);
1637 goto qset_rss_error;
1640 /* Done; Let PF make the BGX's RX and TX switches to ON position */
1641 nicvf_mbox_cfg_done(nic);
1645 nicvf_rss_term(nic);
1647 for (qidx = rx_start; qidx <= rx_end; qidx++)
1648 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1650 for (qidx = tx_start; qidx <= tx_end; qidx++)
1651 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1653 nicvf_qset_rbdr_reclaim(nic, 0);
1654 nicvf_rbdr_release_mbufs(dev, nic);
1657 rte_free(nic->rbdr);
1661 nicvf_qset_reclaim(nic);
1666 nicvf_dev_start(struct rte_eth_dev *dev)
1671 struct nicvf *nic = nicvf_pmd_priv(dev);
1672 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
1674 uint32_t buffsz = 0, rbdrsz = 0;
1675 struct rte_pktmbuf_pool_private *mbp_priv;
1676 struct nicvf_rxq *rxq;
1678 PMD_INIT_FUNC_TRACE();
1680 /* This function must be called for a primary device */
1681 assert_primary(nic);
1683 /* Validate RBDR buff size */
1684 for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1685 rxq = dev->data->rx_queues[qidx];
1686 mbp_priv = rte_mempool_get_priv(rxq->pool);
1687 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1689 PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128");
1694 if (rbdrsz != buffsz) {
1695 PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)",
1696 qidx, rbdrsz, buffsz);
1701 /* Configure loopback */
1702 ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode);
1704 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret);
1708 /* Reset all statistics counters attached to this port */
1709 ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF);
1711 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret);
1715 /* Setup scatter mode if needed by jumbo */
1716 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
1717 2 * VLAN_TAG_SIZE > buffsz)
1718 dev->data->scattered_rx = 1;
1719 if (rx_conf->enable_scatter)
1720 dev->data->scattered_rx = 1;
1722 /* Setup MTU based on max_rx_pkt_len or default */
1723 mtu = dev->data->dev_conf.rxmode.jumbo_frame ?
1724 dev->data->dev_conf.rxmode.max_rx_pkt_len
1725 - ETHER_HDR_LEN - ETHER_CRC_LEN
1728 if (nicvf_dev_set_mtu(dev, mtu)) {
1729 PMD_INIT_LOG(ERR, "Failed to set default mtu size");
1733 ret = nicvf_vf_start(dev, nic, rbdrsz);
1737 for (i = 0; i < nic->sqs_count; i++) {
1738 assert(nic->snicvf[i]);
1740 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz);
1745 /* Configure callbacks based on scatter mode */
1746 nicvf_set_tx_function(dev);
1747 nicvf_set_rx_function(dev);
1753 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup)
1757 struct nicvf *nic = nicvf_pmd_priv(dev);
1759 PMD_INIT_FUNC_TRACE();
1761 /* Teardown secondary vf first */
1762 for (i = 0; i < nic->sqs_count; i++) {
1763 if (!nic->snicvf[i])
1766 nicvf_vf_stop(dev, nic->snicvf[i], cleanup);
1769 /* Stop the primary VF now */
1770 nicvf_vf_stop(dev, nic, cleanup);
1772 /* Disable loopback */
1773 ret = nicvf_loopback_config(nic, 0);
1775 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret);
1777 /* Reclaim CPI configuration */
1778 ret = nicvf_mbox_config_cpi(nic, 0);
1780 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret);
1784 nicvf_dev_stop(struct rte_eth_dev *dev)
1786 PMD_INIT_FUNC_TRACE();
1788 nicvf_dev_stop_cleanup(dev, false);
1792 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup)
1796 uint16_t tx_start, tx_end;
1797 uint16_t rx_start, rx_end;
1799 PMD_INIT_FUNC_TRACE();
1802 /* Let PF make the BGX's RX and TX switches to OFF position */
1803 nicvf_mbox_shutdown(nic);
1806 /* Disable VLAN Strip */
1807 nicvf_vlan_hw_strip(nic, 0);
1809 /* Get queue ranges for this VF */
1810 nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1812 for (qidx = tx_start; qidx <= tx_end; qidx++)
1813 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1815 /* Get queue ranges for this VF */
1816 nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1819 for (qidx = rx_start; qidx <= rx_end; qidx++)
1820 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1823 ret = nicvf_qset_rbdr_reclaim(nic, 0);
1825 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret);
1827 /* Move all charged buffers in RBDR back to pool */
1828 if (nic->rbdr != NULL)
1829 nicvf_rbdr_release_mbufs(dev, nic);
1832 ret = nicvf_qset_reclaim(nic);
1834 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret);
1836 /* Disable all interrupts */
1837 nicvf_disable_all_interrupts(nic);
1839 /* Free RBDR SW structure */
1841 rte_free(nic->rbdr);
1847 nicvf_dev_close(struct rte_eth_dev *dev)
1850 struct nicvf *nic = nicvf_pmd_priv(dev);
1852 PMD_INIT_FUNC_TRACE();
1854 nicvf_dev_stop_cleanup(dev, true);
1855 nicvf_periodic_alarm_stop(nicvf_interrupt, dev);
1857 for (i = 0; i < nic->sqs_count; i++) {
1858 if (!nic->snicvf[i])
1861 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]);
1866 nicvf_request_sqs(struct nicvf *nic)
1870 assert_primary(nic);
1871 assert(nic->sqs_count > 0);
1872 assert(nic->sqs_count <= MAX_SQS_PER_VF);
1874 /* Set no of Rx/Tx queues in each of the SQsets */
1875 for (i = 0; i < nic->sqs_count; i++) {
1876 if (nicvf_svf_empty())
1877 rte_panic("Cannot assign sufficient number of "
1878 "secondary queues to primary VF%" PRIu8 "\n",
1881 nic->snicvf[i] = nicvf_svf_pop();
1882 nic->snicvf[i]->sqs_id = i;
1885 return nicvf_mbox_request_sqs(nic);
1889 nicvf_dev_configure(struct rte_eth_dev *dev)
1891 struct rte_eth_dev_data *data = dev->data;
1892 struct rte_eth_conf *conf = &data->dev_conf;
1893 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1894 struct rte_eth_txmode *txmode = &conf->txmode;
1895 struct nicvf *nic = nicvf_pmd_priv(dev);
1898 PMD_INIT_FUNC_TRACE();
1900 if (!rte_eal_has_hugepages()) {
1901 PMD_INIT_LOG(INFO, "Huge page is not configured");
1905 if (txmode->mq_mode) {
1906 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
1910 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1911 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1912 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
1916 if (!rxmode->hw_strip_crc) {
1917 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
1918 rxmode->hw_strip_crc = 1;
1921 if (rxmode->hw_ip_checksum) {
1922 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
1923 rxmode->hw_ip_checksum = 0;
1926 if (rxmode->split_hdr_size) {
1927 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
1931 if (rxmode->hw_vlan_filter) {
1932 PMD_INIT_LOG(INFO, "VLAN filter not supported");
1936 if (rxmode->hw_vlan_extend) {
1937 PMD_INIT_LOG(INFO, "VLAN extended not supported");
1941 if (rxmode->enable_lro) {
1942 PMD_INIT_LOG(INFO, "LRO not supported");
1946 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1947 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
1951 if (conf->dcb_capability_en) {
1952 PMD_INIT_LOG(INFO, "DCB enable not supported");
1956 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1957 PMD_INIT_LOG(INFO, "Flow director not supported");
1961 assert_primary(nic);
1962 NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS);
1963 cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues);
1964 if (cqcount > MAX_RCV_QUEUES_PER_QS) {
1965 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS);
1966 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1;
1971 assert(nic->sqs_count <= MAX_SQS_PER_VF);
1973 if (nic->sqs_count > 0) {
1974 if (nicvf_request_sqs(nic)) {
1975 rte_panic("Cannot assign sufficient number of "
1976 "secondary queues to PORT%d VF%" PRIu8 "\n",
1977 dev->data->port_id, nic->vf_id);
1981 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
1982 dev->data->port_id, nicvf_hw_cap(nic));
1987 /* Initialize and register driver with DPDK Application */
1988 static const struct eth_dev_ops nicvf_eth_dev_ops = {
1989 .dev_configure = nicvf_dev_configure,
1990 .dev_start = nicvf_dev_start,
1991 .dev_stop = nicvf_dev_stop,
1992 .link_update = nicvf_dev_link_update,
1993 .dev_close = nicvf_dev_close,
1994 .stats_get = nicvf_dev_stats_get,
1995 .stats_reset = nicvf_dev_stats_reset,
1996 .promiscuous_enable = nicvf_dev_promisc_enable,
1997 .dev_infos_get = nicvf_dev_info_get,
1998 .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get,
1999 .mtu_set = nicvf_dev_set_mtu,
2000 .reta_update = nicvf_dev_reta_update,
2001 .reta_query = nicvf_dev_reta_query,
2002 .rss_hash_update = nicvf_dev_rss_hash_update,
2003 .rss_hash_conf_get = nicvf_dev_rss_hash_conf_get,
2004 .rx_queue_start = nicvf_dev_rx_queue_start,
2005 .rx_queue_stop = nicvf_dev_rx_queue_stop,
2006 .tx_queue_start = nicvf_dev_tx_queue_start,
2007 .tx_queue_stop = nicvf_dev_tx_queue_stop,
2008 .rx_queue_setup = nicvf_dev_rx_queue_setup,
2009 .rx_queue_release = nicvf_dev_rx_queue_release,
2010 .rx_queue_count = nicvf_dev_rx_queue_count,
2011 .tx_queue_setup = nicvf_dev_tx_queue_setup,
2012 .tx_queue_release = nicvf_dev_tx_queue_release,
2013 .get_reg = nicvf_dev_get_regs,
2017 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
2020 struct rte_pci_device *pci_dev;
2021 struct nicvf *nic = nicvf_pmd_priv(eth_dev);
2023 PMD_INIT_FUNC_TRACE();
2025 eth_dev->dev_ops = &nicvf_eth_dev_ops;
2027 /* For secondary processes, the primary has done all the work */
2028 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2030 /* Setup callbacks for secondary process */
2031 nicvf_set_tx_function(eth_dev);
2032 nicvf_set_rx_function(eth_dev);
2035 /* If nic == NULL than it is secondary function
2036 * so ethdev need to be released by caller */
2041 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2042 rte_eth_copy_pci_info(eth_dev, pci_dev);
2044 nic->device_id = pci_dev->id.device_id;
2045 nic->vendor_id = pci_dev->id.vendor_id;
2046 nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
2047 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2049 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
2050 pci_dev->id.vendor_id, pci_dev->id.device_id,
2051 pci_dev->addr.domain, pci_dev->addr.bus,
2052 pci_dev->addr.devid, pci_dev->addr.function);
2054 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
2055 if (!nic->reg_base) {
2056 PMD_INIT_LOG(ERR, "Failed to map BAR0");
2061 nicvf_disable_all_interrupts(nic);
2063 ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev);
2065 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2069 ret = nicvf_mbox_check_pf_ready(nic);
2071 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
2075 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
2076 nic->node, nic->vf_id,
2077 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
2078 nic->sqs_mode ? "true" : "false",
2079 nic->loopback_supported ? "true" : "false"
2083 ret = nicvf_base_init(nic);
2085 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
2089 if (nic->sqs_mode) {
2090 /* Push nic to stack of secondary vfs */
2091 nicvf_svf_push(nic);
2093 /* Steal nic pointer from the device for further reuse */
2094 eth_dev->data->dev_private = NULL;
2096 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2097 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic);
2099 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2103 /* Detach port by returning positive error number */
2107 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2108 if (eth_dev->data->mac_addrs == NULL) {
2109 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
2113 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
2114 eth_random_addr(&nic->mac_addr[0]);
2116 ether_addr_copy((struct ether_addr *)nic->mac_addr,
2117 ð_dev->data->mac_addrs[0]);
2119 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
2121 PMD_INIT_LOG(ERR, "Failed to set mac addr");
2125 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
2126 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
2127 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
2128 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
2133 rte_free(eth_dev->data->mac_addrs);
2135 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2140 static const struct rte_pci_id pci_id_nicvf_map[] = {
2142 .class_id = RTE_CLASS_ANY_ID,
2143 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2144 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF,
2145 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2146 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF,
2149 .class_id = RTE_CLASS_ANY_ID,
2150 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2151 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2152 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2153 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF,
2156 .class_id = RTE_CLASS_ANY_ID,
2157 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2158 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2159 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2160 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF,
2163 .class_id = RTE_CLASS_ANY_ID,
2164 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2165 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2166 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2167 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF,
2174 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2175 struct rte_pci_device *pci_dev)
2177 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf),
2178 nicvf_eth_dev_init);
2181 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev)
2183 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
2186 static struct rte_pci_driver rte_nicvf_pmd = {
2187 .id_table = pci_id_nicvf_map,
2188 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES |
2189 RTE_PCI_DRV_INTR_LSC,
2190 .probe = nicvf_eth_pci_probe,
2191 .remove = nicvf_eth_pci_remove,
2194 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd);
2195 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map);
2196 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci");