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35 #ifdef RTE_EXEC_ENV_LINUXAPP
40 #include "virtio_pci.h"
41 #include "virtio_logs.h"
42 #include "virtqueue.h"
45 * Following macros are derived from linux/pci_regs.h, however,
46 * we can't simply include that header here, as there is no such
47 * file for non-Linux platform.
49 #define PCI_CAPABILITY_LIST 0x34
50 #define PCI_CAP_ID_VNDR 0x09
51 #define PCI_CAP_ID_MSIX 0x11
54 * The remaining space is defined by each driver as the per-driver
55 * configuration space.
57 #define VIRTIO_PCI_CONFIG(hw) (((hw)->use_msix) ? 24 : 20)
60 check_vq_phys_addr_ok(struct virtqueue *vq)
62 /* Virtio PCI device VIRTIO_PCI_QUEUE_PF register is 32bit,
63 * and only accepts 32 bit page frame number.
64 * Check if the allocated physical memory exceeds 16TB.
66 if ((vq->vq_ring_mem + vq->vq_ring_size - 1) >>
67 (VIRTIO_PCI_QUEUE_ADDR_SHIFT + 32)) {
68 PMD_INIT_LOG(ERR, "vring address shouldn't be above 16TB!");
76 * Since we are in legacy mode:
77 * http://ozlabs.org/~rusty/virtio-spec/virtio-0.9.5.pdf
79 * "Note that this is possible because while the virtio header is PCI (i.e.
80 * little) endian, the device-specific region is encoded in the native endian of
81 * the guest (where such distinction is applicable)."
83 * For powerpc which supports both, qemu supposes that cpu is big endian and
84 * enforces this for the virtio-net stuff.
87 legacy_read_dev_config(struct virtio_hw *hw, size_t offset,
88 void *dst, int length)
90 #ifdef RTE_ARCH_PPC_64
96 rte_eal_pci_ioport_read(VTPCI_IO(hw), dst, size,
97 VIRTIO_PCI_CONFIG(hw) + offset);
98 *(uint32_t *)dst = rte_be_to_cpu_32(*(uint32_t *)dst);
99 } else if (length >= 2) {
101 rte_eal_pci_ioport_read(VTPCI_IO(hw), dst, size,
102 VIRTIO_PCI_CONFIG(hw) + offset);
103 *(uint16_t *)dst = rte_be_to_cpu_16(*(uint16_t *)dst);
106 rte_eal_pci_ioport_read(VTPCI_IO(hw), dst, size,
107 VIRTIO_PCI_CONFIG(hw) + offset);
110 dst = (char *)dst + size;
115 rte_eal_pci_ioport_read(VTPCI_IO(hw), dst, length,
116 VIRTIO_PCI_CONFIG(hw) + offset);
121 legacy_write_dev_config(struct virtio_hw *hw, size_t offset,
122 const void *src, int length)
124 #ifdef RTE_ARCH_PPC_64
134 tmp.u32 = rte_cpu_to_be_32(*(const uint32_t *)src);
135 rte_eal_pci_ioport_write(VTPCI_IO(hw), &tmp.u32, size,
136 VIRTIO_PCI_CONFIG(hw) + offset);
137 } else if (length >= 2) {
139 tmp.u16 = rte_cpu_to_be_16(*(const uint16_t *)src);
140 rte_eal_pci_ioport_write(VTPCI_IO(hw), &tmp.u16, size,
141 VIRTIO_PCI_CONFIG(hw) + offset);
144 rte_eal_pci_ioport_write(VTPCI_IO(hw), src, size,
145 VIRTIO_PCI_CONFIG(hw) + offset);
148 src = (const char *)src + size;
153 rte_eal_pci_ioport_write(VTPCI_IO(hw), src, length,
154 VIRTIO_PCI_CONFIG(hw) + offset);
159 legacy_get_features(struct virtio_hw *hw)
163 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 4,
164 VIRTIO_PCI_HOST_FEATURES);
169 legacy_set_features(struct virtio_hw *hw, uint64_t features)
171 if ((features >> 32) != 0) {
173 "only 32 bit features are allowed for legacy virtio!");
176 rte_eal_pci_ioport_write(VTPCI_IO(hw), &features, 4,
177 VIRTIO_PCI_GUEST_FEATURES);
181 legacy_get_status(struct virtio_hw *hw)
185 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 1, VIRTIO_PCI_STATUS);
190 legacy_set_status(struct virtio_hw *hw, uint8_t status)
192 rte_eal_pci_ioport_write(VTPCI_IO(hw), &status, 1, VIRTIO_PCI_STATUS);
196 legacy_reset(struct virtio_hw *hw)
198 legacy_set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
202 legacy_get_isr(struct virtio_hw *hw)
206 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 1, VIRTIO_PCI_ISR);
210 /* Enable one vector (0) for Link State Intrerrupt */
212 legacy_set_config_irq(struct virtio_hw *hw, uint16_t vec)
216 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vec, 2,
217 VIRTIO_MSI_CONFIG_VECTOR);
218 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 2,
219 VIRTIO_MSI_CONFIG_VECTOR);
224 legacy_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)
228 rte_eal_pci_ioport_write(VTPCI_IO(hw), &queue_id, 2,
229 VIRTIO_PCI_QUEUE_SEL);
230 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 2, VIRTIO_PCI_QUEUE_NUM);
235 legacy_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)
239 if (!check_vq_phys_addr_ok(vq))
242 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
243 VIRTIO_PCI_QUEUE_SEL);
244 src = vq->vq_ring_mem >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
245 rte_eal_pci_ioport_write(VTPCI_IO(hw), &src, 4, VIRTIO_PCI_QUEUE_PFN);
251 legacy_del_queue(struct virtio_hw *hw, struct virtqueue *vq)
255 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
256 VIRTIO_PCI_QUEUE_SEL);
257 rte_eal_pci_ioport_write(VTPCI_IO(hw), &src, 4, VIRTIO_PCI_QUEUE_PFN);
261 legacy_notify_queue(struct virtio_hw *hw, struct virtqueue *vq)
263 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
264 VIRTIO_PCI_QUEUE_NOTIFY);
267 #ifdef RTE_EXEC_ENV_LINUXAPP
269 legacy_virtio_has_msix(const struct rte_pci_addr *loc)
272 char dirname[PATH_MAX];
274 snprintf(dirname, sizeof(dirname),
275 "%s/" PCI_PRI_FMT "/msi_irqs", pci_get_sysfs_path(),
276 loc->domain, loc->bus, loc->devid, loc->function);
278 d = opendir(dirname);
286 legacy_virtio_has_msix(const struct rte_pci_addr *loc __rte_unused)
288 /* nic_uio does not enable interrupts, return 0 (false). */
294 legacy_virtio_resource_init(struct rte_pci_device *pci_dev,
295 struct virtio_hw *hw, uint32_t *dev_flags)
297 if (rte_eal_pci_ioport_map(pci_dev, 0, VTPCI_IO(hw)) < 0)
300 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UNKNOWN)
301 *dev_flags |= RTE_ETH_DEV_INTR_LSC;
303 *dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
308 const struct virtio_pci_ops legacy_ops = {
309 .read_dev_cfg = legacy_read_dev_config,
310 .write_dev_cfg = legacy_write_dev_config,
311 .reset = legacy_reset,
312 .get_status = legacy_get_status,
313 .set_status = legacy_set_status,
314 .get_features = legacy_get_features,
315 .set_features = legacy_set_features,
316 .get_isr = legacy_get_isr,
317 .set_config_irq = legacy_set_config_irq,
318 .get_queue_num = legacy_get_queue_num,
319 .setup_queue = legacy_setup_queue,
320 .del_queue = legacy_del_queue,
321 .notify_queue = legacy_notify_queue,
325 static inline uint8_t
326 io_read8(uint8_t *addr)
328 return *(volatile uint8_t *)addr;
332 io_write8(uint8_t val, uint8_t *addr)
334 *(volatile uint8_t *)addr = val;
337 static inline uint16_t
338 io_read16(uint16_t *addr)
340 return *(volatile uint16_t *)addr;
344 io_write16(uint16_t val, uint16_t *addr)
346 *(volatile uint16_t *)addr = val;
349 static inline uint32_t
350 io_read32(uint32_t *addr)
352 return *(volatile uint32_t *)addr;
356 io_write32(uint32_t val, uint32_t *addr)
358 *(volatile uint32_t *)addr = val;
362 io_write64_twopart(uint64_t val, uint32_t *lo, uint32_t *hi)
364 io_write32(val & ((1ULL << 32) - 1), lo);
365 io_write32(val >> 32, hi);
369 modern_read_dev_config(struct virtio_hw *hw, size_t offset,
370 void *dst, int length)
374 uint8_t old_gen, new_gen;
377 old_gen = io_read8(&hw->common_cfg->config_generation);
380 for (i = 0; i < length; i++)
381 *p++ = io_read8((uint8_t *)hw->dev_cfg + offset + i);
383 new_gen = io_read8(&hw->common_cfg->config_generation);
384 } while (old_gen != new_gen);
388 modern_write_dev_config(struct virtio_hw *hw, size_t offset,
389 const void *src, int length)
392 const uint8_t *p = src;
394 for (i = 0; i < length; i++)
395 io_write8(*p++, (uint8_t *)hw->dev_cfg + offset + i);
399 modern_get_features(struct virtio_hw *hw)
401 uint32_t features_lo, features_hi;
403 io_write32(0, &hw->common_cfg->device_feature_select);
404 features_lo = io_read32(&hw->common_cfg->device_feature);
406 io_write32(1, &hw->common_cfg->device_feature_select);
407 features_hi = io_read32(&hw->common_cfg->device_feature);
409 return ((uint64_t)features_hi << 32) | features_lo;
413 modern_set_features(struct virtio_hw *hw, uint64_t features)
415 io_write32(0, &hw->common_cfg->guest_feature_select);
416 io_write32(features & ((1ULL << 32) - 1),
417 &hw->common_cfg->guest_feature);
419 io_write32(1, &hw->common_cfg->guest_feature_select);
420 io_write32(features >> 32,
421 &hw->common_cfg->guest_feature);
425 modern_get_status(struct virtio_hw *hw)
427 return io_read8(&hw->common_cfg->device_status);
431 modern_set_status(struct virtio_hw *hw, uint8_t status)
433 io_write8(status, &hw->common_cfg->device_status);
437 modern_reset(struct virtio_hw *hw)
439 modern_set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
440 modern_get_status(hw);
444 modern_get_isr(struct virtio_hw *hw)
446 return io_read8(hw->isr);
450 modern_set_config_irq(struct virtio_hw *hw, uint16_t vec)
452 io_write16(vec, &hw->common_cfg->msix_config);
453 return io_read16(&hw->common_cfg->msix_config);
457 modern_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)
459 io_write16(queue_id, &hw->common_cfg->queue_select);
460 return io_read16(&hw->common_cfg->queue_size);
464 modern_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)
466 uint64_t desc_addr, avail_addr, used_addr;
469 if (!check_vq_phys_addr_ok(vq))
472 desc_addr = vq->vq_ring_mem;
473 avail_addr = desc_addr + vq->vq_nentries * sizeof(struct vring_desc);
474 used_addr = RTE_ALIGN_CEIL(avail_addr + offsetof(struct vring_avail,
475 ring[vq->vq_nentries]),
476 VIRTIO_PCI_VRING_ALIGN);
478 io_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
480 io_write64_twopart(desc_addr, &hw->common_cfg->queue_desc_lo,
481 &hw->common_cfg->queue_desc_hi);
482 io_write64_twopart(avail_addr, &hw->common_cfg->queue_avail_lo,
483 &hw->common_cfg->queue_avail_hi);
484 io_write64_twopart(used_addr, &hw->common_cfg->queue_used_lo,
485 &hw->common_cfg->queue_used_hi);
487 notify_off = io_read16(&hw->common_cfg->queue_notify_off);
488 vq->notify_addr = (void *)((uint8_t *)hw->notify_base +
489 notify_off * hw->notify_off_multiplier);
491 io_write16(1, &hw->common_cfg->queue_enable);
493 PMD_INIT_LOG(DEBUG, "queue %u addresses:", vq->vq_queue_index);
494 PMD_INIT_LOG(DEBUG, "\t desc_addr: %" PRIx64, desc_addr);
495 PMD_INIT_LOG(DEBUG, "\t aval_addr: %" PRIx64, avail_addr);
496 PMD_INIT_LOG(DEBUG, "\t used_addr: %" PRIx64, used_addr);
497 PMD_INIT_LOG(DEBUG, "\t notify addr: %p (notify offset: %u)",
498 vq->notify_addr, notify_off);
504 modern_del_queue(struct virtio_hw *hw, struct virtqueue *vq)
506 io_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
508 io_write64_twopart(0, &hw->common_cfg->queue_desc_lo,
509 &hw->common_cfg->queue_desc_hi);
510 io_write64_twopart(0, &hw->common_cfg->queue_avail_lo,
511 &hw->common_cfg->queue_avail_hi);
512 io_write64_twopart(0, &hw->common_cfg->queue_used_lo,
513 &hw->common_cfg->queue_used_hi);
515 io_write16(0, &hw->common_cfg->queue_enable);
519 modern_notify_queue(struct virtio_hw *hw __rte_unused, struct virtqueue *vq)
521 io_write16(vq->vq_queue_index, vq->notify_addr);
524 const struct virtio_pci_ops modern_ops = {
525 .read_dev_cfg = modern_read_dev_config,
526 .write_dev_cfg = modern_write_dev_config,
527 .reset = modern_reset,
528 .get_status = modern_get_status,
529 .set_status = modern_set_status,
530 .get_features = modern_get_features,
531 .set_features = modern_set_features,
532 .get_isr = modern_get_isr,
533 .set_config_irq = modern_set_config_irq,
534 .get_queue_num = modern_get_queue_num,
535 .setup_queue = modern_setup_queue,
536 .del_queue = modern_del_queue,
537 .notify_queue = modern_notify_queue,
542 vtpci_read_dev_config(struct virtio_hw *hw, size_t offset,
543 void *dst, int length)
545 VTPCI_OPS(hw)->read_dev_cfg(hw, offset, dst, length);
549 vtpci_write_dev_config(struct virtio_hw *hw, size_t offset,
550 const void *src, int length)
552 VTPCI_OPS(hw)->write_dev_cfg(hw, offset, src, length);
556 vtpci_negotiate_features(struct virtio_hw *hw, uint64_t host_features)
561 * Limit negotiated features to what the driver, virtqueue, and
564 features = host_features & hw->guest_features;
565 VTPCI_OPS(hw)->set_features(hw, features);
571 vtpci_reset(struct virtio_hw *hw)
573 VTPCI_OPS(hw)->set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
574 /* flush status write */
575 VTPCI_OPS(hw)->get_status(hw);
579 vtpci_reinit_complete(struct virtio_hw *hw)
581 vtpci_set_status(hw, VIRTIO_CONFIG_STATUS_DRIVER_OK);
585 vtpci_set_status(struct virtio_hw *hw, uint8_t status)
587 if (status != VIRTIO_CONFIG_STATUS_RESET)
588 status |= VTPCI_OPS(hw)->get_status(hw);
590 VTPCI_OPS(hw)->set_status(hw, status);
594 vtpci_get_status(struct virtio_hw *hw)
596 return VTPCI_OPS(hw)->get_status(hw);
600 vtpci_isr(struct virtio_hw *hw)
602 return VTPCI_OPS(hw)->get_isr(hw);
606 /* Enable one vector (0) for Link State Intrerrupt */
608 vtpci_irq_config(struct virtio_hw *hw, uint16_t vec)
610 return VTPCI_OPS(hw)->set_config_irq(hw, vec);
614 get_cfg_addr(struct rte_pci_device *dev, struct virtio_pci_cap *cap)
616 uint8_t bar = cap->bar;
617 uint32_t length = cap->length;
618 uint32_t offset = cap->offset;
622 PMD_INIT_LOG(ERR, "invalid bar: %u", bar);
626 if (offset + length < offset) {
627 PMD_INIT_LOG(ERR, "offset(%u) + length(%u) overflows",
632 if (offset + length > dev->mem_resource[bar].len) {
634 "invalid cap: overflows bar space: %u > %" PRIu64,
635 offset + length, dev->mem_resource[bar].len);
639 base = dev->mem_resource[bar].addr;
641 PMD_INIT_LOG(ERR, "bar %u base addr is NULL", bar);
645 return base + offset;
649 virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw)
652 struct virtio_pci_cap cap;
655 if (rte_eal_pci_map_device(dev)) {
656 PMD_INIT_LOG(DEBUG, "failed to map pci device!");
660 ret = rte_eal_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);
662 PMD_INIT_LOG(DEBUG, "failed to read pci capability list");
667 ret = rte_eal_pci_read_config(dev, &cap, sizeof(cap), pos);
670 "failed to read pci cap at pos: %x", pos);
674 if (cap.cap_vndr == PCI_CAP_ID_MSIX)
677 if (cap.cap_vndr != PCI_CAP_ID_VNDR) {
679 "[%2x] skipping non VNDR cap id: %02x",
685 "[%2x] cfg type: %u, bar: %u, offset: %04x, len: %u",
686 pos, cap.cfg_type, cap.bar, cap.offset, cap.length);
688 switch (cap.cfg_type) {
689 case VIRTIO_PCI_CAP_COMMON_CFG:
690 hw->common_cfg = get_cfg_addr(dev, &cap);
692 case VIRTIO_PCI_CAP_NOTIFY_CFG:
693 rte_eal_pci_read_config(dev, &hw->notify_off_multiplier,
694 4, pos + sizeof(cap));
695 hw->notify_base = get_cfg_addr(dev, &cap);
697 case VIRTIO_PCI_CAP_DEVICE_CFG:
698 hw->dev_cfg = get_cfg_addr(dev, &cap);
700 case VIRTIO_PCI_CAP_ISR_CFG:
701 hw->isr = get_cfg_addr(dev, &cap);
709 if (hw->common_cfg == NULL || hw->notify_base == NULL ||
710 hw->dev_cfg == NULL || hw->isr == NULL) {
711 PMD_INIT_LOG(INFO, "no modern virtio pci device found.");
715 PMD_INIT_LOG(INFO, "found modern virtio pci device.");
717 PMD_INIT_LOG(DEBUG, "common cfg mapped at: %p", hw->common_cfg);
718 PMD_INIT_LOG(DEBUG, "device cfg mapped at: %p", hw->dev_cfg);
719 PMD_INIT_LOG(DEBUG, "isr cfg mapped at: %p", hw->isr);
720 PMD_INIT_LOG(DEBUG, "notify base: %p, notify off multiplier: %u",
721 hw->notify_base, hw->notify_off_multiplier);
728 * if there is error mapping with VFIO/UIO.
729 * if port map error when driver type is KDRV_NONE.
730 * if whitelisted but driver type is KDRV_UNKNOWN.
731 * Return 1 if kernel driver is managing the device.
732 * Return 0 on success.
735 vtpci_init(struct rte_pci_device *dev, struct virtio_hw *hw,
741 * Try if we can succeed reading virtio pci caps, which exists
742 * only on modern pci device. If failed, we fallback to legacy
745 if (virtio_read_caps(dev, hw) == 0) {
746 PMD_INIT_LOG(INFO, "modern virtio pci detected.");
747 virtio_hw_internal[hw->port_id].vtpci_ops = &modern_ops;
749 *dev_flags |= RTE_ETH_DEV_INTR_LSC;
753 PMD_INIT_LOG(INFO, "trying with legacy virtio pci.");
754 if (legacy_virtio_resource_init(dev, hw, dev_flags) < 0) {
755 if (dev->kdrv == RTE_KDRV_UNKNOWN &&
756 (!dev->device.devargs ||
757 dev->device.devargs->type !=
758 RTE_DEVTYPE_WHITELISTED_PCI)) {
760 "skip kernel managed virtio device.");
766 virtio_hw_internal[hw->port_id].vtpci_ops = &legacy_ops;
767 hw->use_msix = legacy_virtio_has_msix(&dev->addr);