1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/device.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 #include <linux/uio_driver.h>
13 #include <linux/irq.h>
14 #include <linux/msi.h>
15 #include <linux/version.h>
16 #include <linux/slab.h>
18 #include <rte_pci_dev_features.h>
23 * A structure describing the private information for a uio device.
25 struct rte_uio_pci_dev {
28 enum rte_intr_mode mode;
33 static int wc_activate;
34 static char *intr_mode;
35 static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
38 show_max_vfs(struct device *dev, struct device_attribute *attr,
41 return snprintf(buf, 10, "%u\n", dev_num_vf(dev));
45 store_max_vfs(struct device *dev, struct device_attribute *attr,
46 const char *buf, size_t count)
49 unsigned long max_vfs;
50 struct pci_dev *pdev = to_pci_dev(dev);
52 if (0 != kstrtoul(buf, 0, &max_vfs))
56 pci_disable_sriov(pdev);
57 else if (0 == pci_num_vf(pdev))
58 err = pci_enable_sriov(pdev, max_vfs);
59 else /* do nothing if change max_vfs number */
62 return err ? err : count;
65 static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
67 static struct attribute *dev_attrs[] = {
68 &dev_attr_max_vfs.attr,
72 static const struct attribute_group dev_attr_grp = {
76 #ifndef HAVE_PCI_MSI_MASK_IRQ
78 * It masks the msix on/off of generating MSI-X messages.
81 igbuio_msix_mask_irq(struct msi_desc *desc, s32 state)
83 u32 mask_bits = desc->masked;
84 unsigned int offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
85 PCI_MSIX_ENTRY_VECTOR_CTRL;
88 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
90 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
92 if (mask_bits != desc->masked) {
93 writel(mask_bits, desc->mask_base + offset);
94 readl(desc->mask_base);
95 desc->masked = mask_bits;
100 * It masks the msi on/off of generating MSI messages.
103 igbuio_msi_mask_irq(struct pci_dev *pdev, struct msi_desc *desc, int32_t state)
105 u32 mask_bits = desc->masked;
106 u32 offset = desc->irq - pdev->irq;
107 u32 mask = 1 << offset;
109 if (!desc->msi_attrib.maskbit)
117 if (mask_bits != desc->masked) {
118 pci_write_config_dword(pdev, desc->mask_pos, mask_bits);
119 desc->masked = mask_bits;
124 igbuio_mask_irq(struct pci_dev *pdev, enum rte_intr_mode mode, s32 irq_state)
126 struct msi_desc *desc;
127 struct list_head *msi_list;
129 #ifdef HAVE_MSI_LIST_IN_GENERIC_DEVICE
130 msi_list = &pdev->dev.msi_list;
132 msi_list = &pdev->msi_list;
135 if (mode == RTE_INTR_MODE_MSIX) {
136 list_for_each_entry(desc, msi_list, list)
137 igbuio_msix_mask_irq(desc, irq_state);
138 } else if (mode == RTE_INTR_MODE_MSI) {
139 list_for_each_entry(desc, msi_list, list)
140 igbuio_msi_mask_irq(pdev, desc, irq_state);
146 * This is the irqcontrol callback to be registered to uio_info.
147 * It can be used to disable/enable interrupt from user space processes.
150 * pointer to uio_info.
152 * state value. 1 to enable interrupt, 0 to disable interrupt.
156 * - On failure, a negative value.
159 igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
161 struct rte_uio_pci_dev *udev = info->priv;
162 struct pci_dev *pdev = udev->pdev;
164 #ifdef HAVE_PCI_MSI_MASK_IRQ
165 struct irq_data *irq = irq_get_irq_data(udev->info.irq);
168 pci_cfg_access_lock(pdev);
170 if (udev->mode == RTE_INTR_MODE_MSIX || udev->mode == RTE_INTR_MODE_MSI) {
171 #ifdef HAVE_PCI_MSI_MASK_IRQ
173 pci_msi_unmask_irq(irq);
175 pci_msi_mask_irq(irq);
177 igbuio_mask_irq(pdev, udev->mode, irq_state);
181 if (udev->mode == RTE_INTR_MODE_LEGACY)
182 pci_intx(pdev, !!irq_state);
184 pci_cfg_access_unlock(pdev);
190 * This is interrupt handler which will check if the interrupt is for the right device.
191 * If yes, disable it here and will be enable later.
194 igbuio_pci_irqhandler(int irq, void *dev_id)
196 struct rte_uio_pci_dev *udev = (struct rte_uio_pci_dev *)dev_id;
197 struct uio_info *info = &udev->info;
199 /* Legacy mode need to mask in hardware */
200 if (udev->mode == RTE_INTR_MODE_LEGACY &&
201 !pci_check_and_mask_intx(udev->pdev))
204 uio_event_notify(info);
206 /* Message signal mode, no share IRQ and automasked */
211 igbuio_pci_enable_interrupts(struct rte_uio_pci_dev *udev)
214 #ifndef HAVE_ALLOC_IRQ_VECTORS
215 struct msix_entry msix_entry;
218 switch (igbuio_intr_mode_preferred) {
219 case RTE_INTR_MODE_MSIX:
220 /* Only 1 msi-x vector needed */
221 #ifndef HAVE_ALLOC_IRQ_VECTORS
222 msix_entry.entry = 0;
223 if (pci_enable_msix(udev->pdev, &msix_entry, 1) == 0) {
224 dev_dbg(&udev->pdev->dev, "using MSI-X");
225 udev->info.irq_flags = IRQF_NO_THREAD;
226 udev->info.irq = msix_entry.vector;
227 udev->mode = RTE_INTR_MODE_MSIX;
231 if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSIX) == 1) {
232 dev_dbg(&udev->pdev->dev, "using MSI-X");
233 udev->info.irq_flags = IRQF_NO_THREAD;
234 udev->info.irq = pci_irq_vector(udev->pdev, 0);
235 udev->mode = RTE_INTR_MODE_MSIX;
240 /* fall back to MSI */
241 case RTE_INTR_MODE_MSI:
242 #ifndef HAVE_ALLOC_IRQ_VECTORS
243 if (pci_enable_msi(udev->pdev) == 0) {
244 dev_dbg(&udev->pdev->dev, "using MSI");
245 udev->info.irq_flags = IRQF_NO_THREAD;
246 udev->info.irq = udev->pdev->irq;
247 udev->mode = RTE_INTR_MODE_MSI;
251 if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSI) == 1) {
252 dev_dbg(&udev->pdev->dev, "using MSI");
253 udev->info.irq_flags = IRQF_NO_THREAD;
254 udev->info.irq = pci_irq_vector(udev->pdev, 0);
255 udev->mode = RTE_INTR_MODE_MSI;
259 /* fall back to INTX */
260 case RTE_INTR_MODE_LEGACY:
261 if (pci_intx_mask_supported(udev->pdev)) {
262 dev_dbg(&udev->pdev->dev, "using INTX");
263 udev->info.irq_flags = IRQF_SHARED | IRQF_NO_THREAD;
264 udev->info.irq = udev->pdev->irq;
265 udev->mode = RTE_INTR_MODE_LEGACY;
268 dev_notice(&udev->pdev->dev, "PCI INTX mask not supported\n");
269 /* fall back to no IRQ */
270 case RTE_INTR_MODE_NONE:
271 udev->mode = RTE_INTR_MODE_NONE;
272 udev->info.irq = UIO_IRQ_NONE;
276 dev_err(&udev->pdev->dev, "invalid IRQ mode %u",
277 igbuio_intr_mode_preferred);
278 udev->info.irq = UIO_IRQ_NONE;
282 if (udev->info.irq != UIO_IRQ_NONE)
283 err = request_irq(udev->info.irq, igbuio_pci_irqhandler,
284 udev->info.irq_flags, udev->info.name,
286 dev_info(&udev->pdev->dev, "uio device registered with irq %ld\n",
293 igbuio_pci_disable_interrupts(struct rte_uio_pci_dev *udev)
295 if (udev->info.irq) {
296 free_irq(udev->info.irq, udev);
300 #ifndef HAVE_ALLOC_IRQ_VECTORS
301 if (udev->mode == RTE_INTR_MODE_MSIX)
302 pci_disable_msix(udev->pdev);
303 if (udev->mode == RTE_INTR_MODE_MSI)
304 pci_disable_msi(udev->pdev);
306 if (udev->mode == RTE_INTR_MODE_MSIX ||
307 udev->mode == RTE_INTR_MODE_MSI)
308 pci_free_irq_vectors(udev->pdev);
314 * This gets called while opening uio device file.
317 igbuio_pci_open(struct uio_info *info, struct inode *inode)
319 struct rte_uio_pci_dev *udev = info->priv;
320 struct pci_dev *dev = udev->pdev;
323 mutex_lock(&udev->lock);
324 if (++udev->refcnt > 1) {
325 mutex_unlock(&udev->lock);
329 /* set bus master, which was cleared by the reset function */
332 /* enable interrupts */
333 err = igbuio_pci_enable_interrupts(udev);
334 mutex_unlock(&udev->lock);
336 dev_err(&dev->dev, "Enable interrupt fails\n");
343 igbuio_pci_release(struct uio_info *info, struct inode *inode)
345 struct rte_uio_pci_dev *udev = info->priv;
346 struct pci_dev *dev = udev->pdev;
348 mutex_lock(&udev->lock);
349 if (--udev->refcnt > 0) {
350 mutex_unlock(&udev->lock);
354 /* disable interrupts */
355 igbuio_pci_disable_interrupts(udev);
357 /* stop the device from further DMA */
358 pci_clear_master(dev);
360 mutex_unlock(&udev->lock);
364 /* Remap pci resources described by bar #pci_bar in uio resource n. */
366 igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
367 int n, int pci_bar, const char *name)
369 unsigned long addr, len;
372 if (n >= ARRAY_SIZE(info->mem))
375 addr = pci_resource_start(dev, pci_bar);
376 len = pci_resource_len(dev, pci_bar);
377 if (addr == 0 || len == 0)
379 if (wc_activate == 0) {
380 internal_addr = ioremap(addr, len);
381 if (internal_addr == NULL)
384 internal_addr = NULL;
386 info->mem[n].name = name;
387 info->mem[n].addr = addr;
388 info->mem[n].internal_addr = internal_addr;
389 info->mem[n].size = len;
390 info->mem[n].memtype = UIO_MEM_PHYS;
394 /* Get pci port io resources described by bar #pci_bar in uio resource n. */
396 igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
397 int n, int pci_bar, const char *name)
399 unsigned long addr, len;
401 if (n >= ARRAY_SIZE(info->port))
404 addr = pci_resource_start(dev, pci_bar);
405 len = pci_resource_len(dev, pci_bar);
406 if (addr == 0 || len == 0)
409 info->port[n].name = name;
410 info->port[n].start = addr;
411 info->port[n].size = len;
412 info->port[n].porttype = UIO_PORT_X86;
417 /* Unmap previously ioremap'd resources */
419 igbuio_pci_release_iomem(struct uio_info *info)
423 for (i = 0; i < MAX_UIO_MAPS; i++) {
424 if (info->mem[i].internal_addr)
425 iounmap(info->mem[i].internal_addr);
430 igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
432 int i, iom, iop, ret;
434 static const char *bar_names[PCI_STD_RESOURCE_END + 1] = {
446 for (i = 0; i < ARRAY_SIZE(bar_names); i++) {
447 if (pci_resource_len(dev, i) != 0 &&
448 pci_resource_start(dev, i) != 0) {
449 flags = pci_resource_flags(dev, i);
450 if (flags & IORESOURCE_MEM) {
451 ret = igbuio_pci_setup_iomem(dev, info, iom,
456 } else if (flags & IORESOURCE_IO) {
457 ret = igbuio_pci_setup_ioport(dev, info, iop,
466 return (iom != 0 || iop != 0) ? ret : -ENOENT;
469 #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
474 igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
476 struct rte_uio_pci_dev *udev;
477 dma_addr_t map_dma_addr;
481 #ifdef HAVE_PCI_IS_BRIDGE_API
482 if (pci_is_bridge(dev)) {
483 dev_warn(&dev->dev, "Ignoring PCI bridge device\n");
488 udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
492 mutex_init(&udev->lock);
494 * enable device: ask low-level code to enable I/O and
497 err = pci_enable_device(dev);
499 dev_err(&dev->dev, "Cannot enable PCI device\n");
503 /* enable bus mastering on the device */
506 /* remap IO memory */
507 err = igbuio_setup_bars(dev, &udev->info);
509 goto fail_release_iomem;
511 /* set 64-bit DMA mask */
512 err = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
514 dev_err(&dev->dev, "Cannot set DMA mask\n");
515 goto fail_release_iomem;
518 err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
520 dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
521 goto fail_release_iomem;
525 udev->info.name = "igb_uio";
526 udev->info.version = "0.1";
527 udev->info.irqcontrol = igbuio_pci_irqcontrol;
528 udev->info.open = igbuio_pci_open;
529 udev->info.release = igbuio_pci_release;
530 udev->info.priv = udev;
533 err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
535 goto fail_release_iomem;
537 /* register uio driver */
538 err = uio_register_device(&dev->dev, &udev->info);
540 goto fail_remove_group;
542 pci_set_drvdata(dev, udev);
545 * Doing a harmless dma mapping for attaching the device to
546 * the iommu identity mapping if kernel boots with iommu=pt.
547 * Note this is not a problem if no IOMMU at all.
549 map_addr = dma_alloc_coherent(&dev->dev, 1024, &map_dma_addr,
552 memset(map_addr, 0, 1024);
555 dev_info(&dev->dev, "dma mapping failed\n");
557 dev_info(&dev->dev, "mapping 1K dma=%#llx host=%p\n",
558 (unsigned long long)map_dma_addr, map_addr);
560 dma_free_coherent(&dev->dev, 1024, map_addr, map_dma_addr);
561 dev_info(&dev->dev, "unmapping 1K dma=%#llx host=%p\n",
562 (unsigned long long)map_dma_addr, map_addr);
568 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
570 igbuio_pci_release_iomem(&udev->info);
571 pci_disable_device(dev);
579 igbuio_pci_remove(struct pci_dev *dev)
581 struct rte_uio_pci_dev *udev = pci_get_drvdata(dev);
583 mutex_destroy(&udev->lock);
584 sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
585 uio_unregister_device(&udev->info);
586 igbuio_pci_release_iomem(&udev->info);
587 pci_disable_device(dev);
588 pci_set_drvdata(dev, NULL);
593 igbuio_config_intr_mode(char *intr_str)
596 pr_info("Use MSIX interrupt by default\n");
600 if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
601 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
602 pr_info("Use MSIX interrupt\n");
603 } else if (!strcmp(intr_str, RTE_INTR_MODE_MSI_NAME)) {
604 igbuio_intr_mode_preferred = RTE_INTR_MODE_MSI;
605 pr_info("Use MSI interrupt\n");
606 } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
607 igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
608 pr_info("Use legacy interrupt\n");
610 pr_info("Error: bad parameter - %s\n", intr_str);
617 static struct pci_driver igbuio_pci_driver = {
620 .probe = igbuio_pci_probe,
621 .remove = igbuio_pci_remove,
625 igbuio_pci_init_module(void)
629 if (igbuio_kernel_is_locked_down()) {
630 pr_err("Not able to use module, kernel lock down is enabled\n");
634 if (wc_activate != 0)
635 pr_info("wc_activate is set\n");
637 ret = igbuio_config_intr_mode(intr_mode);
641 return pci_register_driver(&igbuio_pci_driver);
645 igbuio_pci_exit_module(void)
647 pci_unregister_driver(&igbuio_pci_driver);
650 module_init(igbuio_pci_init_module);
651 module_exit(igbuio_pci_exit_module);
653 module_param(intr_mode, charp, S_IRUGO);
654 MODULE_PARM_DESC(intr_mode,
655 "igb_uio interrupt mode (default=msix):\n"
656 " " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
657 " " RTE_INTR_MODE_MSI_NAME " Use MSI interrupt\n"
658 " " RTE_INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n"
661 module_param(wc_activate, int, 0);
662 MODULE_PARM_DESC(wc_activate,
663 "Activate support for write combining (WC) (default=0)\n"
665 " other - enable\n");
667 MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
668 MODULE_LICENSE("GPL");
669 MODULE_AUTHOR("Intel Corporation");